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Commit 34f80b04 authored by Eilon Greenstein's avatar Eilon Greenstein Committed by David S. Miller
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bnx2x: Add support for BCM57711 HW 

Supporting the 57711 and 57711E - refers to in the code as E1H. The
57710 is referred to as E1.

To support the new members in the family, the bnx2x structure was
divided to 3 parts: common, port and function. These changes caused some
rearrangement in the bnx2x.h file.

A set of accessories macros were added to make access to the bnx2x
structure more readable
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e523287e
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Showing with 3774 additions and 2175 deletions
drivers/net/Kconfig
View file @ 34f80b04
......@@ -2600,6 +2600,7 @@ config BNX2X
tristate "Broadcom NetXtremeII 10Gb support"
depends on PCI
select ZLIB_INFLATE
select LIBCRC32C
help
This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards.
To compile this driver as a module, choose M here: the module
......
drivers/net/bnx2x.h
View file @ 34f80b04
......@@ -14,39 +14,46 @@
#ifndef BNX2X_H
#define BNX2X_H
/* compilation time flags */
/* define this to make the driver freeze on error to allow getting debug info
* (you will need to reboot afterwards) */
/* #define BNX2X_STOP_ON_ERROR */
/* error/debug prints */
#define DRV_MODULE_NAME "bnx2x"
#define PFX DRV_MODULE_NAME ": "
#define DRV_MODULE_NAME "bnx2x"
#define PFX DRV_MODULE_NAME ": "
/* for messages that are currently off */
#define BNX2X_MSG_OFF 0
#define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */
#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */
#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */
#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */
#define BNX2X_MSG_OFF 0
#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
/* regular debug print */
#define DP(__mask, __fmt, __args...) do { \
if (bp->msglevel & (__mask)) \
printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \
__LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
bp->dev?(bp->dev->name):"?", ##__args); \
} while (0)
/* for errors (never masked) */
#define BNX2X_ERR(__fmt, __args...) do { \
printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \
__LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
/* errors debug print */
#define BNX2X_DBG_ERR(__fmt, __args...) do { \
if (bp->msglevel & NETIF_MSG_PROBE) \
printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
bp->dev?(bp->dev->name):"?", ##__args); \
} while (0)
/* for logging (never masked) */
#define BNX2X_LOG(__fmt, __args...) do { \
printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \
__LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
/* for errors (never masked) */
#define BNX2X_ERR(__fmt, __args...) do { \
printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
bp->dev?(bp->dev->name):"?", ##__args); \
} while (0)
/* before we have a dev->name use dev_info() */
......@@ -60,7 +67,7 @@
#define bnx2x_panic() do { \
bp->panic = 1; \
BNX2X_ERR("driver assert\n"); \
bnx2x_disable_int(bp); \
bnx2x_int_disable(bp); \
bnx2x_panic_dump(bp); \
} while (0)
#else
......@@ -71,24 +78,29 @@
#endif
#define U64_LO(x) (((u64)x) & 0xffffffff)
#define U64_HI(x) (((u64)x) >> 32)
#define HILO_U64(hi, lo) (((u64)hi << 32) + lo)
#ifdef NETIF_F_HW_VLAN_TX
#define BCM_VLAN 1
#endif
#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
#define U64_HI(x) (u32)(((u64)(x)) >> 32)
#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
#define REG_ADDR(bp, offset) (bp->regview + offset)
#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
#define REG_ADDR(bp, offset) (bp->regview + offset)
#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
#define REG_RD_DMAE(bp, offset, valp, len32) \
do { \
......@@ -96,28 +108,28 @@
memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
} while (0)
#define REG_WR_DMAE(bp, offset, val, len32) \
#define REG_WR_DMAE(bp, offset, valp, len32) \
do { \
memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
offset, len32); \
} while (0)
#define SHMEM_RD(bp, type) \
REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type))
#define SHMEM_WR(bp, type, val) \
REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val)
#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
offsetof(struct shmem_region, field))
#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
#define NIG_WR(reg, val) REG_WR(bp, reg, val)
#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
#define for_each_nondefault_queue(bp, var) \
for (var = 1; var < bp->num_queues; var++)
#define is_multi(bp) (bp->num_queues > 1)
#define is_multi(bp) (bp->num_queues > 1)
struct regp {
......@@ -358,210 +370,122 @@ struct bnx2x_eth_stats {
u32 number_of_bugs_found_in_stats_spec; /* just kidding */
};
#define MAC_STX_NA 0xffffffff
#ifdef BNX2X_MULTI
#define MAX_CONTEXT 16
#else
#define MAX_CONTEXT 1
#endif
union cdu_context {
struct eth_context eth;
char pad[1024];
};
#define MAX_DMAE_C 5
/* DMA memory not used in fastpath */
struct bnx2x_slowpath {
union cdu_context context[MAX_CONTEXT];
struct eth_stats_query fw_stats;
struct mac_configuration_cmd mac_config;
struct mac_configuration_cmd mcast_config;
/* used by dmae command executer */
struct dmae_command dmae[MAX_DMAE_C];
union mac_stats mac_stats;
struct nig_stats nig;
struct bnx2x_eth_stats eth_stats;
u32 wb_comp;
#define BNX2X_WB_COMP_VAL 0xe0d0d0ae
u32 wb_data[4];
};
#define bnx2x_sp(bp, var) (&bp->slowpath->var)
#define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)
#define bnx2x_sp_mapping(bp, var) \
(bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
struct sw_rx_bd {
struct sk_buff *skb;
struct sk_buff *skb;
DECLARE_PCI_UNMAP_ADDR(mapping)
};
struct sw_tx_bd {
struct sk_buff *skb;
u16 first_bd;
struct sk_buff *skb;
u16 first_bd;
};
struct bnx2x_fastpath {
struct napi_struct napi;
struct napi_struct napi;
struct host_status_block *status_blk;
dma_addr_t status_blk_mapping;
dma_addr_t status_blk_mapping;
struct eth_tx_db_data *hw_tx_prods;
dma_addr_t tx_prods_mapping;
struct eth_tx_db_data *hw_tx_prods;
dma_addr_t tx_prods_mapping;
struct sw_tx_bd *tx_buf_ring;
struct sw_tx_bd *tx_buf_ring;
struct eth_tx_bd *tx_desc_ring;
dma_addr_t tx_desc_mapping;
dma_addr_t tx_desc_mapping;
struct sw_rx_bd *rx_buf_ring;
struct eth_rx_bd *rx_desc_ring;
dma_addr_t rx_desc_mapping;
dma_addr_t rx_desc_mapping;
union eth_rx_cqe *rx_comp_ring;
dma_addr_t rx_comp_mapping;
int state;
#define BNX2X_FP_STATE_CLOSED 0
#define BNX2X_FP_STATE_IRQ 0x80000
#define BNX2X_FP_STATE_OPENING 0x90000
#define BNX2X_FP_STATE_OPEN 0xa0000
#define BNX2X_FP_STATE_HALTING 0xb0000
#define BNX2X_FP_STATE_HALTED 0xc0000
int index;
u16 tx_pkt_prod;
u16 tx_pkt_cons;
u16 tx_bd_prod;
u16 tx_bd_cons;
u16 *tx_cons_sb;
u16 fp_c_idx;
u16 fp_u_idx;
u16 rx_bd_prod;
u16 rx_bd_cons;
u16 rx_comp_prod;
u16 rx_comp_cons;
u16 *rx_cons_sb;
unsigned long tx_pkt,
dma_addr_t rx_comp_mapping;
int state;
#define BNX2X_FP_STATE_CLOSED 0
#define BNX2X_FP_STATE_IRQ 0x80000
#define BNX2X_FP_STATE_OPENING 0x90000
#define BNX2X_FP_STATE_OPEN 0xa0000
#define BNX2X_FP_STATE_HALTING 0xb0000
#define BNX2X_FP_STATE_HALTED 0xc0000
u8 index; /* number in fp array */
u8 cl_id; /* eth client id */
u8 sb_id; /* status block number in HW */
#define FP_IDX(fp) (fp->index)
#define FP_CL_ID(fp) (fp->cl_id)
#define BP_CL_ID(bp) (bp->fp[0].cl_id)
#define FP_SB_ID(fp) (fp->sb_id)
#define CNIC_SB_ID 0
u16 tx_pkt_prod;
u16 tx_pkt_cons;
u16 tx_bd_prod;
u16 tx_bd_cons;
u16 *tx_cons_sb;
u16 fp_c_idx;
u16 fp_u_idx;
u16 rx_bd_prod;
u16 rx_bd_cons;
u16 rx_comp_prod;
u16 rx_comp_cons;
u16 *rx_cons_sb;
unsigned long tx_pkt,
rx_pkt,
rx_calls;
struct bnx2x *bp; /* parent */
};
#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
/* attn group wiring */
#define MAX_DYNAMIC_ATTN_GRPS 8
struct attn_route {
u32 sig[4];
struct bnx2x *bp; /* parent */
};
struct bnx2x {
/* Fields used in the tx and intr/napi performance paths
* are grouped together in the beginning of the structure
*/
struct bnx2x_fastpath *fp;
void __iomem *regview;
void __iomem *doorbells;
struct net_device *dev;
struct pci_dev *pdev;
atomic_t intr_sem;
struct msix_entry msix_table[MAX_CONTEXT+1];
int tx_ring_size;
#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
/* This is needed for determening of last_max */
#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
#ifdef BCM_VLAN
struct vlan_group *vlgrp;
#endif
u32 rx_csum;
u32 rx_offset;
u32 rx_buf_use_size; /* useable size */
u32 rx_buf_size; /* with alignment */
#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
#define ETH_MIN_PACKET_SIZE 60
#define ETH_MAX_PACKET_SIZE 1500
#define ETH_MAX_JUMBO_PACKET_SIZE 9600
/* stuff added to make the code fit 80Col */
struct host_def_status_block *def_status_blk;
#define DEF_SB_ID 16
u16 def_c_idx;
u16 def_u_idx;
u16 def_t_idx;
u16 def_x_idx;
u16 def_att_idx;
u32 attn_state;
struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
u32 aeu_mask;
u32 nig_mask;
#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
/* slow path ring */
struct eth_spe *spq;
dma_addr_t spq_mapping;
u16 spq_prod_idx;
struct eth_spe *spq_prod_bd;
struct eth_spe *spq_last_bd;
u16 *dsb_sp_prod;
u16 spq_left; /* serialize spq */
spinlock_t spq_lock;
/* Flag for marking that there is either
* STAT_QUERY or CFC DELETE ramrod pending
*/
u8 stat_pending;
#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
/* End of fields used in the performance code paths */
int panic;
int msglevel;
#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
u32 flags;
#define PCIX_FLAG 1
#define PCI_32BIT_FLAG 2
#define ONE_TDMA_FLAG 4 /* no longer used */
#define NO_WOL_FLAG 8
#define USING_DAC_FLAG 0x10
#define USING_MSIX_FLAG 0x20
#define ASF_ENABLE_FLAG 0x40
#define BNX2X_RX_SB_INDEX \
(&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
int port;
#define BNX2X_RX_SB_BD_INDEX \
(&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
int pm_cap;
int pcie_cap;
#define BNX2X_RX_SB_INDEX_NUM \
(((U_SB_ETH_RX_CQ_INDEX << \
USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
((U_SB_ETH_RX_BD_INDEX << \
USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
struct work_struct sp_task;
struct work_struct reset_task;
#define BNX2X_TX_SB_INDEX \
(&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
struct timer_list timer;
int timer_interval;
int current_interval;
/* common */
u32 shmem_base;
struct bnx2x_common {
u32 chip_id;
/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
#define CHIP_ID(bp) (bp->chip_id & 0xfffffff0)
#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
#define CHIP_NUM(bp) (bp->chip_id >> 16)
#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
#define CHIP_NUM_57710 0x164e
#define CHIP_NUM_57711 0x164f
#define CHIP_NUM_57711E 0x1650
......@@ -572,7 +496,7 @@ struct bnx2x {
CHIP_IS_57711E(bp))
#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
#define CHIP_REV(bp) (bp->chip_id & 0x0000f000)
#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
#define CHIP_REV_Ax 0x00000000
/* assume maximum 5 revisions */
#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
......@@ -586,86 +510,250 @@ struct bnx2x {
#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
#define CHIP_METAL(bp) (bp->chip_id & 0x00000ff0)
#define CHIP_BOND_ID(bp) (bp->chip_id & 0x0000000f)
#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
u16 fw_seq;
u16 fw_drv_pulse_wr_seq;
u32 fw_mb;
int flash_size;
#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
#define NVRAM_TIMEOUT_COUNT 30000
#define NVRAM_PAGE_SIZE 256
u32 hw_config;
u32 shmem_base;
u32 hw_config;
u32 board;
struct link_params link_params;
u32 bc_ver;
char *name;
};
struct link_vars link_vars;
/* end of common */
/* port */
struct bnx2x_port {
u32 pmf;
u32 link_config;
u32 supported;
u32 supported;
/* link settings - missing defines */
#define SUPPORTED_2500baseX_Full (1 << 15)
u32 advertising;
/* link settings - missing defines */
#define SUPPORTED_2500baseT_Full (1 << 15)
#define ADVERTISED_2500baseX_Full (1 << 15)
u32 phy_addr;
u32 phy_addr;
/* used to synchronize phy accesses */
struct mutex phy_mutex;
u32 phy_id;
u32 port_stx;
struct nig_stats old_nig_stats;
};
u32 advertising;
/* link settings - missing defines */
#define ADVERTISED_2500baseT_Full (1 << 15)
/* end of port */
#define MAC_STX_NA 0xffffffff
#ifdef BNX2X_MULTI
#define MAX_CONTEXT 16
#else
#define MAX_CONTEXT 1
#endif
union cdu_context {
struct eth_context eth;
char pad[1024];
};
#define MAX_DMAE_C 6
/* DMA memory not used in fastpath */
struct bnx2x_slowpath {
union cdu_context context[MAX_CONTEXT];
struct eth_stats_query fw_stats;
struct mac_configuration_cmd mac_config;
struct mac_configuration_cmd mcast_config;
/* used by dmae command executer */
struct dmae_command dmae[MAX_DMAE_C];
union mac_stats mac_stats;
struct nig_stats nig;
struct bnx2x_eth_stats eth_stats;
u32 wb_comp;
#define BNX2X_WB_COMP_VAL 0xe0d0d0ae
u32 wb_data[4];
};
#define bnx2x_sp(bp, var) (&bp->slowpath->var)
#define bnx2x_sp_mapping(bp, var) \
(bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
/* attn group wiring */
#define MAX_DYNAMIC_ATTN_GRPS 8
struct attn_route {
u32 sig[4];
};
struct bnx2x {
/* Fields used in the tx and intr/napi performance paths
* are grouped together in the beginning of the structure
*/
struct bnx2x_fastpath fp[MAX_CONTEXT];
void __iomem *regview;
void __iomem *doorbells;
#define BNX2X_DB_SIZE (16*2048)
struct net_device *dev;
struct pci_dev *pdev;
atomic_t intr_sem;
struct msix_entry msix_table[MAX_CONTEXT+1];
int tx_ring_size;
#ifdef BCM_VLAN
struct vlan_group *vlgrp;
#endif
u32 rx_csum;
u32 rx_offset;
u32 rx_buf_use_size; /* useable size */
u32 rx_buf_size; /* with alignment */
#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
#define ETH_MIN_PACKET_SIZE 60
#define ETH_MAX_PACKET_SIZE 1500
#define ETH_MAX_JUMBO_PACKET_SIZE 9600
u32 bc_ver;
struct host_def_status_block *def_status_blk;
#define DEF_SB_ID 16
u16 def_c_idx;
u16 def_u_idx;
u16 def_x_idx;
u16 def_t_idx;
u16 def_att_idx;
u32 attn_state;
struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
u32 aeu_mask;
u32 nig_mask;
/* slow path ring */
struct eth_spe *spq;
dma_addr_t spq_mapping;
u16 spq_prod_idx;
struct eth_spe *spq_prod_bd;
struct eth_spe *spq_last_bd;
u16 *dsb_sp_prod;
u16 spq_left; /* serialize spq */
/* used to synchronize spq accesses */
spinlock_t spq_lock;
/* Flag for marking that there is either
* STAT_QUERY or CFC DELETE ramrod pending
*/
u8 stat_pending;
/* End of fileds used in the performance code paths */
int panic;
int msglevel;
u32 flags;
#define PCIX_FLAG 1
#define PCI_32BIT_FLAG 2
#define ONE_TDMA_FLAG 4 /* no longer used */
#define NO_WOL_FLAG 8
#define USING_DAC_FLAG 0x10
#define USING_MSIX_FLAG 0x20
#define ASF_ENABLE_FLAG 0x40
#define NO_MCP_FLAG 0x100
#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
int func;
#define BP_PORT(bp) (bp->func % PORT_MAX)
#define BP_FUNC(bp) (bp->func)
#define BP_E1HVN(bp) (bp->func >> 1)
#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
/* assorted E1HVN */
#define IS_E1HMF(bp) (bp->e1hmf != 0)
#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
int pm_cap;
int pcie_cap;
struct work_struct sp_task;
struct work_struct reset_task;
struct timer_list timer;
int timer_interval;
int current_interval;
u16 fw_seq;
u16 fw_drv_pulse_wr_seq;
u32 func_stx;
struct link_params link_params;
struct link_vars link_vars;
int flash_size;
#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
#define NVRAM_TIMEOUT_COUNT 30000
#define NVRAM_PAGE_SIZE 256
struct bnx2x_common common;
struct bnx2x_port port;
u32 mf_config;
u16 e1hov;
u8 e1hmf;
u8 wol;
int rx_ring_size;
int rx_ring_size;
u16 tx_quick_cons_trip_int;
u16 tx_quick_cons_trip;
u16 tx_ticks_int;
u16 tx_ticks;
u16 tx_quick_cons_trip_int;
u16 tx_quick_cons_trip;
u16 tx_ticks_int;
u16 tx_ticks;
u16 rx_quick_cons_trip_int;
u16 rx_quick_cons_trip;
u16 rx_ticks_int;
u16 rx_ticks;
u16 rx_quick_cons_trip_int;
u16 rx_quick_cons_trip;
u16 rx_ticks_int;
u16 rx_ticks;
u32 stats_ticks;
u32 stats_ticks;
u32 lin_cnt;
int state;
#define BNX2X_STATE_CLOSED 0x0
#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
int state;
#define BNX2X_STATE_CLOSED 0x0
#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
#define BNX2X_STATE_OPEN 0x3000
#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
#define BNX2X_STATE_ERROR 0xF000
#define BNX2X_STATE_DISABLED 0xd000
#define BNX2X_STATE_DIAG 0xe000
#define BNX2X_STATE_ERROR 0xf000
int num_queues;
int num_queues;
u32 rx_mode;
#define BNX2X_RX_MODE_NONE 0
#define BNX2X_RX_MODE_NORMAL 1
#define BNX2X_RX_MODE_ALLMULTI 2
#define BNX2X_RX_MODE_PROMISC 3
#define BNX2X_MAX_MULTICAST 64
#define BNX2X_MAX_EMUL_MULTI 16
u32 rx_mode;
#define BNX2X_RX_MODE_NONE 0
#define BNX2X_RX_MODE_NORMAL 1
#define BNX2X_RX_MODE_ALLMULTI 2
#define BNX2X_RX_MODE_PROMISC 3
#define BNX2X_MAX_MULTICAST 64
#define BNX2X_MAX_EMUL_MULTI 16
dma_addr_t def_status_blk_mapping;
dma_addr_t def_status_blk_mapping;
struct bnx2x_slowpath *slowpath;
dma_addr_t slowpath_mapping;
struct bnx2x_slowpath *slowpath;
dma_addr_t slowpath_mapping;
#ifdef BCM_ISCSI
void *t1;
......@@ -742,8 +830,10 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
/* MC hsi */
#define RX_COPY_THRESH 92
#define BCM_PAGE_BITS 12
#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
#define BCM_PAGE_SHIFT 12
#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
#define NUM_TX_RINGS 16
#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
......@@ -795,26 +885,11 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
/* must be used on a CID before placing it on a HW ring */
#define HW_CID(bp, x) (x | (bp->port << 23))
#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
#define ATTN_NIG_FOR_FUNC (1L << 8)
#define ATTN_SW_TIMER_4_FUNC (1L << 9)
#define GPIO_2_FUNC (1L << 10)
#define GPIO_3_FUNC (1L << 11)
#define GPIO_4_FUNC (1L << 12)
#define ATTN_GENERAL_ATTN_1 (1L << 13)
#define ATTN_GENERAL_ATTN_2 (1L << 14)
#define ATTN_GENERAL_ATTN_3 (1L << 15)
#define ATTN_GENERAL_ATTN_4 (1L << 13)
#define ATTN_GENERAL_ATTN_5 (1L << 14)
#define ATTN_GENERAL_ATTN_6 (1L << 15)
#define ATTN_HARD_WIRED_MASK 0xff00
#define ATTENTION_ID 4
#define BNX2X_BTR 3
#define MAX_SPQ_PENDING 8
......@@ -831,6 +906,31 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
DPM_TRIGER_TYPE); \
} while (0)
static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
int wait)
{
u32 val;
do {
val = REG_RD(bp, reg);
if (val == expected)
break;
ms -= wait;
msleep(wait);
} while (ms > 0);
return val;
}
/* load/unload mode */
#define LOAD_NORMAL 0
#define LOAD_OPEN 1
#define LOAD_DIAG 2
#define UNLOAD_NORMAL 0
#define UNLOAD_CLOSE 1
/* DMAE command defines */
#define DMAE_CMD_SRC_PCI 0
#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
......@@ -877,23 +977,48 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
/* stuff added to make the code fit 80Col */
/* must be used on a CID before placing it on a HW ring */
#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
#define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \
(TPA_TYPE_START | TPA_TYPE_END))
#define BNX2X_RX_SUM_OK(cqe) \
(!(cqe->fast_path_cqe.status_flags & \
(ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
#define BNX2X_RX_SUM_FIX(cqe) \
((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
(1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
/* CMNG constants
derived from lab experiments, and not from system spec calculations !!! */
#define DEF_MIN_RATE 100
/* resolution of the rate shaping timer - 100 usec */
#define RS_PERIODIC_TIMEOUT_USEC 100
/* resolution of fairness algorithm in usecs -
coefficient for clauclating the actuall t fair */
#define T_FAIR_COEF 10000000
/* number of bytes in single QM arbitration cycle -
coeffiecnt for calculating the fairness timer */
#define QM_ARB_BYTES 40000
#define FAIR_MEM 2
#define ATTN_NIG_FOR_FUNC (1L << 8)
#define ATTN_SW_TIMER_4_FUNC (1L << 9)
#define GPIO_2_FUNC (1L << 10)
#define GPIO_3_FUNC (1L << 11)
#define GPIO_4_FUNC (1L << 12)
#define ATTN_GENERAL_ATTN_1 (1L << 13)
#define ATTN_GENERAL_ATTN_2 (1L << 14)
#define ATTN_GENERAL_ATTN_3 (1L << 15)
#define ATTN_GENERAL_ATTN_4 (1L << 13)
#define ATTN_GENERAL_ATTN_5 (1L << 14)
#define ATTN_GENERAL_ATTN_6 (1L << 15)
#define ATTN_HARD_WIRED_MASK 0xff00
#define ATTENTION_ID 4
/* stuff added to make the code fit 80Col */
#define BNX2X_PMF_LINK_ASSERT \
GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
#define BNX2X_MC_ASSERT_BITS \
(GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
......@@ -906,12 +1031,20 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
#define BNX2X_DOORQ_ASSERT \
AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
#define HW_INTERRUT_ASSERT_SET_0 \
(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
......@@ -928,7 +1061,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
......@@ -945,7 +1078,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
......@@ -954,42 +1087,44 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
#define MULTI_FLAGS \
(TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
(TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
#define MULTI_MASK 0x7f
#define MULTI_MASK 0x7f
#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
#define BNX2X_RX_SB_INDEX \
&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]
#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
#define BNX2X_TX_SB_INDEX \
&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]
#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
#define BNX2X_SP_DSB_INDEX \
&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]
(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
#define CAM_IS_INVALID(x) \
(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
#define CAM_INVALIDATE(x) \
x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE
(x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
/* Number of u32 elements in MC hash array */
#define MC_HASH_SIZE 8
#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
#ifndef PXP2_REG_PXP2_INT_STS
#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
#endif
/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
#endif /* bnx2x.h */
drivers/net/bnx2x_fw_defs.h
View file @ 34f80b04
......@@ -8,191 +8,390 @@
*/
#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
(0x1922 + (port * 0x40) + (index * 0x4))
#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
(0x1900 + (port * 0x40))
#define CSTORM_HC_BTR_OFFSET(port)\
(0x1984 + (port * 0xc0))
#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
(0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
(0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
(0x1400 + (port * 0x280) + (cpu_id * 0x28))
#define CSTORM_STATS_FLAGS_OFFSET(port) (0x5108 + (port * 0x8))
#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id)\
(0x1510 + (port * 0x240) + (client_id * 0x20))
#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
(0x138a + (port * 0x28) + (index * 0x4))
#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
(0x1370 + (port * 0x28))
#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
(0x4b70 + (port * 0x8))
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function)\
(0x1418 + (function * 0x30))
#define TSTORM_HC_BTR_OFFSET(port)\
(0x13c4 + (port * 0x18))
#define TSTORM_INDIRECTION_TABLE_OFFSET(port)\
(0x22c8 + (port * 0x80))
#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(port)\
(0x1420 + (port * 0x30))
#define TSTORM_RCQ_PROD_OFFSET(port, client_id)\
(0x1508 + (port * 0x240) + (client_id * 0x20))
#define TSTORM_STATS_FLAGS_OFFSET(port) (0x4b90 + (port * 0x8))
#define USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
(0x191a + (port * 0x28) + (index * 0x4))
#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
(0x1900 + (port * 0x28))
#define USTORM_HC_BTR_OFFSET(port)\
(0x1954 + (port * 0xb8))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port)\
(0x5408 + (port * 0x8))
#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
(0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
(0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
(0x1400 + (port * 0x280) + (cpu_id * 0x28))
#define XSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
#define XSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
(0x141a + (port * 0x28) + (index * 0x4))
#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
(0x1400 + (port * 0x28))
#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
(0x5408 + (port * 0x8))
#define XSTORM_HC_BTR_OFFSET(port)\
(0x1454 + (port * 0x18))
#define XSTORM_SPQ_PAGE_BASE_OFFSET(port)\
(0x5328 + (port * 0x18))
#define XSTORM_SPQ_PROD_OFFSET(port)\
(0x5330 + (port * 0x18))
#define XSTORM_STATS_FLAGS_OFFSET(port) (0x53f8 + (port * 0x8))
#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET? 0x7000 : 0x1000)
#define CSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET? (0x8522 + ((function>>1) * 0x40) + ((function&1) \
* 0x100) + (index * 0x4)) : (0x1922 + (function * 0x40) + (index \
* 0x4)))
#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
(IS_E1H_OFFSET? (0x8500 + ((function>>1) * 0x40) + ((function&1) \
* 0x100)) : (0x1900 + (function * 0x40)))
#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
(IS_E1H_OFFSET? (0x8508 + ((function>>1) * 0x40) + ((function&1) \
* 0x100)) : (0x1908 + (function * 0x40)))
#define CSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET? 0x11e8 : 0xffffffff)
#define CSTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)))
#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)))
#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
(0x1400 + (port * 0x280) + (cpu_id * 0x28)))
#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
(0x1408 + (port * 0x280) + (cpu_id * 0x28)))
#define CSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET? (0x1108 + (function * 0x8)) : (0x5108 + \
(function * 0x8)))
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
(IS_E1H_OFFSET? (0x31c0 + (function * 0x20)) : 0xffffffff)
#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET? 0xa000 : 0x1000)
#define TSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
(IS_E1H_OFFSET? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) : \
(0x9c8 + (port * 0x2f8) + (client_id * 0x28)))
#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET? (0xb01a + ((function>>1) * 0x28) + ((function&1) \
* 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \
0x4)))
#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
(IS_E1H_OFFSET? (0xb000 + ((function>>1) * 0x28) + ((function&1) \
* 0xa0)) : (0x1400 + (function * 0x28)))
#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
(IS_E1H_OFFSET? (0xb008 + ((function>>1) * 0x28) + ((function&1) \
* 0xa0)) : (0x1408 + (function * 0x28)))
#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
(IS_E1H_OFFSET? (0x2b80 + (function * 0x8)) : (0x4b68 + \
(function * 0x8)))
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
(IS_E1H_OFFSET? (0x3000 + (function * 0x38)) : (0x1500 + \
(function * 0x38)))
#define TSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET? 0x1ad0 : 0xffffffff)
#define TSTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
(IS_E1H_OFFSET? (0x12c8 + (function * 0x80)) : (0x22c8 + \
(function * 0x80)))
#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
(IS_E1H_OFFSET? (0x3008 + (function * 0x38)) : (0x1508 + \
(function * 0x38)))
#define TSTORM_RX_PRODS_OFFSET(port, client_id) \
(IS_E1H_OFFSET? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) : \
(0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
#define TSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET? (0x2c00 + (function * 0x8)) : (0x4b88 + \
(function * 0x8)))
#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET? 0x3b30 : 0x1c20)
#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET? 0xa040 : 0x2c10)
#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET? 0x2440 : 0x1200)
#define USTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET? 0x8000 : 0x1000)
#define USTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
(IS_E1H_OFFSET? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \
(0x5450 + (port * 0x1c8) + (clientId * 0x18)))
#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET? (0x951a + ((function>>1) * 0x28) + ((function&1) \
* 0xa0) + (index * 0x4)) : (0x191a + (function * 0x28) + (index * \
0x4)))
#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
(IS_E1H_OFFSET? (0x9500 + ((function>>1) * 0x28) + ((function&1) \
* 0xa0)) : (0x1900 + (function * 0x28)))
#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
(IS_E1H_OFFSET? (0x9508 + ((function>>1) * 0x28) + ((function&1) \
* 0xa0)) : (0x1908 + (function * 0x28)))
#define USTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET? 0x2448 : 0xffffffff)
#define USTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))
#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
(IS_E1H_OFFSET? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \
(0x5448 + (port * 0x1c8) + (clientId * 0x18)))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
(IS_E1H_OFFSET? (0x2408 + (function * 0x8)) : (0x5408 + \
(function * 0x8)))
#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)))
#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
(IS_E1H_OFFSET? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
(index * 0x4)))
#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
(0x1400 + (port * 0x280) + (cpu_id * 0x28)))
#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
(IS_E1H_OFFSET? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
(0x1408 + (port * 0x280) + (cpu_id * 0x28)))
#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
(IS_E1H_OFFSET? 0x9000 : 0x1000)
#define XSTORM_ASSERT_LIST_OFFSET(idx) \
(IS_E1H_OFFSET? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
(IS_E1H_OFFSET? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))
#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
(IS_E1H_OFFSET? (0xa01a + ((function>>1) * 0x28) + ((function&1) \
* 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \
0x4)))
#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
(IS_E1H_OFFSET? (0xa000 + ((function>>1) * 0x28) + ((function&1) \
* 0xa0)) : (0x1400 + (function * 0x28)))
#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
(IS_E1H_OFFSET? (0xa008 + ((function>>1) * 0x28) + ((function&1) \
* 0xa0)) : (0x1408 + (function * 0x28)))
#define XSTORM_E1HOV_OFFSET(function) \
(IS_E1H_OFFSET? (0x2ab8 + (function * 0x2)) : 0xffffffff)
#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
(IS_E1H_OFFSET? (0x2418 + (function * 0x8)) : (0x3b70 + \
(function * 0x8)))
#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
(IS_E1H_OFFSET? (0x2568 + (function * 0x70)) : (0x3c60 + \
(function * 0x70)))
#define XSTORM_FUNCTION_MODE_OFFSET \
(IS_E1H_OFFSET? 0x2ac8 : 0xffffffff)
#define XSTORM_HC_BTR_OFFSET(port) \
(IS_E1H_OFFSET? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
(IS_E1H_OFFSET? (0x2528 + (function * 0x70)) : (0x3c20 + \
(function * 0x70)))
#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
(IS_E1H_OFFSET? (0x2000 + (function * 0x10)) : (0x3328 + \
(function * 0x10)))
#define XSTORM_SPQ_PROD_OFFSET(function) \
(IS_E1H_OFFSET? (0x2008 + (function * 0x10)) : (0x3330 + \
(function * 0x10)))
#define XSTORM_STATS_FLAGS_OFFSET(function) \
(IS_E1H_OFFSET? (0x23d8 + (function * 0x8)) : (0x3b60 + \
(function * 0x8)))
#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
/**
* This file defines HSI constatnts for the ETH flow
*/
/* hash types */
#define DEFAULT_HASH_TYPE 0
#define IPV4_HASH_TYPE 1
#define TCP_IPV4_HASH_TYPE 2
#define IPV6_HASH_TYPE 3
#define TCP_IPV6_HASH_TYPE 4
#ifdef _EVEREST_MICROCODE
#include "microcode_constants.h"
#include "eth_rx_bd.h"
#include "eth_tx_bd.h"
#include "eth_rx_cqe.h"
#include "eth_rx_sge.h"
#include "eth_rx_cqe_next_page.h"
#endif
/* RSS hash types */
#define DEFAULT_HASH_TYPE 0
#define IPV4_HASH_TYPE 1
#define TCP_IPV4_HASH_TYPE 2
#define IPV6_HASH_TYPE 3
#define TCP_IPV6_HASH_TYPE 4
/* Ethernet Ring parmaters */
#define X_ETH_LOCAL_RING_SIZE 13
#define FIRST_BD_IN_PKT 0
#define PARSE_BD_INDEX 1
#define NUM_OF_ETH_BDS_IN_PAGE \
((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))
/* Rx ring params */
#define U_ETH_LOCAL_BD_RING_SIZE (16)
#define U_ETH_LOCAL_SGE_RING_SIZE (12)
#define U_ETH_SGL_SIZE (8)
#define U_ETH_BDS_PER_PAGE_MASK \
((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
#define U_ETH_CQE_PER_PAGE_MASK \
((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
#define U_ETH_SGES_PER_PAGE_MASK \
((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
#define TU_ETH_CQES_PER_PAGE \
(PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
#define U_ETH_UNDEFINED_Q 0xFF
/* values of command IDs in the ramrod message */
#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
#define RAMROD_CMD_ID_ETH_UPDATE (100)
#define RAMROD_CMD_ID_ETH_HALT (105)
#define RAMROD_CMD_ID_ETH_SET_MAC (110)
#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
#define RAMROD_CMD_ID_ETH_UPDATE (100)
#define RAMROD_CMD_ID_ETH_HALT (105)
#define RAMROD_CMD_ID_ETH_SET_MAC (110)
#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
/* command values for set mac command */
#define T_ETH_MAC_COMMAND_SET 0
#define T_ETH_MAC_COMMAND_INVALIDATE 1
#define T_ETH_MAC_COMMAND_SET 0
#define T_ETH_MAC_COMMAND_INVALIDATE 1
#define T_ETH_INDIRECTION_TABLE_SIZE 128
#define T_ETH_INDIRECTION_TABLE_SIZE 128
/*The CRC32 seed, that is used for the hash(reduction) multicast address */
#define T_ETH_CRC32_HASH_SEED 0x00000000
/* Maximal L2 clients supported */
#define ETH_MAX_RX_CLIENTS (18)
#define ETH_MAX_RX_CLIENTS_E1 19
#define ETH_MAX_RX_CLIENTS_E1H 25
/* Maximal aggregation queues supported */
#define ETH_MAX_AGGREGATION_QUEUES_E1 (32)
#define ETH_MAX_AGGREGATION_QUEUES_E1H (64)
/**
* This file defines HSI constatnts common to all microcode flows
*/
/* Connection types */
#define ETH_CONNECTION_TYPE 0
#define ETH_CONNECTION_TYPE 0
#define TOE_CONNECTION_TYPE 1
#define RDMA_CONNECTION_TYPE 2
#define ISCSI_CONNECTION_TYPE 3
#define FCOE_CONNECTION_TYPE 4
#define RESERVED_CONNECTION_TYPE_0 5
#define RESERVED_CONNECTION_TYPE_1 6
#define RESERVED_CONNECTION_TYPE_2 7
#define PROTOCOL_STATE_BIT_OFFSET 6
#define PROTOCOL_STATE_BIT_OFFSET 6
#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define ISCSI_STATE \
(ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
#define FCOE_STATE (FCOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
/* microcode fixed page page size 4K (chains and ring segments) */
#define MC_PAGE_SIZE (4096)
#define MC_PAGE_SIZE (4096)
/* Host coalescing constants */
/* IGU constants */
#define IGU_PORT_BASE 0x0400
#define IGU_ADDR_MSIX 0x0000
#define IGU_ADDR_INT_ACK 0x0200
#define IGU_ADDR_PROD_UPD 0x0201
#define IGU_ADDR_ATTN_BITS_UPD 0x0202
#define IGU_ADDR_ATTN_BITS_SET 0x0203
#define IGU_ADDR_ATTN_BITS_CLR 0x0204
#define IGU_ADDR_COALESCE_NOW 0x0205
#define IGU_ADDR_SIMD_MASK 0x0206
#define IGU_ADDR_SIMD_NOMASK 0x0207
#define IGU_ADDR_MSI_CTL 0x0210
#define IGU_ADDR_MSI_ADDR_LO 0x0211
#define IGU_ADDR_MSI_ADDR_HI 0x0212
#define IGU_ADDR_MSI_DATA 0x0213
#define IGU_INT_ENABLE 0
#define IGU_INT_DISABLE 1
#define IGU_INT_NOP 2
#define IGU_INT_NOP2 3
/* Host coalescing constants */
/* index numbers */
#define HC_USTORM_DEF_SB_NUM_INDICES 4
#define HC_CSTORM_DEF_SB_NUM_INDICES 8
#define HC_XSTORM_DEF_SB_NUM_INDICES 4
#define HC_TSTORM_DEF_SB_NUM_INDICES 4
#define HC_USTORM_SB_NUM_INDICES 4
#define HC_CSTORM_SB_NUM_INDICES 4
#define HC_USTORM_DEF_SB_NUM_INDICES 4
#define HC_CSTORM_DEF_SB_NUM_INDICES 8
#define HC_XSTORM_DEF_SB_NUM_INDICES 4
#define HC_TSTORM_DEF_SB_NUM_INDICES 4
#define HC_USTORM_SB_NUM_INDICES 4
#define HC_CSTORM_SB_NUM_INDICES 4
/* index values - which counterto update */
#define HC_INDEX_U_ETH_RX_CQ_CONS 1
#define HC_INDEX_U_TOE_RX_CQ_CONS 0
#define HC_INDEX_U_ETH_RX_CQ_CONS 1
#define HC_INDEX_U_ETH_RX_BD_CONS 2
#define HC_INDEX_U_FCOE_EQ_CONS 3
#define HC_INDEX_C_TOE_TX_CQ_CONS 0
#define HC_INDEX_C_ETH_TX_CQ_CONS 1
#define HC_INDEX_C_ISCSI_EQ_CONS 2
#define HC_INDEX_DEF_X_SPQ_CONS 0
#define HC_INDEX_C_ETH_TX_CQ_CONS 1
#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
#define HC_INDEX_DEF_X_SPQ_CONS 0
#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
/* used by the driver to get the SB offset */
#define USTORM_ID 0
#define CSTORM_ID 1
#define XSTORM_ID 2
#define TSTORM_ID 3
#define ATTENTION_ID 4
#define USTORM_ID 0
#define CSTORM_ID 1
#define XSTORM_ID 2
#define TSTORM_ID 3
#define ATTENTION_ID 4
/* max number of slow path commands per port */
#define MAX_RAMRODS_PER_PORT (8)
#define MAX_RAMRODS_PER_PORT (8)
/* values for RX ETH CQE type field */
#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
/* MAC address list size */
#define T_MAC_ADDRESS_LIST_SIZE (96)
#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
#define EMULATION_FREQUENCY_FACTOR (1600)
#define FPGA_FREQUENCY_FACTOR (100)
#define TIMERS_TICK_SIZE_CHIP (1e-3)
#define TIMERS_TICK_SIZE_EMUL \
((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
#define TIMERS_TICK_SIZE_FPGA \
((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
#define TSEMI_CLK1_RESUL_CHIP (1e-3)
#define TSEMI_CLK1_RESUL_EMUL \
((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
#define TSEMI_CLK1_RESUL_FPGA \
((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
#define USEMI_CLK1_RESUL_CHIP \
(TIMERS_TICK_SIZE_CHIP)
#define USEMI_CLK1_RESUL_EMUL \
(TIMERS_TICK_SIZE_EMUL)
#define USEMI_CLK1_RESUL_FPGA \
(TIMERS_TICK_SIZE_FPGA)
#define XSEMI_CLK1_RESUL_CHIP (1e-3)
#define XSEMI_CLK1_RESUL_EMUL \
((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
#define XSEMI_CLK1_RESUL_FPGA \
((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
#define XSEMI_CLK2_RESUL_CHIP (1e-6)
#define XSEMI_CLK2_RESUL_EMUL \
((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
#define XSEMI_CLK2_RESUL_FPGA \
((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
#define SDM_TIMER_TICK_RESUL_EMUL \
((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
#define SDM_TIMER_TICK_RESUL_FPGA \
((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
#define XSTORM_IP_ID_ROLL_HALF 0x8000
#define XSTORM_IP_ID_ROLL_ALL 0
#define FW_LOG_LIST_SIZE (50)
#define FW_LOG_LIST_SIZE (50)
#define NUM_OF_PROTOCOLS 4
#define MAX_COS_NUMBER 16
#define MAX_T_STAT_COUNTER_ID 18
#define MAX_X_STAT_COUNTER_ID 18
#define NUM_OF_PROTOCOLS 4
#define MAX_COS_NUMBER 16
#define MAX_T_STAT_COUNTER_ID 18
#define UNKNOWN_ADDRESS 0
#define UNICAST_ADDRESS 1
#define MULTICAST_ADDRESS 2
#define BROADCAST_ADDRESS 3
#define T_FAIR 1
#define FAIR_MEM 2
#define RS_PERIODIC_TIMEOUT_IN_SDM_TICS 25
#define SINGLE_FUNCTION 0
#define MULTI_FUNCTION 1
#define UNKNOWN_ADDRESS 0
#define UNICAST_ADDRESS 1
#define MULTICAST_ADDRESS 2
#define BROADCAST_ADDRESS 3
#define IP_V4 0
#define IP_V6 1
drivers/net/bnx2x_hsi.h
View file @ 34f80b04
......@@ -132,6 +132,12 @@ struct shared_hw_cfg { /* NVRAM Offset */
#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009
#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a
#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1023G 0x0000000b
#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1033G 0x0000000c
#define SHARED_HW_CFG_BOARD_TYPE_BCM957711T1101 0x0000000d
#define SHARED_HW_CFG_BOARD_TYPE_BCM957711ET1201 0x0000000e
#define SHARED_HW_CFG_BOARD_TYPE_BCM957711A1133G 0x0000000f
#define SHARED_HW_CFG_BOARD_TYPE_BCM957711EA1233G 0x00000010
#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
#define SHARED_HW_CFG_BOARD_VER_SHIFT 16
......@@ -313,6 +319,7 @@ struct shared_feat_cfg { /* NVRAM Offset */
u32 config; /* 0x450 */
#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
#define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
};
......@@ -502,20 +509,20 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
};
/*****************************************************************************
* Device Information *
*****************************************************************************/
struct dev_info { /* size */
/****************************************************************************
* Device Information *
****************************************************************************/
struct dev_info { /* size */
u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
struct shared_hw_cfg shared_hw_config; /* 40 */
struct shared_hw_cfg shared_hw_config; /* 40 */
struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
struct shared_feat_cfg shared_feature_config; /* 4 */
struct shared_feat_cfg shared_feature_config; /* 4 */
struct port_feat_cfg port_feature_config[PORT_MAX]; /* 116*2=232 */
struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
};
......@@ -632,7 +639,9 @@ struct drv_port_mb {
#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
u32 reserved[3];
u32 port_stx;
u32 reserved[2];
};
......@@ -655,6 +664,11 @@ struct drv_func_mb {
#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
#define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
#define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
u32 drv_mb_param;
......@@ -684,6 +698,11 @@ struct drv_func_mb {
#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
#define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
#define FW_MSG_CODE_LIC_RESPONSE 0xff020000
#define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
#define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
u32 fw_mb_param;
......@@ -709,7 +728,13 @@ struct drv_func_mb {
u32 iscsi_boot_signature;
u32 iscsi_boot_block_offset;
u32 reserved[3];
u32 drv_status;
#define DRV_STATUS_PMF 0x00000001
u32 virt_mac_upper;
#define VIRT_MAC_SIGN_MASK 0xffff0000
#define VIRT_MAC_SIGNATURE 0x564d0000
u32 virt_mac_lower;
};
......@@ -725,6 +750,92 @@ struct mgmtfw_state {
};
/****************************************************************************
* Multi-Function configuration *
****************************************************************************/
struct shared_mf_cfg {
u32 clp_mb;
#define SHARED_MF_CLP_SET_DEFAULT 0x00000000
/* set by CLP */
#define SHARED_MF_CLP_EXIT 0x00000001
/* set by MCP */
#define SHARED_MF_CLP_EXIT_DONE 0x00010000
};
struct port_mf_cfg {
u32 dynamic_cfg; /* device control channel */
#define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
#define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
#define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
#define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
u32 reserved[3];
};
struct func_mf_cfg {
u32 config;
/* E/R/I/D */
/* function 0 of each port cannot be hidden */
#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
#define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
#define FUNC_MF_CFG_PROTOCOL_DEFAULT\
FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
#define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
/* PRI */
/* 0 - low priority, 3 - high priority */
#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
/* MINBW, MAXBW */
/* value range - 0..100, increments in 100Mbps */
#define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
#define FUNC_MF_CFG_MIN_BW_SHIFT 16
#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
#define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
#define FUNC_MF_CFG_MAX_BW_SHIFT 24
#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
u32 mac_upper; /* MAC */
#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
u32 mac_lower;
#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
u32 e1hov_tag; /* VNI */
#define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
#define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
u32 reserved[2];
};
struct mf_cfg {
struct shared_mf_cfg shared_mf_config;
struct port_mf_cfg port_mf_config[PORT_MAX];
#if defined(b710)
struct func_mf_cfg func_mf_config[E1_FUNC_MAX];
#else
struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
#endif
};
/****************************************************************************
* Shared Memory Region *
****************************************************************************/
......@@ -760,18 +871,18 @@ struct shmem_region { /* SharedMem Offset (size) */
struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
#if defined(b710)
struct drv_func_mb func_mb[E1_FUNC_MAX]; /* 0x684 (44*2=0x58) */
#else
struct drv_func_mb func_mb[E1H_FUNC_MAX];
#endif
struct mf_cfg mf_cfg;
}; /* 0x6dc */
#define BCM_5710_FW_MAJOR_VERSION 4
#define BCM_5710_FW_MINOR_VERSION 0
#define BCM_5710_FW_REVISION_VERSION 14
#define BCM_5710_FW_MINOR_VERSION 5
#define BCM_5710_FW_REVISION_VERSION 1
#define BCM_5710_FW_COMPILE_FLAGS 1
......@@ -810,7 +921,7 @@ struct doorbell_hdr {
};
/*
* doorbell message send to the chip
* doorbell message sent to the chip
*/
struct doorbell {
#if defined(__BIG_ENDIAN)
......@@ -866,8 +977,10 @@ struct parsing_flags {
u16 flags;
#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS (0x3<<1)
#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS_SHIFT 1
#define PARSING_FLAGS_VLAN (0x1<<1)
#define PARSING_FLAGS_VLAN_SHIFT 1
#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
......@@ -891,6 +1004,12 @@ struct parsing_flags {
};
struct regpair {
u32 lo;
u32 hi;
};
/*
* dmae command structure
*/
......@@ -971,72 +1090,107 @@ struct double_regpair {
/*
* The eth Rx Buffer Descriptor
* The eth storm context of Ustorm (configuration part)
*/
struct eth_rx_bd {
u32 addr_lo;
u32 addr_hi;
};
/*
* The eth storm context of Ustorm
*/
struct ustorm_eth_st_context {
struct ustorm_eth_st_context_config {
#if defined(__BIG_ENDIAN)
u8 sb_index_number;
u8 flags;
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
u8 status_block_id;
u8 __local_rx_bd_cons;
u8 __local_rx_bd_prod;
u8 clientId;
u8 sb_index_numbers;
#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
#elif defined(__LITTLE_ENDIAN)
u8 __local_rx_bd_prod;
u8 __local_rx_bd_cons;
u8 sb_index_numbers;
#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
u8 clientId;
u8 status_block_id;
u8 sb_index_number;
u8 flags;
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
#endif
#if defined(__BIG_ENDIAN)
u16 rcq_cons;
u16 rx_bd_cons;
u16 bd_buff_size;
u16 mc_alignment_size;
#elif defined(__LITTLE_ENDIAN)
u16 rx_bd_cons;
u16 rcq_cons;
u16 mc_alignment_size;
u16 bd_buff_size;
#endif
u32 rx_bd_page_base_lo;
u32 rx_bd_page_base_hi;
u32 rcq_base_address_lo;
u32 rcq_base_address_hi;
#if defined(__BIG_ENDIAN)
u16 __num_of_returned_cqes;
u8 num_rss;
u8 flags;
#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
u8 __local_sge_prod;
u8 __local_bd_prod;
u16 sge_buff_size;
#elif defined(__LITTLE_ENDIAN)
u8 flags;
#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
u8 num_rss;
u16 __num_of_returned_cqes;
u16 sge_buff_size;
u8 __local_bd_prod;
u8 __local_sge_prod;
#endif
#if defined(__BIG_ENDIAN)
u16 mc_alignment_size;
u16 agg_threshold;
u16 __bd_cons;
u16 __sge_cons;
#elif defined(__LITTLE_ENDIAN)
u16 agg_threshold;
u16 mc_alignment_size;
u16 __sge_cons;
u16 __bd_cons;
#endif
u32 bd_page_base_lo;
u32 bd_page_base_hi;
u32 sge_page_base_lo;
u32 sge_page_base_hi;
};
/*
* The eth Rx Buffer Descriptor
*/
struct eth_rx_bd {
u32 addr_lo;
u32 addr_hi;
};
/*
* The eth Rx SGE Descriptor
*/
struct eth_rx_sge {
u32 addr_lo;
u32 addr_hi;
};
/*
* Local BDs and SGEs rings (in ETH)
*/
struct eth_local_rx_rings {
struct eth_rx_bd __local_bd_ring[16];
struct eth_rx_sge __local_sge_ring[12];
};
/*
* The eth storm context of Ustorm
*/
struct ustorm_eth_st_context {
struct ustorm_eth_st_context_config common;
struct eth_local_rx_rings __rings;
};
/*
......@@ -1107,9 +1261,9 @@ struct xstorm_eth_extra_ag_context_section {
#if defined(__BIG_ENDIAN)
u16 __reserved3;
u8 __reserved2;
u8 __agg_misc7;
u8 __da_only_cnt;
#elif defined(__LITTLE_ENDIAN)
u8 __agg_misc7;
u8 __da_only_cnt;
u8 __reserved2;
u16 __reserved3;
#endif
......@@ -1387,7 +1541,13 @@ struct timers_block_context {
u32 __reserved_0;
u32 __reserved_1;
u32 __reserved_2;
u32 __reserved_flags;
u32 flags;
#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
};
/*
......@@ -1497,11 +1657,19 @@ struct xstorm_eth_st_context {
u32 tx_bd_page_base_hi;
#if defined(__BIG_ENDIAN)
u16 tx_bd_cons;
u8 __reserved0;
u8 statistics_data;
#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
u8 __local_tx_bd_prod;
#elif defined(__LITTLE_ENDIAN)
u8 __local_tx_bd_prod;
u8 __reserved0;
u8 statistics_data;
#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
u16 tx_bd_cons;
#endif
u32 db_data_addr_lo;
......@@ -1578,7 +1746,7 @@ struct eth_tx_doorbell {
struct ustorm_def_status_block {
u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
u16 status_block_index;
u8 reserved0;
u8 func;
u8 status_block_id;
u32 __flags;
};
......@@ -1589,7 +1757,7 @@ struct ustorm_def_status_block {
struct cstorm_def_status_block {
u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
u16 status_block_index;
u8 reserved0;
u8 func;
u8 status_block_id;
u32 __flags;
};
......@@ -1600,7 +1768,7 @@ struct cstorm_def_status_block {
struct xstorm_def_status_block {
u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
u16 status_block_index;
u8 reserved0;
u8 func;
u8 status_block_id;
u32 __flags;
};
......@@ -1611,7 +1779,7 @@ struct xstorm_def_status_block {
struct tstorm_def_status_block {
u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
u16 status_block_index;
u8 reserved0;
u8 func;
u8 status_block_id;
u32 __flags;
};
......@@ -1634,7 +1802,7 @@ struct host_def_status_block {
struct ustorm_status_block {
u16 index_values[HC_USTORM_SB_NUM_INDICES];
u16 status_block_index;
u8 reserved0;
u8 func;
u8 status_block_id;
u32 __flags;
};
......@@ -1645,7 +1813,7 @@ struct ustorm_status_block {
struct cstorm_status_block {
u16 index_values[HC_CSTORM_SB_NUM_INDICES];
u16 status_block_index;
u8 reserved0;
u8 func;
u8 status_block_id;
u32 __flags;
};
......@@ -1683,20 +1851,21 @@ struct eth_dynamic_hc_config {
* regular eth FP CQE parameters struct
*/
struct eth_fast_path_rx_cqe {
u8 type;
u8 error_type_flags;
#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0)
#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0
#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1)
#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1
#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2)
#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2
#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<3)
#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 3
#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<4)
#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 4
#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x7<<5)
#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 5
u8 type_error_flags;
#define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
u8 status_flags;
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
......@@ -1711,11 +1880,13 @@ struct eth_fast_path_rx_cqe {
#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
u8 placement_offset;
u8 queue_index;
u32 rss_hash_result;
u16 vlan_tag;
u16 pkt_len;
u16 queue_index;
u16 len_on_bd;
struct parsing_flags pars_flags;
u16 sgl[8];
};
......@@ -1728,6 +1899,23 @@ struct eth_halt_ramrod_data {
};
/*
* The data for statistics query ramrod
*/
struct eth_query_ramrod_data {
#if defined(__BIG_ENDIAN)
u8 reserved0;
u8 collect_port_1b;
u16 drv_counter;
#elif defined(__LITTLE_ENDIAN)
u16 drv_counter;
u8 collect_port_1b;
u8 reserved0;
#endif
u32 ctr_id_vector;
};
/*
* Place holder for ramrods protocol specific data
*/
......@@ -1758,15 +1946,20 @@ struct eth_rx_bd_next_page {
* Eth Rx Cqe structure- general structure for ramrods
*/
struct common_ramrod_eth_rx_cqe {
u8 type;
u8 ramrod_type;
#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
u8 conn_type_3b;
u16 reserved;
u16 reserved1;
u32 conn_and_cmd_data;
#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
struct ramrod_data protocol_data;
u32 reserved2[4];
};
/*
......@@ -1775,8 +1968,7 @@ struct common_ramrod_eth_rx_cqe {
struct eth_rx_cqe_next_page {
u32 addr_lo;
u32 addr_hi;
u32 reserved0;
u32 reserved1;
u32 reserved[6];
};
/*
......@@ -1806,11 +1998,6 @@ struct spe_hdr {
u16 reserved;
};
struct regpair {
u32 lo;
u32 hi;
};
/*
* ethernet slow path element
*/
......@@ -1821,6 +2008,7 @@ union eth_specific_data {
struct eth_halt_ramrod_data halt_ramrod_data;
struct regpair leading_cqe_addr;
struct regpair update_data_addr;
struct eth_query_ramrod_data query_ramrod_data;
};
/*
......@@ -1843,10 +2031,13 @@ struct eth_tx_db_data {
/*
* Common configuration parameters per port in Tstorm
* Common configuration parameters per function in Tstorm
*/
struct tstorm_eth_function_common_config {
u32 config_flags;
#if defined(__BIG_ENDIAN)
u8 leading_client_id;
u8 rss_result_mask;
u16 config_flags;
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
......@@ -1859,17 +2050,32 @@ struct tstorm_eth_function_common_config {
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3FFFFFF<<6)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 6
#if defined(__BIG_ENDIAN)
u16 __secondary_vlan_id;
u8 leading_client_id;
u8 rss_result_mask;
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
#elif defined(__LITTLE_ENDIAN)
u16 config_flags;
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
u8 rss_result_mask;
u8 leading_client_id;
u16 __secondary_vlan_id;
#endif
u16 vlan_id[2];
};
/*
......@@ -1887,7 +2093,7 @@ struct eth_update_ramrod_data {
struct mac_configuration_hdr {
u8 length_6b;
u8 offset;
u16 reserved0;
u16 client_id;
u32 reserved1;
};
......@@ -1943,16 +2149,56 @@ struct mac_configuration_cmd {
};
/*
* MAC address in list for ramrod
*/
struct mac_configuration_entry_e1h {
u16 lsb_mac_addr;
u16 middle_mac_addr;
u16 msb_mac_addr;
u16 vlan_id;
u16 e1hov_id;
u8 client_id;
u8 flags;
#define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
#define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
};
/*
* MAC filtering configuration command
*/
struct mac_configuration_cmd_e1h {
struct mac_configuration_hdr hdr;
struct mac_configuration_entry_e1h config_table[32];
};
/*
* approximate-match multicast filtering for E1H per function in Tstorm
*/
struct tstorm_eth_approximate_match_multicast_filtering {
u32 mcast_add_hash_bit_array[8];
};
/*
* Configuration parameters per client in Tstorm
*/
struct tstorm_eth_client_config {
#if defined(__BIG_ENDIAN)
u16 statistics_counter_id;
u8 max_sges_for_packet;
u8 statistics_counter_id;
u16 mtu;
#elif defined(__LITTLE_ENDIAN)
u16 mtu;
u16 statistics_counter_id;
u8 statistics_counter_id;
u8 max_sges_for_packet;
#endif
#if defined(__BIG_ENDIAN)
u16 drop_flags;
......@@ -1960,42 +2206,42 @@ struct tstorm_eth_client_config {
#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
u16 config_flags;
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
#elif defined(__LITTLE_ENDIAN)
u16 config_flags;
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
u16 drop_flags;
#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
#endif
};
......@@ -2011,96 +2257,112 @@ struct tstorm_eth_mac_filter_config {
u32 bcast_drop_all;
u32 bcast_accept_all;
u32 strict_vlan;
u32 __secondary_vlan_clients;
u32 vlan_filter[2];
u32 reserved;
};
struct rate_shaping_per_protocol {
/*
* Three RX producers for ETH
*/
struct tstorm_eth_rx_producers {
#if defined(__BIG_ENDIAN)
u16 reserved0;
u16 protocol_rate;
u16 bd_prod;
u16 cqe_prod;
#elif defined(__LITTLE_ENDIAN)
u16 protocol_rate;
u16 reserved0;
u16 cqe_prod;
u16 bd_prod;
#endif
u32 protocol_quota;
s32 current_credit;
u32 reserved;
};
struct rate_shaping_vars {
struct rate_shaping_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
u32 pause_mask;
u32 periodic_stop;
u32 rs_periodic_timeout;
u32 rs_threshold;
u32 last_periodic_time;
u32 reserved;
};
struct fairness_per_protocol {
u32 credit_delta;
s32 fair_credit;
#if defined(__BIG_ENDIAN)
u16 reserved0;
u8 state;
u8 weight;
u16 reserved;
u16 sge_prod;
#elif defined(__LITTLE_ENDIAN)
u8 weight;
u8 state;
u16 reserved0;
u16 sge_prod;
u16 reserved;
#endif
u32 reserved1;
};
struct fairness_vars {
struct fairness_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
u32 upper_bound;
u32 port_rate;
u32 pause_mask;
u32 fair_threshold;
};
struct safc_struct {
u32 cur_pause_mask;
u32 expire_time;
/*
* common flag to indicate existance of TPA.
*/
struct tstorm_eth_tpa_exist {
#if defined(__BIG_ENDIAN)
u16 reserved0;
u8 cur_cos_types;
u8 safc_timeout_usec;
u16 reserved1;
u8 reserved0;
u8 tpa_exist;
#elif defined(__LITTLE_ENDIAN)
u8 safc_timeout_usec;
u8 cur_cos_types;
u16 reserved0;
u8 tpa_exist;
u8 reserved0;
u16 reserved1;
#endif
u32 reserved1;
u32 reserved2;
};
struct demo_struct {
/*
* per-port SAFC demo variables
*/
struct cmng_flags_per_port {
u8 con_number[NUM_OF_PROTOCOLS];
#if defined(__BIG_ENDIAN)
u8 reserved1;
u8 fairness_enable;
u8 rate_shaping_enable;
u8 cmng_enable;
u8 cmng_protocol_enable;
u8 cmng_vn_enable;
#elif defined(__LITTLE_ENDIAN)
u8 cmng_enable;
u8 cmng_vn_enable;
u8 cmng_protocol_enable;
u8 rate_shaping_enable;
u8 fairness_enable;
u8 reserved1;
#endif
};
struct cmng_struct {
struct rate_shaping_vars rs_vars;
struct fairness_vars fair_vars;
struct safc_struct safc_vars;
struct demo_struct demo_vars;
/*
* per-port rate shaping variables
*/
struct rate_shaping_vars_per_port {
u32 rs_periodic_timeout;
u32 rs_threshold;
};
/*
* per-port fairness variables
*/
struct fairness_vars_per_port {
u32 upper_bound;
u32 fair_threshold;
u32 fairness_timeout;
};
/*
* per-port SAFC variables
*/
struct safc_struct_per_port {
#if defined(__BIG_ENDIAN)
u16 __reserved0;
u8 cur_cos_types;
u8 safc_timeout_usec;
#elif defined(__LITTLE_ENDIAN)
u8 safc_timeout_usec;
u8 cur_cos_types;
u16 __reserved0;
#endif
u8 cos_to_protocol[MAX_COS_NUMBER];
};
struct cos_to_protocol {
u8 mask[MAX_COS_NUMBER];
/*
* Per-port congestion management variables
*/
struct cmng_struct_per_port {
struct rate_shaping_vars_per_port rs_vars;
struct fairness_vars_per_port fair_vars;
struct safc_struct_per_port safc_vars;
struct cmng_flags_per_port flags;
};
......@@ -2161,6 +2423,16 @@ struct eth_stats_query {
};
/*
* per-vnic fairness variables
*/
struct fairness_vars_per_vn {
u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
u32 vn_credit_delta;
u32 __reserved0;
};
/*
* FW version stored in the Xstorm RAM
*/
......@@ -2179,8 +2451,10 @@ struct fw_version {
#define FW_VERSION_OPTIMIZED_SHIFT 0
#define FW_VERSION_BIG_ENDIEN (0x1<<1)
#define FW_VERSION_BIG_ENDIEN_SHIFT 1
#define __FW_VERSION_RESERVED (0x3FFFFFFF<<2)
#define __FW_VERSION_RESERVED_SHIFT 2
#define FW_VERSION_CHIP_VERSION (0x3<<2)
#define FW_VERSION_CHIP_VERSION_SHIFT 2
#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
#define __FW_VERSION_RESERVED_SHIFT 4
};
......@@ -2188,15 +2462,9 @@ struct fw_version {
* FW version stored in first line of pram
*/
struct pram_fw_version {
#if defined(__BIG_ENDIAN)
u16 patch;
u8 primary;
u8 client;
#elif defined(__LITTLE_ENDIAN)
u8 client;
u8 primary;
u16 patch;
#endif
u8 flags;
#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
......@@ -2204,8 +2472,34 @@ struct pram_fw_version {
#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
#define __PRAM_FW_VERSION_RESERVED0 (0xF<<4)
#define __PRAM_FW_VERSION_RESERVED0_SHIFT 4
#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
};
/*
* a single rate shaping counter. can be used as protocol or vnic counter
*/
struct rate_shaping_counter {
u32 quota;
#if defined(__BIG_ENDIAN)
u16 __reserved0;
u16 rate;
#elif defined(__LITTLE_ENDIAN)
u16 rate;
u16 __reserved0;
#endif
};
/*
* per-vnic rate shaping variables
*/
struct rate_shaping_vars_per_vn {
struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
struct rate_shaping_counter vn_counter;
};
......
drivers/net/bnx2x_init.h
View file @ 34f80b04
......@@ -226,28 +226,28 @@ static const u32 *bnx2x_sel_blob(u32 addr, const u32 *data, int is_e1)
tsem_int_table_data_e1h;
else
IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
data = is_e1 ? csem_int_table_data_e1 :
csem_int_table_data_e1h;
data = is_e1 ? csem_int_table_data_e1 :
csem_int_table_data_e1h;
else
IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
data = is_e1 ? usem_int_table_data_e1 :
usem_int_table_data_e1h;
data = is_e1 ? usem_int_table_data_e1 :
usem_int_table_data_e1h;
else
IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
data = is_e1 ? xsem_int_table_data_e1 :
xsem_int_table_data_e1h;
data = is_e1 ? xsem_int_table_data_e1 :
xsem_int_table_data_e1h;
else
IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
data = is_e1 ? tsem_pram_data_e1 : tsem_pram_data_e1h;
data = is_e1 ? tsem_pram_data_e1 : tsem_pram_data_e1h;
else
IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
data = is_e1 ? csem_pram_data_e1 : csem_pram_data_e1h;
data = is_e1 ? csem_pram_data_e1 : csem_pram_data_e1h;
else
IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
data = is_e1 ? usem_pram_data_e1 : usem_pram_data_e1h;
data = is_e1 ? usem_pram_data_e1 : usem_pram_data_e1h;
else
IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
data = is_e1 ? xsem_pram_data_e1 : xsem_pram_data_e1h;
data = is_e1 ? xsem_pram_data_e1 : xsem_pram_data_e1h;
return data;
}
......
drivers/net/bnx2x_link.c
View file @ 34f80b04
......@@ -3572,7 +3572,8 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
LED_BLINK_RATE_VAL);
REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
port*4, 1);
if (((speed == SPEED_2500) ||
if (!CHIP_IS_E1H(bp) &&
((speed == SPEED_2500) ||
(speed == SPEED_1000) ||
(speed == SPEED_100) ||
(speed == SPEED_10))) {
......@@ -3753,6 +3754,14 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
vars->duplex = DUPLEX_FULL;
vars->flow_ctrl = FLOW_CTRL_NONE;
vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
/* enable on E1.5 FPGA */
if (CHIP_IS_E1H(bp)) {
vars->flow_ctrl |=
(FLOW_CTRL_TX | FLOW_CTRL_RX);
vars->link_status |=
(LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
}
bnx2x_emac_enable(params, vars, 0);
bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
......
drivers/net/bnx2x_main.c
View file @ 34f80b04
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/net/bnx2x_reg.h
View file @ 34f80b04
......@@ -38,21 +38,19 @@
was asserted. */
#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
#define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0
#define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4
#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
asserted. */
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4
/* [RW 10] Write client 0: De-assert pause threshold. */
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
/* [RW 10] Write client 0: Assert pause threshold. */
#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
/* [R 24] The number of full blocks occpied by port. */
#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
/* [RW 1] Reset the design by software. */
#define BRB1_REG_SOFT_RESET 0x600dc
/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
......@@ -513,7 +511,6 @@
/* [RW 15] Interrupt table Read and write access to it is not possible in
the middle of the work */
#define CSEM_REG_INT_TABLE 0x200400
#define CSEM_REG_INT_TABLE_SIZE 256
/* [ST 24] Statistics register. The number of messages that entered through
FIC0 */
#define CSEM_REG_MSG_NUM_FIC0 0x200000
......@@ -587,13 +584,10 @@
#define DBG_REG_DBG_PRTY_MASK 0xc0a8
/* [R 1] Parity register #0 read */
#define DBG_REG_DBG_PRTY_STS 0xc09c
/* [RW 2] debug only: These bits indicate the credit for PCI request type 4
interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are
configured */
#define DBG_REG_PCI_REQ_CREDIT 0xc120
/* [RW 32] Commands memory. The address to command X; row Y is to calculated
as 14*X+Y. */
#define DMAE_REG_CMD_MEM 0x102400
#define DMAE_REG_CMD_MEM_SIZE 224
/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
initial value is all ones. */
#define DMAE_REG_CRC16C_INIT 0x10201c
......@@ -1626,7 +1620,7 @@
is reset to 0x080; giving a default blink period of approximately 8Hz. */
#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
/* [RW 1] Port0: If set along with the
nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
bit; the Traffic LED will blink with the blink rate specified in
~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
......@@ -1733,9 +1727,21 @@
/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
for port0 */
#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
between 1024 and 1522 bytes for port0 */
#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
between 1523 bytes and above for port0 */
#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
for port1 */
#define NIG_REG_STAT1_BRB_DISCARD 0x10628
/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
between 1024 and 1522 bytes for port1 */
#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
between 1523 bytes and above for port1 */
#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
/* [WB_R 64] Rx statistics : User octets received for LP */
#define NIG_REG_STAT2_BRB_OCTET 0x107e0
#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
......@@ -1849,7 +1855,6 @@
#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
/* [RW 24] CID for port 0 if no match */
#define PRS_REG_CID_PORT_0 0x400fc
#define PRS_REG_CID_PORT_1 0x40100
/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
load response is reset and packet type is 0. Used in packet start message
to TCM. */
......@@ -1957,6 +1962,10 @@
#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
/* [R 7] Debug only: Number of used entries in the header FIFO */
#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
#define PXP2_REG_PGL_ADDR_88_F0 0x120534
#define PXP2_REG_PGL_ADDR_8C_F0 0x120538
#define PXP2_REG_PGL_ADDR_90_F0 0x12053c
#define PXP2_REG_PGL_ADDR_94_F0 0x120540
#define PXP2_REG_PGL_CONTROL0 0x120490
#define PXP2_REG_PGL_CONTROL1 0x120514
/* [RW 32] third dword data of expansion rom request. this register is
......@@ -2060,12 +2069,13 @@
#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
/* [RW 25] Interrupt mask register #0 read/write */
#define PXP2_REG_PXP2_INT_MASK 0x120578
/* [R 25] Interrupt register #0 read */
#define PXP2_REG_PXP2_INT_STS 0x12056c
/* [RC 25] Interrupt register #0 read clear */
#define PXP2_REG_PXP2_INT_STS_CLR 0x120570
/* [RW 32] Interrupt mask register #0 read/write */
#define PXP2_REG_PXP2_INT_MASK_0 0x120578
/* [R 32] Interrupt register #0 read */
#define PXP2_REG_PXP2_INT_STS_0 0x12056c
#define PXP2_REG_PXP2_INT_STS_1 0x120608
/* [RC 32] Interrupt register #0 read clear */
#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
/* [RW 32] Parity mask register #0 read/write */
#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
......@@ -2811,22 +2821,6 @@
#define QM_REG_QVOQIDX_97 0x16e490
#define QM_REG_QVOQIDX_98 0x16e494
#define QM_REG_QVOQIDX_99 0x16e498
/* [R 24] Remaining pause timeout for queues 15-0 */
#define QM_REG_REMAINPAUSETM0 0x168418
/* [R 24] Remaining pause timeout for queues 31-16 */
#define QM_REG_REMAINPAUSETM1 0x16841c
/* [R 24] Remaining pause timeout for queues 47-32 */
#define QM_REG_REMAINPAUSETM2 0x16e69c
/* [R 24] Remaining pause timeout for queues 63-48 */
#define QM_REG_REMAINPAUSETM3 0x16e6a0
/* [R 24] Remaining pause timeout for queues 79-64 */
#define QM_REG_REMAINPAUSETM4 0x16e6a4
/* [R 24] Remaining pause timeout for queues 95-80 */
#define QM_REG_REMAINPAUSETM5 0x16e6a8
/* [R 24] Remaining pause timeout for queues 111-96 */
#define QM_REG_REMAINPAUSETM6 0x16e6ac
/* [R 24] Remaining pause timeout for queues 127-112 */
#define QM_REG_REMAINPAUSETM7 0x16e6b0
/* [RW 1] Initialization bit command */
#define QM_REG_SOFT_RESET 0x168428
/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
......@@ -3826,7 +3820,6 @@
/* [RW 15] Interrupt table Read and write access to it is not possible in
the middle of the work */
#define TSEM_REG_INT_TABLE 0x180400
#define TSEM_REG_INT_TABLE_SIZE 256
/* [ST 24] Statistics register. The number of messages that entered through
FIC0 */
#define TSEM_REG_MSG_NUM_FIC0 0x180000
......@@ -4283,7 +4276,6 @@
/* [RW 15] Interrupt table Read and write access to it is not possible in
the middle of the work */
#define USEM_REG_INT_TABLE 0x300400
#define USEM_REG_INT_TABLE_SIZE 256
/* [ST 24] Statistics register. The number of messages that entered through
FIC0 */
#define USEM_REG_MSG_NUM_FIC0 0x300000
......@@ -4802,7 +4794,6 @@
/* [RW 15] Interrupt table Read and write access to it is not possible in
the middle of the work */
#define XSEM_REG_INT_TABLE 0x280400
#define XSEM_REG_INT_TABLE_SIZE 256
/* [ST 24] Statistics register. The number of messages that entered through
FIC0 */
#define XSEM_REG_MSG_NUM_FIC0 0x280000
......@@ -4930,10 +4921,7 @@
#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
#define EMAC_MODE_25G_MODE (1L<<5)
#define EMAC_MODE_ACPI_RCVD (1L<<20)
#define EMAC_MODE_HALF_DUPLEX (1L<<1)
#define EMAC_MODE_MPKT (1L<<18)
#define EMAC_MODE_MPKT_RCVD (1L<<19)
#define EMAC_MODE_PORT_GMII (2L<<2)
#define EMAC_MODE_PORT_MII (1L<<2)
#define EMAC_MODE_PORT_MII_10M (3L<<2)
......
include/linux/pci_ids.h
View file @ 34f80b04
......@@ -1949,6 +1949,8 @@
#define PCI_DEVICE_ID_NX2_5708 0x164c
#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
#define PCI_DEVICE_ID_NX2_57710 0x164e
#define PCI_DEVICE_ID_NX2_57711 0x164f
#define PCI_DEVICE_ID_NX2_57711E 0x1650
#define PCI_DEVICE_ID_TIGON3_5705 0x1653
#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
#define PCI_DEVICE_ID_TIGON3_5720 0x1658
......
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