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Commit 3a86d7f6 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
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drm/amd/powerplay: update Arcturus default dpm table setting 

Preparing for coming code sharing around performance level
setting.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c1a9e61c
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Showing with 119 additions and 178 deletions
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
View file @ 3a86d7f6
......@@ -291,7 +291,6 @@ static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
return mapping.map_to;
}
static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
{
struct smu_11_0_cmn2aisc_mapping mapping;
......@@ -338,23 +337,11 @@ static int arcturus_allocate_dpm_context(struct smu_context *smu)
{
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
if (smu_dpm->dpm_context)
return -EINVAL;
smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
GFP_KERNEL);
if (!smu_dpm->dpm_context)
return -ENOMEM;
if (smu_dpm->golden_dpm_context)
return -EINVAL;
smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
GFP_KERNEL);
if (!smu_dpm->golden_dpm_context)
return -ENOMEM;
smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
GFP_KERNEL);
......@@ -382,119 +369,84 @@ arcturus_get_allowed_feature_mask(struct smu_context *smu,
return 0;
}
static int
arcturus_set_single_dpm_table(struct smu_context *smu,
struct arcturus_single_dpm_table *single_dpm_table,
PPCLK_e clk_id)
{
int ret = 0;
uint32_t i, num_of_levels = 0, clk;
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_GetDpmFreqByIndex,
(clk_id << 16 | 0xFF),
&num_of_levels);
if (ret) {
dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
return ret;
}
single_dpm_table->count = num_of_levels;
for (i = 0; i < num_of_levels; i++) {
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_GetDpmFreqByIndex,
(clk_id << 16 | i),
&clk);
if (ret) {
dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
return ret;
}
single_dpm_table->dpm_levels[i].value = clk;
single_dpm_table->dpm_levels[i].enabled = true;
}
return 0;
}
static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
{
dpm_state->soft_min_level = 0x0;
dpm_state->soft_max_level = 0xffff;
dpm_state->hard_min_level = 0x0;
dpm_state->hard_max_level = 0xffff;
}
static int arcturus_set_default_dpm_table(struct smu_context *smu)
{
int ret;
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
struct arcturus_dpm_table *dpm_table = NULL;
struct arcturus_single_dpm_table *single_dpm_table;
dpm_table = smu_dpm->dpm_context;
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
struct smu_11_0_dpm_table *dpm_table = NULL;
int ret = 0;
/* socclk */
single_dpm_table = &(dpm_table->soc_table);
/* socclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.soc_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
PPCLK_SOCCLK);
if (ret) {
dev_err(smu->adev->dev, "[%s] failed to get socclk dpm levels!\n", __func__);
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_SOCCLK,
dpm_table);
if (ret)
return ret;
}
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
} else {
single_dpm_table->count = 1;
single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
/* gfxclk */
single_dpm_table = &(dpm_table->gfx_table);
/* gfxclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.gfx_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
PPCLK_GFXCLK);
if (ret) {
dev_err(smu->adev->dev, "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_GFXCLK,
dpm_table);
if (ret)
return ret;
}
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
} else {
single_dpm_table->count = 1;
single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
/* memclk */
single_dpm_table = &(dpm_table->mem_table);
/* memclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.uclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
PPCLK_UCLK);
if (ret) {
dev_err(smu->adev->dev, "[SetupDefaultDpmTable] failed to get memclk dpm levels!");
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_UCLK,
dpm_table);
if (ret)
return ret;
}
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
} else {
single_dpm_table->count = 1;
single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
/* fclk */
single_dpm_table = &(dpm_table->fclk_table);
/* fclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.fclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
PPCLK_FCLK);
if (ret) {
dev_err(smu->adev->dev, "[SetupDefaultDpmTable] failed to get fclk dpm levels!");
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_FCLK,
dpm_table);
if (ret)
return ret;
}
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
} else {
single_dpm_table->count = 1;
single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
memcpy(smu_dpm->golden_dpm_context, dpm_table,
sizeof(struct arcturus_dpm_table));
return 0;
}
......@@ -622,7 +574,7 @@ static int arcturus_populate_umd_state_clk(struct smu_context *smu)
static int arcturus_get_clk_table(struct smu_context *smu,
struct pp_clock_levels_with_latency *clocks,
struct arcturus_single_dpm_table *dpm_table)
struct smu_11_0_dpm_table *dpm_table)
{
int i, count;
......@@ -824,14 +776,14 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
int i, now, size = 0;
int ret = 0;
struct pp_clock_levels_with_latency clocks;
struct arcturus_single_dpm_table *single_dpm_table;
struct smu_11_0_dpm_table *single_dpm_table;
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
struct arcturus_dpm_table *dpm_table = NULL;
struct smu_11_0_dpm_context *dpm_context = NULL;
if (amdgpu_ras_intr_triggered())
return snprintf(buf, PAGE_SIZE, "unavailable\n");
dpm_table = smu_dpm->dpm_context;
dpm_context = smu_dpm->dpm_context;
switch (type) {
case SMU_SCLK:
......@@ -841,7 +793,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
return ret;
}
single_dpm_table = &(dpm_table->gfx_table);
single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
if (ret) {
dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
......@@ -868,7 +820,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
return ret;
}
single_dpm_table = &(dpm_table->mem_table);
single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
if (ret) {
dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
......@@ -891,7 +843,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
return ret;
}
single_dpm_table = &(dpm_table->soc_table);
single_dpm_table = &(dpm_context->dpm_tables.soc_table);
ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
if (ret) {
dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
......@@ -914,7 +866,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
return ret;
}
single_dpm_table = &(dpm_table->fclk_table);
single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
if (ret) {
dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
......@@ -937,20 +889,19 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
return size;
}
static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
uint32_t feature_mask)
static int arcturus_upload_dpm_level(struct smu_context *smu,
bool max,
uint32_t feature_mask,
uint32_t level)
{
struct arcturus_single_dpm_table *single_dpm_table;
struct arcturus_dpm_table *dpm_table =
struct smu_11_0_dpm_context *dpm_context =
smu->smu_dpm.dpm_context;
uint32_t freq;
int ret = 0;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
(feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
single_dpm_table = &(dpm_table->gfx_table);
freq = max ? single_dpm_table->dpm_state.soft_max_level :
single_dpm_table->dpm_state.soft_min_level;
freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
ret = smu_send_smc_msg_with_param(smu,
(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
(PPCLK_GFXCLK << 16) | (freq & 0xffff),
......@@ -964,9 +915,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
(feature_mask & FEATURE_DPM_UCLK_MASK)) {
single_dpm_table = &(dpm_table->mem_table);
freq = max ? single_dpm_table->dpm_state.soft_max_level :
single_dpm_table->dpm_state.soft_min_level;
freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
ret = smu_send_smc_msg_with_param(smu,
(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
(PPCLK_UCLK << 16) | (freq & 0xffff),
......@@ -980,9 +929,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
(feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
single_dpm_table = &(dpm_table->soc_table);
freq = max ? single_dpm_table->dpm_state.soft_max_level :
single_dpm_table->dpm_state.soft_min_level;
freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
ret = smu_send_smc_msg_with_param(smu,
(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
(PPCLK_SOCCLK << 16) | (freq & 0xffff),
......@@ -1000,8 +947,8 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
static int arcturus_force_clk_levels(struct smu_context *smu,
enum smu_clk_type type, uint32_t mask)
{
struct arcturus_dpm_table *dpm_table;
struct arcturus_single_dpm_table *single_dpm_table;
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
struct smu_11_0_dpm_table *single_dpm_table = NULL;
uint32_t soft_min_level, soft_max_level;
uint32_t smu_version;
int ret = 0;
......@@ -1021,12 +968,9 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
dpm_table = smu->smu_dpm.dpm_context;
switch (type) {
case SMU_SCLK:
single_dpm_table = &(dpm_table->gfx_table);
single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
if (soft_max_level >= single_dpm_table->count) {
dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
soft_max_level, single_dpm_table->count - 1);
......@@ -1034,18 +978,19 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
break;
}
single_dpm_table->dpm_state.soft_min_level =
single_dpm_table->dpm_levels[soft_min_level].value;
single_dpm_table->dpm_state.soft_max_level =
single_dpm_table->dpm_levels[soft_max_level].value;
ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
ret = arcturus_upload_dpm_level(smu,
false,
FEATURE_DPM_GFXCLK_MASK,
soft_min_level);
if (ret) {
dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
break;
}
ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
ret = arcturus_upload_dpm_level(smu,
true,
FEATURE_DPM_GFXCLK_MASK,
soft_max_level);
if (ret)
dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
......@@ -1256,8 +1201,7 @@ static int arcturus_get_fan_speed_percent(struct smu_context *smu,
return ret;
}
static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
static uint32_t arcturus_find_lowest_dpm_level(struct smu_11_0_dpm_table *table)
{
uint32_t i;
......@@ -1274,7 +1218,7 @@ static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table
}
static uint32_t arcturus_find_highest_dpm_level(struct smu_context *smu,
struct arcturus_single_dpm_table *table)
struct smu_11_0_dpm_table *table)
{
int i = 0;
......@@ -1299,34 +1243,33 @@ static uint32_t arcturus_find_highest_dpm_level(struct smu_context *smu,
return i;
}
static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
{
struct arcturus_dpm_table *dpm_table =
(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
uint32_t soft_level;
int ret = 0;
/* gfxclk */
if (highest)
soft_level = arcturus_find_highest_dpm_level(smu, &(dpm_table->gfx_table));
soft_level = arcturus_find_highest_dpm_level(smu, &(dpm_context->dpm_tables.gfx_table));
else
soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
soft_level = arcturus_find_lowest_dpm_level(&(dpm_context->dpm_tables.gfx_table));
dpm_table->gfx_table.dpm_state.soft_min_level =
dpm_table->gfx_table.dpm_state.soft_max_level =
dpm_table->gfx_table.dpm_levels[soft_level].value;
ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
ret = arcturus_upload_dpm_level(smu,
false,
FEATURE_DPM_GFXCLK_MASK,
soft_level);
if (ret) {
dev_err(smu->adev->dev, "Failed to upload boot level to %s!\n",
highest ? "highest" : "lowest");
return ret;
}
ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
ret = arcturus_upload_dpm_level(smu,
true,
FEATURE_DPM_GFXCLK_MASK,
soft_level);
if (ret) {
dev_err(smu->adev->dev, "Failed to upload dpm max level to %s!\n!",
highest ? "highest" : "lowest");
......@@ -1345,27 +1288,29 @@ static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
static int arcturus_unforce_dpm_levels(struct smu_context *smu)
{
struct arcturus_dpm_table *dpm_table =
(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
struct smu_11_0_dpm_context *dpm_context =
(struct smu_11_0_dpm_context *)smu->smu_dpm.dpm_context;
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
uint32_t soft_min_level, soft_max_level;
int ret = 0;
/* gfxclk */
soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
soft_max_level = arcturus_find_highest_dpm_level(smu, &(dpm_table->gfx_table));
dpm_table->gfx_table.dpm_state.soft_min_level =
dpm_table->gfx_table.dpm_levels[soft_min_level].value;
dpm_table->gfx_table.dpm_state.soft_max_level =
dpm_table->gfx_table.dpm_levels[soft_max_level].value;
ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_context->dpm_tables.gfx_table));
soft_max_level = arcturus_find_highest_dpm_level(smu, &(dpm_context->dpm_tables.gfx_table));
ret = arcturus_upload_dpm_level(smu,
false,
FEATURE_DPM_GFXCLK_MASK,
soft_min_level);
if (ret) {
dev_err(smu->adev->dev, "Failed to upload DPM Bootup Levels!");
return ret;
}
ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
ret = arcturus_upload_dpm_level(smu,
true,
FEATURE_DPM_GFXCLK_MASK,
soft_max_level);
if (ret) {
dev_err(smu->adev->dev, "Failed to upload DPM Max Levels!");
return ret;
......@@ -1388,18 +1333,15 @@ arcturus_get_profiling_clk_mask(struct smu_context *smu,
uint32_t *mclk_mask,
uint32_t *soc_mask)
{
struct arcturus_dpm_table *dpm_table =
(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
struct arcturus_single_dpm_table *gfx_dpm_table;
struct arcturus_single_dpm_table *mem_dpm_table;
struct arcturus_single_dpm_table *soc_dpm_table;
struct smu_11_0_dpm_context *dpm_context =
(struct smu_11_0_dpm_context *)smu->smu_dpm.dpm_context;
struct smu_11_0_dpm_table *gfx_dpm_table;
struct smu_11_0_dpm_table *mem_dpm_table;
struct smu_11_0_dpm_table *soc_dpm_table;
if (!smu->smu_dpm.dpm_context)
return -EINVAL;
gfx_dpm_table = &dpm_table->gfx_table;
mem_dpm_table = &dpm_table->mem_table;
soc_dpm_table = &dpm_table->soc_table;
gfx_dpm_table = &dpm_context->dpm_tables.gfx_table;
mem_dpm_table = &dpm_context->dpm_tables.uclk_table;
soc_dpm_table = &dpm_context->dpm_tables.soc_table;
*sclk_mask = 0;
*mclk_mask = 0;
......@@ -2153,7 +2095,6 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
return ret;
}
static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t *req, bool write,
uint8_t address, uint32_t numbytes,
uint8_t *data)
......
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