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Commit 3afb244b authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
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drm/amd/powerplay: update Navi10 default dpm table setup 

Cache all clocks levels for every dpm table. They are needed
by other APIs.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3a86d7f6
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Showing with 158 additions and 24 deletions
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
View file @ 3afb244b
......@@ -689,41 +689,175 @@ static int navi10_allocate_dpm_context(struct smu_context *smu)
static int navi10_set_default_dpm_table(struct smu_context *smu)
{
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
struct smu_table_context *table_context = &smu->smu_table;
struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
PPTable_t *driver_ppt = NULL;
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
struct smu_11_0_dpm_table *dpm_table;
int ret = 0;
int i;
driver_ppt = table_context->driver_pptable;
dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
/* socclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.soc_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_SOCCLK,
dpm_table);
if (ret)
return ret;
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
} else {
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
/* gfxclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.gfx_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_GFXCLK,
dpm_table);
if (ret)
return ret;
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
} else {
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
/* uclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.uclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_UCLK,
dpm_table);
if (ret)
return ret;
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
} else {
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
/* vclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.vclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_VCLK,
dpm_table);
if (ret)
return ret;
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
} else {
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
/* dclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.dclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_DCLK,
dpm_table);
if (ret)
return ret;
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
} else {
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
/* dcefclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.dcef_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_DCEFCLK,
dpm_table);
if (ret)
return ret;
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
} else {
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
/* pixelclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.pixel_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_PIXCLK,
dpm_table);
if (ret)
return ret;
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
} else {
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
/* displayclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.display_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_DISPCLK,
dpm_table);
if (ret)
return ret;
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
} else {
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
/* phyclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.phy_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu,
SMU_PHYCLK,
dpm_table);
if (ret)
return ret;
dpm_table->is_fine_grained =
!driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
} else {
dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
dpm_table->dpm_levels[0].enabled = true;
dpm_table->min = dpm_table->dpm_levels[0].value;
dpm_table->max = dpm_table->dpm_levels[0].value;
}
/* lclk dpm table setup */
for (i = 0; i < MAX_PCIE_CONF; i++) {
dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
......
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