Commit 3b86616e authored by Paul Walmsley's avatar Paul Walmsley

Merge branch 'prcm-a-for-v4.3' into hwmod-prcm-for-v4.3

parents 9a0cb985 8740a144
...@@ -86,6 +86,7 @@ l4_wkup: l4_wkup@44c00000 { ...@@ -86,6 +86,7 @@ l4_wkup: l4_wkup@44c00000 {
prcm: prcm@1f0000 { prcm: prcm@1f0000 {
compatible = "ti,am4-prcm"; compatible = "ti,am4-prcm";
reg = <0x1f0000 0x11000>; reg = <0x1f0000 0x11000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prcm_clocks: clocks { prcm_clocks: clocks {
#address-cells = <1>; #address-cells = <1>;
......
...@@ -472,6 +472,7 @@ struct omap_prcm_irq { ...@@ -472,6 +472,7 @@ struct omap_prcm_irq {
* struct omap_prcm_irq_setup - PRCM interrupt controller details * struct omap_prcm_irq_setup - PRCM interrupt controller details
* @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
* @mask: PRM register offset for the first PRM_IRQENABLE_MPU register * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
* @pm_ctrl: PRM register offset for the PRM_IO_PMCTRL register
* @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
* @nr_irqs: number of entries in the @irqs array * @nr_irqs: number of entries in the @irqs array
* @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
...@@ -494,6 +495,7 @@ struct omap_prcm_irq { ...@@ -494,6 +495,7 @@ struct omap_prcm_irq {
struct omap_prcm_irq_setup { struct omap_prcm_irq_setup {
u16 ack; u16 ack;
u16 mask; u16 mask;
u16 pm_ctrl;
u8 nr_regs; u8 nr_regs;
u8 nr_irqs; u8 nr_irqs;
const struct omap_prcm_irq *irqs; const struct omap_prcm_irq *irqs;
......
...@@ -25,6 +25,13 @@ ...@@ -25,6 +25,13 @@
#define AM43XX_PRM_WKUP_INST 0x2000 #define AM43XX_PRM_WKUP_INST 0x2000
#define AM43XX_PRM_DEVICE_INST 0x4000 #define AM43XX_PRM_DEVICE_INST 0x4000
/* PRM_IRQ offsets */
#define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
#define AM43XX_PRM_IRQENABLE_MPU_OFFSET 0x0008
/* Other PRM offsets */
#define AM43XX_PRM_IO_PMCTRL_OFFSET 0x0024
/* RM RSTCTRL offsets */ /* RM RSTCTRL offsets */
#define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 #define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010
#define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 #define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010
......
...@@ -18,13 +18,14 @@ ...@@ -18,13 +18,14 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of_irq.h> #include <linux/of_irq.h>
#include <linux/of.h>
#include "soc.h" #include "soc.h"
#include "iomap.h" #include "iomap.h"
#include "common.h" #include "common.h"
#include "vp.h" #include "vp.h"
#include "prm44xx.h" #include "prm44xx.h"
#include "prcm43xx.h"
#include "prm-regbits-44xx.h" #include "prm-regbits-44xx.h"
#include "prcm44xx.h" #include "prcm44xx.h"
#include "prminst44xx.h" #include "prminst44xx.h"
...@@ -45,6 +46,7 @@ static const struct omap_prcm_irq omap4_prcm_irqs[] = { ...@@ -45,6 +46,7 @@ static const struct omap_prcm_irq omap4_prcm_irqs[] = {
static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
.ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
.mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET, .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
.pm_ctrl = OMAP4_PRM_IO_PMCTRL_OFFSET,
.nr_regs = 2, .nr_regs = 2,
.irqs = omap4_prcm_irqs, .irqs = omap4_prcm_irqs,
.nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
...@@ -216,11 +218,11 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs) ...@@ -216,11 +218,11 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
*/ */
static void omap44xx_prm_read_pending_irqs(unsigned long *events) static void omap44xx_prm_read_pending_irqs(unsigned long *events)
{ {
events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, int i;
OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET, for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); events[i] = _read_pending_irq_reg(omap4_prcm_irq_setup.mask +
i * 4, omap4_prcm_irq_setup.ack + i * 4);
} }
/** /**
...@@ -250,17 +252,17 @@ static void omap44xx_prm_ocp_barrier(void) ...@@ -250,17 +252,17 @@ static void omap44xx_prm_ocp_barrier(void)
*/ */
static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
{ {
saved_mask[0] = int i;
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, u16 reg;
OMAP4_PRM_IRQENABLE_MPU_OFFSET);
saved_mask[1] =
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) {
OMAP4_PRM_IRQENABLE_MPU_OFFSET); reg = omap4_prcm_irq_setup.mask + i * 4;
omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); saved_mask[i] =
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
reg);
omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, reg);
}
/* OCP barrier */ /* OCP barrier */
omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
...@@ -279,10 +281,12 @@ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) ...@@ -279,10 +281,12 @@ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
*/ */
static void omap44xx_prm_restore_irqen(u32 *saved_mask) static void omap44xx_prm_restore_irqen(u32 *saved_mask)
{ {
omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST, int i;
OMAP4_PRM_IRQENABLE_MPU_OFFSET);
omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST, for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); omap4_prm_write_inst_reg(saved_mask[i],
OMAP4430_PRM_OCP_SOCKET_INST,
omap4_prcm_irq_setup.mask + i * 4);
} }
/** /**
...@@ -306,10 +310,10 @@ static void omap44xx_prm_reconfigure_io_chain(void) ...@@ -306,10 +310,10 @@ static void omap44xx_prm_reconfigure_io_chain(void)
omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
OMAP4430_WUCLK_CTRL_MASK, OMAP4430_WUCLK_CTRL_MASK,
inst, inst,
OMAP4_PRM_IO_PMCTRL_OFFSET); omap4_prcm_irq_setup.pm_ctrl);
omap_test_timeout( omap_test_timeout(
(((omap4_prm_read_inst_reg(inst, (((omap4_prm_read_inst_reg(inst,
OMAP4_PRM_IO_PMCTRL_OFFSET) & omap4_prcm_irq_setup.pm_ctrl) &
OMAP4430_WUCLK_STATUS_MASK) >> OMAP4430_WUCLK_STATUS_MASK) >>
OMAP4430_WUCLK_STATUS_SHIFT) == 1), OMAP4430_WUCLK_STATUS_SHIFT) == 1),
MAX_IOPAD_LATCH_TIME, i); MAX_IOPAD_LATCH_TIME, i);
...@@ -319,10 +323,10 @@ static void omap44xx_prm_reconfigure_io_chain(void) ...@@ -319,10 +323,10 @@ static void omap44xx_prm_reconfigure_io_chain(void)
/* Trigger WUCLKIN disable */ /* Trigger WUCLKIN disable */
omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0, omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
inst, inst,
OMAP4_PRM_IO_PMCTRL_OFFSET); omap4_prcm_irq_setup.pm_ctrl);
omap_test_timeout( omap_test_timeout(
(((omap4_prm_read_inst_reg(inst, (((omap4_prm_read_inst_reg(inst,
OMAP4_PRM_IO_PMCTRL_OFFSET) & omap4_prcm_irq_setup.pm_ctrl) &
OMAP4430_WUCLK_STATUS_MASK) >> OMAP4430_WUCLK_STATUS_MASK) >>
OMAP4430_WUCLK_STATUS_SHIFT) == 0), OMAP4430_WUCLK_STATUS_SHIFT) == 0),
MAX_IOPAD_LATCH_TIME, i); MAX_IOPAD_LATCH_TIME, i);
...@@ -350,7 +354,7 @@ static void __init omap44xx_prm_enable_io_wakeup(void) ...@@ -350,7 +354,7 @@ static void __init omap44xx_prm_enable_io_wakeup(void)
omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_GLOBAL_WUEN_MASK,
inst, inst,
OMAP4_PRM_IO_PMCTRL_OFFSET); omap4_prcm_irq_setup.pm_ctrl);
} }
/** /**
...@@ -719,6 +723,15 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data) ...@@ -719,6 +723,15 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
omap4_prminst_set_prm_dev_inst(data->device_inst_offset); omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
/* Add AM437X specific differences */
if (of_device_is_compatible(data->np, "ti,am4-prcm")) {
omap4_prcm_irq_setup.nr_irqs = 1;
omap4_prcm_irq_setup.nr_regs = 1;
omap4_prcm_irq_setup.pm_ctrl = AM43XX_PRM_IO_PMCTRL_OFFSET;
omap4_prcm_irq_setup.ack = AM43XX_PRM_IRQSTATUS_MPU_OFFSET;
omap4_prcm_irq_setup.mask = AM43XX_PRM_IRQENABLE_MPU_OFFSET;
}
return prm_register(&omap44xx_prm_ll_data); return prm_register(&omap44xx_prm_ll_data);
} }
......
...@@ -696,6 +696,7 @@ static struct omap_prcm_init_data am4_prm_data __initdata = { ...@@ -696,6 +696,7 @@ static struct omap_prcm_init_data am4_prm_data __initdata = {
.index = TI_CLKM_PRM, .index = TI_CLKM_PRM,
.init = omap44xx_prm_init, .init = omap44xx_prm_init,
.device_inst_offset = AM43XX_PRM_DEVICE_INST, .device_inst_offset = AM43XX_PRM_DEVICE_INST,
.flags = PRM_HAS_IO_WAKEUP,
}; };
#endif #endif
......
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