Commit 3d6271f9 authored by Kyle Manna's avatar Kyle Manna Committed by Samuel Ortiz

mfd: Turn on the twl4030-madc MADC clock

Without turning the MADC clock on, no MADC conversions occur.

$ cat /sys/class/hwmon/hwmon0/device/in8_input
[   53.428436] twl4030_madc twl4030_madc: conversion timeout!
cat: read error: Resource temporarily unavailable
Signed-off-by: default avatarKyle Manna <kyle@kylemanna.com>
Signed-off-by: default avatarSamuel Ortiz <sameo@linux.intel.com>
parent 881de670
...@@ -740,6 +740,28 @@ static int __devinit twl4030_madc_probe(struct platform_device *pdev) ...@@ -740,6 +740,28 @@ static int __devinit twl4030_madc_probe(struct platform_device *pdev)
TWL4030_BCI_BCICTL1); TWL4030_BCI_BCICTL1);
goto err_i2c; goto err_i2c;
} }
/* Check that MADC clock is on */
ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &regval, TWL4030_REG_GPBR1);
if (ret) {
dev_err(&pdev->dev, "unable to read reg GPBR1 0x%X\n",
TWL4030_REG_GPBR1);
goto err_i2c;
}
/* If MADC clk is not on, turn it on */
if (!(regval & TWL4030_GPBR1_MADC_HFCLK_EN)) {
dev_info(&pdev->dev, "clk disabled, enabling\n");
regval |= TWL4030_GPBR1_MADC_HFCLK_EN;
ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, regval,
TWL4030_REG_GPBR1);
if (ret) {
dev_err(&pdev->dev, "unable to write reg GPBR1 0x%X\n",
TWL4030_REG_GPBR1);
goto err_i2c;
}
}
platform_set_drvdata(pdev, madc); platform_set_drvdata(pdev, madc);
mutex_init(&madc->lock); mutex_init(&madc->lock);
ret = request_threaded_irq(platform_get_irq(pdev, 0), NULL, ret = request_threaded_irq(platform_get_irq(pdev, 0), NULL,
......
...@@ -129,6 +129,10 @@ enum sample_type { ...@@ -129,6 +129,10 @@ enum sample_type {
#define REG_BCICTL2 0x024 #define REG_BCICTL2 0x024
#define TWL4030_BCI_ITHSENS 0x007 #define TWL4030_BCI_ITHSENS 0x007
/* Register and bits for GPBR1 register */
#define TWL4030_REG_GPBR1 0x0c
#define TWL4030_GPBR1_MADC_HFCLK_EN (1 << 7)
struct twl4030_madc_user_parms { struct twl4030_madc_user_parms {
int channel; int channel;
int average; int average;
......
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