Commit 3e32011d authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by David S. Miller

[SUNGEM]: Updates from PowerPC people.

Support more chips and split out all the complex PHY
handling into a seperate file.
parent a7a905fa
......@@ -24,7 +24,7 @@ obj-$(CONFIG_SUNLANCE) += sunlance.o
obj-$(CONFIG_SUNQE) += sunqe.o
obj-$(CONFIG_SUNBMAC) += sunbmac.o
obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
obj-$(CONFIG_SUNGEM) += sungem.o
obj-$(CONFIG_SUNGEM) += sungem.o sungem_phy.o
obj-$(CONFIG_MACE) += mace.o
obj-$(CONFIG_BMAC) += bmac.o
......
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/* $Id: sungem.h,v 1.12 2002/01/23 15:40:45 davem Exp $
/* $Id: sungem.h,v 1.10.2.4 2002/03/11 08:54:48 davem Exp $
* sungem.h: Definitions for Sun GEM ethernet driver.
*
* Copyright (C) 2000 David S. Miller (davem@redhat.com)
......@@ -936,16 +936,6 @@ enum gem_phy_type {
phy_serdes,
};
enum gem_phy_model {
phymod_generic,
phymod_bcm5201,
phymod_bcm5221,
phymod_bcm5400,
phymod_bcm5401,
phymod_bcm5411,
phymod_m1011,
};
enum link_state {
link_down = 0, /* No link, will retry */
link_aneg, /* Autoneg in progress */
......@@ -980,21 +970,20 @@ struct gem {
struct net_device_stats net_stats;
enum gem_phy_type phy_type;
enum gem_phy_model phy_mod;
struct mii_phy phy_mii;
int tx_fifo_sz;
int rx_fifo_sz;
int rx_pause_off;
int rx_pause_on;
int mii_phy_addr;
int gigabit_capable;
u32 mac_rx_cfg;
u32 swrst_base;
/* Autoneg & PHY control */
int link_cntl;
int link_advertise;
int link_fcntl;
int want_autoneg;
int last_forced_speed;
enum link_state lstate;
struct timer_list link_timer;
int timer_ticks;
......@@ -1014,6 +1003,9 @@ struct gem {
#endif
};
#define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) \
&& gp->phy_mii.def && gp->phy_mii.def->ops)
#define ALIGNED_RX_SKB_ADDR(addr) \
((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
static __inline__ struct sk_buff *gem_alloc_skb(int size, int gfp_flags)
......
This diff is collapsed.
#ifndef __SUNGEM_PHY_H__
#define __SUNGEM_PHY_H__
struct mii_phy;
/* Operations supported by any kind of PHY */
struct mii_phy_ops
{
int (*init)(struct mii_phy *phy);
int (*suspend)(struct mii_phy *phy, int wol_options);
int (*setup_aneg)(struct mii_phy *phy, u32 advertise);
int (*setup_forced)(struct mii_phy *phy, int speed, int fd);
int (*poll_link)(struct mii_phy *phy);
int (*read_link)(struct mii_phy *phy);
};
/* Structure used to statically define an mii/gii based PHY */
struct mii_phy_def
{
u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
u32 phy_id_mask; /* Significant bits */
u32 features; /* Ethtool SUPPORTED_* defines */
int magic_aneg; /* Autoneg does all speed test for us */
const char* name;
const struct mii_phy_ops* ops;
};
/* An instance of a PHY, partially borrowed from mii_if_info */
struct mii_phy
{
struct mii_phy_def* def;
int advertising;
int mii_id;
/* 1: autoneg enabled, 0: disabled */
int autoneg;
/* forced speed & duplex (no autoneg)
* partner speed & duplex & pause (autoneg)
*/
int speed;
int duplex;
int pause;
/* Provided by host chip */
struct net_device* dev;
int (*mdio_read) (struct net_device *dev, int mii_id, int reg);
void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val);
};
/* Pass in a struct mii_phy with dev, mdio_read and mdio_write
* filled, the remaining fields will be filled on return
*/
extern int mii_phy_probe(struct mii_phy *phy, int mii_id);
/* MII definitions missing from mii.h */
#define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */
#define LPA_PAUSE 0x0400
/* More PHY registers (model specific) */
/* MII BCM5201 MULTIPHY interrupt register */
#define MII_BCM5201_INTERRUPT 0x1A
#define MII_BCM5201_INTERRUPT_INTENABLE 0x4000
#define MII_BCM5201_AUXMODE2 0x1B
#define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008
#define MII_BCM5201_MULTIPHY 0x1E
/* MII BCM5201 MULTIPHY register bits */
#define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
#define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
/* MII BCM5221 Additional registers */
#define MII_BCM5221_TEST 0x1f
#define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080
#define MII_BCM5221_SHDOW_AUX_STAT2 0x1b
#define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020
#define MII_BCM5221_SHDOW_AUX_MODE4 0x1a
#define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004
/* MII BCM5400 1000-BASET Control register */
#define MII_BCM5400_GB_CONTROL 0x09
#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200
/* MII BCM5400 AUXCONTROL register */
#define MII_BCM5400_AUXCONTROL 0x18
#define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004
/* MII BCM5400 AUXSTATUS register */
#define MII_BCM5400_AUXSTATUS 0x19
#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700
#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8
/* 1000BT control (Marvell & BCM54xx at least) */
#define MII_1000BASETCONTROL 0x09
#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
/* Marvell 88E1011 PHY control */
#define MII_M1011_PHY_SPEC_CONTROL 0x10
#define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20
#define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40
/* Marvell 88E1011 PHY status */
#define MII_M1011_PHY_SPEC_STATUS 0x11
#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
#endif /* __SUNGEM_PHY_H__ */
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