Commit 40c68f20 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by John W. Linville

b43; N-PHY: write most of the missing code for revs 7+

Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 303415e2
...@@ -4360,7 +4360,7 @@ static int b43_phy_versioning(struct b43_wldev *dev) ...@@ -4360,7 +4360,7 @@ static int b43_phy_versioning(struct b43_wldev *dev)
#endif #endif
#ifdef CONFIG_B43_PHY_N #ifdef CONFIG_B43_PHY_N
case B43_PHYTYPE_N: case B43_PHYTYPE_N:
if (phy_rev > 9) if (phy_rev >= 19)
unsupported = 1; unsupported = 1;
break; break;
#endif #endif
......
This diff is collapsed.
...@@ -857,6 +857,15 @@ ...@@ -857,6 +857,15 @@
#define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF) #define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF)
#define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0) #define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0)
#define B43_NPHY_REV7_RF_CTL_MISC_REG3 B43_PHY_N(0x340)
#define B43_NPHY_REV7_RF_CTL_MISC_REG4 B43_PHY_N(0x341)
#define B43_NPHY_REV7_RF_CTL_OVER3 B43_PHY_N(0x342)
#define B43_NPHY_REV7_RF_CTL_OVER4 B43_PHY_N(0x343)
#define B43_NPHY_REV7_RF_CTL_MISC_REG5 B43_PHY_N(0x344)
#define B43_NPHY_REV7_RF_CTL_MISC_REG6 B43_PHY_N(0x345)
#define B43_NPHY_REV7_RF_CTL_OVER5 B43_PHY_N(0x346)
#define B43_NPHY_REV7_RF_CTL_OVER6 B43_PHY_N(0x347)
#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */ #define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */
#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A) #define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A)
...@@ -935,6 +944,8 @@ struct b43_phy_n { ...@@ -935,6 +944,8 @@ struct b43_phy_n {
bool gain_boost; bool gain_boost;
bool elna_gain_config; bool elna_gain_config;
bool band5g_pwrgain; bool band5g_pwrgain;
bool use_int_tx_iq_lo_cal;
bool lpf_bw_overrode_for_sample_play;
u8 mphase_cal_phase_id; u8 mphase_cal_phase_id;
u16 mphase_txcal_cmdidx; u16 mphase_txcal_cmdidx;
......
...@@ -84,6 +84,8 @@ ...@@ -84,6 +84,8 @@
#define R2057_CMOSBUF_RX_RCCR 0x04c #define R2057_CMOSBUF_RX_RCCR 0x04c
#define R2057_LOGEN_SEL_PKDET 0x04d #define R2057_LOGEN_SEL_PKDET 0x04d
#define R2057_CMOSBUF_SHAREIQ_PTAT 0x04e #define R2057_CMOSBUF_SHAREIQ_PTAT 0x04e
/* MISC core 0 */
#define R2057_RXTXBIAS_CONFIG_CORE0 0x04f #define R2057_RXTXBIAS_CONFIG_CORE0 0x04f
#define R2057_TXGM_TXRF_PUS_CORE0 0x050 #define R2057_TXGM_TXRF_PUS_CORE0 0x050
#define R2057_TXGM_IDAC_BLEED_CORE0 0x051 #define R2057_TXGM_IDAC_BLEED_CORE0 0x051
...@@ -204,6 +206,8 @@ ...@@ -204,6 +206,8 @@
#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0x0d1 #define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0x0d1
#define R2057_LPF_GAIN_CORE0 0x0d2 #define R2057_LPF_GAIN_CORE0 0x0d2
#define R2057_DACBUF_IDACS_BW_CORE0 0x0d3 #define R2057_DACBUF_IDACS_BW_CORE0 0x0d3
/* MISC core 1 */
#define R2057_RXTXBIAS_CONFIG_CORE1 0x0d4 #define R2057_RXTXBIAS_CONFIG_CORE1 0x0d4
#define R2057_TXGM_TXRF_PUS_CORE1 0x0d5 #define R2057_TXGM_TXRF_PUS_CORE1 0x0d5
#define R2057_TXGM_IDAC_BLEED_CORE1 0x0d6 #define R2057_TXGM_IDAC_BLEED_CORE1 0x0d6
...@@ -324,6 +328,7 @@ ...@@ -324,6 +328,7 @@
#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156 #define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156
#define R2057_LPF_GAIN_CORE1 0x157 #define R2057_LPF_GAIN_CORE1 0x157
#define R2057_DACBUF_IDACS_BW_CORE1 0x158 #define R2057_DACBUF_IDACS_BW_CORE1 0x158
#define R2057_DACBUF_VINCM_CORE1 0x159 #define R2057_DACBUF_VINCM_CORE1 0x159
#define R2057_RCCAL_START_R1_Q1_P1 0x15a #define R2057_RCCAL_START_R1_Q1_P1 0x15a
#define R2057_RCCAL_X1 0x15b #define R2057_RCCAL_X1 0x15b
...@@ -345,6 +350,8 @@ ...@@ -345,6 +350,8 @@
#define R2057_RCCAL_BCAP_VAL 0x16b #define R2057_RCCAL_BCAP_VAL 0x16b
#define R2057_RCCAL_HPC_VAL 0x16c #define R2057_RCCAL_HPC_VAL 0x16c
#define R2057_RCCAL_OVERRIDES 0x16d #define R2057_RCCAL_OVERRIDES 0x16d
/* TX core 0 */
#define R2057_TX0_IQCAL_GAIN_BW 0x170 #define R2057_TX0_IQCAL_GAIN_BW 0x170
#define R2057_TX0_LOFT_FINE_I 0x171 #define R2057_TX0_LOFT_FINE_I 0x171
#define R2057_TX0_LOFT_FINE_Q 0x172 #define R2057_TX0_LOFT_FINE_Q 0x172
...@@ -362,6 +369,8 @@ ...@@ -362,6 +369,8 @@
#define R2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e #define R2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e
#define R2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f #define R2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f
#define R2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180 #define R2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180
/* TX core 1 */
#define R2057_TX1_IQCAL_GAIN_BW 0x190 #define R2057_TX1_IQCAL_GAIN_BW 0x190
#define R2057_TX1_LOFT_FINE_I 0x191 #define R2057_TX1_LOFT_FINE_I 0x191
#define R2057_TX1_LOFT_FINE_Q 0x192 #define R2057_TX1_LOFT_FINE_Q 0x192
...@@ -379,6 +388,7 @@ ...@@ -379,6 +388,7 @@
#define R2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e #define R2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e
#define R2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f #define R2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f
#define R2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0 #define R2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0
#define R2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1 #define R2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1
#define R2057_AFE_SET_VCM_I_CORE0 0x1a2 #define R2057_AFE_SET_VCM_I_CORE0 0x1a2
#define R2057_AFE_SET_VCM_Q_CORE0 0x1a3 #define R2057_AFE_SET_VCM_Q_CORE0 0x1a3
......
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