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Commit 43cc6725 authored by Jes Sorensen's avatar Jes Sorensen Committed by Tony Luck
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[IA64-SGI] cleanup shubio.h 

This patch cleans up include/asm/sn/shubio.h by removing a ton of
whitespaces and running it through Lindent, reducing it's size by almost
30KB. No actual content has been changed.
Signed-off-by: default avatarJes Sorensen <jes@wildopensource.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
parent 6adc4cc0
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Showing with 1499 additions and 1617 deletions
include/asm-ia64/sn/shubio.h
View file @ 43cc6725
......@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
* Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_SHUBIO_H
......@@ -65,7 +65,6 @@
#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */
#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */
#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */
#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */
......@@ -216,7 +215,6 @@
#define IIO_IPCR 0x00430000 /* IO Performance Control */
#define IIO_IPPR 0x00430008 /* IO Performance Profiling */
/************************************************************************
* *
* Description: This register echoes some information from the *
......@@ -231,15 +229,14 @@
typedef union ii_wid_u {
uint64_t ii_wid_regval;
struct {
uint64_t w_rsvd_1 : 1;
uint64_t w_mfg_num : 11;
uint64_t w_part_num : 16;
uint64_t w_rev_num : 4;
uint64_t w_rsvd : 32;
uint64_t w_rsvd_1:1;
uint64_t w_mfg_num:11;
uint64_t w_part_num:16;
uint64_t w_rev_num:4;
uint64_t w_rsvd:32;
} ii_wid_fld_s;
} ii_wid_u_t;
/************************************************************************
* *
* The fields in this register are set upon detection of an error *
......@@ -251,20 +248,19 @@ typedef union ii_wid_u {
typedef union ii_wstat_u {
uint64_t ii_wstat_regval;
struct {
uint64_t w_pending : 4;
uint64_t w_xt_crd_to : 1;
uint64_t w_xt_tail_to : 1;
uint64_t w_rsvd_3 : 3;
uint64_t w_tx_mx_rty : 1;
uint64_t w_rsvd_2 : 6;
uint64_t w_llp_tx_cnt : 8;
uint64_t w_rsvd_1 : 8;
uint64_t w_crazy : 1;
uint64_t w_rsvd : 31;
uint64_t w_pending:4;
uint64_t w_xt_crd_to:1;
uint64_t w_xt_tail_to:1;
uint64_t w_rsvd_3:3;
uint64_t w_tx_mx_rty:1;
uint64_t w_rsvd_2:6;
uint64_t w_llp_tx_cnt:8;
uint64_t w_rsvd_1:8;
uint64_t w_crazy:1;
uint64_t w_rsvd:31;
} ii_wstat_fld_s;
} ii_wstat_u_t;
/************************************************************************
* *
* Description: This is a read-write enabled register. It controls *
......@@ -275,18 +271,17 @@ typedef union ii_wstat_u {
typedef union ii_wcr_u {
uint64_t ii_wcr_regval;
struct {
uint64_t w_wid : 4;
uint64_t w_tag : 1;
uint64_t w_rsvd_1 : 8;
uint64_t w_dst_crd : 3;
uint64_t w_f_bad_pkt : 1;
uint64_t w_dir_con : 1;
uint64_t w_e_thresh : 5;
uint64_t w_rsvd : 41;
uint64_t w_wid:4;
uint64_t w_tag:1;
uint64_t w_rsvd_1:8;
uint64_t w_dst_crd:3;
uint64_t w_f_bad_pkt:1;
uint64_t w_dir_con:1;
uint64_t w_e_thresh:5;
uint64_t w_rsvd:41;
} ii_wcr_fld_s;
} ii_wcr_u_t;
/************************************************************************
* *
* Description: This register's value is a bit vector that guards *
......@@ -317,13 +312,10 @@ typedef union ii_wcr_u {
typedef union ii_ilapr_u {
uint64_t ii_ilapr_regval;
struct {
uint64_t i_region : 64;
uint64_t i_region:64;
} ii_ilapr_fld_s;
} ii_ilapr_u_t;
/************************************************************************
* *
* Description: A write to this register of the 64-bit value *
......@@ -340,12 +332,10 @@ typedef union ii_ilapr_u {
typedef union ii_ilapo_u {
uint64_t ii_ilapo_regval;
struct {
uint64_t i_io_ovrride : 64;
uint64_t i_io_ovrride:64;
} ii_ilapo_fld_s;
} ii_ilapo_u_t;
/************************************************************************
* *
* This register qualifies all the PIO and Graphics writes launched *
......@@ -356,14 +346,13 @@ typedef union ii_ilapo_u {
typedef union ii_iowa_u {
uint64_t ii_iowa_regval;
struct {
uint64_t i_w0_oac : 1;
uint64_t i_rsvd_1 : 7;
uint64_t i_wx_oac : 8;
uint64_t i_rsvd : 48;
uint64_t i_w0_oac:1;
uint64_t i_rsvd_1:7;
uint64_t i_wx_oac:8;
uint64_t i_rsvd:48;
} ii_iowa_fld_s;
} ii_iowa_u_t;
/************************************************************************
* *
* Description: This register qualifies all the requests launched *
......@@ -376,15 +365,13 @@ typedef union ii_iowa_u {
typedef union ii_iiwa_u {
uint64_t ii_iiwa_regval;
struct {
uint64_t i_w0_iac : 1;
uint64_t i_rsvd_1 : 7;
uint64_t i_wx_iac : 8;
uint64_t i_rsvd : 48;
uint64_t i_w0_iac:1;
uint64_t i_rsvd_1:7;
uint64_t i_wx_iac:8;
uint64_t i_rsvd:48;
} ii_iiwa_fld_s;
} ii_iiwa_u_t;
/************************************************************************
* *
* Description: This register qualifies all the operations launched *
......@@ -407,18 +394,17 @@ typedef union ii_iiwa_u {
typedef union ii_iidem_u {
uint64_t ii_iidem_regval;
struct {
uint64_t i_w8_dxs : 8;
uint64_t i_w9_dxs : 8;
uint64_t i_wa_dxs : 8;
uint64_t i_wb_dxs : 8;
uint64_t i_wc_dxs : 8;
uint64_t i_wd_dxs : 8;
uint64_t i_we_dxs : 8;
uint64_t i_wf_dxs : 8;
uint64_t i_w8_dxs:8;
uint64_t i_w9_dxs:8;
uint64_t i_wa_dxs:8;
uint64_t i_wb_dxs:8;
uint64_t i_wc_dxs:8;
uint64_t i_wd_dxs:8;
uint64_t i_we_dxs:8;
uint64_t i_wf_dxs:8;
} ii_iidem_fld_s;
} ii_iidem_u_t;
/************************************************************************
* *
* This register contains the various programmable fields necessary *
......@@ -429,25 +415,24 @@ typedef union ii_iidem_u {
typedef union ii_ilcsr_u {
uint64_t ii_ilcsr_regval;
struct {
uint64_t i_nullto : 6;
uint64_t i_rsvd_4 : 2;
uint64_t i_wrmrst : 1;
uint64_t i_rsvd_3 : 1;
uint64_t i_llp_en : 1;
uint64_t i_bm8 : 1;
uint64_t i_llp_stat : 2;
uint64_t i_remote_power : 1;
uint64_t i_rsvd_2 : 1;
uint64_t i_maxrtry : 10;
uint64_t i_d_avail_sel : 2;
uint64_t i_rsvd_1 : 4;
uint64_t i_maxbrst : 10;
uint64_t i_rsvd : 22;
uint64_t i_nullto:6;
uint64_t i_rsvd_4:2;
uint64_t i_wrmrst:1;
uint64_t i_rsvd_3:1;
uint64_t i_llp_en:1;
uint64_t i_bm8:1;
uint64_t i_llp_stat:2;
uint64_t i_remote_power:1;
uint64_t i_rsvd_2:1;
uint64_t i_maxrtry:10;
uint64_t i_d_avail_sel:2;
uint64_t i_rsvd_1:4;
uint64_t i_maxbrst:10;
uint64_t i_rsvd:22;
} ii_ilcsr_fld_s;
} ii_ilcsr_u_t;
/************************************************************************
* *
* This is simply a status registers that monitors the LLP error *
......@@ -458,13 +443,12 @@ typedef union ii_ilcsr_u {
typedef union ii_illr_u {
uint64_t ii_illr_regval;
struct {
uint64_t i_sn_cnt : 16;
uint64_t i_cb_cnt : 16;
uint64_t i_rsvd : 32;
uint64_t i_sn_cnt:16;
uint64_t i_cb_cnt:16;
uint64_t i_rsvd:32;
} ii_illr_fld_s;
} ii_illr_u_t;
/************************************************************************
* *
* Description: All II-detected non-BTE error interrupts are *
......@@ -482,22 +466,20 @@ typedef union ii_illr_u {
typedef union ii_iidsr_u {
uint64_t ii_iidsr_regval;
struct {
uint64_t i_level : 8;
uint64_t i_pi_id : 1;
uint64_t i_node : 11;
uint64_t i_rsvd_3 : 4;
uint64_t i_enable : 1;
uint64_t i_rsvd_2 : 3;
uint64_t i_int_sent : 2;
uint64_t i_rsvd_1 : 2;
uint64_t i_pi0_forward_int : 1;
uint64_t i_pi1_forward_int : 1;
uint64_t i_rsvd : 30;
uint64_t i_level:8;
uint64_t i_pi_id:1;
uint64_t i_node:11;
uint64_t i_rsvd_3:4;
uint64_t i_enable:1;
uint64_t i_rsvd_2:3;
uint64_t i_int_sent:2;
uint64_t i_rsvd_1:2;
uint64_t i_pi0_forward_int:1;
uint64_t i_pi1_forward_int:1;
uint64_t i_rsvd:30;
} ii_iidsr_fld_s;
} ii_iidsr_u_t;
/************************************************************************
* *
* There are two instances of this register. This register is used *
......@@ -512,15 +494,14 @@ typedef union ii_iidsr_u {
typedef union ii_igfx0_u {
uint64_t ii_igfx0_regval;
struct {
uint64_t i_w_num : 4;
uint64_t i_pi_id : 1;
uint64_t i_n_num : 12;
uint64_t i_p_num : 1;
uint64_t i_rsvd : 46;
uint64_t i_w_num:4;
uint64_t i_pi_id:1;
uint64_t i_n_num:12;
uint64_t i_p_num:1;
uint64_t i_rsvd:46;
} ii_igfx0_fld_s;
} ii_igfx0_u_t;
/************************************************************************
* *
* There are two instances of this register. This register is used *
......@@ -535,15 +516,14 @@ typedef union ii_igfx0_u {
typedef union ii_igfx1_u {
uint64_t ii_igfx1_regval;
struct {
uint64_t i_w_num : 4;
uint64_t i_pi_id : 1;
uint64_t i_n_num : 12;
uint64_t i_p_num : 1;
uint64_t i_rsvd : 46;
uint64_t i_w_num:4;
uint64_t i_pi_id:1;
uint64_t i_n_num:12;
uint64_t i_p_num:1;
uint64_t i_rsvd:46;
} ii_igfx1_fld_s;
} ii_igfx1_u_t;
/************************************************************************
* *
* There are two instances of this registers. These registers are *
......@@ -554,12 +534,10 @@ typedef union ii_igfx1_u {
typedef union ii_iscr0_u {
uint64_t ii_iscr0_regval;
struct {
uint64_t i_scratch : 64;
uint64_t i_scratch:64;
} ii_iscr0_fld_s;
} ii_iscr0_u_t;
/************************************************************************
* *
* There are two instances of this registers. These registers are *
......@@ -570,11 +548,10 @@ typedef union ii_iscr0_u {
typedef union ii_iscr1_u {
uint64_t ii_iscr1_regval;
struct {
uint64_t i_scratch : 64;
uint64_t i_scratch:64;
} ii_iscr1_fld_s;
} ii_iscr1_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
......@@ -605,15 +582,14 @@ typedef union ii_iscr1_u {
typedef union ii_itte1_u {
uint64_t ii_itte1_regval;
struct {
uint64_t i_offset : 5;
uint64_t i_rsvd_1 : 3;
uint64_t i_w_num : 4;
uint64_t i_iosp : 1;
uint64_t i_rsvd : 51;
uint64_t i_offset:5;
uint64_t i_rsvd_1:3;
uint64_t i_w_num:4;
uint64_t i_iosp:1;
uint64_t i_rsvd:51;
} ii_itte1_fld_s;
} ii_itte1_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
......@@ -644,15 +620,14 @@ typedef union ii_itte1_u {
typedef union ii_itte2_u {
uint64_t ii_itte2_regval;
struct {
uint64_t i_offset : 5;
uint64_t i_rsvd_1 : 3;
uint64_t i_w_num : 4;
uint64_t i_iosp : 1;
uint64_t i_rsvd : 51;
uint64_t i_offset:5;
uint64_t i_rsvd_1:3;
uint64_t i_w_num:4;
uint64_t i_iosp:1;
uint64_t i_rsvd:51;
} ii_itte2_fld_s;
} ii_itte2_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
......@@ -683,15 +658,14 @@ typedef union ii_itte2_u {
typedef union ii_itte3_u {
uint64_t ii_itte3_regval;
struct {
uint64_t i_offset : 5;
uint64_t i_rsvd_1 : 3;
uint64_t i_w_num : 4;
uint64_t i_iosp : 1;
uint64_t i_rsvd : 51;
uint64_t i_offset:5;
uint64_t i_rsvd_1:3;
uint64_t i_w_num:4;
uint64_t i_iosp:1;
uint64_t i_rsvd:51;
} ii_itte3_fld_s;
} ii_itte3_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
......@@ -722,15 +696,14 @@ typedef union ii_itte3_u {
typedef union ii_itte4_u {
uint64_t ii_itte4_regval;
struct {
uint64_t i_offset : 5;
uint64_t i_rsvd_1 : 3;
uint64_t i_w_num : 4;
uint64_t i_iosp : 1;
uint64_t i_rsvd : 51;
uint64_t i_offset:5;
uint64_t i_rsvd_1:3;
uint64_t i_w_num:4;
uint64_t i_iosp:1;
uint64_t i_rsvd:51;
} ii_itte4_fld_s;
} ii_itte4_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
......@@ -761,15 +734,14 @@ typedef union ii_itte4_u {
typedef union ii_itte5_u {
uint64_t ii_itte5_regval;
struct {
uint64_t i_offset : 5;
uint64_t i_rsvd_1 : 3;
uint64_t i_w_num : 4;
uint64_t i_iosp : 1;
uint64_t i_rsvd : 51;
uint64_t i_offset:5;
uint64_t i_rsvd_1:3;
uint64_t i_w_num:4;
uint64_t i_iosp:1;
uint64_t i_rsvd:51;
} ii_itte5_fld_s;
} ii_itte5_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
......@@ -800,15 +772,14 @@ typedef union ii_itte5_u {
typedef union ii_itte6_u {
uint64_t ii_itte6_regval;
struct {
uint64_t i_offset : 5;
uint64_t i_rsvd_1 : 3;
uint64_t i_w_num : 4;
uint64_t i_iosp : 1;
uint64_t i_rsvd : 51;
uint64_t i_offset:5;
uint64_t i_rsvd_1:3;
uint64_t i_w_num:4;
uint64_t i_iosp:1;
uint64_t i_rsvd:51;
} ii_itte6_fld_s;
} ii_itte6_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
......@@ -839,15 +810,14 @@ typedef union ii_itte6_u {
typedef union ii_itte7_u {
uint64_t ii_itte7_regval;
struct {
uint64_t i_offset : 5;
uint64_t i_rsvd_1 : 3;
uint64_t i_w_num : 4;
uint64_t i_iosp : 1;
uint64_t i_rsvd : 51;
uint64_t i_offset:5;
uint64_t i_rsvd_1:3;
uint64_t i_w_num:4;
uint64_t i_iosp:1;
uint64_t i_rsvd:51;
} ii_itte7_fld_s;
} ii_itte7_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
......@@ -875,24 +845,23 @@ typedef union ii_itte7_u {
typedef union ii_iprb0_u {
uint64_t ii_iprb0_regval;
struct {
uint64_t i_c : 8;
uint64_t i_na : 14;
uint64_t i_rsvd_2 : 2;
uint64_t i_nb : 14;
uint64_t i_rsvd_1 : 2;
uint64_t i_m : 2;
uint64_t i_f : 1;
uint64_t i_of_cnt : 5;
uint64_t i_error : 1;
uint64_t i_rd_to : 1;
uint64_t i_spur_wr : 1;
uint64_t i_spur_rd : 1;
uint64_t i_rsvd : 11;
uint64_t i_mult_err : 1;
uint64_t i_c:8;
uint64_t i_na:14;
uint64_t i_rsvd_2:2;
uint64_t i_nb:14;
uint64_t i_rsvd_1:2;
uint64_t i_m:2;
uint64_t i_f:1;
uint64_t i_of_cnt:5;
uint64_t i_error:1;
uint64_t i_rd_to:1;
uint64_t i_spur_wr:1;
uint64_t i_spur_rd:1;
uint64_t i_rsvd:11;
uint64_t i_mult_err:1;
} ii_iprb0_fld_s;
} ii_iprb0_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
......@@ -920,24 +889,23 @@ typedef union ii_iprb0_u {
typedef union ii_iprb8_u {
uint64_t ii_iprb8_regval;
struct {
uint64_t i_c : 8;
uint64_t i_na : 14;
uint64_t i_rsvd_2 : 2;
uint64_t i_nb : 14;
uint64_t i_rsvd_1 : 2;
uint64_t i_m : 2;
uint64_t i_f : 1;
uint64_t i_of_cnt : 5;
uint64_t i_error : 1;
uint64_t i_rd_to : 1;
uint64_t i_spur_wr : 1;
uint64_t i_spur_rd : 1;
uint64_t i_rsvd : 11;
uint64_t i_mult_err : 1;
uint64_t i_c:8;
uint64_t i_na:14;
uint64_t i_rsvd_2:2;
uint64_t i_nb:14;
uint64_t i_rsvd_1:2;
uint64_t i_m:2;
uint64_t i_f:1;
uint64_t i_of_cnt:5;
uint64_t i_error:1;
uint64_t i_rd_to:1;
uint64_t i_spur_wr:1;
uint64_t i_spur_rd:1;
uint64_t i_rsvd:11;
uint64_t i_mult_err:1;
} ii_iprb8_fld_s;
} ii_iprb8_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
......@@ -965,24 +933,23 @@ typedef union ii_iprb8_u {
typedef union ii_iprb9_u {
uint64_t ii_iprb9_regval;
struct {
uint64_t i_c : 8;
uint64_t i_na : 14;
uint64_t i_rsvd_2 : 2;
uint64_t i_nb : 14;
uint64_t i_rsvd_1 : 2;
uint64_t i_m : 2;
uint64_t i_f : 1;
uint64_t i_of_cnt : 5;
uint64_t i_error : 1;
uint64_t i_rd_to : 1;
uint64_t i_spur_wr : 1;
uint64_t i_spur_rd : 1;
uint64_t i_rsvd : 11;
uint64_t i_mult_err : 1;
uint64_t i_c:8;
uint64_t i_na:14;
uint64_t i_rsvd_2:2;
uint64_t i_nb:14;
uint64_t i_rsvd_1:2;
uint64_t i_m:2;
uint64_t i_f:1;
uint64_t i_of_cnt:5;
uint64_t i_error:1;
uint64_t i_rd_to:1;
uint64_t i_spur_wr:1;
uint64_t i_spur_rd:1;
uint64_t i_rsvd:11;
uint64_t i_mult_err:1;
} ii_iprb9_fld_s;
} ii_iprb9_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
......@@ -1010,24 +977,23 @@ typedef union ii_iprb9_u {
typedef union ii_iprba_u {
uint64_t ii_iprba_regval;
struct {
uint64_t i_c : 8;
uint64_t i_na : 14;
uint64_t i_rsvd_2 : 2;
uint64_t i_nb : 14;
uint64_t i_rsvd_1 : 2;
uint64_t i_m : 2;
uint64_t i_f : 1;
uint64_t i_of_cnt : 5;
uint64_t i_error : 1;
uint64_t i_rd_to : 1;
uint64_t i_spur_wr : 1;
uint64_t i_spur_rd : 1;
uint64_t i_rsvd : 11;
uint64_t i_mult_err : 1;
uint64_t i_c:8;
uint64_t i_na:14;
uint64_t i_rsvd_2:2;
uint64_t i_nb:14;
uint64_t i_rsvd_1:2;
uint64_t i_m:2;
uint64_t i_f:1;
uint64_t i_of_cnt:5;
uint64_t i_error:1;
uint64_t i_rd_to:1;
uint64_t i_spur_wr:1;
uint64_t i_spur_rd:1;
uint64_t i_rsvd:11;
uint64_t i_mult_err:1;
} ii_iprba_fld_s;
} ii_iprba_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
......@@ -1055,24 +1021,23 @@ typedef union ii_iprba_u {
typedef union ii_iprbb_u {
uint64_t ii_iprbb_regval;
struct {
uint64_t i_c : 8;
uint64_t i_na : 14;
uint64_t i_rsvd_2 : 2;
uint64_t i_nb : 14;
uint64_t i_rsvd_1 : 2;
uint64_t i_m : 2;
uint64_t i_f : 1;
uint64_t i_of_cnt : 5;
uint64_t i_error : 1;
uint64_t i_rd_to : 1;
uint64_t i_spur_wr : 1;
uint64_t i_spur_rd : 1;
uint64_t i_rsvd : 11;
uint64_t i_mult_err : 1;
uint64_t i_c:8;
uint64_t i_na:14;
uint64_t i_rsvd_2:2;
uint64_t i_nb:14;
uint64_t i_rsvd_1:2;
uint64_t i_m:2;
uint64_t i_f:1;
uint64_t i_of_cnt:5;
uint64_t i_error:1;
uint64_t i_rd_to:1;
uint64_t i_spur_wr:1;
uint64_t i_spur_rd:1;
uint64_t i_rsvd:11;
uint64_t i_mult_err:1;
} ii_iprbb_fld_s;
} ii_iprbb_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
......@@ -1100,24 +1065,23 @@ typedef union ii_iprbb_u {
typedef union ii_iprbc_u {
uint64_t ii_iprbc_regval;
struct {
uint64_t i_c : 8;
uint64_t i_na : 14;
uint64_t i_rsvd_2 : 2;
uint64_t i_nb : 14;
uint64_t i_rsvd_1 : 2;
uint64_t i_m : 2;
uint64_t i_f : 1;
uint64_t i_of_cnt : 5;
uint64_t i_error : 1;
uint64_t i_rd_to : 1;
uint64_t i_spur_wr : 1;
uint64_t i_spur_rd : 1;
uint64_t i_rsvd : 11;
uint64_t i_mult_err : 1;
uint64_t i_c:8;
uint64_t i_na:14;
uint64_t i_rsvd_2:2;
uint64_t i_nb:14;
uint64_t i_rsvd_1:2;
uint64_t i_m:2;
uint64_t i_f:1;
uint64_t i_of_cnt:5;
uint64_t i_error:1;
uint64_t i_rd_to:1;
uint64_t i_spur_wr:1;
uint64_t i_spur_rd:1;
uint64_t i_rsvd:11;
uint64_t i_mult_err:1;
} ii_iprbc_fld_s;
} ii_iprbc_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
......@@ -1145,24 +1109,23 @@ typedef union ii_iprbc_u {
typedef union ii_iprbd_u {
uint64_t ii_iprbd_regval;
struct {
uint64_t i_c : 8;
uint64_t i_na : 14;
uint64_t i_rsvd_2 : 2;
uint64_t i_nb : 14;
uint64_t i_rsvd_1 : 2;
uint64_t i_m : 2;
uint64_t i_f : 1;
uint64_t i_of_cnt : 5;
uint64_t i_error : 1;
uint64_t i_rd_to : 1;
uint64_t i_spur_wr : 1;
uint64_t i_spur_rd : 1;
uint64_t i_rsvd : 11;
uint64_t i_mult_err : 1;
uint64_t i_c:8;
uint64_t i_na:14;
uint64_t i_rsvd_2:2;
uint64_t i_nb:14;
uint64_t i_rsvd_1:2;
uint64_t i_m:2;
uint64_t i_f:1;
uint64_t i_of_cnt:5;
uint64_t i_error:1;
uint64_t i_rd_to:1;
uint64_t i_spur_wr:1;
uint64_t i_spur_rd:1;
uint64_t i_rsvd:11;
uint64_t i_mult_err:1;
} ii_iprbd_fld_s;
} ii_iprbd_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
......@@ -1190,24 +1153,23 @@ typedef union ii_iprbd_u {
typedef union ii_iprbe_u {
uint64_t ii_iprbe_regval;
struct {
uint64_t i_c : 8;
uint64_t i_na : 14;
uint64_t i_rsvd_2 : 2;
uint64_t i_nb : 14;
uint64_t i_rsvd_1 : 2;
uint64_t i_m : 2;
uint64_t i_f : 1;
uint64_t i_of_cnt : 5;
uint64_t i_error : 1;
uint64_t i_rd_to : 1;
uint64_t i_spur_wr : 1;
uint64_t i_spur_rd : 1;
uint64_t i_rsvd : 11;
uint64_t i_mult_err : 1;
uint64_t i_c:8;
uint64_t i_na:14;
uint64_t i_rsvd_2:2;
uint64_t i_nb:14;
uint64_t i_rsvd_1:2;
uint64_t i_m:2;
uint64_t i_f:1;
uint64_t i_of_cnt:5;
uint64_t i_error:1;
uint64_t i_rd_to:1;
uint64_t i_spur_wr:1;
uint64_t i_spur_rd:1;
uint64_t i_rsvd:11;
uint64_t i_mult_err:1;
} ii_iprbe_fld_s;
} ii_iprbe_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
......@@ -1235,24 +1197,23 @@ typedef union ii_iprbe_u {
typedef union ii_iprbf_u {
uint64_t ii_iprbf_regval;
struct {
uint64_t i_c : 8;
uint64_t i_na : 14;
uint64_t i_rsvd_2 : 2;
uint64_t i_nb : 14;
uint64_t i_rsvd_1 : 2;
uint64_t i_m : 2;
uint64_t i_f : 1;
uint64_t i_of_cnt : 5;
uint64_t i_error : 1;
uint64_t i_rd_to : 1;
uint64_t i_spur_wr : 1;
uint64_t i_spur_rd : 1;
uint64_t i_rsvd : 11;
uint64_t i_mult_err : 1;
uint64_t i_c:8;
uint64_t i_na:14;
uint64_t i_rsvd_2:2;
uint64_t i_nb:14;
uint64_t i_rsvd_1:2;
uint64_t i_m:2;
uint64_t i_f:1;
uint64_t i_of_cnt:5;
uint64_t i_error:1;
uint64_t i_rd_to:1;
uint64_t i_spur_wr:1;
uint64_t i_spur_rd:1;
uint64_t i_rsvd:11;
uint64_t i_mult_err:1;
} ii_iprbe_fld_s;
} ii_iprbf_u_t;
/************************************************************************
* *
* This register specifies the timeout value to use for monitoring *
......@@ -1273,12 +1234,11 @@ typedef union ii_iprbf_u {
typedef union ii_ixcc_u {
uint64_t ii_ixcc_regval;
struct {
uint64_t i_time_out : 26;
uint64_t i_rsvd : 38;
uint64_t i_time_out:26;
uint64_t i_rsvd:38;
} ii_ixcc_fld_s;
} ii_ixcc_u_t;
/************************************************************************
* *
* Description: This register qualifies all the PIO and DMA *
......@@ -1298,19 +1258,17 @@ typedef union ii_ixcc_u {
typedef union ii_imem_u {
uint64_t ii_imem_regval;
struct {
uint64_t i_w0_esd : 1;
uint64_t i_rsvd_3 : 3;
uint64_t i_b0_esd : 1;
uint64_t i_rsvd_2 : 3;
uint64_t i_b1_esd : 1;
uint64_t i_rsvd_1 : 3;
uint64_t i_clr_precise : 1;
uint64_t i_rsvd : 51;
uint64_t i_w0_esd:1;
uint64_t i_rsvd_3:3;
uint64_t i_b0_esd:1;
uint64_t i_rsvd_2:3;
uint64_t i_b1_esd:1;
uint64_t i_rsvd_1:3;
uint64_t i_clr_precise:1;
uint64_t i_rsvd:51;
} ii_imem_fld_s;
} ii_imem_u_t;
/************************************************************************
* *
* Description: This register specifies the timeout value to use for *
......@@ -1338,15 +1296,14 @@ typedef union ii_imem_u {
typedef union ii_ixtt_u {
uint64_t ii_ixtt_regval;
struct {
uint64_t i_tail_to : 26;
uint64_t i_rsvd_1 : 6;
uint64_t i_rrsp_ps : 23;
uint64_t i_rrsp_to : 5;
uint64_t i_rsvd : 4;
uint64_t i_tail_to:26;
uint64_t i_rsvd_1:6;
uint64_t i_rrsp_ps:23;
uint64_t i_rrsp_to:5;
uint64_t i_rsvd:4;
} ii_ixtt_fld_s;
} ii_ixtt_u_t;
/************************************************************************
* *
* Writing a 1 to the fields of this register clears the appropriate *
......@@ -1361,39 +1318,38 @@ typedef union ii_ixtt_u {
typedef union ii_ieclr_u {
uint64_t ii_ieclr_regval;
struct {
uint64_t i_e_prb_0 : 1;
uint64_t i_rsvd : 7;
uint64_t i_e_prb_8 : 1;
uint64_t i_e_prb_9 : 1;
uint64_t i_e_prb_a : 1;
uint64_t i_e_prb_b : 1;
uint64_t i_e_prb_c : 1;
uint64_t i_e_prb_d : 1;
uint64_t i_e_prb_e : 1;
uint64_t i_e_prb_f : 1;
uint64_t i_e_crazy : 1;
uint64_t i_e_bte_0 : 1;
uint64_t i_e_bte_1 : 1;
uint64_t i_reserved_1 : 10;
uint64_t i_spur_rd_hdr : 1;
uint64_t i_cam_intr_to : 1;
uint64_t i_cam_overflow : 1;
uint64_t i_cam_read_miss : 1;
uint64_t i_ioq_rep_underflow : 1;
uint64_t i_ioq_req_underflow : 1;
uint64_t i_ioq_rep_overflow : 1;
uint64_t i_ioq_req_overflow : 1;
uint64_t i_iiq_rep_overflow : 1;
uint64_t i_iiq_req_overflow : 1;
uint64_t i_ii_xn_rep_cred_overflow : 1;
uint64_t i_ii_xn_req_cred_overflow : 1;
uint64_t i_ii_xn_invalid_cmd : 1;
uint64_t i_xn_ii_invalid_cmd : 1;
uint64_t i_reserved_2 : 21;
uint64_t i_e_prb_0:1;
uint64_t i_rsvd:7;
uint64_t i_e_prb_8:1;
uint64_t i_e_prb_9:1;
uint64_t i_e_prb_a:1;
uint64_t i_e_prb_b:1;
uint64_t i_e_prb_c:1;
uint64_t i_e_prb_d:1;
uint64_t i_e_prb_e:1;
uint64_t i_e_prb_f:1;
uint64_t i_e_crazy:1;
uint64_t i_e_bte_0:1;
uint64_t i_e_bte_1:1;
uint64_t i_reserved_1:10;
uint64_t i_spur_rd_hdr:1;
uint64_t i_cam_intr_to:1;
uint64_t i_cam_overflow:1;
uint64_t i_cam_read_miss:1;
uint64_t i_ioq_rep_underflow:1;
uint64_t i_ioq_req_underflow:1;
uint64_t i_ioq_rep_overflow:1;
uint64_t i_ioq_req_overflow:1;
uint64_t i_iiq_rep_overflow:1;
uint64_t i_iiq_req_overflow:1;
uint64_t i_ii_xn_rep_cred_overflow:1;
uint64_t i_ii_xn_req_cred_overflow:1;
uint64_t i_ii_xn_invalid_cmd:1;
uint64_t i_xn_ii_invalid_cmd:1;
uint64_t i_reserved_2:21;
} ii_ieclr_fld_s;
} ii_ieclr_u_t;
/************************************************************************
* *
* This register controls both BTEs. SOFT_RESET is intended for *
......@@ -1406,14 +1362,13 @@ typedef union ii_ieclr_u {
typedef union ii_ibcr_u {
uint64_t ii_ibcr_regval;
struct {
uint64_t i_count : 4;
uint64_t i_rsvd_1 : 4;
uint64_t i_soft_reset : 1;
uint64_t i_rsvd : 55;
uint64_t i_count:4;
uint64_t i_rsvd_1:4;
uint64_t i_soft_reset:1;
uint64_t i_rsvd:55;
} ii_ibcr_fld_s;
} ii_ibcr_u_t;
/************************************************************************
* *
* This register contains the header of a spurious read response *
......@@ -1446,24 +1401,23 @@ typedef union ii_ibcr_u {
typedef union ii_ixsm_u {
uint64_t ii_ixsm_regval;
struct {
uint64_t i_byte_en : 32;
uint64_t i_reserved : 1;
uint64_t i_tag : 3;
uint64_t i_alt_pactyp : 4;
uint64_t i_bo : 1;
uint64_t i_error : 1;
uint64_t i_vbpm : 1;
uint64_t i_gbr : 1;
uint64_t i_ds : 2;
uint64_t i_ct : 1;
uint64_t i_tnum : 5;
uint64_t i_pactyp : 4;
uint64_t i_sidn : 4;
uint64_t i_didn : 4;
uint64_t i_byte_en:32;
uint64_t i_reserved:1;
uint64_t i_tag:3;
uint64_t i_alt_pactyp:4;
uint64_t i_bo:1;
uint64_t i_error:1;
uint64_t i_vbpm:1;
uint64_t i_gbr:1;
uint64_t i_ds:2;
uint64_t i_ct:1;
uint64_t i_tnum:5;
uint64_t i_pactyp:4;
uint64_t i_sidn:4;
uint64_t i_didn:4;
} ii_ixsm_fld_s;
} ii_ixsm_u_t;
/************************************************************************
* *
* This register contains the sideband bits of a spurious read *
......@@ -1474,13 +1428,12 @@ typedef union ii_ixsm_u {
typedef union ii_ixss_u {
uint64_t ii_ixss_regval;
struct {
uint64_t i_sideband : 8;
uint64_t i_rsvd : 55;
uint64_t i_valid : 1;
uint64_t i_sideband:8;
uint64_t i_rsvd:55;
uint64_t i_valid:1;
} ii_ixss_fld_s;
} ii_ixss_u_t;
/************************************************************************
* *
* This register enables software to access the II LLP's test port. *
......@@ -1496,19 +1449,18 @@ typedef union ii_ixss_u {
typedef union ii_ilct_u {
uint64_t ii_ilct_regval;
struct {
uint64_t i_test_seed : 20;
uint64_t i_test_mask : 8;
uint64_t i_test_data : 20;
uint64_t i_test_valid : 1;
uint64_t i_test_cberr : 1;
uint64_t i_test_flit : 3;
uint64_t i_test_clear : 1;
uint64_t i_test_err_capture : 1;
uint64_t i_rsvd : 9;
uint64_t i_test_seed:20;
uint64_t i_test_mask:8;
uint64_t i_test_data:20;
uint64_t i_test_valid:1;
uint64_t i_test_cberr:1;
uint64_t i_test_flit:3;
uint64_t i_test_clear:1;
uint64_t i_test_err_capture:1;
uint64_t i_rsvd:9;
} ii_ilct_fld_s;
} ii_ilct_u_t;
/************************************************************************
* *
* If the II detects an illegal incoming Duplonet packet (request or *
......@@ -1532,22 +1484,21 @@ typedef union ii_ilct_u {
typedef union ii_iieph1_u {
uint64_t ii_iieph1_regval;
struct {
uint64_t i_command : 7;
uint64_t i_rsvd_5 : 1;
uint64_t i_suppl : 14;
uint64_t i_rsvd_4 : 1;
uint64_t i_source : 14;
uint64_t i_rsvd_3 : 1;
uint64_t i_err_type : 4;
uint64_t i_rsvd_2 : 4;
uint64_t i_overrun : 1;
uint64_t i_rsvd_1 : 3;
uint64_t i_valid : 1;
uint64_t i_rsvd : 13;
uint64_t i_command:7;
uint64_t i_rsvd_5:1;
uint64_t i_suppl:14;
uint64_t i_rsvd_4:1;
uint64_t i_source:14;
uint64_t i_rsvd_3:1;
uint64_t i_err_type:4;
uint64_t i_rsvd_2:4;
uint64_t i_overrun:1;
uint64_t i_rsvd_1:3;
uint64_t i_valid:1;
uint64_t i_rsvd:13;
} ii_iieph1_fld_s;
} ii_iieph1_u_t;
/************************************************************************
* *
* This register holds the Address field from the header flit of an *
......@@ -1562,19 +1513,16 @@ typedef union ii_iieph1_u {
typedef union ii_iieph2_u {
uint64_t ii_iieph2_regval;
struct {
uint64_t i_rsvd_0 : 3;
uint64_t i_address : 47;
uint64_t i_rsvd_1 : 10;
uint64_t i_tail : 1;
uint64_t i_rsvd : 3;
uint64_t i_rsvd_0:3;
uint64_t i_address:47;
uint64_t i_rsvd_1:10;
uint64_t i_tail:1;
uint64_t i_rsvd:3;
} ii_iieph2_fld_s;
} ii_iieph2_u_t;
/******************************/
/************************************************************************
* *
* This register's value is a bit vector that guards access from SXBs *
......@@ -1586,11 +1534,10 @@ typedef union ii_iieph2_u {
typedef union ii_islapr_u {
uint64_t ii_islapr_regval;
struct {
uint64_t i_region : 64;
uint64_t i_region:64;
} ii_islapr_fld_s;
} ii_islapr_u_t;
/************************************************************************
* *
* A write to this register of the 56-bit value "Pup+Bun" will cause *
......@@ -1602,8 +1549,8 @@ typedef union ii_islapr_u {
typedef union ii_islapo_u {
uint64_t ii_islapo_regval;
struct {
uint64_t i_io_sbx_ovrride : 56;
uint64_t i_rsvd : 8;
uint64_t i_io_sbx_ovrride:56;
uint64_t i_rsvd:8;
} ii_islapo_fld_s;
} ii_islapo_u_t;
......@@ -1618,12 +1565,12 @@ typedef union ii_islapo_u {
typedef union ii_iwi_u {
uint64_t ii_iwi_regval;
struct {
uint64_t i_prescale : 24;
uint64_t i_rsvd : 8;
uint64_t i_timeout : 8;
uint64_t i_rsvd1 : 8;
uint64_t i_intrpt_retry_period : 8;
uint64_t i_rsvd2 : 8;
uint64_t i_prescale:24;
uint64_t i_rsvd:8;
uint64_t i_timeout:8;
uint64_t i_rsvd1:8;
uint64_t i_intrpt_retry_period:8;
uint64_t i_rsvd2:8;
} ii_iwi_fld_s;
} ii_iwi_u_t;
......@@ -1637,24 +1584,24 @@ typedef union ii_iwi_u {
typedef union ii_iwel_u {
uint64_t ii_iwel_regval;
struct {
uint64_t i_intr_timed_out : 1;
uint64_t i_rsvd : 7;
uint64_t i_cam_overflow : 1;
uint64_t i_cam_read_miss : 1;
uint64_t i_rsvd1 : 2;
uint64_t i_ioq_rep_underflow : 1;
uint64_t i_ioq_req_underflow : 1;
uint64_t i_ioq_rep_overflow : 1;
uint64_t i_ioq_req_overflow : 1;
uint64_t i_iiq_rep_overflow : 1;
uint64_t i_iiq_req_overflow : 1;
uint64_t i_rsvd2 : 6;
uint64_t i_ii_xn_rep_cred_over_under: 1;
uint64_t i_ii_xn_req_cred_over_under: 1;
uint64_t i_rsvd3 : 6;
uint64_t i_ii_xn_invalid_cmd : 1;
uint64_t i_xn_ii_invalid_cmd : 1;
uint64_t i_rsvd4 : 30;
uint64_t i_intr_timed_out:1;
uint64_t i_rsvd:7;
uint64_t i_cam_overflow:1;
uint64_t i_cam_read_miss:1;
uint64_t i_rsvd1:2;
uint64_t i_ioq_rep_underflow:1;
uint64_t i_ioq_req_underflow:1;
uint64_t i_ioq_rep_overflow:1;
uint64_t i_ioq_req_overflow:1;
uint64_t i_iiq_rep_overflow:1;
uint64_t i_iiq_req_overflow:1;
uint64_t i_rsvd2:6;
uint64_t i_ii_xn_rep_cred_over_under:1;
uint64_t i_ii_xn_req_cred_over_under:1;
uint64_t i_rsvd3:6;
uint64_t i_ii_xn_invalid_cmd:1;
uint64_t i_xn_ii_invalid_cmd:1;
uint64_t i_rsvd4:30;
} ii_iwel_fld_s;
} ii_iwel_u_t;
......@@ -1667,20 +1614,20 @@ typedef union ii_iwel_u {
typedef union ii_iwc_u {
uint64_t ii_iwc_regval;
struct {
uint64_t i_dma_byte_swap : 1;
uint64_t i_rsvd : 3;
uint64_t i_cam_read_lines_reset : 1;
uint64_t i_rsvd1 : 3;
uint64_t i_ii_xn_cred_over_under_log: 1;
uint64_t i_rsvd2 : 19;
uint64_t i_xn_rep_iq_depth : 5;
uint64_t i_rsvd3 : 3;
uint64_t i_xn_req_iq_depth : 5;
uint64_t i_rsvd4 : 3;
uint64_t i_iiq_depth : 6;
uint64_t i_rsvd5 : 12;
uint64_t i_force_rep_cred : 1;
uint64_t i_force_req_cred : 1;
uint64_t i_dma_byte_swap:1;
uint64_t i_rsvd:3;
uint64_t i_cam_read_lines_reset:1;
uint64_t i_rsvd1:3;
uint64_t i_ii_xn_cred_over_under_log:1;
uint64_t i_rsvd2:19;
uint64_t i_xn_rep_iq_depth:5;
uint64_t i_rsvd3:3;
uint64_t i_xn_req_iq_depth:5;
uint64_t i_rsvd4:3;
uint64_t i_iiq_depth:6;
uint64_t i_rsvd5:12;
uint64_t i_force_rep_cred:1;
uint64_t i_force_req_cred:1;
} ii_iwc_fld_s;
} ii_iwc_u_t;
......@@ -1693,10 +1640,10 @@ typedef union ii_iwc_u {
typedef union ii_iws_u {
uint64_t ii_iws_regval;
struct {
uint64_t i_xn_rep_iq_credits : 5;
uint64_t i_rsvd : 3;
uint64_t i_xn_req_iq_credits : 5;
uint64_t i_rsvd1 : 51;
uint64_t i_xn_rep_iq_credits:5;
uint64_t i_rsvd:3;
uint64_t i_xn_req_iq_credits:5;
uint64_t i_rsvd1:51;
} ii_iws_fld_s;
} ii_iws_u_t;
......@@ -1709,28 +1656,27 @@ typedef union ii_iws_u {
typedef union ii_iweim_u {
uint64_t ii_iweim_regval;
struct {
uint64_t i_intr_timed_out : 1;
uint64_t i_rsvd : 7;
uint64_t i_cam_overflow : 1;
uint64_t i_cam_read_miss : 1;
uint64_t i_rsvd1 : 2;
uint64_t i_ioq_rep_underflow : 1;
uint64_t i_ioq_req_underflow : 1;
uint64_t i_ioq_rep_overflow : 1;
uint64_t i_ioq_req_overflow : 1;
uint64_t i_iiq_rep_overflow : 1;
uint64_t i_iiq_req_overflow : 1;
uint64_t i_rsvd2 : 6;
uint64_t i_ii_xn_rep_cred_overflow : 1;
uint64_t i_ii_xn_req_cred_overflow : 1;
uint64_t i_rsvd3 : 6;
uint64_t i_ii_xn_invalid_cmd : 1;
uint64_t i_xn_ii_invalid_cmd : 1;
uint64_t i_rsvd4 : 30;
uint64_t i_intr_timed_out:1;
uint64_t i_rsvd:7;
uint64_t i_cam_overflow:1;
uint64_t i_cam_read_miss:1;
uint64_t i_rsvd1:2;
uint64_t i_ioq_rep_underflow:1;
uint64_t i_ioq_req_underflow:1;
uint64_t i_ioq_rep_overflow:1;
uint64_t i_ioq_req_overflow:1;
uint64_t i_iiq_rep_overflow:1;
uint64_t i_iiq_req_overflow:1;
uint64_t i_rsvd2:6;
uint64_t i_ii_xn_rep_cred_overflow:1;
uint64_t i_ii_xn_req_cred_overflow:1;
uint64_t i_rsvd3:6;
uint64_t i_ii_xn_invalid_cmd:1;
uint64_t i_xn_ii_invalid_cmd:1;
uint64_t i_rsvd4:30;
} ii_iweim_fld_s;
} ii_iweim_u_t;
/************************************************************************
* *
* A write to this register causes a particular field in the *
......@@ -1744,15 +1690,14 @@ typedef union ii_iweim_u {
typedef union ii_ipca_u {
uint64_t ii_ipca_regval;
struct {
uint64_t i_wid : 4;
uint64_t i_adjust : 1;
uint64_t i_rsvd_1 : 3;
uint64_t i_field : 2;
uint64_t i_rsvd : 54;
uint64_t i_wid:4;
uint64_t i_adjust:1;
uint64_t i_rsvd_1:3;
uint64_t i_field:2;
uint64_t i_rsvd:54;
} ii_ipca_fld_s;
} ii_ipca_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1763,18 +1708,16 @@ typedef union ii_ipca_u {
* *
************************************************************************/
typedef union ii_iprte0a_u {
uint64_t ii_iprte0a_regval;
struct {
uint64_t i_rsvd_1 : 54;
uint64_t i_widget : 4;
uint64_t i_to_cnt : 5;
uint64_t i_vld : 1;
uint64_t i_rsvd_1:54;
uint64_t i_widget:4;
uint64_t i_to_cnt:5;
uint64_t i_vld:1;
} ii_iprte0a_fld_s;
} ii_iprte0a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1788,14 +1731,13 @@ typedef union ii_iprte0a_u {
typedef union ii_iprte1a_u {
uint64_t ii_iprte1a_regval;
struct {
uint64_t i_rsvd_1 : 54;
uint64_t i_widget : 4;
uint64_t i_to_cnt : 5;
uint64_t i_vld : 1;
uint64_t i_rsvd_1:54;
uint64_t i_widget:4;
uint64_t i_to_cnt:5;
uint64_t i_vld:1;
} ii_iprte1a_fld_s;
} ii_iprte1a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1809,14 +1751,13 @@ typedef union ii_iprte1a_u {
typedef union ii_iprte2a_u {
uint64_t ii_iprte2a_regval;
struct {
uint64_t i_rsvd_1 : 54;
uint64_t i_widget : 4;
uint64_t i_to_cnt : 5;
uint64_t i_vld : 1;
uint64_t i_rsvd_1:54;
uint64_t i_widget:4;
uint64_t i_to_cnt:5;
uint64_t i_vld:1;
} ii_iprte2a_fld_s;
} ii_iprte2a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1830,14 +1771,13 @@ typedef union ii_iprte2a_u {
typedef union ii_iprte3a_u {
uint64_t ii_iprte3a_regval;
struct {
uint64_t i_rsvd_1 : 54;
uint64_t i_widget : 4;
uint64_t i_to_cnt : 5;
uint64_t i_vld : 1;
uint64_t i_rsvd_1:54;
uint64_t i_widget:4;
uint64_t i_to_cnt:5;
uint64_t i_vld:1;
} ii_iprte3a_fld_s;
} ii_iprte3a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1851,14 +1791,13 @@ typedef union ii_iprte3a_u {
typedef union ii_iprte4a_u {
uint64_t ii_iprte4a_regval;
struct {
uint64_t i_rsvd_1 : 54;
uint64_t i_widget : 4;
uint64_t i_to_cnt : 5;
uint64_t i_vld : 1;
uint64_t i_rsvd_1:54;
uint64_t i_widget:4;
uint64_t i_to_cnt:5;
uint64_t i_vld:1;
} ii_iprte4a_fld_s;
} ii_iprte4a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1872,14 +1811,13 @@ typedef union ii_iprte4a_u {
typedef union ii_iprte5a_u {
uint64_t ii_iprte5a_regval;
struct {
uint64_t i_rsvd_1 : 54;
uint64_t i_widget : 4;
uint64_t i_to_cnt : 5;
uint64_t i_vld : 1;
uint64_t i_rsvd_1:54;
uint64_t i_widget:4;
uint64_t i_to_cnt:5;
uint64_t i_vld:1;
} ii_iprte5a_fld_s;
} ii_iprte5a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1893,14 +1831,13 @@ typedef union ii_iprte5a_u {
typedef union ii_iprte6a_u {
uint64_t ii_iprte6a_regval;
struct {
uint64_t i_rsvd_1 : 54;
uint64_t i_widget : 4;
uint64_t i_to_cnt : 5;
uint64_t i_vld : 1;
uint64_t i_rsvd_1:54;
uint64_t i_widget:4;
uint64_t i_to_cnt:5;
uint64_t i_vld:1;
} ii_iprte6a_fld_s;
} ii_iprte6a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1914,15 +1851,13 @@ typedef union ii_iprte6a_u {
typedef union ii_iprte7a_u {
uint64_t ii_iprte7a_regval;
struct {
uint64_t i_rsvd_1 : 54;
uint64_t i_widget : 4;
uint64_t i_to_cnt : 5;
uint64_t i_vld : 1;
uint64_t i_rsvd_1:54;
uint64_t i_widget:4;
uint64_t i_to_cnt:5;
uint64_t i_vld:1;
} ii_iprtea7_fld_s;
} ii_iprte7a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1933,18 +1868,16 @@ typedef union ii_iprte7a_u {
* *
************************************************************************/
typedef union ii_iprte0b_u {
uint64_t ii_iprte0b_regval;
struct {
uint64_t i_rsvd_1 : 3;
uint64_t i_address : 47;
uint64_t i_init : 3;
uint64_t i_source : 11;
uint64_t i_rsvd_1:3;
uint64_t i_address:47;
uint64_t i_init:3;
uint64_t i_source:11;
} ii_iprte0b_fld_s;
} ii_iprte0b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1958,14 +1891,13 @@ typedef union ii_iprte0b_u {
typedef union ii_iprte1b_u {
uint64_t ii_iprte1b_regval;
struct {
uint64_t i_rsvd_1 : 3;
uint64_t i_address : 47;
uint64_t i_init : 3;
uint64_t i_source : 11;
uint64_t i_rsvd_1:3;
uint64_t i_address:47;
uint64_t i_init:3;
uint64_t i_source:11;
} ii_iprte1b_fld_s;
} ii_iprte1b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -1979,14 +1911,13 @@ typedef union ii_iprte1b_u {
typedef union ii_iprte2b_u {
uint64_t ii_iprte2b_regval;
struct {
uint64_t i_rsvd_1 : 3;
uint64_t i_address : 47;
uint64_t i_init : 3;
uint64_t i_source : 11;
uint64_t i_rsvd_1:3;
uint64_t i_address:47;
uint64_t i_init:3;
uint64_t i_source:11;
} ii_iprte2b_fld_s;
} ii_iprte2b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -2000,14 +1931,13 @@ typedef union ii_iprte2b_u {
typedef union ii_iprte3b_u {
uint64_t ii_iprte3b_regval;
struct {
uint64_t i_rsvd_1 : 3;
uint64_t i_address : 47;
uint64_t i_init : 3;
uint64_t i_source : 11;
uint64_t i_rsvd_1:3;
uint64_t i_address:47;
uint64_t i_init:3;
uint64_t i_source:11;
} ii_iprte3b_fld_s;
} ii_iprte3b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -2021,14 +1951,13 @@ typedef union ii_iprte3b_u {
typedef union ii_iprte4b_u {
uint64_t ii_iprte4b_regval;
struct {
uint64_t i_rsvd_1 : 3;
uint64_t i_address : 47;
uint64_t i_init : 3;
uint64_t i_source : 11;
uint64_t i_rsvd_1:3;
uint64_t i_address:47;
uint64_t i_init:3;
uint64_t i_source:11;
} ii_iprte4b_fld_s;
} ii_iprte4b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -2042,14 +1971,13 @@ typedef union ii_iprte4b_u {
typedef union ii_iprte5b_u {
uint64_t ii_iprte5b_regval;
struct {
uint64_t i_rsvd_1 : 3;
uint64_t i_address : 47;
uint64_t i_init : 3;
uint64_t i_source : 11;
uint64_t i_rsvd_1:3;
uint64_t i_address:47;
uint64_t i_init:3;
uint64_t i_source:11;
} ii_iprte5b_fld_s;
} ii_iprte5b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -2063,15 +1991,14 @@ typedef union ii_iprte5b_u {
typedef union ii_iprte6b_u {
uint64_t ii_iprte6b_regval;
struct {
uint64_t i_rsvd_1 : 3;
uint64_t i_address : 47;
uint64_t i_init : 3;
uint64_t i_source : 11;
uint64_t i_rsvd_1:3;
uint64_t i_address:47;
uint64_t i_init:3;
uint64_t i_source:11;
} ii_iprte6b_fld_s;
} ii_iprte6b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
......@@ -2085,14 +2012,13 @@ typedef union ii_iprte6b_u {
typedef union ii_iprte7b_u {
uint64_t ii_iprte7b_regval;
struct {
uint64_t i_rsvd_1 : 3;
uint64_t i_address : 47;
uint64_t i_init : 3;
uint64_t i_source : 11;
uint64_t i_rsvd_1:3;
uint64_t i_address:47;
uint64_t i_init:3;
uint64_t i_source:11;
} ii_iprte7b_fld_s;
} ii_iprte7b_u_t;
/************************************************************************
* *
* Description: SHub II contains a feature which did not exist in *
......@@ -2114,15 +2040,14 @@ typedef union ii_iprte7b_u {
typedef union ii_ipdr_u {
uint64_t ii_ipdr_regval;
struct {
uint64_t i_te : 3;
uint64_t i_rsvd_1 : 1;
uint64_t i_pnd : 1;
uint64_t i_init_rpcnt : 1;
uint64_t i_rsvd : 58;
uint64_t i_te:3;
uint64_t i_rsvd_1:1;
uint64_t i_pnd:1;
uint64_t i_init_rpcnt:1;
uint64_t i_rsvd:58;
} ii_ipdr_fld_s;
} ii_ipdr_u_t;
/************************************************************************
* *
* A write to this register causes a CRB entry to be returned to the *
......@@ -2143,13 +2068,12 @@ typedef union ii_ipdr_u {
typedef union ii_icdr_u {
uint64_t ii_icdr_regval;
struct {
uint64_t i_crb_num : 4;
uint64_t i_pnd : 1;
uint64_t i_rsvd : 59;
uint64_t i_crb_num:4;
uint64_t i_pnd:1;
uint64_t i_rsvd:59;
} ii_icdr_fld_s;
} ii_icdr_u_t;
/************************************************************************
* *
* This register provides debug access to two FIFOs inside of II. *
......@@ -2170,15 +2094,14 @@ typedef union ii_icdr_u {
typedef union ii_ifdr_u {
uint64_t ii_ifdr_regval;
struct {
uint64_t i_ioq_max_rq : 7;
uint64_t i_set_ioq_rq : 1;
uint64_t i_ioq_max_rp : 7;
uint64_t i_set_ioq_rp : 1;
uint64_t i_rsvd : 48;
uint64_t i_ioq_max_rq:7;
uint64_t i_set_ioq_rq:1;
uint64_t i_ioq_max_rp:7;
uint64_t i_set_ioq_rp:1;
uint64_t i_rsvd:48;
} ii_ifdr_fld_s;
} ii_ifdr_u_t;
/************************************************************************
* *
* This register allows the II to become sluggish in removing *
......@@ -2193,14 +2116,13 @@ typedef union ii_ifdr_u {
typedef union ii_iiap_u {
uint64_t ii_iiap_regval;
struct {
uint64_t i_rq_mls : 6;
uint64_t i_rsvd_1 : 2;
uint64_t i_rp_mls : 6;
uint64_t i_rsvd : 50;
uint64_t i_rq_mls:6;
uint64_t i_rsvd_1:2;
uint64_t i_rp_mls:6;
uint64_t i_rsvd:50;
} ii_iiap_fld_s;
} ii_iiap_u_t;
/************************************************************************
* *
* This register allows several parameters of CRB operation to be *
......@@ -2213,24 +2135,23 @@ typedef union ii_iiap_u {
typedef union ii_icmr_u {
uint64_t ii_icmr_regval;
struct {
uint64_t i_sp_msg : 1;
uint64_t i_rd_hdr : 1;
uint64_t i_rsvd_4 : 2;
uint64_t i_c_cnt : 4;
uint64_t i_rsvd_3 : 4;
uint64_t i_clr_rqpd : 1;
uint64_t i_clr_rppd : 1;
uint64_t i_rsvd_2 : 2;
uint64_t i_fc_cnt : 4;
uint64_t i_crb_vld : 15;
uint64_t i_crb_mark : 15;
uint64_t i_rsvd_1 : 2;
uint64_t i_precise : 1;
uint64_t i_rsvd : 11;
uint64_t i_sp_msg:1;
uint64_t i_rd_hdr:1;
uint64_t i_rsvd_4:2;
uint64_t i_c_cnt:4;
uint64_t i_rsvd_3:4;
uint64_t i_clr_rqpd:1;
uint64_t i_clr_rppd:1;
uint64_t i_rsvd_2:2;
uint64_t i_fc_cnt:4;
uint64_t i_crb_vld:15;
uint64_t i_crb_mark:15;
uint64_t i_rsvd_1:2;
uint64_t i_precise:1;
uint64_t i_rsvd:11;
} ii_icmr_fld_s;
} ii_icmr_u_t;
/************************************************************************
* *
* This register allows control of the table portion of the CRB *
......@@ -2242,15 +2163,14 @@ typedef union ii_icmr_u {
typedef union ii_iccr_u {
uint64_t ii_iccr_regval;
struct {
uint64_t i_crb_num : 4;
uint64_t i_rsvd_1 : 4;
uint64_t i_cmd : 8;
uint64_t i_pending : 1;
uint64_t i_rsvd : 47;
uint64_t i_crb_num:4;
uint64_t i_rsvd_1:4;
uint64_t i_cmd:8;
uint64_t i_pending:1;
uint64_t i_rsvd:47;
} ii_iccr_fld_s;
} ii_iccr_u_t;
/************************************************************************
* *
* This register allows the maximum timeout value to be programmed. *
......@@ -2260,12 +2180,11 @@ typedef union ii_iccr_u {
typedef union ii_icto_u {
uint64_t ii_icto_regval;
struct {
uint64_t i_timeout : 8;
uint64_t i_rsvd : 56;
uint64_t i_timeout:8;
uint64_t i_rsvd:56;
} ii_icto_fld_s;
} ii_icto_u_t;
/************************************************************************
* *
* This register allows the timeout prescalar to be programmed. An *
......@@ -2280,12 +2199,11 @@ typedef union ii_icto_u {
typedef union ii_ictp_u {
uint64_t ii_ictp_regval;
struct {
uint64_t i_prescale : 24;
uint64_t i_rsvd : 40;
uint64_t i_prescale:24;
uint64_t i_rsvd:40;
} ii_ictp_fld_s;
} ii_ictp_u_t;
/************************************************************************
* *
* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
......@@ -2312,16 +2230,15 @@ typedef union ii_ictp_u {
typedef union ii_icrb0_a_u {
uint64_t ii_icrb0_a_regval;
struct {
uint64_t ia_iow : 1;
uint64_t ia_vld : 1;
uint64_t ia_addr : 47;
uint64_t ia_tnum : 5;
uint64_t ia_sidn : 4;
uint64_t ia_rsvd : 6;
uint64_t ia_iow:1;
uint64_t ia_vld:1;
uint64_t ia_addr:47;
uint64_t ia_tnum:5;
uint64_t ia_sidn:4;
uint64_t ia_rsvd:6;
} ii_icrb0_a_fld_s;
} ii_icrb0_a_u_t;
/************************************************************************
* *
* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
......@@ -2334,32 +2251,31 @@ typedef union ii_icrb0_a_u {
typedef union ii_icrb0_b_u {
uint64_t ii_icrb0_b_regval;
struct {
uint64_t ib_xt_err : 1;
uint64_t ib_mark : 1;
uint64_t ib_ln_uce : 1;
uint64_t ib_errcode : 3;
uint64_t ib_error : 1;
uint64_t ib_stall__bte_1 : 1;
uint64_t ib_stall__bte_0 : 1;
uint64_t ib_stall__intr : 1;
uint64_t ib_stall_ib : 1;
uint64_t ib_intvn : 1;
uint64_t ib_wb : 1;
uint64_t ib_hold : 1;
uint64_t ib_ack : 1;
uint64_t ib_resp : 1;
uint64_t ib_ack_cnt : 11;
uint64_t ib_rsvd : 7;
uint64_t ib_exc : 5;
uint64_t ib_init : 3;
uint64_t ib_imsg : 8;
uint64_t ib_imsgtype : 2;
uint64_t ib_use_old : 1;
uint64_t ib_rsvd_1 : 11;
uint64_t ib_xt_err:1;
uint64_t ib_mark:1;
uint64_t ib_ln_uce:1;
uint64_t ib_errcode:3;
uint64_t ib_error:1;
uint64_t ib_stall__bte_1:1;
uint64_t ib_stall__bte_0:1;
uint64_t ib_stall__intr:1;
uint64_t ib_stall_ib:1;
uint64_t ib_intvn:1;
uint64_t ib_wb:1;
uint64_t ib_hold:1;
uint64_t ib_ack:1;
uint64_t ib_resp:1;
uint64_t ib_ack_cnt:11;
uint64_t ib_rsvd:7;
uint64_t ib_exc:5;
uint64_t ib_init:3;
uint64_t ib_imsg:8;
uint64_t ib_imsgtype:2;
uint64_t ib_use_old:1;
uint64_t ib_rsvd_1:11;
} ii_icrb0_b_fld_s;
} ii_icrb0_b_u_t;
/************************************************************************
* *
* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
......@@ -2372,19 +2288,18 @@ typedef union ii_icrb0_b_u {
typedef union ii_icrb0_c_u {
uint64_t ii_icrb0_c_regval;
struct {
uint64_t ic_source : 15;
uint64_t ic_size : 2;
uint64_t ic_ct : 1;
uint64_t ic_bte_num : 1;
uint64_t ic_gbr : 1;
uint64_t ic_resprqd : 1;
uint64_t ic_bo : 1;
uint64_t ic_suppl : 15;
uint64_t ic_rsvd : 27;
uint64_t ic_source:15;
uint64_t ic_size:2;
uint64_t ic_ct:1;
uint64_t ic_bte_num:1;
uint64_t ic_gbr:1;
uint64_t ic_resprqd:1;
uint64_t ic_bo:1;
uint64_t ic_suppl:15;
uint64_t ic_rsvd:27;
} ii_icrb0_c_fld_s;
} ii_icrb0_c_u_t;
/************************************************************************
* *
* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
......@@ -2397,16 +2312,15 @@ typedef union ii_icrb0_c_u {
typedef union ii_icrb0_d_u {
uint64_t ii_icrb0_d_regval;
struct {
uint64_t id_pa_be : 43;
uint64_t id_bte_op : 1;
uint64_t id_pr_psc : 4;
uint64_t id_pr_cnt : 4;
uint64_t id_sleep : 1;
uint64_t id_rsvd : 11;
uint64_t id_pa_be:43;
uint64_t id_bte_op:1;
uint64_t id_pr_psc:4;
uint64_t id_pr_cnt:4;
uint64_t id_sleep:1;
uint64_t id_rsvd:11;
} ii_icrb0_d_fld_s;
} ii_icrb0_d_u_t;
/************************************************************************
* *
* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
......@@ -2419,16 +2333,15 @@ typedef union ii_icrb0_d_u {
typedef union ii_icrb0_e_u {
uint64_t ii_icrb0_e_regval;
struct {
uint64_t ie_timeout : 8;
uint64_t ie_context : 15;
uint64_t ie_rsvd : 1;
uint64_t ie_tvld : 1;
uint64_t ie_cvld : 1;
uint64_t ie_rsvd_0 : 38;
uint64_t ie_timeout:8;
uint64_t ie_context:15;
uint64_t ie_rsvd:1;
uint64_t ie_tvld:1;
uint64_t ie_cvld:1;
uint64_t ie_rsvd_0:38;
} ii_icrb0_e_fld_s;
} ii_icrb0_e_u_t;
/************************************************************************
* *
* This register contains the lower 64 bits of the header of the *
......@@ -2440,14 +2353,13 @@ typedef union ii_icrb0_e_u {
typedef union ii_icsml_u {
uint64_t ii_icsml_regval;
struct {
uint64_t i_tt_addr : 47;
uint64_t i_newsuppl_ex : 14;
uint64_t i_reserved : 2;
uint64_t i_overflow : 1;
uint64_t i_tt_addr:47;
uint64_t i_newsuppl_ex:14;
uint64_t i_reserved:2;
uint64_t i_overflow:1;
} ii_icsml_fld_s;
} ii_icsml_u_t;
/************************************************************************
* *
* This register contains the middle 64 bits of the header of the *
......@@ -2459,12 +2371,11 @@ typedef union ii_icsml_u {
typedef union ii_icsmm_u {
uint64_t ii_icsmm_regval;
struct {
uint64_t i_tt_ack_cnt : 11;
uint64_t i_reserved : 53;
uint64_t i_tt_ack_cnt:11;
uint64_t i_reserved:53;
} ii_icsmm_fld_s;
} ii_icsmm_u_t;
/************************************************************************
* *
* This register contains the microscopic state, all the inputs to *
......@@ -2476,50 +2387,49 @@ typedef union ii_icsmm_u {
typedef union ii_icsmh_u {
uint64_t ii_icsmh_regval;
struct {
uint64_t i_tt_vld : 1;
uint64_t i_xerr : 1;
uint64_t i_ft_cwact_o : 1;
uint64_t i_ft_wact_o : 1;
uint64_t i_ft_active_o : 1;
uint64_t i_sync : 1;
uint64_t i_mnusg : 1;
uint64_t i_mnusz : 1;
uint64_t i_plusz : 1;
uint64_t i_plusg : 1;
uint64_t i_tt_exc : 5;
uint64_t i_tt_wb : 1;
uint64_t i_tt_hold : 1;
uint64_t i_tt_ack : 1;
uint64_t i_tt_resp : 1;
uint64_t i_tt_intvn : 1;
uint64_t i_g_stall_bte1 : 1;
uint64_t i_g_stall_bte0 : 1;
uint64_t i_g_stall_il : 1;
uint64_t i_g_stall_ib : 1;
uint64_t i_tt_imsg : 8;
uint64_t i_tt_imsgtype : 2;
uint64_t i_tt_use_old : 1;
uint64_t i_tt_respreqd : 1;
uint64_t i_tt_bte_num : 1;
uint64_t i_cbn : 1;
uint64_t i_match : 1;
uint64_t i_rpcnt_lt_34 : 1;
uint64_t i_rpcnt_ge_34 : 1;
uint64_t i_rpcnt_lt_18 : 1;
uint64_t i_rpcnt_ge_18 : 1;
uint64_t i_rpcnt_lt_2 : 1;
uint64_t i_rpcnt_ge_2 : 1;
uint64_t i_rqcnt_lt_18 : 1;
uint64_t i_rqcnt_ge_18 : 1;
uint64_t i_rqcnt_lt_2 : 1;
uint64_t i_rqcnt_ge_2 : 1;
uint64_t i_tt_device : 7;
uint64_t i_tt_init : 3;
uint64_t i_reserved : 5;
uint64_t i_tt_vld:1;
uint64_t i_xerr:1;
uint64_t i_ft_cwact_o:1;
uint64_t i_ft_wact_o:1;
uint64_t i_ft_active_o:1;
uint64_t i_sync:1;
uint64_t i_mnusg:1;
uint64_t i_mnusz:1;
uint64_t i_plusz:1;
uint64_t i_plusg:1;
uint64_t i_tt_exc:5;
uint64_t i_tt_wb:1;
uint64_t i_tt_hold:1;
uint64_t i_tt_ack:1;
uint64_t i_tt_resp:1;
uint64_t i_tt_intvn:1;
uint64_t i_g_stall_bte1:1;
uint64_t i_g_stall_bte0:1;
uint64_t i_g_stall_il:1;
uint64_t i_g_stall_ib:1;
uint64_t i_tt_imsg:8;
uint64_t i_tt_imsgtype:2;
uint64_t i_tt_use_old:1;
uint64_t i_tt_respreqd:1;
uint64_t i_tt_bte_num:1;
uint64_t i_cbn:1;
uint64_t i_match:1;
uint64_t i_rpcnt_lt_34:1;
uint64_t i_rpcnt_ge_34:1;
uint64_t i_rpcnt_lt_18:1;
uint64_t i_rpcnt_ge_18:1;
uint64_t i_rpcnt_lt_2:1;
uint64_t i_rpcnt_ge_2:1;
uint64_t i_rqcnt_lt_18:1;
uint64_t i_rqcnt_ge_18:1;
uint64_t i_rqcnt_lt_2:1;
uint64_t i_rqcnt_ge_2:1;
uint64_t i_tt_device:7;
uint64_t i_tt_init:3;
uint64_t i_reserved:5;
} ii_icsmh_fld_s;
} ii_icsmh_u_t;
/************************************************************************
* *
* The Shub DEBUG unit provides a 3-bit selection signal to the *
......@@ -2531,16 +2441,15 @@ typedef union ii_icsmh_u {
typedef union ii_idbss_u {
uint64_t ii_idbss_regval;
struct {
uint64_t i_iioclk_core_submenu : 3;
uint64_t i_rsvd : 5;
uint64_t i_fsbclk_wrapper_submenu : 3;
uint64_t i_rsvd_1 : 5;
uint64_t i_iioclk_menu : 5;
uint64_t i_rsvd_2 : 43;
uint64_t i_iioclk_core_submenu:3;
uint64_t i_rsvd:5;
uint64_t i_fsbclk_wrapper_submenu:3;
uint64_t i_rsvd_1:5;
uint64_t i_iioclk_menu:5;
uint64_t i_rsvd_2:43;
} ii_idbss_fld_s;
} ii_idbss_u_t;
/************************************************************************
* *
* Description: This register is used to set up the length for a *
......@@ -2559,15 +2468,14 @@ typedef union ii_idbss_u {
typedef union ii_ibls0_u {
uint64_t ii_ibls0_regval;
struct {
uint64_t i_length : 16;
uint64_t i_error : 1;
uint64_t i_rsvd_1 : 3;
uint64_t i_busy : 1;
uint64_t i_rsvd : 43;
uint64_t i_length:16;
uint64_t i_error:1;
uint64_t i_rsvd_1:3;
uint64_t i_busy:1;
uint64_t i_rsvd:43;
} ii_ibls0_fld_s;
} ii_ibls0_u_t;
/************************************************************************
* *
* This register should be loaded before a transfer is started. The *
......@@ -2581,13 +2489,12 @@ typedef union ii_ibls0_u {
typedef union ii_ibsa0_u {
uint64_t ii_ibsa0_regval;
struct {
uint64_t i_rsvd_1 : 7;
uint64_t i_addr : 42;
uint64_t i_rsvd : 15;
uint64_t i_rsvd_1:7;
uint64_t i_addr:42;
uint64_t i_rsvd:15;
} ii_ibsa0_fld_s;
} ii_ibsa0_u_t;
/************************************************************************
* *
* This register should be loaded before a transfer is started. The *
......@@ -2601,13 +2508,12 @@ typedef union ii_ibsa0_u {
typedef union ii_ibda0_u {
uint64_t ii_ibda0_regval;
struct {
uint64_t i_rsvd_1 : 7;
uint64_t i_addr : 42;
uint64_t i_rsvd : 15;
uint64_t i_rsvd_1:7;
uint64_t i_addr:42;
uint64_t i_rsvd:15;
} ii_ibda0_fld_s;
} ii_ibda0_u_t;
/************************************************************************
* *
* Writing to this register sets up the attributes of the transfer *
......@@ -2623,16 +2529,15 @@ typedef union ii_ibda0_u {
typedef union ii_ibct0_u {
uint64_t ii_ibct0_regval;
struct {
uint64_t i_zerofill : 1;
uint64_t i_rsvd_2 : 3;
uint64_t i_notify : 1;
uint64_t i_rsvd_1 : 3;
uint64_t i_poison : 1;
uint64_t i_rsvd : 55;
uint64_t i_zerofill:1;
uint64_t i_rsvd_2:3;
uint64_t i_notify:1;
uint64_t i_rsvd_1:3;
uint64_t i_poison:1;
uint64_t i_rsvd:55;
} ii_ibct0_fld_s;
} ii_ibct0_u_t;
/************************************************************************
* *
* This register contains the address to which the WINV is sent. *
......@@ -2643,13 +2548,12 @@ typedef union ii_ibct0_u {
typedef union ii_ibna0_u {
uint64_t ii_ibna0_regval;
struct {
uint64_t i_rsvd_1 : 7;
uint64_t i_addr : 42;
uint64_t i_rsvd : 15;
uint64_t i_rsvd_1:7;
uint64_t i_addr:42;
uint64_t i_rsvd:15;
} ii_ibna0_fld_s;
} ii_ibna0_u_t;
/************************************************************************
* *
* This register contains the programmable level as well as the node *
......@@ -2661,15 +2565,14 @@ typedef union ii_ibna0_u {
typedef union ii_ibia0_u {
uint64_t ii_ibia0_regval;
struct {
uint64_t i_rsvd_2 : 1;
uint64_t i_node_id : 11;
uint64_t i_rsvd_1 : 4;
uint64_t i_level : 7;
uint64_t i_rsvd : 41;
uint64_t i_rsvd_2:1;
uint64_t i_node_id:11;
uint64_t i_rsvd_1:4;
uint64_t i_level:7;
uint64_t i_rsvd:41;
} ii_ibia0_fld_s;
} ii_ibia0_u_t;
/************************************************************************
* *
* Description: This register is used to set up the length for a *
......@@ -2688,15 +2591,14 @@ typedef union ii_ibia0_u {
typedef union ii_ibls1_u {
uint64_t ii_ibls1_regval;
struct {
uint64_t i_length : 16;
uint64_t i_error : 1;
uint64_t i_rsvd_1 : 3;
uint64_t i_busy : 1;
uint64_t i_rsvd : 43;
uint64_t i_length:16;
uint64_t i_error:1;
uint64_t i_rsvd_1:3;
uint64_t i_busy:1;
uint64_t i_rsvd:43;
} ii_ibls1_fld_s;
} ii_ibls1_u_t;
/************************************************************************
* *
* This register should be loaded before a transfer is started. The *
......@@ -2710,13 +2612,12 @@ typedef union ii_ibls1_u {
typedef union ii_ibsa1_u {
uint64_t ii_ibsa1_regval;
struct {
uint64_t i_rsvd_1 : 7;
uint64_t i_addr : 33;
uint64_t i_rsvd : 24;
uint64_t i_rsvd_1:7;
uint64_t i_addr:33;
uint64_t i_rsvd:24;
} ii_ibsa1_fld_s;
} ii_ibsa1_u_t;
/************************************************************************
* *
* This register should be loaded before a transfer is started. The *
......@@ -2730,13 +2631,12 @@ typedef union ii_ibsa1_u {
typedef union ii_ibda1_u {
uint64_t ii_ibda1_regval;
struct {
uint64_t i_rsvd_1 : 7;
uint64_t i_addr : 33;
uint64_t i_rsvd : 24;
uint64_t i_rsvd_1:7;
uint64_t i_addr:33;
uint64_t i_rsvd:24;
} ii_ibda1_fld_s;
} ii_ibda1_u_t;
/************************************************************************
* *
* Writing to this register sets up the attributes of the transfer *
......@@ -2752,16 +2652,15 @@ typedef union ii_ibda1_u {
typedef union ii_ibct1_u {
uint64_t ii_ibct1_regval;
struct {
uint64_t i_zerofill : 1;
uint64_t i_rsvd_2 : 3;
uint64_t i_notify : 1;
uint64_t i_rsvd_1 : 3;
uint64_t i_poison : 1;
uint64_t i_rsvd : 55;
uint64_t i_zerofill:1;
uint64_t i_rsvd_2:3;
uint64_t i_notify:1;
uint64_t i_rsvd_1:3;
uint64_t i_poison:1;
uint64_t i_rsvd:55;
} ii_ibct1_fld_s;
} ii_ibct1_u_t;
/************************************************************************
* *
* This register contains the address to which the WINV is sent. *
......@@ -2772,13 +2671,12 @@ typedef union ii_ibct1_u {
typedef union ii_ibna1_u {
uint64_t ii_ibna1_regval;
struct {
uint64_t i_rsvd_1 : 7;
uint64_t i_addr : 33;
uint64_t i_rsvd : 24;
uint64_t i_rsvd_1:7;
uint64_t i_addr:33;
uint64_t i_rsvd:24;
} ii_ibna1_fld_s;
} ii_ibna1_u_t;
/************************************************************************
* *
* This register contains the programmable level as well as the node *
......@@ -2790,15 +2688,14 @@ typedef union ii_ibna1_u {
typedef union ii_ibia1_u {
uint64_t ii_ibia1_regval;
struct {
uint64_t i_pi_id : 1;
uint64_t i_node_id : 8;
uint64_t i_rsvd_1 : 7;
uint64_t i_level : 7;
uint64_t i_rsvd : 41;
uint64_t i_pi_id:1;
uint64_t i_node_id:8;
uint64_t i_rsvd_1:7;
uint64_t i_level:7;
uint64_t i_rsvd:41;
} ii_ibia1_fld_s;
} ii_ibia1_u_t;
/************************************************************************
* *
* This register defines the resources that feed information into *
......@@ -2817,14 +2714,13 @@ typedef union ii_ibia1_u {
typedef union ii_ipcr_u {
uint64_t ii_ipcr_regval;
struct {
uint64_t i_ippr0_c : 4;
uint64_t i_ippr1_c : 4;
uint64_t i_icct : 8;
uint64_t i_rsvd : 48;
uint64_t i_ippr0_c:4;
uint64_t i_ippr1_c:4;
uint64_t i_icct:8;
uint64_t i_rsvd:48;
} ii_ipcr_fld_s;
} ii_ipcr_u_t;
/************************************************************************
* *
* *
......@@ -2834,14 +2730,12 @@ typedef union ii_ipcr_u {
typedef union ii_ippr_u {
uint64_t ii_ippr_regval;
struct {
uint64_t i_ippr0 : 32;
uint64_t i_ippr1 : 32;
uint64_t i_ippr0:32;
uint64_t i_ippr1:32;
} ii_ippr_fld_s;
} ii_ippr_u_t;
/**************************************************************************
/************************************************************************
* *
* The following defines which were not formed into structures are *
* probably indentical to another register, and the name of the *
......@@ -2919,8 +2813,7 @@ typedef union ii_ippr_u {
* IIO_ICRBE_D IIO_ICRB0_D *
* IIO_ICRBE_E IIO_ICRB0_E *
* *
**************************************************************************/
************************************************************************/
/*
* Slightly friendlier names for some common registers.
......@@ -2935,7 +2828,7 @@ typedef union ii_ippr_u {
#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
#define IIO_LLP_LOG IIO_ILLR /* LLP log */
#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/
#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout */
#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
#define IIO_IGFX_0 IIO_IGFX0
......@@ -2960,7 +2853,7 @@ typedef union ii_ippr_u {
#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
#define IIO_NUM_IPRBS (9)
#define IIO_NUM_IPRBS 9
#define IIO_LLP_CSR_IS_UP 0x00002000
#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
......@@ -2990,7 +2883,6 @@ typedef union ii_ippr_u {
#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
/* names used in shub diags */
#define IIO_BASE_BTE0 IIO_IBLS_0
#define IIO_BASE_BTE1 IIO_IBLS_1
......@@ -3005,7 +2897,6 @@ typedef union ii_ippr_u {
(_x) : \
(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
/* GFX Flow Control Node/Widget Register */
#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
......@@ -3025,7 +2916,6 @@ typedef union ii_ippr_u {
(((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
(((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
/* Scratch registers (all bits available) */
#define IIO_SCRATCH_REG0 IIO_ISCR0
#define IIO_SCRATCH_REG1 IIO_ISCR1
......@@ -3242,16 +3132,16 @@ typedef union ii_ippr_u {
/*
* IIO CRB control register Fields: IIO_ICCR
*/
#define IIO_ICCR_PENDING (0x10000)
#define IIO_ICCR_CMD_MASK (0xFF)
#define IIO_ICCR_CMD_SHFT (7)
#define IIO_ICCR_CMD_NOP (0x0) /* No Op */
#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */
#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */
#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory
#define IIO_ICCR_PENDING 0x10000
#define IIO_ICCR_CMD_MASK 0xFF
#define IIO_ICCR_CMD_SHFT 7
#define IIO_ICCR_CMD_NOP 0x0 /* No Op */
#define IIO_ICCR_CMD_WAKE 0x100 /* Reactivate CRB entry and process */
#define IIO_ICCR_CMD_TIMEOUT 0x200 /* Make CRB timeout & mark invalid */
#define IIO_ICCR_CMD_EJECT 0x400 /* Contents of entry written to memory
* via a WB
*/
#define IIO_ICCR_CMD_FLUSH (0x800)
#define IIO_ICCR_CMD_FLUSH 0x800
/*
*
......@@ -3324,14 +3214,13 @@ typedef ii_icrb0_c_u_t icrbc_t;
#define c_source ii_icrb0_c_fld_s.ic_source
#define c_regvalue ii_icrb0_c_regval
typedef ii_icrb0_d_u_t icrbd_t;
#define d_sleep ii_icrb0_d_fld_s.id_sleep
#define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt
#define d_pripsc ii_icrb0_d_fld_s.id_pr_psc
#define d_bteop ii_icrb0_d_fld_s.id_bte_op
#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
#define d_regvalue ii_icrb0_d_regval
typedef ii_icrb0_e_u_t icrbe_t;
......@@ -3341,7 +3230,6 @@ typedef ii_icrb0_e_u_t icrbe_t;
#define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout
#define e_regvalue ii_icrb0_e_regval
/* Number of widgets supported by shub */
#define HUB_NUM_WIDGET 9
#define HUB_WIDGET_ID_MIN 0x8
......@@ -3369,8 +3257,8 @@ typedef ii_icrb0_e_u_t icrbe_t;
#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
#define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */
#define IIO_WSTAT_TXRETRY_SHFT (16)
#define IIO_WSTAT_TXRETRY_MASK 0x7F /* should be 0xFF?? */
#define IIO_WSTAT_TXRETRY_SHFT 16
#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
IIO_WSTAT_TXRETRY_MASK)
......@@ -3416,14 +3304,14 @@ typedef ii_icrb0_e_u_t icrbe_t;
typedef union hubii_wcr_u {
uint64_t wcr_reg_value;
struct {
uint64_t wcr_widget_id: 4, /* LLP crossbar credit */
wcr_tag_mode: 1, /* Tag mode */
wcr_rsvd1: 8, /* Reserved */
wcr_xbar_crd: 3, /* LLP crossbar credit */
wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
wcr_dir_con: 1, /* widget direct connect */
wcr_e_thresh: 5, /* elasticity threshold */
wcr_rsvd: 41; /* unused */
uint64_t wcr_widget_id:4, /* LLP crossbar credit */
wcr_tag_mode:1, /* Tag mode */
wcr_rsvd1:8, /* Reserved */
wcr_xbar_crd:3, /* LLP crossbar credit */
wcr_f_bad_pkt:1, /* Force bad llp pkt enable */
wcr_dir_con:1, /* widget direct connect */
wcr_e_thresh:5, /* elasticity threshold */
wcr_rsvd:41; /* unused */
} wcr_fields_s;
} hubii_wcr_t;
......@@ -3438,10 +3326,7 @@ performance registers */
typedef union io_perf_sel {
uint64_t perf_sel_reg;
struct {
uint64_t perf_ippr0 : 4,
perf_ippr1 : 4,
perf_icct : 8,
perf_rsvd : 48;
uint64_t perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
} perf_sel_bits;
} io_perf_sel_t;
......@@ -3451,9 +3336,7 @@ typedef union io_perf_sel {
typedef union io_perf_cnt {
uint64_t perf_cnt;
struct {
uint64_t perf_cnt : 20,
perf_rsvd2 : 12,
perf_rsvd1 : 32;
uint64_t perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
} perf_cnt_bits;
} io_perf_cnt_t;
......@@ -3461,16 +3344,15 @@ typedef union io_perf_cnt {
typedef union iprte_a {
uint64_t entry;
struct {
uint64_t i_rsvd_1 : 3;
uint64_t i_addr : 38;
uint64_t i_init : 3;
uint64_t i_source : 8;
uint64_t i_rsvd : 2;
uint64_t i_widget : 4;
uint64_t i_to_cnt : 5;
uint64_t i_vld : 1;
uint64_t i_rsvd_1:3;
uint64_t i_addr:38;
uint64_t i_init:3;
uint64_t i_source:8;
uint64_t i_rsvd:2;
uint64_t i_widget:4;
uint64_t i_to_cnt:5;
uint64_t i_vld:1;
} iprte_fields;
} iprte_a_t;
#endif /* _ASM_IA64_SN_SHUBIO_H */
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