Commit 4434c5c7 authored by Dan Williams's avatar Dan Williams Committed by Russell King

[ARM] 4186/1: iop: remove cp6_enable/disable routines

This functionality is replaced by cp6_trap
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent f80dff9d
...@@ -161,65 +161,49 @@ static void write_intsize(u32 val) ...@@ -161,65 +161,49 @@ static void write_intsize(u32 val)
static void static void
iop13xx_irq_mask0 (unsigned int irq) iop13xx_irq_mask0 (unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_0(read_intctl_0() & ~(1 << (irq - 0))); write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_mask1 (unsigned int irq) iop13xx_irq_mask1 (unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_1(read_intctl_1() & ~(1 << (irq - 32))); write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_mask2 (unsigned int irq) iop13xx_irq_mask2 (unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_2(read_intctl_2() & ~(1 << (irq - 64))); write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_mask3 (unsigned int irq) iop13xx_irq_mask3 (unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_3(read_intctl_3() & ~(1 << (irq - 96))); write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_unmask0(unsigned int irq) iop13xx_irq_unmask0(unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_0(read_intctl_0() | (1 << (irq - 0))); write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_unmask1(unsigned int irq) iop13xx_irq_unmask1(unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_1(read_intctl_1() | (1 << (irq - 32))); write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_unmask2(unsigned int irq) iop13xx_irq_unmask2(unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_2(read_intctl_2() | (1 << (irq - 64))); write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_unmask3(unsigned int irq) iop13xx_irq_unmask3(unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_3(read_intctl_3() | (1 << (irq - 96))); write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
iop13xx_cp6_restore(cp_flags);
} }
static struct irq_chip iop13xx_irqchip1 = { static struct irq_chip iop13xx_irqchip1 = {
...@@ -256,7 +240,6 @@ void __init iop13xx_init_irq(void) ...@@ -256,7 +240,6 @@ void __init iop13xx_init_irq(void)
{ {
unsigned int i; unsigned int i;
u32 cp_flags = iop13xx_cp6_save();
iop_init_cp6_handler(); iop_init_cp6_handler();
/* disable all interrupts */ /* disable all interrupts */
...@@ -288,6 +271,4 @@ void __init iop13xx_init_irq(void) ...@@ -288,6 +271,4 @@ void __init iop13xx_init_irq(void)
set_irq_handler(i, handle_level_irq); set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
} }
iop13xx_cp6_restore(cp_flags);
} }
...@@ -38,11 +38,8 @@ static inline u32 read_tcr1(void) ...@@ -38,11 +38,8 @@ static inline u32 read_tcr1(void)
unsigned long iop13xx_gettimeoffset(void) unsigned long iop13xx_gettimeoffset(void)
{ {
unsigned long offset; unsigned long offset;
u32 cp_flags;
cp_flags = iop13xx_cp6_save();
offset = next_jiffy_time - read_tcr1(); offset = next_jiffy_time - read_tcr1();
iop13xx_cp6_restore(cp_flags);
return offset / ticks_per_usec; return offset / ticks_per_usec;
} }
...@@ -50,8 +47,6 @@ unsigned long iop13xx_gettimeoffset(void) ...@@ -50,8 +47,6 @@ unsigned long iop13xx_gettimeoffset(void)
static irqreturn_t static irqreturn_t
iop13xx_timer_interrupt(int irq, void *dev_id) iop13xx_timer_interrupt(int irq, void *dev_id)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_seqlock(&xtime_lock); write_seqlock(&xtime_lock);
asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1)); asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
...@@ -64,8 +59,6 @@ iop13xx_timer_interrupt(int irq, void *dev_id) ...@@ -64,8 +59,6 @@ iop13xx_timer_interrupt(int irq, void *dev_id)
write_sequnlock(&xtime_lock); write_sequnlock(&xtime_lock);
iop13xx_cp6_restore(cp_flags);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
...@@ -78,7 +71,6 @@ static struct irqaction iop13xx_timer_irq = { ...@@ -78,7 +71,6 @@ static struct irqaction iop13xx_timer_irq = {
void __init iop13xx_init_time(unsigned long tick_rate) void __init iop13xx_init_time(unsigned long tick_rate)
{ {
u32 timer_ctl; u32 timer_ctl;
u32 cp_flags;
ticks_per_jiffy = (tick_rate + HZ/2) / HZ; ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
ticks_per_usec = tick_rate / 1000000; ticks_per_usec = tick_rate / 1000000;
...@@ -91,12 +83,10 @@ void __init iop13xx_init_time(unsigned long tick_rate) ...@@ -91,12 +83,10 @@ void __init iop13xx_init_time(unsigned long tick_rate)
* We use timer 0 for our timer interrupt, and timer 1 as * We use timer 0 for our timer interrupt, and timer 1 as
* monotonic counter for tracking missed jiffies. * monotonic counter for tracking missed jiffies.
*/ */
cp_flags = iop13xx_cp6_save();
asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1)); asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl)); asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff)); asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl)); asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
iop13xx_cp6_restore(cp_flags);
setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq); setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
} }
...@@ -23,16 +23,12 @@ static u32 iop32x_mask; ...@@ -23,16 +23,12 @@ static u32 iop32x_mask;
static inline void intctl_write(u32 val) static inline void intctl_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intstr_write(u32 val) static inline void intstr_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static void static void
......
...@@ -24,44 +24,32 @@ static u32 iop33x_mask1; ...@@ -24,44 +24,32 @@ static u32 iop33x_mask1;
static inline void intctl0_write(u32 val) static inline void intctl0_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intctl1_write(u32 val) static inline void intctl1_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intstr0_write(u32 val) static inline void intstr0_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intstr1_write(u32 val) static inline void intstr1_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intbase_write(u32 val) static inline void intbase_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intsize_write(u32 val) static inline void intsize_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static void static void
......
...@@ -51,9 +51,7 @@ iop3xx_timer_interrupt(int irq, void *dev_id) ...@@ -51,9 +51,7 @@ iop3xx_timer_interrupt(int irq, void *dev_id)
{ {
write_seqlock(&xtime_lock); write_seqlock(&xtime_lock);
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1)); asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
iop3xx_cp6_disable();
while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
>= ticks_per_jiffy) { >= ticks_per_jiffy) {
...@@ -87,12 +85,10 @@ void __init iop3xx_init_time(unsigned long tick_rate) ...@@ -87,12 +85,10 @@ void __init iop3xx_init_time(unsigned long tick_rate)
* We use timer 0 for our timer interrupt, and timer 1 as * We use timer 0 for our timer interrupt, and timer 1 as
* monotonic counter for tracking missed jiffies. * monotonic counter for tracking missed jiffies.
*/ */
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1));
asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff));
asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl)); asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
iop3xx_cp6_disable();
setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq); setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
} }
...@@ -12,32 +12,6 @@ void iop13xx_init_irq(void); ...@@ -12,32 +12,6 @@ void iop13xx_init_irq(void);
void iop13xx_init_time(unsigned long tickrate); void iop13xx_init_time(unsigned long tickrate);
unsigned long iop13xx_gettimeoffset(void); unsigned long iop13xx_gettimeoffset(void);
/* handle cp6 access
* to do: handle access in entry-armv5.S and unify with
* the iop3xx implementation
* note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
* when interrupts are enabled
*/
static inline unsigned long iop13xx_cp6_save(void)
{
u32 temp, cp_flags;
asm volatile (
"mrc p15, 0, %1, c15, c1, 0\n\t"
"orr %0, %1, #(1 << 6)\n\t"
"mcr p15, 0, %0, c15, c1, 0\n\t"
: "=r" (temp), "=r"(cp_flags));
return cp_flags;
}
static inline void iop13xx_cp6_restore(unsigned long cp_flags)
{
asm volatile (
"mcr p15, 0, %0, c15, c1, 0\n\t"
: : "r" (cp_flags) );
}
/* CPUID CP6 R0 Page 0 */ /* CPUID CP6 R0 Page 0 */
static inline int iop13xx_cpu_id(void) static inline int iop13xx_cpu_id(void)
{ {
......
...@@ -3,8 +3,6 @@ ...@@ -3,8 +3,6 @@
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
#include <linux/types.h> #include <linux/types.h>
#include <asm/system.h> /* local_irq_save */
#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
/* INTPND0 CP6 R0 Page 3 /* INTPND0 CP6 R0 Page 3
*/ */
...@@ -41,21 +39,6 @@ static inline u32 read_intpnd_3(void) ...@@ -41,21 +39,6 @@ static inline u32 read_intpnd_3(void)
asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
return val; return val;
} }
static inline void
iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
{
local_irq_save(*irq_flags);
*cp_flags = iop13xx_cp6_save();
}
static inline void
iop13xx_cp6_irq_restore(unsigned long *cp_flags,
unsigned long *irq_flags)
{
iop13xx_cp6_restore(*cp_flags);
local_irq_restore(*irq_flags);
}
#endif #endif
#define INTBASE 0 #define INTBASE 0
......
...@@ -48,12 +48,10 @@ static inline void arch_reset(char mode) ...@@ -48,12 +48,10 @@ static inline void arch_reset(char mode)
/* /*
* Reset the internal bus (warning both cores are reset) * Reset the internal bus (warning both cores are reset)
*/ */
u32 cp_flags = iop13xx_cp6_save();
write_wdtcr(IOP13XX_WDTCR_EN_ARM); write_wdtcr(IOP13XX_WDTCR_EN_ARM);
write_wdtcr(IOP13XX_WDTCR_EN); write_wdtcr(IOP13XX_WDTCR_EN);
write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
write_wdtcr(0x1000); write_wdtcr(0x1000);
iop13xx_cp6_restore(cp_flags);
for(;;); for(;;);
} }
...@@ -283,33 +283,6 @@ void iop_init_cp6_handler(void); ...@@ -283,33 +283,6 @@ void iop_init_cp6_handler(void);
extern struct platform_device iop3xx_i2c0_device; extern struct platform_device iop3xx_i2c0_device;
extern struct platform_device iop3xx_i2c1_device; extern struct platform_device iop3xx_i2c1_device;
extern inline void iop3xx_cp6_enable(void)
{
u32 temp;
asm volatile (
"mrc p15, 0, %0, c15, c1, 0\n\t"
"orr %0, %0, #(1 << 6)\n\t"
"mcr p15, 0, %0, c15, c1, 0\n\t"
"mrc p15, 0, %0, c15, c1, 0\n\t"
"mov %0, %0\n\t"
"sub pc, pc, #4\n\t"
: "=r" (temp) );
}
extern inline void iop3xx_cp6_disable(void)
{
u32 temp;
asm volatile (
"mrc p15, 0, %0, c15, c1, 0\n\t"
"bic %0, %0, #(1 << 6)\n\t"
"mcr p15, 0, %0, c15, c1, 0\n\t"
"mrc p15, 0, %0, c15, c1, 0\n\t"
"mov %0, %0\n\t"
"sub pc, pc, #4\n\t"
: "=r" (temp) );
}
#endif #endif
......
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