Commit 45a284bc authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas

arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable()

__flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after
writing the new table entry and therefore avoid the barrier prior to the
TLBI instruction.

In preparation for delaying our walk-cache invalidation on the unmap()
path, move the DSB into the TLB invalidation routines.
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 6899a4c8
...@@ -213,6 +213,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, ...@@ -213,6 +213,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm,
{ {
unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm)); unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm));
dsb(ishst);
__tlbi(vae1is, addr); __tlbi(vae1is, addr);
__tlbi_user(vae1is, addr); __tlbi_user(vae1is, addr);
dsb(ish); dsb(ish);
...@@ -222,6 +223,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) ...@@ -222,6 +223,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
{ {
unsigned long addr = __TLBI_VADDR(kaddr, 0); unsigned long addr = __TLBI_VADDR(kaddr, 0);
dsb(ishst);
__tlbi(vaae1is, addr); __tlbi(vaae1is, addr);
dsb(ish); dsb(ish);
} }
......
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