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Commit 482c3e88 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "A couple of interesting new SoC platforms are now supported, these are
  the respective DTS sources:

   - Samsung Exynos5433 mobile phone platform, including an (almost)
     fully supported phone reference board.
   - Hisilicon Hip07 server platform and D05 board, the latest iteration
     of their product line, now with 64 Cortex-A72 cores across two
     sockets.
   - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product
     line, used in Android tablets and ultra-cheap development boards
   - NXP LS1046A Communication processor, improving on the earlier
     LS1043A with faster CPU cores
   - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810)
     mobile phone SoCs
   - Early support for the Nvidia Tegra Tegra186 SoC
   - Amlogic S905D is a minor variant of their existing Android consumer
     product line
   - Rockchip PX5 automotive platform, a close relative of their popular
     rk3368 Android tablet chips

  Aside from the respective evaluation platforms for the above chips,
  there are only a few consumer devices and boards added this time:

   - Huawei Nexus 6P (Angler) mobile phone
   - LG Nexus 5x (Bullhead) mobile phone
   - Nexbox A1 and A95X Android TV boxes
   - Pine64 development board based on Allwinner A64
   - Globalscale Marvell ESPRESSOBin community board based on Armada 3700
   - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

  For the existing platforms, we get bug fixes and new peripheral
  support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom,
  Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits)
  arm64: dts: fix build errors from missing dependencies
  ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible
  ARM64: dts: meson-gxl: Add support for Nexbox A95X
  ARM64: dts: meson-gxm: Add support for the Nexbox A1
  ARM: dts: artpec: add pcie support
  arm64: dts: berlin4ct-dmp: add missing unit name to /memory node
  arm64: dts: berlin4ct-stb: add missing unit name to /memory node
  arm64: dts: berlin4ct: add missing unit name to /soc node
  arm64: dts: qcom: msm8916: Add ddr support to sdhc1
  arm64: dts: exynos: Enable HS400 mode for eMMC for TM2
  ARM: dts: Add xo to sdhc clock node on qcom platforms
  ARM64: dts: Add support for Meson GXM
  dt-bindings: add rockchip RK1108 Evaluation board
  arm64: dts: NS2: Add PCI PHYs
  arm64: dts: NS2: enable sdio1
  arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash
  arm64: tegra: Add NVIDIA P2771 board support
  arm64: tegra: Enable PSCI on P3310
  arm64: tegra: Add NVIDIA P3310 processor module support
  arm64: tegra: Add GPIO controllers on Tegra186
  ...
parents 786a72d7 09a56651
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Documentation/devicetree/bindings/arm/amlogic.txt
View file @ 482c3e88
......@@ -17,6 +17,18 @@ Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson-gxbb";
Boards with the Amlogic Meson GXL S905X SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905x", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXL S905D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905d", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
Board compatible values:
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
......@@ -28,3 +40,10 @@ Board compatible values:
- "hardkernel,odroid-c2" (Meson gxbb)
- "amlogic,p200" (Meson gxbb)
- "amlogic,p201" (Meson gxbb)
- "amlogic,p212" (Meson gxl s905x)
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
- "nexbox,a1" (Meson gxm s912)
Documentation/devicetree/bindings/arm/fsl.txt
View file @ 482c3e88
......@@ -97,7 +97,7 @@ Freescale LS1021A Platform Device Tree Bindings
Required root node compatible properties:
- compatible = "fsl,ls1021a";
Freescale LS1021A SoC-specific Device Tree Bindings
Freescale SoC-specific Device Tree Bindings
-------------------------------------------
Freescale SCFG
......@@ -105,7 +105,11 @@ Freescale SCFG
configuration and status registers for the chip. Such as getting PEX port
status.
Required properties:
- compatible: should be "fsl,ls1021a-scfg"
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-scfg",
The following <chip>s are known to be supported:
ls1021a, ls1043a, ls1046a, ls2080a.
- reg: should contain base address and length of SCFG memory-mapped registers
Example:
......@@ -119,7 +123,11 @@ Freescale DCFG
configuration and status for the device. Such as setting the secondary
core start address and release the secondary core from holdoff and startup.
Required properties:
- compatible: should be "fsl,ls1021a-dcfg"
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
ls1021a, ls1043a, ls1046a, ls2080a.
- reg : should contain base address and length of DCFG memory-mapped registers
Example:
......@@ -131,6 +139,10 @@ Example:
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
----------------------------------------------------------------
LS1043A SoC
Required root node properties:
- compatible = "fsl,ls1043a";
LS1043A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
......@@ -139,6 +151,22 @@ LS1043A ARMv8 based QDS Board
Required root node properties:
- compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
LS1046A SoC
Required root node properties:
- compatible = "fsl,ls1046a";
LS1046A ARMv8 based QDS Board
Required root node properties:
- compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
LS1046A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
LS2080A SoC
Required root node properties:
- compatible = "fsl,ls2080a";
LS2080A ARMv8 based Simulator model
Required root node properties:
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
......
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View file @ 482c3e88
......@@ -28,6 +28,10 @@ HiP06 D03 Board
Required root node properties:
- compatible = "hisilicon,hip06-d03";
HiP07 D05 Board
Required root node properties:
- compatible = "hisilicon,hip07-d05";
Hisilicon system controller
Required properties:
......
Documentation/devicetree/bindings/arm/qcom.txt
View file @ 482c3e88
......@@ -21,6 +21,8 @@ The 'SoC' element must be one of the following strings:
apq8096
msm8916
msm8974
msm8992
msm8994
msm8996
mdm9615
......
Documentation/devicetree/bindings/arm/rockchip.txt
View file @ 482c3e88
......@@ -103,6 +103,18 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "mqmaker,miqi", "rockchip,rk3288";
- Rockchip PX3 Evaluation board:
Required root node properties:
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
- Rockchip PX5 Evaluation board:
Required root node properties:
- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
- Rockchip RK1108 Evaluation board
Required root node properties:
- compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
- Rockchip RK3368 evb:
Required root node properties:
- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
......
Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
View file @ 482c3e88
......@@ -15,6 +15,8 @@ Required root node properties:
- "samsung,xyref5260" - for Exynos5260-based Samsung board.
- "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
- "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
- "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
- "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
- "samsung,sd5v1" - for Exynos5440-based Samsung board.
- "samsung,ssdk5440" - for Exynos5440-based Samsung board.
......
Documentation/devicetree/bindings/arm/shmobile.txt
View file @ 482c3e88
......@@ -53,7 +53,7 @@ Boards:
compatible = "renesas,genmai", "renesas,r7s72100"
- Gose (RTP0RC7793SEB00010S)
compatible = "renesas,gose", "renesas,r8a7793"
- H3ULCB (RTP0RC7795SKB00010S)
- H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S)
compatible = "renesas,h3ulcb", "renesas,r8a7795";
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
......@@ -65,6 +65,8 @@ Boards:
compatible = "renesas,kzm9g", "renesas,sh73a0"
- Lager (RTP0RC7790SEB00010S)
compatible = "renesas,lager", "renesas,r8a7790"
- M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S)
compatible = "renesas,m3ulcb", "renesas,r8a7796";
- Marzen (R0P7779A00010S)
compatible = "renesas,marzen", "renesas,r8a7779"
- Porter (M2-LCDP)
......
Documentation/devicetree/bindings/arm/sunxi.txt
View file @ 482c3e88
......@@ -14,4 +14,5 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h3
allwinner,sun9i-a80
allwinner,sun50i-a64
nextthing,gr8
Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
View file @ 482c3e88
......@@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
Required properties:
- reg: Physical base address and size of the controller's register area.
- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
chip could be ls1021a, ls2080a, ls1043a etc.
chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
- clocks: Input clock specifier. Refer to common clock bindings.
- interrupts: Interrupt specifier. Refer to interrupt binding.
......
Documentation/devicetree/bindings/clock/qoriq-clock.txt
View file @ 482c3e88
......@@ -32,6 +32,9 @@ Required properties:
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
* "fsl,ls1021a-clockgen"
* "fsl,ls1043a-clockgen"
* "fsl,ls1046a-clockgen"
* "fsl,ls2080a-clockgen"
Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
......
Documentation/devicetree/bindings/i2c/trivial-devices.txt
View file @ 482c3e88
......@@ -138,6 +138,8 @@ nuvoton,npct501 i2c trusted platform module (TPM)
nuvoton,npct601 i2c trusted platform module (TPM2)
nxp,pca9556 Octal SMBus and I2C registered interface
nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
nxp,pcf2127 Real-time clock
nxp,pcf2129 Real-time clock
nxp,pcf8563 Real-time clock/calendar
nxp,pcf85063 Tiny Real-Time Clock
oki,ml86v7667 OKI ML86V7667 video decoder
......
Documentation/devicetree/bindings/media/renesas,fcp.txt
View file @ 482c3e88
......@@ -11,15 +11,9 @@ are paired with. These DT bindings currently support the FCPV and FCPF.
- compatible: Must be one or more of the following
- "renesas,r8a7795-fcpv" for R8A7795 (R-Car H3) compatible 'FCP for VSP'
- "renesas,r8a7795-fcpf" for R8A7795 (R-Car H3) compatible 'FCP for FDP'
- "renesas,fcpv" for generic compatible 'FCP for VSP'
- "renesas,fcpf" for generic compatible 'FCP for FDP'
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first, followed by the
family-specific and/or generic versions.
- reg: the register base and size for the device registers
- clocks: Reference to the functional clock
......@@ -32,7 +26,7 @@ Device node example
-------------------
fcpvd1: fcp@fea2f000 {
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7795_PD_A3VP>;
......
Documentation/devicetree/bindings/vendor-prefixes.txt
View file @ 482c3e88
......@@ -197,6 +197,7 @@ neonode Neonode Inc.
netgear NETGEAR
netlogic Broadcom Corporation (formerly NetLogic Microsystems)
netxeon Shenzhen Netxeon Technology CO., LTD
nexbox Nexbox
newhaven Newhaven Display International
ni National Instruments
nintendo Nintendo
......@@ -222,6 +223,7 @@ parade Parade Technologies Inc.
pericom Pericom Technology Inc.
phytec PHYTEC Messtechnik GmbH
picochip Picochip Ltd
pine64 Pine64
pixcir PIXCIR MICROELECTRONICS Co., Ltd
plathome Plat'Home Co., Ltd.
plda PLDA
......
MAINTAINERS
View file @ 482c3e88
......@@ -1042,6 +1042,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
N: sun[x456789]i
F: arch/arm/boot/dts/ntc-gr8*
F: arch/arm64/boot/dts/allwinner/
ARM/Allwinner SoC Clock Support
M: Emilio López <emilio@elopez.com.ar>
......
arch/arm64/boot/dts/Makefile
View file @ 482c3e88
dts-dirs += al
dts-dirs += allwinner
dts-dirs += altera
dts-dirs += amd
dts-dirs += amlogic
......
arch/arm64/boot/dts/allwinner/Makefile 0 → 100644
View file @ 482c3e88
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sun50i-a64-pine64.dts"
/ {
model = "Pine64+";
compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
/* TODO: Camera, Ethernet PHY, touchscreen, etc. */
};
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-a64.dtsi"
/ {
model = "Pine64";
compatible = "pine64,pine64", "allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c1_pins {
bias-pull-up;
};
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 0 → 100644
View file @ 482c3e88
/*
* Copyright (C) 2016 ARM Ltd.
* based on the Allwinner H3 dtsi:
* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
};
};
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ccu: clock@01c20000 {
compatible = "allwinner,sun50i-a64-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
pio: pinctrl@1c20800 {
compatible = "allwinner,sun50i-a64-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 58>;
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
i2c1_pins: i2c1_pins {
pins = "PH2", "PH3";
function = "i2c1";
};
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
};
};
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 67>;
resets = <&ccu 46>;
status = "disabled";
};
uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 68>;
resets = <&ccu 47>;
status = "disabled";
};
uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 69>;
resets = <&ccu 48>;
status = "disabled";
};
uart3: serial@1c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 70>;
resets = <&ccu 49>;
status = "disabled";
};
uart4: serial@1c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 71>;
resets = <&ccu 50>;
status = "disabled";
};
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 63>;
resets = <&ccu 42>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@1c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 64>;
resets = <&ccu 43>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@1c2b400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 65>;
resets = <&ccu 44>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
#interrupt-cells = <3>;
};
rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
arch/arm64/boot/dts/amlogic/Makefile
View file @ 482c3e88
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either
* the pin-compatible S912 (GXM) or S905D (GXL) SoCs.
*/
/ {
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
};
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&ethmac {
status = "okay";
};
arch/arm64/boot/dts/amlogic/meson-gx.dtsi 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Andreas Färber
*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
firmware {
sm: secure-monitor {
compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
};
};
efuse: efuse {
compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
#address-cells = <1>;
#size-cells = <1>;
sn: sn@14 {
reg = <0x14 0x10>;
};
eth_mac: eth_mac@34 {
reg = <0x34 0x10>;
};
bid: bid@46 {
reg = <0x46 0x30>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
cbus: cbus@c1100000 {
compatible = "simple-bus";
reg = <0x0 0xc1100000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
reset: reset-controller@4404 {
compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
reg = <0x0 0x04404 0x0 0x20>;
#reset-cells = <1>;
};
uart_A: serial@84c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x84c0 0x0 0x14>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
uart_B: serial@84dc {
compatible = "amlogic,meson-uart";
reg = <0x0 0x84dc 0x0 0x14>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
i2c_A: i2c@8500 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x08500 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm_ab: pwm@8550 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x08550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_cd: pwm@8650 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x08650 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
uart_C: serial@8700 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x8700 0x0 0x14>;
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
i2c_B: i2c@87c0 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087c0 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_C: i2c@87e0 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087e0 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
watchdog@98d0 {
compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
reg = <0x0 0x098d0 0x0 0x10>;
clocks = <&xtal>;
};
};
gic: interrupt-controller@c4301000 {
compatible = "arm,gic-400";
reg = <0x0 0xc4301000 0 0x1000>,
<0x0 0xc4302000 0 0x2000>,
<0x0 0xc4304000 0 0x2000>,
<0x0 0xc4306000 0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
aobus: aobus@c8100000 {
compatible = "simple-bus";
reg = <0x0 0xc8100000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
ir: ir@580 {
compatible = "amlogic,meson-gxbb-ir";
reg = <0x0 0x00580 0x0 0x40>;
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};
periphs: periphs@c8834000 {
compatible = "simple-bus";
reg = <0x0 0xc8834000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
};
hiubus: hiubus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
mailbox: mailbox@404 {
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
reg = <0 0x404 0 0x4c>;
interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
<0 209 IRQ_TYPE_EDGE_RISING>,
<0 210 IRQ_TYPE_EDGE_RISING>;
#mbox-cells = <1>;
};
};
ethmac: ethernet@c9410000 {
compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
reg = <0x0 0xc9410000 0x0 0x10000
0x0 0xc8834540 0x0 0x4>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
phy-mode = "rgmii";
status = "disabled";
};
apb: apb@d0000000 {
compatible = "simple-bus";
reg = <0x0 0xd0000000 0x0 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
sd_emmc_a: mmc@70000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x70000 0x0 0x2000>;
interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
sd_emmc_b: mmc@72000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x72000 0x0 0x2000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
sd_emmc_c: mmc@74000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x74000 0x0 0x2000>;
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};
};
};
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Neil Armstrong <narmstrong@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxbb.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "nexbox,a95x", "amlogic,meson-gxbb";
model = "NEXBOX A95X";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
leds {
compatible = "gpio-leds";
blue {
label = "a95x:system-status";
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
};
};
vddio_card: gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "VDDIO_CARD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
states = <1800000 0
3300000 1>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rmii_pins>;
pinctrl-names = "default";
phy-mode = "rmii";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_card>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
View file @ 482c3e88
......@@ -64,6 +64,18 @@ memory@0 {
reg = <0x0 0x0 0x0 0x80000000>;
};
usb_otg_pwr: regulator-usb-pwrs {
compatible = "regulator-fixed";
regulator-name = "USB_OTG_PWR";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
leds {
compatible = "gpio-leds";
blue {
......@@ -73,6 +85,56 @@ blue {
default-state = "off";
};
};
tflash_vdd: regulator-tflash_vdd {
/*
* signal name from schematics: TFLASH_VDD_EN
*/
compatible = "regulator-fixed";
regulator-name = "TFLASH_VDD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_ao GPIOAO_12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
tf_io: gpio-regulator-tf_io {
compatible = "regulator-gpio";
regulator-name = "TF_IO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
/*
* signal name from schematics: TF_3V3N_1V8_EN
*/
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <3300000 0
1800000 1>;
};
vcc1v8: regulator-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
};
&uart_AO {
......@@ -83,7 +145,7 @@ &uart_AO {
&ethmac {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
};
......@@ -98,3 +160,58 @@ &i2c_A {
pinctrl-0 = <&i2c_a_pins>;
pinctrl-names = "default";
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_otg_pwr>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
/* SD */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&tflash_vdd>;
vqmmc-supply = <&tf_io>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc3v3>;
vqmmc-supply = <&vcc1v8>;
};
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
View file @ 482c3e88
......@@ -70,6 +70,61 @@ usb_pwr: regulator-usb-pwrs {
gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vddio_card: gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "VDDIO_CARD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
states = <1800000 0
3300000 1>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
};
/* This UART is brought out to the DB9 connector */
......@@ -81,7 +136,7 @@ &uart_AO {
&ethmac {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
};
......@@ -107,3 +162,75 @@ &usb0 {
&usb1 {
status = "okay";
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_card>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
View file @ 482c3e88
......@@ -65,6 +65,39 @@ usb_vbus: regulator-usb0-vbus {
enable-active-high;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_1v8: regulator-vcc_1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>,
<&gpio GPIOX_20 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
};
&uart_AO {
......@@ -82,7 +115,7 @@ &ir {
&ethmac {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
};
......@@ -102,3 +135,74 @@ &usb0 {
&usb1 {
status = "okay";
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins &sdio_irq_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vcc_3v3>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vmmcq-sumpply = <&vcc_1v8>;
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View file @ 482c3e88
......@@ -40,9 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "meson-gx.dtsi"
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
#include <dt-bindings/clock/gxbb-clkc.h>
......@@ -51,106 +49,30 @@
/ {
compatible = "amlogic,meson-gxbb";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
scpi {
compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
mboxes = <&mailbox 1 &mailbox 2>;
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
clocks {
compatible = "arm,scpi-clocks";
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
firmware {
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
};
};
efuse: efuse {
compatible = "amlogic,meson-gxbb-efuse";
#address-cells = <1>;
#size-cells = <1>;
sn: sn@14 {
reg = <0x14 0x10>;
};
eth_mac: eth_mac@34 {
reg = <0x34 0x10>;
scpi_dvfs: scpi_clocks@0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>;
clock-output-names = "vcpu";
};
};
bid: bid@46 {
reg = <0x46 0x30>;
scpi_sensors: sensors {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
usb0_phy: phy@c0000000 {
compatible = "amlogic,meson-gxbb-usb2-phy";
#phy-cells = <0>;
......@@ -165,505 +87,422 @@ usb1_phy: phy@c0000020 {
compatible = "amlogic,meson-gxbb-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0xc0000020 0x0 0x20>;
resets = <&reset RESET_USB_OTG>;
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
clock-names = "usb_general", "usb";
status = "disabled";
};
cbus: cbus@c1100000 {
compatible = "simple-bus";
reg = <0x0 0xc1100000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
sram: sram@c8000000 {
compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
reg = <0x0 0xc8000000 0x0 0x14000>;
reset: reset-controller@4404 {
compatible = "amlogic,meson-gxbb-reset";
reg = <0x0 0x04404 0x0 0x20>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0xc8000000 0x14000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "amlogic,meson-gxbb-scp-shmem";
reg = <0x13000 0x400>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "amlogic,meson-gxbb-scp-shmem";
reg = <0x13400 0x400>;
};
};
usb0: usb@c9000000 {
compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
reg = <0x0 0xc9000000 0x0 0x40000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
clock-names = "otg";
phys = <&usb0_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
status = "disabled";
};
usb1: usb@c9100000 {
compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
reg = <0x0 0xc9100000 0x0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "otg";
phys = <&usb1_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
status = "disabled";
};
};
};
&cpu0 {
clocks = <&scpi_dvfs 0>;
};
&cpu1 {
clocks = <&scpi_dvfs 0>;
};
&cpu2 {
clocks = <&scpi_dvfs 0>;
};
&cpu3 {
clocks = <&scpi_dvfs 0>;
};
&cbus {
spifc: spi@8c80 {
compatible = "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SPI>;
status = "disabled";
};
};
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
};
&aobus {
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-gxbb-aobus-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio_ao: bank@14 {
reg = <0x0 0x00014 0x0 0x8>,
<0x0 0x0002c 0x0 0x4>,
<0x0 0x00024 0x0 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
uart_A: serial@84c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x84c0 0x0 0x14>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
};
};
uart_B: serial@84dc {
compatible = "amlogic,meson-uart";
reg = <0x0 0x84dc 0x0 0x14>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
remote_input_ao_pins: remote_input_ao {
mux {
groups = "remote_input_ao";
function = "remote_input_ao";
};
};
pwm_ab: pwm@8550 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x08550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
i2c_ao_pins: i2c_ao {
mux {
groups = "i2c_sck_ao",
"i2c_sda_ao";
function = "i2c_ao";
};
};
pwm_cd: pwm@8650 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x08650 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
pwm_ao_a_3_pins: pwm_ao_a_3 {
mux {
groups = "pwm_ao_a_3";
function = "pwm_ao_a_3";
};
};
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
pwm_ao_a_6_pins: pwm_ao_a_6 {
mux {
groups = "pwm_ao_a_6";
function = "pwm_ao_a_6";
};
};
uart_C: serial@8700 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x8700 0x0 0x14>;
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
pwm_ao_a_12_pins: pwm_ao_a_12 {
mux {
groups = "pwm_ao_a_12";
function = "pwm_ao_a_12";
};
};
watchdog@98d0 {
compatible = "amlogic,meson-gxbb-wdt";
reg = <0x0 0x098d0 0x0 0x10>;
clocks = <&xtal>;
pwm_ao_b_pins: pwm_ao_b {
mux {
groups = "pwm_ao_b";
function = "pwm_ao_b";
};
};
};
clkc_AO: clock-controller@040 {
compatible = "amlogic,gxbb-aoclkc";
reg = <0x0 0x00040 0x0 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pwm_ab_AO: pwm@550 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x0550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x500 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_AO_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@4b0 {
reg = <0x0 0x004b0 0x0 0x28>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00120 0x0 0x14>,
<0x0 0x00430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
spifc: spi@8c80 {
compatible = "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SPI>;
status = "disabled";
emmc_pins: emmc {
mux {
groups = "emmc_nand_d07",
"emmc_cmd",
"emmc_clk",
"emmc_ds";
function = "emmc";
};
};
i2c_A: i2c@8500 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x08500 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
nor_pins: nor {
mux {
groups = "nor_d",
"nor_q",
"nor_c",
"nor_cs";
function = "nor";
};
};
i2c_B: i2c@87c0 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087c0 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
"sdcard_d1",
"sdcard_d2",
"sdcard_d3",
"sdcard_cmd",
"sdcard_clk";
function = "sdcard";
};
};
i2c_C: i2c@87e0 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087e0 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sdio_pins: sdio {
mux {
groups = "sdio_d0",
"sdio_d1",
"sdio_d2",
"sdio_d3",
"sdio_cmd",
"sdio_clk";
function = "sdio";
};
};
gic: interrupt-controller@c4301000 {
compatible = "arm,gic-400";
reg = <0x0 0xc4301000 0 0x1000>,
<0x0 0xc4302000 0 0x2000>,
<0x0 0xc4304000 0 0x2000>,
<0x0 0xc4306000 0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
aobus: aobus@c8100000 {
compatible = "simple-bus";
reg = <0x0 0xc8100000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-gxbb-aobus-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio_ao: bank@14 {
reg = <0x0 0x00014 0x0 0x8>,
<0x0 0x0002c 0x0 0x4>,
<0x0 0x00024 0x0 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
};
};
remote_input_ao_pins: remote_input_ao {
mux {
groups = "remote_input_ao";
function = "remote_input_ao";
};
};
i2c_ao_pins: i2c_ao {
mux {
groups = "i2c_sck_ao",
"i2c_sda_ao";
function = "i2c_ao";
};
};
pwm_ao_a_3_pins: pwm_ao_a_3 {
mux {
groups = "pwm_ao_a_3";
function = "pwm_ao_a_3";
};
};
pwm_ao_a_6_pins: pwm_ao_a_6 {
mux {
groups = "pwm_ao_a_6";
function = "pwm_ao_a_6";
};
};
pwm_ao_a_12_pins: pwm_ao_a_12 {
mux {
groups = "pwm_ao_a_12";
function = "pwm_ao_a_12";
};
};
pwm_ao_b_pins: pwm_ao_b {
mux {
groups = "pwm_ao_b";
function = "pwm_ao_b";
};
};
sdio_irq_pins: sdio_irq {
mux {
groups = "sdio_irq";
function = "sdio";
};
};
clkc_AO: clock-controller@040 {
compatible = "amlogic,gxbb-aoclkc";
reg = <0x0 0x00040 0x0 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
uart_a_pins: uart_a {
mux {
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
};
};
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
uart_b_pins: uart_b {
mux {
groups = "uart_tx_b",
"uart_rx_b";
function = "uart_b";
};
};
ir: ir@580 {
compatible = "amlogic,meson-gxbb-ir";
reg = <0x0 0x00580 0x0 0x40>;
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
uart_c_pins: uart_c {
mux {
groups = "uart_tx_c",
"uart_rx_c";
function = "uart_c";
};
};
pwm_ab_AO: pwm@550 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x0550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
i2c_a_pins: i2c_a {
mux {
groups = "i2c_sck_a",
"i2c_sda_a";
function = "i2c_a";
};
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x500 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_AO_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
i2c_b_pins: i2c_b {
mux {
groups = "i2c_sck_b",
"i2c_sda_b";
function = "i2c_b";
};
};
periphs: periphs@c8834000 {
compatible = "simple-bus";
reg = <0x0 0xc8834000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
i2c_c_pins: i2c_c {
mux {
groups = "i2c_sck_c",
"i2c_sda_c";
function = "i2c_c";
};
};
rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
eth_rgmii_pins: eth-rgmii {
mux {
groups = "eth_mdio",
"eth_mdc",
"eth_clk_rx_clk",
"eth_rx_dv",
"eth_rxd0",
"eth_rxd1",
"eth_rxd2",
"eth_rxd3",
"eth_rgmii_tx_clk",
"eth_tx_en",
"eth_txd0",
"eth_txd1",
"eth_txd2",
"eth_txd3";
function = "eth";
};
};
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@4b0 {
reg = <0x0 0x004b0 0x0 0x28>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00120 0x0 0x14>,
<0x0 0x00430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
emmc_pins: emmc {
mux {
groups = "emmc_nand_d07",
"emmc_cmd",
"emmc_clk";
function = "emmc";
};
};
nor_pins: nor {
mux {
groups = "nor_d",
"nor_q",
"nor_c",
"nor_cs";
function = "nor";
};
};
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
"sdcard_d1",
"sdcard_d2",
"sdcard_d3",
"sdcard_cmd",
"sdcard_clk";
function = "sdcard";
};
};
sdio_pins: sdio {
mux {
groups = "sdio_d0",
"sdio_d1",
"sdio_d2",
"sdio_d3",
"sdio_cmd",
"sdio_clk";
function = "sdio";
};
};
sdio_irq_pins: sdio_irq {
mux {
groups = "sdio_irq";
function = "sdio";
};
};
uart_a_pins: uart_a {
mux {
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
};
};
uart_b_pins: uart_b {
mux {
groups = "uart_tx_b",
"uart_rx_b";
function = "uart_b";
};
};
uart_c_pins: uart_c {
mux {
groups = "uart_tx_c",
"uart_rx_c";
function = "uart_c";
};
};
i2c_a_pins: i2c_a {
mux {
groups = "i2c_sck_a",
"i2c_sda_a";
function = "i2c_a";
};
};
i2c_b_pins: i2c_b {
mux {
groups = "i2c_sck_b",
"i2c_sda_b";
function = "i2c_b";
};
};
i2c_c_pins: i2c_c {
mux {
groups = "i2c_sck_c",
"i2c_sda_c";
function = "i2c_c";
};
};
eth_pins: eth_c {
mux {
groups = "eth_mdio",
"eth_mdc",
"eth_clk_rx_clk",
"eth_rx_dv",
"eth_rxd0",
"eth_rxd1",
"eth_rxd2",
"eth_rxd3",
"eth_rgmii_tx_clk",
"eth_tx_en",
"eth_txd0",
"eth_txd1",
"eth_txd2",
"eth_txd3";
function = "eth";
};
};
pwm_a_x_pins: pwm_a_x {
mux {
groups = "pwm_a_x";
function = "pwm_a_x";
};
};
pwm_a_y_pins: pwm_a_y {
mux {
groups = "pwm_a_y";
function = "pwm_a_y";
};
};
pwm_b_pins: pwm_b {
mux {
groups = "pwm_b";
function = "pwm_b";
};
};
pwm_d_pins: pwm_d {
mux {
groups = "pwm_d";
function = "pwm_d";
};
};
pwm_e_pins: pwm_e {
mux {
groups = "pwm_e";
function = "pwm_e";
};
};
pwm_f_x_pins: pwm_f_x {
mux {
groups = "pwm_f_x";
function = "pwm_f_x";
};
};
pwm_f_y_pins: pwm_f_y {
mux {
groups = "pwm_f_y";
function = "pwm_f_y";
};
};
eth_rmii_pins: eth-rmii {
mux {
groups = "eth_mdio",
"eth_mdc",
"eth_clk_rx_clk",
"eth_rx_dv",
"eth_rxd0",
"eth_rxd1",
"eth_tx_en",
"eth_txd0",
"eth_txd1";
function = "eth";
};
};
hiubus: hiubus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
pwm_a_x_pins: pwm_a_x {
mux {
groups = "pwm_a_x";
function = "pwm_a_x";
};
};
clkc: clock-controller@0 {
compatible = "amlogic,gxbb-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3db>;
pwm_a_y_pins: pwm_a_y {
mux {
groups = "pwm_a_y";
function = "pwm_a_y";
};
};
mailbox: mailbox@404 {
compatible = "amlogic,meson-gxbb-mhu";
reg = <0 0x404 0 0x4c>;
interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
<0 209 IRQ_TYPE_EDGE_RISING>,
<0 210 IRQ_TYPE_EDGE_RISING>;
#mbox-cells = <1>;
pwm_b_pins: pwm_b {
mux {
groups = "pwm_b";
function = "pwm_b";
};
};
apb: apb@d0000000 {
compatible = "simple-bus";
reg = <0x0 0xd0000000 0x0 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
pwm_d_pins: pwm_d {
mux {
groups = "pwm_d";
function = "pwm_d";
};
};
usb0: usb@c9000000 {
compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
reg = <0x0 0xc9000000 0x0 0x40000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
clock-names = "otg";
phys = <&usb0_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
status = "disabled";
pwm_e_pins: pwm_e {
mux {
groups = "pwm_e";
function = "pwm_e";
};
};
usb1: usb@c9100000 {
compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
reg = <0x0 0xc9100000 0x0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "otg";
phys = <&usb1_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
status = "disabled";
pwm_f_x_pins: pwm_f_x {
mux {
groups = "pwm_f_x";
function = "pwm_f_x";
};
};
ethmac: ethernet@c9410000 {
compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
reg = <0x0 0xc9410000 0x0 0x10000
0x0 0xc8834540 0x0 0x4>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
phy-mode = "rgmii";
status = "disabled";
pwm_f_y_pins: pwm_f_y {
mux {
groups = "pwm_f_y";
function = "pwm_f_y";
};
};
};
};
&hiubus {
clkc: clock-controller@0 {
compatible = "amlogic,gxbb-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3db>;
};
};
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
&i2c_C {
clocks = <&clkc CLKID_I2C>;
};
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};
&sd_emmc_b {
clocks = <&clkc CLKID_SD_EMMC_B>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};
&sd_emmc_c {
clocks = <&clkc CLKID_SD_EMMC_C>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};
arch/arm64/boot/dts/amlogic/meson-gxl-nexbox-a95x.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Neil Armstrong <narmstrong@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxl-s905x.dtsi"
/ {
compatible = "nexbox,a95x", "amlogic,s905x", "amlogic,meson-gxl";
model = "NEXBOX A95X (S905X)";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
vddio_card: gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "VDDIO_CARD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
states = <1800000 0
3300000 1>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ethmac {
status = "okay";
phy-mode = "rmii";
phy-handle = <&internal_phy>;
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_card>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxl-s905d.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
model = "Amlogic Meson GXL (S905D) P230 Development Board";
};
/* P230 has exclusive choice between internal or external PHY */
&ethmac {
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
/* Select external PHY by default */
phy-handle = <&external_phy>;
/* External PHY reset is shared with internal PHY Led signals */
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
/* External PHY is in RGMII */
phy-mode = "rgmii";
};
&external_mdio {
external_phy: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
};
};
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxl-s905d.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl";
model = "Amlogic Meson GXL (S905D) P231 Development Board";
};
/* P231 has only internal PHY port */
&ethmac {
phy-mode = "rmii";
phy-handle = <&internal_phy>;
};
arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxl.dtsi"
/ {
compatible = "amlogic,s905d", "amlogic,meson-gxl";
};
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxl-s905x.dtsi"
/ {
compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl";
model = "Amlogic Meson GXL (S905X) P212 Development Board";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
};
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxl.dtsi"
/ {
compatible = "amlogic,s905x", "amlogic,meson-gxl";
};
/* S905X Only has access to its internal PHY */
&ethmac {
phy-mode = "rmii";
phy-handle = <&internal_phy>;
};
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gx.dtsi"
#include <dt-bindings/clock/gxbb-clkc.h>
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
/ {
compatible = "amlogic,meson-gxl";
};
&ethmac {
reg = <0x0 0xc9410000 0x0 0x10000
0x0 0xc8834540 0x0 0x4>;
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
};
&aobus {
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-gxl-aobus-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio_ao: bank@14 {
reg = <0x0 0x00014 0x0 0x8>,
<0x0 0x0002c 0x0 0x4>,
<0x0 0x00024 0x0 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
};
};
remote_input_ao_pins: remote_input_ao {
mux {
groups = "remote_input_ao";
function = "remote_input_ao";
};
};
};
};
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxl-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@4b0 {
reg = <0x0 0x004b0 0x0 0x28>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00120 0x0 0x14>,
<0x0 0x00430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
emmc_pins: emmc {
mux {
groups = "emmc_nand_d07",
"emmc_cmd",
"emmc_clk",
"emmc_ds";
function = "emmc";
};
};
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
"sdcard_d1",
"sdcard_d2",
"sdcard_d3",
"sdcard_cmd",
"sdcard_clk";
function = "sdcard";
};
};
sdio_pins: sdio {
mux {
groups = "sdio_d0",
"sdio_d1",
"sdio_d2",
"sdio_d3",
"sdio_cmd",
"sdio_clk";
function = "sdio";
};
};
sdio_irq_pins: sdio_irq {
mux {
groups = "sdio_irq";
function = "sdio";
};
};
uart_a_pins: uart_a {
mux {
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
};
};
uart_b_pins: uart_b {
mux {
groups = "uart_tx_b",
"uart_rx_b";
function = "uart_b";
};
};
uart_c_pins: uart_c {
mux {
groups = "uart_tx_c",
"uart_rx_c";
function = "uart_c";
};
};
i2c_a_pins: i2c_a {
mux {
groups = "i2c_sck_a",
"i2c_sda_a";
function = "i2c_a";
};
};
i2c_b_pins: i2c_b {
mux {
groups = "i2c_sck_b",
"i2c_sda_b";
function = "i2c_b";
};
};
i2c_c_pins: i2c_c {
mux {
groups = "i2c_sck_c",
"i2c_sda_c";
function = "i2c_c";
};
};
eth_pins: eth_c {
mux {
groups = "eth_mdio",
"eth_mdc",
"eth_clk_rx_clk",
"eth_rx_dv",
"eth_rxd0",
"eth_rxd1",
"eth_rxd2",
"eth_rxd3",
"eth_rgmii_tx_clk",
"eth_tx_en",
"eth_txd0",
"eth_txd1",
"eth_txd2",
"eth_txd3";
function = "eth";
};
};
pwm_e_pins: pwm_e {
mux {
groups = "pwm_e";
function = "pwm_e";
};
};
};
eth-phy-mux {
compatible = "mdio-mux-mmioreg", "mdio-mux";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x55c 0x0 0x4>;
mux-mask = <0xffffffff>;
mdio-parent-bus = <&mdio0>;
internal_mdio: mdio@e40908ff {
reg = <0xe40908ff>;
#address-cells = <1>;
#size-cells = <0>;
internal_phy: ethernet-phy@8 {
compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
reg = <8>;
max-speed = <100>;
};
};
external_mdio: mdio@2009087f {
reg = <0x2009087f>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&hiubus {
clkc: clock-controller@0 {
compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3db>;
};
};
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
&i2c_C {
clocks = <&clkc CLKID_I2C>;
};
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};
&sd_emmc_b {
clocks = <&clkc CLKID_SD_EMMC_B>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};
&sd_emmc_c {
clocks = <&clkc CLKID_SD_EMMC_C>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxm.dtsi"
/ {
compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm";
model = "NEXBOX A1";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
};
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
/* Select external PHY by default */
phy-handle = <&external_phy>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
/* External PHY is in RGMII */
phy-mode = "rgmii";
};
&external_mdio {
external_phy: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
};
};
arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxm.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm";
model = "Amlogic Meson GXM (S912) Q200 Development Board";
};
/* Q200 has exclusive choice between internal or external PHY */
&ethmac {
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
/* Select external PHY by default */
phy-handle = <&external_phy>;
/* External PHY reset is shared with internal PHY Led signals */
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
/* External PHY is in RGMII */
phy-mode = "rgmii";
};
&external_mdio {
external_phy: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
};
};
arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxm.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "amlogic,q201", "amlogic,s912", "amlogic,meson-gxm";
model = "Amlogic Meson GXM (S912) Q201 Development Board";
};
/* Q201 has only internal PHY port */
&ethmac {
phy-mode = "rmii";
phy-handle = <&internal_phy>;
};
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxl.dtsi"
/ {
compatible = "amlogic,meson-gxm";
cpus {
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};
};
arch/arm64/boot/dts/arm/juno-base.dtsi
View file @ 482c3e88
......@@ -29,6 +29,28 @@ mailbox: mhu@2b1f0000 {
clock-names = "apb_pclk";
};
smmu_pcie: iommu@2b500000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x2b500000 0x0 0x10000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
dma-coherent;
status = "disabled";
};
smmu_etr: iommu@2b600000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x2b600000 0x0 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
dma-coherent;
status = "disabled";
};
gic: interrupt-controller@2c010000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
reg = <0x0 0x2c010000 0 0x1000>,
......@@ -146,6 +168,7 @@ main_funnel_in_port1: endpoint {
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x20070000 0 0x1000>;
iommus = <&smmu_etr 0>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
......@@ -404,6 +427,8 @@ pcie_ctlr: pcie-controller@40000000 {
<0 0 0 4 &gic 0 0 0 139 4>;
msi-parent = <&v2m_0>;
status = "disabled";
iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
};
scpi {
......@@ -484,6 +509,48 @@ gpu1_thermal_zone: gpu1 {
/include/ "juno-clocks.dtsi"
smmu_dma: iommu@7fb00000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x7fb00000 0x0 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
dma-coherent;
status = "disabled";
};
smmu_hdlcd1: iommu@7fb10000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x7fb10000 0x0 0x10000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
status = "disabled";
};
smmu_hdlcd0: iommu@7fb20000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x7fb20000 0x0 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
status = "disabled";
};
smmu_usb: iommu@7fb30000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x7fb30000 0x0 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
dma-coherent;
status = "disabled";
};
dma@7ff00000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x7ff00000 0 0x1000>;
......@@ -499,6 +566,15 @@ dma@7ff00000 {
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_dma 0>,
<&smmu_dma 1>,
<&smmu_dma 2>,
<&smmu_dma 3>,
<&smmu_dma 4>,
<&smmu_dma 5>,
<&smmu_dma 6>,
<&smmu_dma 7>,
<&smmu_dma 8>;
clocks = <&soc_faxiclk>;
clock-names = "apb_pclk";
};
......@@ -507,6 +583,7 @@ hdlcd@7ff50000 {
compatible = "arm,hdlcd";
reg = <0 0x7ff50000 0 0x1000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_hdlcd1 0>;
clocks = <&scpi_clk 3>;
clock-names = "pxlclk";
......@@ -521,6 +598,7 @@ hdlcd@7ff60000 {
compatible = "arm,hdlcd";
reg = <0 0x7ff60000 0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_hdlcd0 0>;
clocks = <&scpi_clk 3>;
clock-names = "pxlclk";
......@@ -574,6 +652,7 @@ ohci@7ffb0000 {
compatible = "generic-ohci";
reg = <0x0 0x7ffb0000 0x0 0x10000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_usb 0>;
clocks = <&soc_usb48mhz>;
};
......@@ -581,6 +660,7 @@ ehci@7ffc0000 {
compatible = "generic-ehci";
reg = <0x0 0x7ffc0000 0x0 0x10000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_usb 0>;
clocks = <&soc_usb48mhz>;
};
......
arch/arm64/boot/dts/arm/juno-r1.dts
View file @ 482c3e88
......@@ -90,6 +90,7 @@ A57_0: cpu@0 {
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
};
A57_1: cpu@1 {
......@@ -100,6 +101,7 @@ A57_1: cpu@1 {
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
};
A53_0: cpu@100 {
......@@ -110,6 +112,7 @@ A53_0: cpu@100 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
A53_1: cpu@101 {
......@@ -120,6 +123,7 @@ A53_1: cpu@101 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
A53_2: cpu@102 {
......@@ -130,6 +134,7 @@ A53_2: cpu@102 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
A53_3: cpu@103 {
......@@ -140,6 +145,7 @@ A53_3: cpu@103 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
A57_L2: l2-cache0 {
......
arch/arm64/boot/dts/arm/juno-r2.dts
View file @ 482c3e88
......@@ -90,6 +90,7 @@ A72_0: cpu@0 {
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
};
A72_1: cpu@1 {
......@@ -100,6 +101,7 @@ A72_1: cpu@1 {
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
};
A53_0: cpu@100 {
......@@ -110,6 +112,7 @@ A53_0: cpu@100 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <485>;
};
A53_1: cpu@101 {
......@@ -120,6 +123,7 @@ A53_1: cpu@101 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <485>;
};
A53_2: cpu@102 {
......@@ -130,6 +134,7 @@ A53_2: cpu@102 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <485>;
};
A53_3: cpu@103 {
......@@ -140,6 +145,7 @@ A53_3: cpu@103 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <485>;
};
A72_L2: l2-cache0 {
......
arch/arm64/boot/dts/arm/juno.dts
View file @ 482c3e88
......@@ -90,6 +90,7 @@ A57_0: cpu@0 {
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
};
A57_1: cpu@1 {
......@@ -100,6 +101,7 @@ A57_1: cpu@1 {
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
};
A53_0: cpu@100 {
......@@ -110,6 +112,7 @@ A53_0: cpu@100 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
A53_1: cpu@101 {
......@@ -120,6 +123,7 @@ A53_1: cpu@101 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
A53_2: cpu@102 {
......@@ -130,6 +134,7 @@ A53_2: cpu@102 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
A53_3: cpu@103 {
......@@ -140,6 +145,7 @@ A53_3: cpu@103 {
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
A57_L2: l2-cache0 {
......
arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
View file @ 482c3e88
......@@ -2,6 +2,7 @@
#include "bcm2837.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
......@@ -15,13 +16,6 @@ leds {
act {
gpios = <&gpio 47 0>;
};
pwr {
label = "PWR";
gpios = <&gpio 35 0>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};
};
......
arch/arm64/boot/dts/broadcom/bcm2837.dtsi
View file @ 482c3e88
#include "bcm283x.dtsi"
/ {
compatible = "brcm,bcm2836";
compatible = "brcm,bcm2837";
soc {
ranges = <0x7e000000 0x3f000000 0x1000000>,
......@@ -74,3 +74,9 @@ &intc {
interrupt-parent = <&local_intc>;
interrupts = <8>;
};
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2837-thermal";
status = "okay";
};
arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi 0 → 120000
View file @ 482c3e88
../../../../arm/boot/dts/bcm283x-rpi-usb-host.dtsi
\ No newline at end of file
arch/arm64/boot/dts/broadcom/ns2-svk.dts
View file @ 482c3e88
......@@ -161,6 +161,10 @@ &sdio0 {
status = "ok";
};
&sdio1 {
status = "ok";
};
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
......@@ -192,3 +196,37 @@ nand_sel: nand_sel {
groups = "nand_grp";
};
};
&qspi {
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
reg = <0x0>;
spi-max-frequency = <12500000>;
m25p,fast-read;
spi-cpol;
spi-cpha;
partition@0 {
label = "boot";
reg = <0x00000000 0x000a0000>;
};
partition@a0000 {
label = "env";
reg = <0x000a0000 0x00060000>;
};
partition@100000 {
label = "system";
reg = <0x00100000 0x00600000>;
};
partition@700000 {
label = "rootfs";
reg = <0x00700000 0x01900000>;
};
};
};
arch/arm64/boot/dts/broadcom/ns2.dtsi
View file @ 482c3e88
......@@ -133,6 +133,9 @@ pcie0: pcie@20020000 {
status = "disabled";
phys = <&pci_phy0>;
phy-names = "pcie-phy";
msi-parent = <&msi0>;
msi0: msi@20020000 {
compatible = "brcm,iproc-msi";
......@@ -171,6 +174,9 @@ pcie4: pcie@50020000 {
status = "disabled";
phys = <&pci_phy1>;
phy-names = "pcie-phy";
msi-parent = <&msi4>;
msi4: msi@50020000 {
compatible = "brcm,iproc-msi";
......@@ -203,6 +209,42 @@ enet: ethernet@61000000 {
status = "disabled";
};
pdc0: iproc-pdc0@612c0000 {
compatible = "brcm,iproc-pdc-mbox";
reg = <0x612c0000 0x445>; /* PDC FS0 regs */
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
brcm,rx-status-len = <32>;
brcm,use-bcm-hdr;
};
pdc1: iproc-pdc1@612e0000 {
compatible = "brcm,iproc-pdc-mbox";
reg = <0x612e0000 0x445>; /* PDC FS1 regs */
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
brcm,rx-status-len = <32>;
brcm,use-bcm-hdr;
};
pdc2: iproc-pdc2@61300000 {
compatible = "brcm,iproc-pdc-mbox";
reg = <0x61300000 0x445>; /* PDC FS2 regs */
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
brcm,rx-status-len = <32>;
brcm,use-bcm-hdr;
};
pdc3: iproc-pdc3@61320000 {
compatible = "brcm,iproc-pdc-mbox";
reg = <0x61320000 0x445>; /* PDC FS3 regs */
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
brcm,rx-status-len = <32>;
brcm,use-bcm-hdr;
};
dma0: dma@61360000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x61360000 0x1000>;
......@@ -260,7 +302,7 @@ smmu: mmu@64000000 {
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
mmu-masters;
#iommu-cells = <1>;
};
pinctrl: pinctrl@6501d130 {
......@@ -577,5 +619,23 @@ nand: nand@66460000 {
brcm,nand-has-wp;
};
qspi: spi@66470200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
reg = <0x66470200 0x184>,
<0x66470000 0x124>,
<0x67017408 0x004>,
<0x664703a0 0x01c>;
reg-names = "mspi", "bspi", "intr_regs",
"intr_status_reg";
interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "spi_l1_intr";
clocks = <&iprocmed>;
clock-names = "iprocmed";
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
arch/arm64/boot/dts/exynos/Makefile
View file @ 482c3e88
dtb-$(CONFIG_ARCH_EXYNOS) += exynos7-espresso.dtb
dtb-$(CONFIG_ARCH_EXYNOS) += \
exynos5433-tm2.dtb \
exynos5433-tm2e.dtb \
exynos7-espresso.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi 0 → 100644
View file @ 482c3e88
/*
* Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* Chanwoo Choi <cw00.choi@samsung.com>
*
* Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
* tree nodes are listed in this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define PIN_PULL_NONE 0
#define PIN_PULL_DOWN 1
#define PIN_PULL_UP 3
#define PIN_DRV_LV1 0
#define PIN_DRV_LV2 2
#define PIN_DRV_LV3 1
#define PIN_DRV_LV4 3
#define PIN_IN 0
#define PIN_OUT 1
#define PIN_FUNC1 2
#define PIN(_func, _pin, _pull, _drv) \
_pin { \
samsung,pins = #_pin; \
samsung,pin-function = <PIN_ ##_func>; \
samsung,pin-pud = <PIN_PULL_ ##_pull>; \
samsung,pin-drv = <PIN_DRV_ ##_drv>; \
}
&pinctrl_alive {
gpa0: gpa0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
gpa1: gpa1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
gpa2: gpa2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa3: gpa3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf2: gpf2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf3: gpf3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf4: gpf4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf5: gpf5 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&pinctrl_aud {
gpz0: gpz0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpz1: gpz1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2s0_bus: i2s0-bus {
samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
"gpz0-4", "gpz0-5", "gpz0-6";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
pcm0_bus: pcm0-bus {
samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
uart_aud_bus: uart-aud-bus {
samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};
&pinctrl_cpif {
gpv6: gpv6 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&pinctrl_ese {
gpj2: gpj2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&pinctrl_finger {
gpd5: gpd5 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
spi2_bus: spi2-bus {
samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c6_bus: hs-i2c6-bus {
samsung,pins = "gpd5-3", "gpd5-2";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
&pinctrl_fsys {
gph1: gph1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpr4: gpr4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpr0: gpr0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpr1: gpr1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpr2: gpr2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpr3: gpr3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sd0_clk: sd0-clk {
samsung,pins = "gpr0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpr0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_rdqs: sd0-rdqs {
samsung,pins = "gpr0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <3>;
};
sd0_qrdy: sd0-qrdy {
samsung,pins = "gpr0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <3>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpr1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd1_clk: sd1-clk {
samsung,pins = "gpr2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd1_cmd: sd1-cmd {
samsung,pins = "gpr2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd1_bus1: sd1-bus-width1 {
samsung,pins = "gpr3-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd1_bus4: sd1-bus-width4 {
samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd1_bus8: sd1-bus-width8 {
samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
pcie_bus: pcie_bus {
samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
};
sd2_clk: sd2-clk {
samsung,pins = "gpr4-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cmd: sd2-cmd {
samsung,pins = "gpr4-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cd: sd2-cd {
samsung,pins = "gpr4-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_bus1: sd2-bus-width1 {
samsung,pins = "gpr4-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_bus4: sd2-bus-width4 {
samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_clk_output: sd2-clk-output {
samsung,pins = "gpr4-0";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <2>;
};
sd2_cmd_output: sd2-cmd-output {
samsung,pins = "gpr4-1";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <2>;
};
};
&pinctrl_imem {
gpf0: gpf0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&pinctrl_nfc {
gpj0: gpj0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
hs_i2c4_bus: hs-i2c4-bus {
samsung,pins = "gpj0-1", "gpj0-0";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
&pinctrl_peric {
gpv7: gpv7 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb0: gpb0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc0: gpc0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc2: gpc2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc3: gpc3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg0: gpg0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd0: gpd0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd1: gpd1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd2: gpd2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd4: gpd4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd8: gpd8 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd6: gpd6 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd7: gpd7 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg1: gpg1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg2: gpg2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg3: gpg3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
hs_i2c8_bus: hs-i2c8-bus {
samsung,pins = "gpb0-1", "gpb0-0";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c9_bus: hs-i2c9-bus {
samsung,pins = "gpb0-3", "gpb0-2";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2s1_bus: i2s1-bus {
samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
"gpd4-3", "gpd4-4";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
pcm1_bus: pcm1-bus {
samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
"gpd4-3", "gpd4-4";
samsung,pin-function = <3>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
spdif_bus: spdif-bus {
samsung,pins = "gpd4-3", "gpd4-4";
samsung,pin-function = <4>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
fimc_is_spi_pin0: fimc-is-spi-pin0 {
samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_spi_pin1: fimc-is-spi-pin1 {
samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart0_bus: uart0-bus {
samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
};
hs_i2c2_bus: hs-i2c2-bus {
samsung,pins = "gpd0-3", "gpd0-2";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
uart2_bus: uart2-bus {
samsung,pins = "gpd1-5", "gpd1-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
};
uart1_bus: uart1-bus {
samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
};
hs_i2c3_bus: hs-i2c3-bus {
samsung,pins = "gpd1-3", "gpd1-2";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c0_bus: hs-i2c0-bus {
samsung,pins = "gpd2-1", "gpd2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c1_bus: hs-i2c1-bus {
samsung,pins = "gpd2-3", "gpd2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
pwm0_out: pwm0-out {
samsung,pins = "gpd2-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm1_out: pwm1-out {
samsung,pins = "gpd2-5";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm2_out: pwm2-out {
samsung,pins = "gpd2-6";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm3_out: pwm3-out {
samsung,pins = "gpd2-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spi1_bus: spi1-bus {
samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c7_bus: hs-i2c7-bus {
samsung,pins = "gpd2-7", "gpd2-6";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi0_bus: spi0-bus {
samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c10_bus: hs-i2c10-bus {
samsung,pins = "gpg3-1", "gpg3-0";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c11_bus: hs-i2c11-bus {
samsung,pins = "gpg3-3", "gpg3-2";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi3_bus: spi3-bus {
samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi4_bus: spi4-bus {
samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
fimc_is_uart: fimc-is-uart {
samsung,pins = "gpc1-1", "gpc0-7";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_ch0_i2c: fimc-is-ch0_i2c {
samsung,pins = "gpc2-1", "gpc2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_ch0_mclk: fimc-is-ch0_mclk {
samsung,pins = "gpd7-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_ch1_i2c: fimc-is-ch1-i2c {
samsung,pins = "gpc2-3", "gpc2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_ch1_mclk: fimc-is-ch1-mclk {
samsung,pins = "gpd7-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_ch2_i2c: fimc-is-ch2-i2c {
samsung,pins = "gpc2-5", "gpc2-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_ch2_mclk: fimc-is-ch2-mclk {
samsung,pins = "gpd7-2";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};
&pinctrl_touch {
gpj1: gpj1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
hs_i2c5_bus: hs-i2c5-bus {
samsung,pins = "gpj1-1", "gpj1-0";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts 0 → 100644
View file @ 482c3e88
/*
* SAMSUNG Exynos5433 TM2 board device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
*
* Device tree source file for Samsung's TM2 board which is based on
* Samsung Exynos5433 SoC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos5433.dtsi"
#include <dt-bindings/clock/samsung,s2mps11.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Samsung TM2 board";
compatible = "samsung,tm2", "samsung,exynos5433";
aliases {
gsc0 = &gsc_0;
gsc1 = &gsc_1;
gsc2 = &gsc_2;
pinctrl0 = &pinctrl_alive;
pinctrl1 = &pinctrl_aud;
pinctrl2 = &pinctrl_cpif;
pinctrl3 = &pinctrl_ese;
pinctrl4 = &pinctrl_finger;
pinctrl5 = &pinctrl_fsys;
pinctrl6 = &pinctrl_imem;
pinctrl7 = &pinctrl_nfc;
pinctrl8 = &pinctrl_peric;
pinctrl9 = &pinctrl_touch;
serial0 = &serial_0;
serial1 = &serial_1;
serial2 = &serial_2;
serial3 = &serial_3;
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
spi3 = &spi_3;
spi4 = &spi_4;
mshc0 = &mshc_0;
mshc2 = &mshc_2;
};
chosen {
stdout-path = &serial_1;
};
memory@20000000 {
device_type = "memory";
reg = <0x0 0x20000000 0x0 0xc0000000>;
};
gpio-keys {
compatible = "gpio-keys";
power-key {
gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "power key";
debounce-interval = <10>;
};
volume-up-key {
gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
label = "volume-up key";
debounce-interval = <10>;
};
volume-down-key {
gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
label = "volume-down key";
debounce-interval = <10>;
};
homepage-key {
gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
label = "homepage key";
debounce-interval = <10>;
};
};
i2c_max98504: i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
&gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
max98504: max98504@31 {
compatible = "maxim,max98504";
reg = <0x31>;
maxim,rx-path = <1>;
maxim,tx-path = <1>;
maxim,tx-channel-mask = <3>;
maxim,tx-channel-source = <2>;
};
};
sound {
compatible = "samsung,tm2-audio";
audio-codec = <&wm5110>;
i2s-controller = <&i2s0>;
audio-amplifier = <&max98504>;
mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
model = "wm5110";
samsung,audio-routing =
/* Headphone */
"HP", "HPOUT1L",
"HP", "HPOUT1R",
/* Speaker */
"SPK", "SPKOUT",
"SPKOUT", "HPOUT2L",
"SPKOUT", "HPOUT2R",
/* Receiver */
"RCV", "HPOUT3L",
"RCV", "HPOUT3R";
status = "okay";
};
};
&adc {
vdd-supply = <&ldo3_reg>;
status = "okay";
thermistor-ap {
compatible = "murata,ncp03wf104";
pullup-uv = <1800000>;
pullup-ohm = <100000>;
pulldown-ohm = <0>;
io-channels = <&adc 0>;
};
thermistor-battery {
compatible = "murata,ncp03wf104";
pullup-uv = <1800000>;
pullup-ohm = <100000>;
pulldown-ohm = <0>;
io-channels = <&adc 1>;
#thermal-sensor-cells = <0>;
};
thermistor-charger {
compatible = "murata,ncp03wf104";
pullup-uv = <1800000>;
pullup-ohm = <100000>;
pulldown-ohm = <0>;
io-channels = <&adc 2>;
};
};
&cmu_aud {
assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
};
&cmu_fsys {
assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
<&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
<&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
<&cmu_top CLK_DIV_SCLK_USBDRD30>,
<&cmu_top CLK_DIV_SCLK_USBHOST30>;
assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
<&cmu_top CLK_MOUT_BUS_PLL_USER>,
<&cmu_top CLK_SCLK_USBDRD30_FSYS>,
<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
<66700000>, <66700000>;
};
&cmu_gscl {
assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
<&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
<&cmu_top CLK_ACLK_GSCL_333>;
};
&cmu_mfc {
assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
};
&cmu_mscl {
assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
<&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
<&cmu_mscl CLK_MOUT_SCLK_JPEG>,
<&cmu_top CLK_MOUT_SCLK_JPEG_A>;
assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
<&cmu_top CLK_SCLK_JPEG_MSCL>,
<&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
<&cmu_top CLK_MOUT_BUS_PLL_USER>;
};
&cpu0 {
cpu-supply = <&buck3_reg>;
};
&cpu4 {
cpu-supply = <&buck2_reg>;
};
&decon {
status = "okay";
i80-if-timings {
};
};
&dsi {
status = "okay";
vddcore-supply = <&ldo6_reg>;
vddio-supply = <&ldo7_reg>;
samsung,pll-clock-frequency = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&te_irq>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi_out: endpoint {
samsung,burst-clock-frequency = <512000000>;
samsung,esc-clock-frequency = <16000000>;
};
};
};
};
&hsi2c_0 {
status = "okay";
clock-frequency = <2500000>;
s2mps13-pmic@66 {
compatible = "samsung,s2mps13-pmic";
interrupt-parent = <&gpa0>;
interrupts = <7 IRQ_TYPE_NONE>;
reg = <0x66>;
samsung,s2mps11-wrstbi-ground;
s2mps13_osc: clocks {
compatible = "samsung,s2mps13-clk";
#clock-cells = <1>;
clock-output-names = "s2mps13_ap", "s2mps13_cp",
"s2mps13_bt";
};
regulators {
ldo1_reg: LDO1 {
regulator-name = "VDD_ALIVE_0.9V_AP";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
};
ldo2_reg: LDO2 {
regulator-name = "VDDQ_MMC2_2.8V_AP";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo3_reg: LDO3 {
regulator-name = "VDD1_E_1.8V_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "VDD10_MIF_PLL_1.0V_AP";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo5_reg: LDO5 {
regulator-name = "VDD10_DPLL_1.0V_AP";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo6_reg: LDO6 {
regulator-name = "VDD10_MIPI2L_1.0V_AP";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo7_reg: LDO7 {
regulator-name = "VDD18_MIPI2L_1.8V_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo8_reg: LDO8 {
regulator-name = "VDD18_LLI_1.8V_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo9_reg: LDO9 {
regulator-name = "VDD18_ABB_ETC_1.8V_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo10_reg: LDO10 {
regulator-name = "VDD33_USB30_3.0V_AP";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo11_reg: LDO11 {
regulator-name = "VDD_INT_M_1.0V_AP";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo12_reg: LDO12 {
regulator-name = "VDD_KFC_M_1.1V_AP";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
ldo13_reg: LDO13 {
regulator-name = "VDD_G3D_M_0.95V_AP";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo14_reg: LDO14 {
regulator-name = "VDDQ_M1_LDO_1.2V_AP";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo15_reg: LDO15 {
regulator-name = "VDDQ_M2_LDO_1.2V_AP";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo16_reg: LDO16 {
regulator-name = "VDDQ_EFUSE";
regulator-min-microvolt = <1400000>;
regulator-max-microvolt = <3400000>;
regulator-always-on;
};
ldo17_reg: LDO17 {
regulator-name = "V_TFLASH_2.8V_AP";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo18_reg: LDO18 {
regulator-name = "V_CODEC_1.8V_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo19_reg: LDO19 {
regulator-name = "VDDA_1.8V_COMP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo20_reg: LDO20 {
regulator-name = "VCC_2.8V_AP";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo21_reg: LDO21 {
regulator-name = "VT_CAM_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo22_reg: LDO22 {
regulator-name = "CAM_IO_1.8V_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo23_reg: LDO23 {
regulator-name = "CAM_SEN_CORE_1.2V_AP";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1200000>;
};
ldo24_reg: LDO24 {
regulator-name = "VT_CAM_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo25_reg: LDO25 {
regulator-name = "CAM_SEN_A2.8V_AP";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo26_reg: LDO26 {
regulator-name = "CAM_AF_2.8V_AP";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo27_reg: LDO27 {
regulator-name = "VCC_3.0V_LCD_AP";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
ldo28_reg: LDO28 {
regulator-name = "VCC_1.8V_LCD_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo29_reg: LDO29 {
regulator-name = "VT_CAM_2.8V";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
ldo30_reg: LDO30 {
regulator-name = "TSP_AVDD_3.3V_AP";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo31_reg: LDO31 {
regulator-name = "TSP_VDD_1.85V_AP";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1850000>;
};
ldo32_reg: LDO32 {
regulator-name = "VTOUCH_1.8V_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo33_reg: LDO33 {
regulator-name = "VTOUCH_LED_3.3V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
};
ldo34_reg: LDO34 {
regulator-name = "VCC_1.8V_MHL_AP";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <2100000>;
};
ldo35_reg: LDO35 {
regulator-name = "OIS_VM_2.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
};
ldo36_reg: LDO36 {
regulator-name = "VSIL_1.0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
ldo37_reg: LDO37 {
regulator-name = "VF_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo38_reg: LDO38 {
regulator-name = "VCC_3.0V_MOTOR_AP";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
ldo39_reg: LDO39 {
regulator-name = "V_HRM_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo40_reg: LDO40 {
regulator-name = "V_HRM_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
buck1_reg: BUCK1 {
regulator-name = "VDD_MIF_0.9V_AP";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
buck2_reg: BUCK2 {
regulator-name = "VDD_EGL_1.0V_AP";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
buck3_reg: BUCK3 {
regulator-name = "VDD_KFC_1.0V_AP";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
buck4_reg: BUCK4 {
regulator-name = "VDD_INT_0.95V_AP";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
buck5_reg: BUCK5 {
regulator-name = "VDD_DISP_CAM0_0.9V_AP";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
buck6_reg: BUCK6 {
regulator-name = "VDD_G3D_0.9V_AP";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
buck7_reg: BUCK7 {
regulator-name = "VDD_MEM1_1.2V_AP";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
buck8_reg: BUCK8 {
regulator-name = "VDD_LLDO_1.35V_AP";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
buck9_reg: BUCK9 {
regulator-name = "VDD_MLDO_2.0V_AP";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
buck10_reg: BUCK10 {
regulator-name = "vdd_mem2";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
};
};
};
&hsi2c_8 {
status = "okay";
max77843@66 {
compatible = "maxim,max77843";
interrupt-parent = <&gpa1>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reg = <0x66>;
muic: max77843-muic {
compatible = "maxim,max77843-muic";
};
regulators {
compatible = "maxim,max77843-regulator";
safeout1_reg: SAFEOUT1 {
regulator-name = "SAFEOUT1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <4950000>;
};
safeout2_reg: SAFEOUT2 {
regulator-name = "SAFEOUT2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <4950000>;
};
charger_reg: CHARGER {
regulator-name = "CHARGER";
regulator-min-microamp = <100000>;
regulator-max-microamp = <3150000>;
};
};
haptic: max77843-haptic {
compatible = "maxim,max77843-haptic";
haptic-supply = <&ldo38_reg>;
pwms = <&pwm 0 33670 0>;
pwm-names = "haptic";
};
};
};
&i2s0 {
status = "okay";
};
&mshc_0 {
status = "okay";
num-slots = <1>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-highspeed;
non-removable;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
samsung,dw-mshc-hs400-timing = <0 3>;
samsung,read-strobe-delay = <90>;
fifo-depth = <0x80>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
&sd0_bus8 &sd0_rdqs>;
bus-width = <8>;
assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
assigned-clock-rates = <800000000>;
};
&mshc_2 {
status = "okay";
num-slots = <1>;
cap-sd-highspeed;
disable-wp;
cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
cd-inverted;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
fifo-depth = <0x80>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
};
&pinctrl_alive {
pinctrl-names = "default";
pinctrl-0 = <&initial_alive>;
initial_alive: initial-state {
PIN(IN, gpa0-0, DOWN, LV1);
PIN(IN, gpa0-1, NONE, LV1);
PIN(IN, gpa0-2, DOWN, LV1);
PIN(IN, gpa0-3, NONE, LV1);
PIN(IN, gpa0-4, NONE, LV1);
PIN(IN, gpa0-5, DOWN, LV1);
PIN(IN, gpa0-6, NONE, LV1);
PIN(IN, gpa0-7, NONE, LV1);
PIN(IN, gpa1-0, UP, LV1);
PIN(IN, gpa1-1, NONE, LV1);
PIN(IN, gpa1-2, NONE, LV1);
PIN(IN, gpa1-3, DOWN, LV1);
PIN(IN, gpa1-4, DOWN, LV1);
PIN(IN, gpa1-5, NONE, LV1);
PIN(IN, gpa1-6, NONE, LV1);
PIN(IN, gpa1-7, NONE, LV1);
PIN(IN, gpa2-0, NONE, LV1);
PIN(IN, gpa2-1, NONE, LV1);
PIN(IN, gpa2-2, NONE, LV1);
PIN(IN, gpa2-3, DOWN, LV1);
PIN(IN, gpa2-4, NONE, LV1);
PIN(IN, gpa2-5, DOWN, LV1);
PIN(IN, gpa2-6, DOWN, LV1);
PIN(IN, gpa2-7, NONE, LV1);
PIN(IN, gpa3-0, DOWN, LV1);
PIN(IN, gpa3-1, DOWN, LV1);
PIN(IN, gpa3-2, NONE, LV1);
PIN(IN, gpa3-3, DOWN, LV1);
PIN(IN, gpa3-4, NONE, LV1);
PIN(IN, gpa3-5, DOWN, LV1);
PIN(IN, gpa3-6, DOWN, LV1);
PIN(IN, gpa3-7, DOWN, LV1);
PIN(IN, gpf1-0, NONE, LV1);
PIN(IN, gpf1-1, NONE, LV1);
PIN(IN, gpf1-2, DOWN, LV1);
PIN(IN, gpf1-4, UP, LV1);
PIN(OUT, gpf1-5, NONE, LV1);
PIN(IN, gpf1-6, DOWN, LV1);
PIN(IN, gpf1-7, DOWN, LV1);
PIN(IN, gpf2-0, DOWN, LV1);
PIN(IN, gpf2-1, DOWN, LV1);
PIN(IN, gpf2-2, DOWN, LV1);
PIN(IN, gpf2-3, DOWN, LV1);
PIN(IN, gpf3-0, DOWN, LV1);
PIN(IN, gpf3-1, DOWN, LV1);
PIN(IN, gpf3-2, NONE, LV1);
PIN(IN, gpf3-3, DOWN, LV1);
PIN(IN, gpf4-0, DOWN, LV1);
PIN(IN, gpf4-1, DOWN, LV1);
PIN(IN, gpf4-2, DOWN, LV1);
PIN(IN, gpf4-3, DOWN, LV1);
PIN(IN, gpf4-4, DOWN, LV1);
PIN(IN, gpf4-5, DOWN, LV1);
PIN(IN, gpf4-6, DOWN, LV1);
PIN(IN, gpf4-7, DOWN, LV1);
PIN(IN, gpf5-0, DOWN, LV1);
PIN(IN, gpf5-1, DOWN, LV1);
PIN(IN, gpf5-2, DOWN, LV1);
PIN(IN, gpf5-3, DOWN, LV1);
PIN(OUT, gpf5-4, NONE, LV1);
PIN(IN, gpf5-5, DOWN, LV1);
PIN(IN, gpf5-6, DOWN, LV1);
PIN(IN, gpf5-7, DOWN, LV1);
};
te_irq: te_irq {
samsung,pins = "gpf1-3";
samsung,pin-function = <0xf>;
};
};
&pinctrl_cpif {
pinctrl-names = "default";
pinctrl-0 = <&initial_cpif>;
initial_cpif: initial-state {
PIN(IN, gpv6-0, DOWN, LV1);
PIN(IN, gpv6-1, DOWN, LV1);
};
};
&pinctrl_ese {
pinctrl-names = "default";
pinctrl-0 = <&initial_ese>;
initial_ese: initial-state {
PIN(IN, gpj2-0, DOWN, LV1);
PIN(IN, gpj2-1, DOWN, LV1);
PIN(IN, gpj2-2, DOWN, LV1);
};
};
&pinctrl_fsys {
pinctrl-names = "default";
pinctrl-0 = <&initial_fsys>;
initial_fsys: initial-state {
PIN(IN, gpr3-0, NONE, LV1);
PIN(IN, gpr3-1, DOWN, LV1);
PIN(IN, gpr3-2, DOWN, LV1);
PIN(IN, gpr3-3, DOWN, LV1);
PIN(IN, gpr3-7, NONE, LV1);
};
};
&pinctrl_imem {
pinctrl-names = "default";
pinctrl-0 = <&initial_imem>;
initial_imem: initial-state {
PIN(IN, gpf0-0, UP, LV1);
PIN(IN, gpf0-1, UP, LV1);
PIN(IN, gpf0-2, DOWN, LV1);
PIN(IN, gpf0-3, UP, LV1);
PIN(IN, gpf0-4, DOWN, LV1);
PIN(IN, gpf0-5, NONE, LV1);
PIN(IN, gpf0-6, DOWN, LV1);
PIN(IN, gpf0-7, UP, LV1);
};
};
&pinctrl_nfc {
pinctrl-names = "default";
pinctrl-0 = <&initial_nfc>;
initial_nfc: initial-state {
PIN(IN, gpj0-2, DOWN, LV1);
};
};
&pinctrl_peric {
pinctrl-names = "default";
pinctrl-0 = <&initial_peric>;
initial_peric: initial-state {
PIN(IN, gpv7-0, DOWN, LV1);
PIN(IN, gpv7-1, DOWN, LV1);
PIN(IN, gpv7-2, NONE, LV1);
PIN(IN, gpv7-3, DOWN, LV1);
PIN(IN, gpv7-4, DOWN, LV1);
PIN(IN, gpv7-5, DOWN, LV1);
PIN(IN, gpb0-4, DOWN, LV1);
PIN(IN, gpc0-2, DOWN, LV1);
PIN(IN, gpc0-5, DOWN, LV1);
PIN(IN, gpc0-7, DOWN, LV1);
PIN(IN, gpc1-1, DOWN, LV1);
PIN(IN, gpc3-4, NONE, LV1);
PIN(IN, gpc3-5, NONE, LV1);
PIN(IN, gpc3-6, NONE, LV1);
PIN(IN, gpc3-7, NONE, LV1);
PIN(OUT, gpg0-0, NONE, LV1);
PIN(FUNC1, gpg0-1, DOWN, LV1);
PIN(IN, gpd2-5, DOWN, LV1);
PIN(IN, gpd4-0, NONE, LV1);
PIN(IN, gpd4-1, DOWN, LV1);
PIN(IN, gpd4-2, DOWN, LV1);
PIN(IN, gpd4-3, DOWN, LV1);
PIN(IN, gpd4-4, DOWN, LV1);
PIN(IN, gpd6-3, DOWN, LV1);
PIN(IN, gpd8-1, UP, LV1);
PIN(IN, gpg1-0, DOWN, LV1);
PIN(IN, gpg1-1, DOWN, LV1);
PIN(IN, gpg1-2, DOWN, LV1);
PIN(IN, gpg1-3, DOWN, LV1);
PIN(IN, gpg1-4, DOWN, LV1);
PIN(IN, gpg2-0, DOWN, LV1);
PIN(IN, gpg2-1, DOWN, LV1);
PIN(IN, gpg3-0, DOWN, LV1);
PIN(IN, gpg3-1, DOWN, LV1);
PIN(IN, gpg3-5, DOWN, LV1);
PIN(IN, gpg3-7, DOWN, LV1);
};
};
&pinctrl_touch {
pinctrl-names = "default";
pinctrl-0 = <&initial_touch>;
initial_touch: initial-state {
PIN(IN, gpj1-2, DOWN, LV1);
};
};
&pwm {
pinctrl-0 = <&pwm0_out>;
pinctrl-names = "default";
status = "okay";
};
&mic {
status = "okay";
i80-if-timings {
};
};
&pmu_system_controller {
assigned-clocks = <&pmu_system_controller 0>;
assigned-clock-parents = <&xxti>;
};
&serial_1 {
status = "okay";
};
&spi_1 {
cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
status = "okay";
wm5110: wm5110-codec@0 {
compatible = "wlf,wm5110";
reg = <0x0>;
spi-max-frequency = <20000000>;
interrupt-parent = <&gpa0>;
interrupts = <4 IRQ_TYPE_NONE>;
clocks = <&pmu_system_controller 0>,
<&s2mps13_osc S2MPS11_CLK_BT>;
clock-names = "mclk1", "mclk2";
gpio-controller;
#gpio-cells = <2>;
wlf,micd-detect-debounce = <300>;
wlf,micd-bias-start-time = <0x1>;
wlf,micd-rate = <0x7>;
wlf,micd-dbtime = <0x1>;
wlf,micd-force-micbias;
wlf,micd-configs = <0x0 1 0>;
wlf,hpdet-channel = <1>;
wlf,gpsw = <0x1>;
wlf,inmode = <2 0 2 0>;
wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
/* core supplies */
AVDD-supply = <&ldo18_reg>;
DBVDD1-supply = <&ldo18_reg>;
CPVDD-supply = <&ldo18_reg>;
DBVDD2-supply = <&ldo18_reg>;
DBVDD3-supply = <&ldo18_reg>;
controller-data {
samsung,spi-feedback-delay = <0>;
};
};
};
&timer {
clock-frequency = <24000000>;
};
&tmu_atlas0 {
vtmu-supply = <&ldo3_reg>;
status = "okay";
};
&tmu_apollo {
vtmu-supply = <&ldo3_reg>;
status = "okay";
};
&tmu_g3d {
vtmu-supply = <&ldo3_reg>;
status = "okay";
};
&usbdrd30 {
vdd33-supply = <&ldo10_reg>;
vdd10-supply = <&ldo6_reg>;
status = "okay";
};
&usbdrd_dwc3_0 {
dr_mode = "otg";
};
&usbdrd30_phy {
vbus-supply = <&safeout1_reg>;
status = "okay";
};
&xxti {
clock-frequency = <24000000>;
};
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts 0 → 100644
View file @ 482c3e88
/*
* SAMSUNG Exynos5433 TM2E board device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
*
* Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
* Samsung Exynos5433 SoC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exynos5433-tm2.dts"
/ {
model = "Samsung TM2E board";
compatible = "samsung,tm2e", "samsung,exynos5433";
};
&ldo23_reg {
regulator-name = "CAM_SEN_CORE_1.025V_AP";
regulator-max-microvolt = <1050000>;
};
&ldo25_reg {
regulator-name = "UNUSED_LDO25";
regulator-always-off;
};
&ldo31_reg {
regulator-name = "TSP_VDD_1.8V_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
&ldo38_reg {
regulator-name = "VCC_3.3V_MOTOR_AP";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi 0 → 100644
View file @ 482c3e88
/*
* Device tree sources for Exynos5433 TMU sensor configuration
*
* Copyright (c) 2016 Jonghwa Lee <jonghwa3.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/thermal/thermal_exynos.h>
#thermal-sensor-cells = <0>;
samsung,tmu_gain = <8>;
samsung,tmu_reference_voltage = <23>;
samsung,tmu_noise_cancel_mode = <4>;
samsung,tmu_efuse_value = <75>;
samsung,tmu_min_efuse_value = <40>;
samsung,tmu_max_efuse_value = <150>;
samsung,tmu_first_point_trim = <25>;
samsung,tmu_second_point_trim = <85>;
samsung,tmu_default_temp_offset = <50>;
samsung,tmu_mux_addr = <6>;
arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi 0 → 100644
View file @ 482c3e88
/*
* Device tree sources for Exynos5433 TMU sensor configuration
*
* Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/thermal/thermal_exynos.h>
#thermal-sensor-cells = <0>;
samsung,tmu_gain = <8>;
samsung,tmu_reference_voltage = <16>;
samsung,tmu_noise_cancel_mode = <4>;
samsung,tmu_efuse_value = <75>;
samsung,tmu_min_efuse_value = <40>;
samsung,tmu_max_efuse_value = <150>;
samsung,tmu_first_point_trim = <25>;
samsung,tmu_second_point_trim = <85>;
samsung,tmu_default_temp_offset = <50>;
arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi 0 → 100644
View file @ 482c3e88
/*
* Device tree sources for Exynos5433 thermal zone
*
* Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/thermal/thermal.h>
/ {
thermal-zones {
atlas0_thermal: atlas0-thermal {
thermal-sensors = <&tmu_atlas0>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
atlas0_alert_0: atlas0-alert-0 {
temperature = <65000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_1: atlas0-alert-1 {
temperature = <70000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_2: atlas0-alert-2 {
temperature = <75000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_3: atlas0-alert-3 {
temperature = <80000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_4: atlas0-alert-4 {
temperature = <85000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_5: atlas0-alert-5 {
temperature = <90000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_6: atlas0-alert-6 {
temperature = <95000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
cooling-maps {
map0 {
/* Set maximum frequency as 1800MHz */
trip = <&atlas0_alert_0>;
cooling-device = <&cpu4 1 2>;
};
map1 {
/* Set maximum frequency as 1700MHz */
trip = <&atlas0_alert_1>;
cooling-device = <&cpu4 2 3>;
};
map2 {
/* Set maximum frequency as 1600MHz */
trip = <&atlas0_alert_2>;
cooling-device = <&cpu4 3 4>;
};
map3 {
/* Set maximum frequency as 1500MHz */
trip = <&atlas0_alert_3>;
cooling-device = <&cpu4 4 5>;
};
map4 {
/* Set maximum frequency as 1400MHz */
trip = <&atlas0_alert_4>;
cooling-device = <&cpu4 5 7>;
};
map5 {
/* Set maximum frequencyas 1200MHz */
trip = <&atlas0_alert_5>;
cooling-device = <&cpu4 7 9>;
};
map6 {
/* Set maximum frequency as 1000MHz */
trip = <&atlas0_alert_6>;
cooling-device = <&cpu4 9 14>;
};
};
};
atlas1_thermal: atlas1-thermal {
thermal-sensors = <&tmu_atlas1>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
atlas1_alert_0: atlas1-alert-0 {
temperature = <65000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_1: atlas1-alert-1 {
temperature = <70000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_2: atlas1-alert-2 {
temperature = <75000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_3: atlas1-alert-3 {
temperature = <80000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_4: atlas1-alert-4 {
temperature = <85000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_5: atlas1-alert-5 {
temperature = <90000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_6: atlas1-alert-6 {
temperature = <95000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
};
g3d_thermal: g3d-thermal {
thermal-sensors = <&tmu_g3d>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
g3d_alert_0: g3d-alert-0 {
temperature = <70000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_1: g3d-alert-1 {
temperature = <75000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_2: g3d-alert-2 {
temperature = <80000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_3: g3d-alert-3 {
temperature = <85000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_4: g3d-alert-4 {
temperature = <90000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_5: g3d-alert-5 {
temperature = <95000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_6: g3d-alert-6 {
temperature = <100000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
};
apollo_thermal: apollo-thermal {
thermal-sensors = <&tmu_apollo>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
apollo_alert_0: apollo-alert-0 {
temperature = <65000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_1: apollo-alert-1 {
temperature = <70000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_2: apollo-alert-2 {
temperature = <75000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_3: apollo-alert-3 {
temperature = <80000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_4: apollo-alert-4 {
temperature = <85000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_5: apollo-alert-5 {
temperature = <90000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_6: apollo-alert-6 {
temperature = <95000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
cooling-maps {
map0 {
/* Set maximum frequency as 1200MHz */
trip = <&apollo_alert_2>;
cooling-device = <&cpu0 1 2>;
};
map1 {
/* Set maximum frequency as 1100MHz */
trip = <&apollo_alert_3>;
cooling-device = <&cpu0 2 3>;
};
map2 {
/* Set maximum frequency as 1000MHz */
trip = <&apollo_alert_4>;
cooling-device = <&cpu0 3 4>;
};
map3 {
/* Set maximum frequency as 900MHz */
trip = <&apollo_alert_5>;
cooling-device = <&cpu0 4 5>;
};
map4 {
/* Set maximum frequency as 800MHz */
trip = <&apollo_alert_6>;
cooling-device = <&cpu0 5 9>;
};
};
};
isp_thermal: isp-thermal {
thermal-sensors = <&tmu_isp>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
isp_alert_0: isp-alert-0 {
temperature = <80000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_1: isp-alert-1 {
temperature = <85000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_2: isp-alert-2 {
temperature = <90000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_3: isp-alert-3 {
temperature = <95000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_4: isp-alert-4 {
temperature = <100000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_5: isp-alert-5 {
temperature = <105000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_6: isp-alert-6 {
temperature = <110000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
};
};
};
arch/arm64/boot/dts/exynos/exynos5433.dtsi 0 → 100644
View file @ 482c3e88
/*
* Samsung's Exynos5433 SoC device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
*
* Samsung's Exynos5433 SoC device nodes are listed in this file.
* Exynos5433 based board files can include this file and provide
* values for board specific bindings.
*
* Note: This file does not include device nodes for all the controllers in
* Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
* additional nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "samsung,exynos5433";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
reg = <0x100>;
clock-frequency = <1300000000>;
clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
clock-names = "apolloclk";
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
};
cpu1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
reg = <0x101>;
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
};
cpu2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
reg = <0x102>;
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
};
cpu3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
reg = <0x103>;
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
};
cpu4: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x0>;
clock-frequency = <1900000000>;
clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
clock-names = "atlasclk";
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
};
cpu5: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x1>;
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
};
cpu6: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x2>;
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
};
cpu7: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x3>;
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
};
};
cluster_a53_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <900000>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <925000>;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
};
opp@700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <975000>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1000000>;
};
opp@900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1050000>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1075000>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1112500>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1112500>;
};
opp@1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1150000>;
};
};
cluster_a57_opp_table: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <900000>;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <900000>;
};
opp@700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <912500>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <912500>;
};
opp@900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <937500>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <975000>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1012500>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1037500>;
};
opp@1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1062500>;
};
opp@1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1087500>;
};
opp@1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1125000>;
};
opp@1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <1137500>;
};
opp@1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <1175000>;
};
opp@1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1212500>;
};
opp@1900000000 {
opp-hz = /bits/ 64 <1900000000>;
opp-microvolt = <1262500>;
};
};
psci {
compatible = "arm,psci";
method = "smc";
cpu_off = <0x84000002>;
cpu_on = <0xC4000003>;
};
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&pmu_system_controller>;
offset = <0x400>; /* SWRESET */
mask = <0x1>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x18000000>;
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
xxti: xxti {
compatible = "fixed-clock";
clock-output-names = "oscclk";
#clock-cells = <0>;
};
cmu_top: clock-controller@10030000 {
compatible = "samsung,exynos5433-cmu-top";
reg = <0x10030000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_mphy_pll",
"sclk_mfc_pll",
"sclk_bus_pll";
clocks = <&xxti>,
<&cmu_cpif CLK_SCLK_MPHY_PLL>,
<&cmu_mif CLK_SCLK_MFC_PLL>,
<&cmu_mif CLK_SCLK_BUS_PLL>;
};
cmu_cpif: clock-controller@10fc0000 {
compatible = "samsung,exynos5433-cmu-cpif";
reg = <0x10fc0000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk";
clocks = <&xxti>;
};
cmu_mif: clock-controller@105b0000 {
compatible = "samsung,exynos5433-cmu-mif";
reg = <0x105b0000 0x2000>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_mphy_pll";
clocks = <&xxti>,
<&cmu_cpif CLK_SCLK_MPHY_PLL>;
};
cmu_peric: clock-controller@14c80000 {
compatible = "samsung,exynos5433-cmu-peric";
reg = <0x14c80000 0x1000>;
#clock-cells = <1>;
};
cmu_peris: clock-controller@0x10040000 {
compatible = "samsung,exynos5433-cmu-peris";
reg = <0x10040000 0x1000>;
#clock-cells = <1>;
};
cmu_fsys: clock-controller@156e0000 {
compatible = "samsung,exynos5433-cmu-fsys";
reg = <0x156e0000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_ufs_mphy",
"aclk_fsys_200",
"sclk_pcie_100_fsys",
"sclk_ufsunipro_fsys",
"sclk_mmc2_fsys",
"sclk_mmc1_fsys",
"sclk_mmc0_fsys",
"sclk_usbhost30_fsys",
"sclk_usbdrd30_fsys";
clocks = <&xxti>,
<&cmu_cpif CLK_SCLK_UFS_MPHY>,
<&cmu_top CLK_ACLK_FSYS_200>,
<&cmu_top CLK_SCLK_PCIE_100_FSYS>,
<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
<&cmu_top CLK_SCLK_MMC2_FSYS>,
<&cmu_top CLK_SCLK_MMC1_FSYS>,
<&cmu_top CLK_SCLK_MMC0_FSYS>,
<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
<&cmu_top CLK_SCLK_USBDRD30_FSYS>;
};
cmu_g2d: clock-controller@12460000 {
compatible = "samsung,exynos5433-cmu-g2d";
reg = <0x12460000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_g2d_266",
"aclk_g2d_400";
clocks = <&xxti>,
<&cmu_top CLK_ACLK_G2D_266>,
<&cmu_top CLK_ACLK_G2D_400>;
};
cmu_disp: clock-controller@13b90000 {
compatible = "samsung,exynos5433-cmu-disp";
reg = <0x13b90000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_dsim1_disp",
"sclk_dsim0_disp",
"sclk_dsd_disp",
"sclk_decon_tv_eclk_disp",
"sclk_decon_vclk_disp",
"sclk_decon_eclk_disp",
"sclk_decon_tv_vclk_disp",
"aclk_disp_333";
clocks = <&xxti>,
<&cmu_mif CLK_SCLK_DSIM1_DISP>,
<&cmu_mif CLK_SCLK_DSIM0_DISP>,
<&cmu_mif CLK_SCLK_DSD_DISP>,
<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
<&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
<&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
<&cmu_mif CLK_ACLK_DISP_333>;
};
cmu_aud: clock-controller@114c0000 {
compatible = "samsung,exynos5433-cmu-aud";
reg = <0x114c0000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk", "fout_aud_pll";
clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
};
cmu_bus0: clock-controller@13600000 {
compatible = "samsung,exynos5433-cmu-bus0";
reg = <0x13600000 0x1000>;
#clock-cells = <1>;
clock-names = "aclk_bus0_400";
clocks = <&cmu_top CLK_ACLK_BUS0_400>;
};
cmu_bus1: clock-controller@14800000 {
compatible = "samsung,exynos5433-cmu-bus1";
reg = <0x14800000 0x1000>;
#clock-cells = <1>;
clock-names = "aclk_bus1_400";
clocks = <&cmu_top CLK_ACLK_BUS1_400>;
};
cmu_bus2: clock-controller@13400000 {
compatible = "samsung,exynos5433-cmu-bus2";
reg = <0x13400000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk", "aclk_bus2_400";
clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
};
cmu_g3d: clock-controller@14aa0000 {
compatible = "samsung,exynos5433-cmu-g3d";
reg = <0x14aa0000 0x2000>;
#clock-cells = <1>;
clock-names = "oscclk", "aclk_g3d_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
};
cmu_gscl: clock-controller@13cf0000 {
compatible = "samsung,exynos5433-cmu-gscl";
reg = <0x13cf0000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_gscl_111",
"aclk_gscl_333";
clocks = <&xxti>,
<&cmu_top CLK_ACLK_GSCL_111>,
<&cmu_top CLK_ACLK_GSCL_333>;
};
cmu_apollo: clock-controller@11900000 {
compatible = "samsung,exynos5433-cmu-apollo";
reg = <0x11900000 0x2000>;
#clock-cells = <1>;
clock-names = "oscclk", "sclk_bus_pll_apollo";
clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
};
cmu_atlas: clock-controller@11800000 {
compatible = "samsung,exynos5433-cmu-atlas";
reg = <0x11800000 0x2000>;
#clock-cells = <1>;
clock-names = "oscclk", "sclk_bus_pll_atlas";
clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
};
cmu_mscl: clock-controller@105d0000 {
compatible = "samsung,exynos5433-cmu-mscl";
reg = <0x150d0000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_jpeg_mscl",
"aclk_mscl_400";
clocks = <&xxti>,
<&cmu_top CLK_SCLK_JPEG_MSCL>,
<&cmu_top CLK_ACLK_MSCL_400>;
};
cmu_mfc: clock-controller@15280000 {
compatible = "samsung,exynos5433-cmu-mfc";
reg = <0x15280000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk", "aclk_mfc_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
};
cmu_hevc: clock-controller@14f80000 {
compatible = "samsung,exynos5433-cmu-hevc";
reg = <0x14f80000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk", "aclk_hevc_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
};
cmu_isp: clock-controller@146d0000 {
compatible = "samsung,exynos5433-cmu-isp";
reg = <0x146d0000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_isp_dis_400",
"aclk_isp_400";
clocks = <&xxti>,
<&cmu_top CLK_ACLK_ISP_DIS_400>,
<&cmu_top CLK_ACLK_ISP_400>;
};
cmu_cam0: clock-controller@120d0000 {
compatible = "samsung,exynos5433-cmu-cam0";
reg = <0x120d0000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_cam0_333",
"aclk_cam0_400",
"aclk_cam0_552";
clocks = <&xxti>,
<&cmu_top CLK_ACLK_CAM0_333>,
<&cmu_top CLK_ACLK_CAM0_400>,
<&cmu_top CLK_ACLK_CAM0_552>;
};
cmu_cam1: clock-controller@145d0000 {
compatible = "samsung,exynos5433-cmu-cam1";
reg = <0x145d0000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"sclk_isp_uart_cam1",
"sclk_isp_spi1_cam1",
"sclk_isp_spi0_cam1",
"aclk_cam1_333",
"aclk_cam1_400",
"aclk_cam1_552";
clocks = <&xxti>,
<&cmu_top CLK_SCLK_ISP_UART_CAM1>,
<&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
<&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
<&cmu_top CLK_ACLK_CAM1_333>,
<&cmu_top CLK_ACLK_CAM1_400>,
<&cmu_top CLK_ACLK_CAM1_552>;
};
tmu_atlas0: tmu@10060000 {
compatible = "samsung,exynos5433-tmu";
reg = <0x10060000 0x200>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
<&cmu_peris CLK_SCLK_TMU0>;
clock-names = "tmu_apbif", "tmu_sclk";
#include "exynos5433-tmu-sensor-conf.dtsi"
status = "disabled";
};
tmu_atlas1: tmu@10068000 {
compatible = "samsung,exynos5433-tmu";
reg = <0x10068000 0x200>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
<&cmu_peris CLK_SCLK_TMU0>;
clock-names = "tmu_apbif", "tmu_sclk";
#include "exynos5433-tmu-sensor-conf.dtsi"
status = "disabled";
};
tmu_g3d: tmu@10070000 {
compatible = "samsung,exynos5433-tmu";
reg = <0x10070000 0x200>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
<&cmu_peris CLK_SCLK_TMU1>;
clock-names = "tmu_apbif", "tmu_sclk";
#include "exynos5433-tmu-g3d-sensor-conf.dtsi"
status = "disabled";
};
tmu_apollo: tmu@10078000 {
compatible = "samsung,exynos5433-tmu";
reg = <0x10078000 0x200>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
<&cmu_peris CLK_SCLK_TMU1>;
clock-names = "tmu_apbif", "tmu_sclk";
#include "exynos5433-tmu-sensor-conf.dtsi"
status = "disabled";
};
tmu_isp: tmu@1007c000 {
compatible = "samsung,exynos5433-tmu";
reg = <0x1007c000 0x200>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
<&cmu_peris CLK_SCLK_TMU1>;
clock-names = "tmu_apbif", "tmu_sclk";
#include "exynos5433-tmu-sensor-conf.dtsi"
status = "disabled";
};
mct@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101c0000 0x800>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
clock-names = "fin_pll", "mct";
};
pinctrl_alive: pinctrl@10580000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_aud: pinctrl@114b0000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x114b0000 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_cpif: pinctrl@10fe0000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x10fe0000 0x1000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_ese: pinctrl@14ca0000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x14ca0000 0x1000>;
interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_finger: pinctrl@14cb0000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x14cb0000 0x1000>;
interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_fsys: pinctrl@15690000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x15690000 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_imem: pinctrl@11090000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x11090000 0x1000>;
interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_nfc: pinctrl@14cd0000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x14cd0000 0x1000>;
interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_peric: pinctrl@14cc0000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x14cc0000 0x1100>;
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_touch: pinctrl@14ce0000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x14ce0000 0x1100>;
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller@105c0000 {
compatible = "samsung,exynos5433-pmu", "syscon";
reg = <0x105c0000 0x5008>;
#clock-cells = <1>;
clock-names = "clkout16";
clocks = <&xxti>;
};
gic: interrupt-controller@11001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x11001000 0x1000>,
<0x11002000 0x2000>,
<0x11004000 0x2000>,
<0x11006000 0x2000>;
interrupts = <GIC_PPI 9 0xf04>;
};
mipi_phy: video-phy@105c0710 {
compatible = "samsung,exynos5433-mipi-video-phy";
#phy-cells = <1>;
samsung,pmu-syscon = <&pmu_system_controller>;
samsung,cam0-sysreg = <&syscon_cam0>;
samsung,cam1-sysreg = <&syscon_cam1>;
samsung,disp-sysreg = <&syscon_disp>;
};
decon: decon@13800000 {
compatible = "samsung,exynos5433-decon";
reg = <0x13800000 0x2104>;
clocks = <&cmu_disp CLK_PCLK_DECON>,
<&cmu_disp CLK_ACLK_DECON>,
<&cmu_disp CLK_ACLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_XIU_DECON0X>,
<&cmu_disp CLK_PCLK_SMMU_DECON0X>,
<&cmu_disp CLK_SCLK_DECON_VCLK>,
<&cmu_disp CLK_SCLK_DECON_ECLK>;
clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
"aclk_xiu_decon0x", "pclk_smmu_decon0x",
"sclk_decon_vclk", "sclk_decon_eclk";
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
samsung,disp-sysreg = <&syscon_disp>;
status = "disabled";
iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
iommu-names = "m0", "m1";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
decon_to_mic: endpoint {
remote-endpoint =
<&mic_to_decon>;
};
};
};
};
dsi: dsi@13900000 {
compatible = "samsung,exynos5433-mipi-dsi";
reg = <0x13900000 0xC0>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&cmu_disp CLK_PCLK_DSIM0>,
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
<&cmu_disp CLK_SCLK_DSIM0>;
clock-names = "bus_clk",
"phyclk_mipidphy0_bitclkdiv8",
"phyclk_mipidphy0_rxclkesc0",
"sclk_rgb_vclk_to_dsim0",
"sclk_mipi";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_to_mic: endpoint {
remote-endpoint = <&mic_to_dsi>;
};
};
};
};
mic: mic@13930000 {
compatible = "samsung,exynos5433-mic";
reg = <0x13930000 0x48>;
clocks = <&cmu_disp CLK_PCLK_MIC0>,
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
samsung,disp-syscon = <&syscon_disp>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mic_to_decon: endpoint {
remote-endpoint =
<&decon_to_mic>;
};
};
port@1 {
reg = <1>;
mic_to_dsi: endpoint {
remote-endpoint = <&dsi_to_mic>;
};
};
};
};
syscon_disp: syscon@13b80000 {
compatible = "syscon";
reg = <0x13b80000 0x1010>;
};
syscon_cam0: syscon@120f0000 {
compatible = "syscon";
reg = <0x120f0000 0x1020>;
};
syscon_cam1: syscon@145f0000 {
compatible = "syscon";
reg = <0x145f0000 0x1038>;
};
gsc_0: video-scaler@13C00000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c00000 0x1000>;
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu",
"aclk_gsclbend";
clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
<&cmu_gscl CLK_ACLK_GSCL0>,
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
iommus = <&sysmmu_gscl0>;
};
gsc_1: video-scaler@13C10000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c10000 0x1000>;
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu",
"aclk_gsclbend";
clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
<&cmu_gscl CLK_ACLK_GSCL1>,
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
iommus = <&sysmmu_gscl1>;
};
gsc_2: video-scaler@13C20000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c20000 0x1000>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu",
"aclk_gsclbend";
clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
<&cmu_gscl CLK_ACLK_GSCL2>,
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
iommus = <&sysmmu_gscl2>;
};
jpeg: codec@15020000 {
compatible = "samsung,exynos5433-jpeg";
reg = <0x15020000 0x10000>;
interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
clocks = <&cmu_mscl CLK_PCLK_JPEG>,
<&cmu_mscl CLK_ACLK_JPEG>,
<&cmu_mscl CLK_ACLK_XIU_MSCLX>,
<&cmu_mscl CLK_SCLK_JPEG>;
iommus = <&sysmmu_jpeg>;
};
mfc: codec@152E0000 {
compatible = "samsung,exynos5433-mfc";
reg = <0x152E0000 0x10000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu";
clocks = <&cmu_mfc CLK_PCLK_MFC>,
<&cmu_mfc CLK_ACLK_MFC>,
<&cmu_mfc CLK_ACLK_XIU_MFCX>;
iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
iommu-names = "left", "right";
};
sysmmu_decon0x: sysmmu@0x13a00000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13a00000 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk";
clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_SMMU_DECON0X>;
#iommu-cells = <0>;
};
sysmmu_decon1x: sysmmu@0x13a10000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13a10000 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk";
clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
<&cmu_disp CLK_ACLK_SMMU_DECON1X>;
#iommu-cells = <0>;
};
sysmmu_gscl0: sysmmu@0x13C80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13C80000 0x1000>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk", "pclk";
clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
<&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
#iommu-cells = <0>;
};
sysmmu_gscl1: sysmmu@0x13C90000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13C90000 0x1000>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk", "pclk";
clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
<&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
#iommu-cells = <0>;
};
sysmmu_gscl2: sysmmu@0x13CA0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13CA0000 0x1000>;
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk", "pclk";
clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
<&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
#iommu-cells = <0>;
};
sysmmu_jpeg: sysmmu@0x15060000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x15060000 0x1000>;
interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk";
clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
<&cmu_mscl CLK_ACLK_SMMU_JPEG>;
#iommu-cells = <0>;
};
sysmmu_mfc_0: sysmmu@0x15200000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x15200000 0x1000>;
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk";
clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
<&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
#iommu-cells = <0>;
};
sysmmu_mfc_1: sysmmu@0x15210000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x15210000 0x1000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk";
clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
<&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
#iommu-cells = <0>;
};
serial_0: serial@14c10000 {
compatible = "samsung,exynos5433-uart";
reg = <0x14c10000 0x100>;
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peric CLK_PCLK_UART0>,
<&cmu_peric CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>;
status = "disabled";
};
serial_1: serial@14c20000 {
compatible = "samsung,exynos5433-uart";
reg = <0x14c20000 0x100>;
interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peric CLK_PCLK_UART1>,
<&cmu_peric CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart1_bus>;
status = "disabled";
};
serial_2: serial@14c30000 {
compatible = "samsung,exynos5433-uart";
reg = <0x14c30000 0x100>;
interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peric CLK_PCLK_UART2>,
<&cmu_peric CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart2_bus>;
status = "disabled";
};
spi_0: spi@14d20000 {
compatible = "samsung,exynos5433-spi";
reg = <0x14d20000 0x100>;
interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 9>, <&pdma0 8>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_peric CLK_PCLK_SPI0>,
<&cmu_peric CLK_SCLK_SPI0>,
<&cmu_peric CLK_SCLK_IOCLK_SPI0>;
clock-names = "spi", "spi_busclk0", "spi_ioclk";
samsung,spi-src-clk = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
num-cs = <1>;
status = "disabled";
};
spi_1: spi@14d30000 {
compatible = "samsung,exynos5433-spi";
reg = <0x14d30000 0x100>;
interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 11>, <&pdma0 10>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_peric CLK_PCLK_SPI1>,
<&cmu_peric CLK_SCLK_SPI1>,
<&cmu_peric CLK_SCLK_IOCLK_SPI1>;
clock-names = "spi", "spi_busclk0", "spi_ioclk";
samsung,spi-src-clk = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
num-cs = <1>;
status = "disabled";
};
spi_2: spi@14d40000 {
compatible = "samsung,exynos5433-spi";
reg = <0x14d40000 0x100>;
interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 13>, <&pdma0 12>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_peric CLK_PCLK_SPI2>,
<&cmu_peric CLK_SCLK_SPI2>,
<&cmu_peric CLK_SCLK_IOCLK_SPI2>;
clock-names = "spi", "spi_busclk0", "spi_ioclk";
samsung,spi-src-clk = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
num-cs = <1>;
status = "disabled";
};
spi_3: spi@14d50000 {
compatible = "samsung,exynos5433-spi";
reg = <0x14d50000 0x100>;
interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 23>, <&pdma0 22>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_peric CLK_PCLK_SPI3>,
<&cmu_peric CLK_SCLK_SPI3>,
<&cmu_peric CLK_SCLK_IOCLK_SPI3>;
clock-names = "spi", "spi_busclk0", "spi_ioclk";
samsung,spi-src-clk = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi3_bus>;
num-cs = <1>;
status = "disabled";
};
spi_4: spi@14d00000 {
compatible = "samsung,exynos5433-spi";
reg = <0x14d00000 0x100>;
interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 25>, <&pdma0 24>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_peric CLK_PCLK_SPI4>,
<&cmu_peric CLK_SCLK_SPI4>,
<&cmu_peric CLK_SCLK_IOCLK_SPI4>;
clock-names = "spi", "spi_busclk0", "spi_ioclk";
samsung,spi-src-clk = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi4_bus>;
num-cs = <1>;
status = "disabled";
};
adc: adc@14d10000 {
compatible = "samsung,exynos7-adc";
reg = <0x14d10000 0x100>;
interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "adc";
clocks = <&cmu_peric CLK_PCLK_ADCIF>;
#io-channel-cells = <1>;
io-channel-ranges;
status = "disabled";
};
pwm: pwm@14dd0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x14dd0000 0x100>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
clocks = <&cmu_peric CLK_PCLK_PWM>;
clock-names = "timers";
#pwm-cells = <3>;
status = "disabled";
};
hsi2c_0: hsi2c@14e40000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e40000 0x1000>;
interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c0_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_1: hsi2c@14e50000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e50000 0x1000>;
interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c1_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_2: hsi2c@14e60000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e60000 0x1000>;
interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c2_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_3: hsi2c@14e70000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e70000 0x1000>;
interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c3_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_4: hsi2c@14ec0000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14ec0000 0x1000>;
interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c4_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_5: hsi2c@14ed0000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14ed0000 0x1000>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c5_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_6: hsi2c@14ee0000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14ee0000 0x1000>;
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c6_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_7: hsi2c@14ef0000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14ef0000 0x1000>;
interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c7_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_8: hsi2c@14d90000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14d90000 0x1000>;
interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c8_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_9: hsi2c@14da0000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14da0000 0x1000>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c9_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_10: hsi2c@14de0000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14de0000 0x1000>;
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c10_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_11: hsi2c@14df0000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14df0000 0x1000>;
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c11_bus>;
clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
clock-names = "hsi2c";
status = "disabled";
};
usbdrd30: usb@15400000 {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
<&cmu_fsys CLK_SCLK_USBDRD30>;
clock-names = "usbdrd30", "usbdrd30_susp_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
dwc3@15400000 {
compatible = "snps,dwc3";
reg = <0x15400000 0x10000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
};
};
usbdrd30_phy: phy@15500000 {
compatible = "samsung,exynos5433-usbdrd-phy";
reg = <0x15500000 0x100>;
clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
<&cmu_fsys CLK_SCLK_USBDRD30>;
clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
"itp";
#phy-cells = <1>;
samsung,pmu-syscon = <&pmu_system_controller>;
status = "disabled";
};
usbhost30_phy: phy@15580000 {
compatible = "samsung,exynos5433-usbdrd-phy";
reg = <0x15580000 0x100>;
clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
<&cmu_fsys CLK_SCLK_USBHOST30>;
clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
"itp";
#phy-cells = <1>;
samsung,pmu-syscon = <&pmu_system_controller>;
status = "disabled";
};
usbhost30: usb@15a00000 {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
<&cmu_fsys CLK_SCLK_USBHOST30>;
clock-names = "usbdrd30", "usbdrd30_susp_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
usbdrd_dwc3_0: dwc3@15a00000 {
compatible = "snps,dwc3";
reg = <0x15a00000 0x10000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
};
};
mshc_0: mshc@15540000 {
compatible = "samsung,exynos7-dw-mshc-smu";
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15540000 0x2000>;
clocks = <&cmu_fsys CLK_ACLK_MMC0>,
<&cmu_fsys CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
mshc_1: mshc@15550000 {
compatible = "samsung,exynos7-dw-mshc-smu";
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15550000 0x2000>;
clocks = <&cmu_fsys CLK_ACLK_MMC1>,
<&cmu_fsys CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
mshc_2: mshc@15560000 {
compatible = "samsung,exynos7-dw-mshc-smu";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15560000 0x2000>;
clocks = <&cmu_fsys CLK_ACLK_MMC2>,
<&cmu_fsys CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pdma0: pdma@15610000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x15610000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_fsys CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@15600000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x15600000 0x1000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_fsys CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
};
audio-subsystem@11400000 {
compatible = "samsung,exynos5433-lpass";
reg = <0x11400000 0x100>, <0x11500000 0x08>;
samsung,pmu-syscon = <&pmu_system_controller>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
adma: adma@11420000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11420000 0x1000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_aud CLK_ACLK_DMAC>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
i2s0: i2s0@11440000 {
compatible = "samsung,exynos7-i2s";
reg = <0x11440000 0x100>;
dmas = <&adma 0 &adma 2>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
<&cmu_aud CLK_SCLK_AUD_I2S>,
<&cmu_aud CLK_SCLK_I2S_BCLK>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
status = "disabled";
};
serial_3: serial@11460000 {
compatible = "samsung,exynos5433-uart";
reg = <0x11460000 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
<&cmu_aud CLK_SCLK_AUD_UART>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart_aud_bus>;
status = "disabled";
};
};
};
timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
};
#include "exynos5433-pinctrl.dtsi"
#include "exynos5433-tmu.dtsi"
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
View file @ 482c3e88
......@@ -20,8 +20,14 @@ gpa0: gpa0 {
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
gpa1: gpa1 {
......@@ -31,8 +37,14 @@ gpa1: gpa1 {
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
gpa2: gpa2 {
......
arch/arm64/boot/dts/exynos/exynos7.dtsi
View file @ 482c3e88
......@@ -35,28 +35,28 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu_atlas0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
enable-method = "psci";
};
cpu@1 {
cpu_atlas1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>;
enable-method = "psci";
};
cpu@2 {
cpu_atlas2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x2>;
enable-method = "psci";
};
cpu@3 {
cpu_atlas3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x3>;
......@@ -106,7 +106,7 @@ amba {
pdma0: pdma@10E10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10E10000 0x1000>;
interrupts = <0 225 0>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_fsys0 ACLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
......@@ -117,7 +117,7 @@ pdma0: pdma@10E10000 {
pdma1: pdma@10EB0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10EB0000 0x1000>;
interrupts = <0 226 0>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_fsys0 ACLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
......@@ -220,7 +220,7 @@ clock_fsys1: clock-controller@156e0000 {
serial_0: serial@13630000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13630000 0x100>;
interrupts = <0 440 0>;
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric0 PCLK_UART0>,
<&clock_peric0 SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
......@@ -230,7 +230,7 @@ serial_0: serial@13630000 {
serial_1: serial@14c20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14c20000 0x100>;
interrupts = <0 456 0>;
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric1 PCLK_UART1>,
<&clock_peric1 SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
......@@ -240,7 +240,7 @@ serial_1: serial@14c20000 {
serial_2: serial@14c30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14c30000 0x100>;
interrupts = <0 457 0>;
interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric1 PCLK_UART2>,
<&clock_peric1 SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
......@@ -250,7 +250,7 @@ serial_2: serial@14c30000 {
serial_3: serial@14c40000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14c40000 0x100>;
interrupts = <0 458 0>;
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric1 PCLK_UART3>,
<&clock_peric1 SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
......@@ -264,62 +264,62 @@ pinctrl_alive: pinctrl@10580000 {
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 16 0>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_bus0: pinctrl@13470000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x13470000 0x1000>;
interrupts = <0 383 0>;
interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_nfc: pinctrl@14cd0000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14cd0000 0x1000>;
interrupts = <0 473 0>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_touch: pinctrl@14ce0000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14ce0000 0x1000>;
interrupts = <0 474 0>;
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_ff: pinctrl@14c90000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14c90000 0x1000>;
interrupts = <0 475 0>;
interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_ese: pinctrl@14ca0000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14ca0000 0x1000>;
interrupts = <0 476 0>;
interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_fsys0: pinctrl@10e60000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x10e60000 0x1000>;
interrupts = <0 221 0>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_fsys1: pinctrl@15690000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x15690000 0x1000>;
interrupts = <0 203 0>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_bus1: pinctrl@14870000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14870000 0x1000>;
interrupts = <0 384 0>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
};
hsi2c_0: hsi2c@13640000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13640000 0x1000>;
interrupts = <0 441 0>;
interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -332,7 +332,7 @@ hsi2c_0: hsi2c@13640000 {
hsi2c_1: hsi2c@13650000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13650000 0x1000>;
interrupts = <0 442 0>;
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -345,7 +345,7 @@ hsi2c_1: hsi2c@13650000 {
hsi2c_2: hsi2c@14e60000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e60000 0x1000>;
interrupts = <0 459 0>;
interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -358,7 +358,7 @@ hsi2c_2: hsi2c@14e60000 {
hsi2c_3: hsi2c@14e70000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e70000 0x1000>;
interrupts = <0 460 0>;
interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -371,7 +371,7 @@ hsi2c_3: hsi2c@14e70000 {
hsi2c_4: hsi2c@13660000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13660000 0x1000>;
interrupts = <0 443 0>;
interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -384,7 +384,7 @@ hsi2c_4: hsi2c@13660000 {
hsi2c_5: hsi2c@13670000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13670000 0x1000>;
interrupts = <0 444 0>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -397,7 +397,7 @@ hsi2c_5: hsi2c@13670000 {
hsi2c_6: hsi2c@14e00000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e00000 0x1000>;
interrupts = <0 461 0>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -410,7 +410,7 @@ hsi2c_6: hsi2c@14e00000 {
hsi2c_7: hsi2c@13e10000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13e10000 0x1000>;
interrupts = <0 462 0>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -423,7 +423,7 @@ hsi2c_7: hsi2c@13e10000 {
hsi2c_8: hsi2c@14e20000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e20000 0x1000>;
interrupts = <0 463 0>;
interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -436,7 +436,7 @@ hsi2c_8: hsi2c@14e20000 {
hsi2c_9: hsi2c@13680000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13680000 0x1000>;
interrupts = <0 445 0>;
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -449,7 +449,7 @@ hsi2c_9: hsi2c@13680000 {
hsi2c_10: hsi2c@13690000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13690000 0x1000>;
interrupts = <0 446 0>;
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -462,7 +462,7 @@ hsi2c_10: hsi2c@13690000 {
hsi2c_11: hsi2c@136a0000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x136a0000 0x1000>;
interrupts = <0 447 0>;
interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
......@@ -472,6 +472,16 @@ hsi2c_11: hsi2c@136a0000 {
status = "disabled";
};
arm-pmu {
compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
<&cpu_atlas2>, <&cpu_atlas3>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
......@@ -499,7 +509,8 @@ reboot: syscon-reboot {
rtc: rtc@10590000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10590000 0x100>;
interrupts = <0 355 0>, <0 356 0>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_ccore PCLK_RTC>;
clock-names = "rtc";
status = "disabled";
......@@ -508,7 +519,7 @@ rtc: rtc@10590000 {
watchdog: watchdog@101d0000 {
compatible = "samsung,exynos7-wdt";
reg = <0x101d0000 0x100>;
interrupts = <0 110 0>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peris PCLK_WDT>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
......@@ -517,7 +528,7 @@ watchdog: watchdog@101d0000 {
mmc_0: mmc@15740000 {
compatible = "samsung,exynos7-dw-mshc-smu";
interrupts = <0 201 0>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15740000 0x2000>;
......@@ -530,7 +541,7 @@ mmc_0: mmc@15740000 {
mmc_1: mmc@15750000 {
compatible = "samsung,exynos7-dw-mshc";
interrupts = <0 202 0>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15750000 0x2000>;
......@@ -543,7 +554,7 @@ mmc_1: mmc@15750000 {
mmc_2: mmc@15560000 {
compatible = "samsung,exynos7-dw-mshc-smu";
interrupts = <0 216 0>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15560000 0x2000>;
......@@ -557,7 +568,7 @@ mmc_2: mmc@15560000 {
adc: adc@13620000 {
compatible = "samsung,exynos7-adc";
reg = <0x13620000 0x100>;
interrupts = <0 448 0>;
interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric0 PCLK_ADCIF>;
clock-names = "adc";
#io-channel-cells = <1>;
......@@ -577,7 +588,7 @@ pwm: pwm@136c0000 {
tmuctrl_0: tmu@10060000 {
compatible = "samsung,exynos7-tmu";
reg = <0x10060000 0x200>;
interrupts = <0 108 0>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peris PCLK_TMU>,
<&clock_peris SCLK_TMU>;
clock-names = "tmu_apbif", "tmu_sclk";
......
arch/arm64/boot/dts/freescale/Makefile
View file @ 482c3e88
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
......
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
View file @ 482c3e88
......@@ -45,7 +45,7 @@
*/
/dts-v1/;
/include/ "fsl-ls1043a.dtsi"
#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
......
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
View file @ 482c3e88
......@@ -45,7 +45,7 @@
*/
/dts-v1/;
/include/ "fsl-ls1043a.dtsi"
#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
......
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View file @ 482c3e88
......@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <&gic>;
......@@ -66,6 +68,7 @@ cpu0: cpu@0 {
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
......@@ -255,6 +258,81 @@ ddr: memory-controller@1080000 {
big-endian;
};
tmu: tmu@1f00000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f00000 0x0 0x10000>;
interrupts = <0 33 0x4>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
fsl,tmu-calibration = <0x00000000 0x00000026
0x00000001 0x0000002d
0x00000002 0x00000032
0x00000003 0x00000039
0x00000004 0x0000003f
0x00000005 0x00000046
0x00000006 0x0000004d
0x00000007 0x00000054
0x00000008 0x0000005a
0x00000009 0x00000061
0x0000000a 0x0000006a
0x0000000b 0x00000071
0x00010000 0x00000025
0x00010001 0x0000002c
0x00010002 0x00000035
0x00010003 0x0000003d
0x00010004 0x00000045
0x00010005 0x0000004e
0x00010006 0x00000057
0x00010007 0x00000061
0x00010008 0x0000006b
0x00010009 0x00000076
0x00020000 0x00000029
0x00020001 0x00000033
0x00020002 0x0000003d
0x00020003 0x00000049
0x00020004 0x00000056
0x00020005 0x00000061
0x00020006 0x0000006d
0x00030000 0x00000021
0x00030001 0x0000002a
0x00030002 0x0000003c
0x00030003 0x0000004e>;
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
dspi0: dspi@2100000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
......
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts 0 → 100644
View file @ 482c3e88
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016, Freescale Semiconductor, Inc.
*
* Shaohui Xie <Shaohui.Xie@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "fsl-ls1046a.dtsi"
/ {
model = "LS1046A QDS Board";
compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&dspi {
bus-num = <0>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a11", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
};
flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst25wf040b", "jedec,spi-nor";
spi-cpol;
spi-cpha;
reg = <1>;
spi-max-frequency = <10000000>;
};
flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "en25s64", "jedec,spi-nor";
spi-cpol;
spi-cpha;
reg = <2>;
spi-max-frequency = <10000000>;
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
ina220@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
/* IRQ10_B */
interrupts = <0 150 0x4>;
};
eeprom@56 {
compatible = "atmel,24c512";
reg = <0x56>;
};
eeprom@57 {
compatible = "atmel,24c512";
reg = <0x57>;
};
temp-sensor@4c {
compatible = "adi,adt7461a";
reg = <0x4c>;
};
};
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
0x1 0x0 0x0 0x7e800000 0x00010000
0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
nor@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@1,0 {
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x10000>;
};
fpga: board-control@2,0 {
compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
reg = <0x2 0x0 0x0000100>;
};
};
&lpuart0 {
status = "okay";
};
&qspi {
num-cs = <2>;
bus-num = <0>;
status = "okay";
qflash0: s25fl128s@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
};
};
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts 0 → 100644
View file @ 482c3e88
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016, Freescale Semiconductor, Inc.
*
* Mingkai Hu <mingkai.hu@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "fsl-ls1046a.dtsi"
/ {
model = "LS1046A RDB Board";
compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
aliases {
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&i2c0 {
status = "okay";
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
temp-sensor@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
eeprom@56 {
compatible = "atmel,24c512";
reg = <0x52>;
};
eeprom@57 {
compatible = "atmel,24c512";
reg = <0x53>;
};
};
&i2c3 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NAND Flashe and CPLD on board */
ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
nand@0,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x10000>;
};
cpld: board-control@2,0 {
compatible = "fsl,ls1046ardb-cpld";
reg = <0x2 0x0 0x0000100>;
};
};
&qspi {
num-cs = <2>;
bus-num = <0>;
status = "okay";
qflash0: s25fs512s@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
};
qflash1: s25fs512s@1 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <1>;
};
};
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi 0 → 100644
View file @ 482c3e88
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016, Freescale Semiconductor, Inc.
*
* Mingkai Hu <mingkai.hu@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "fsl,ls1046a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
crypto = &crypto;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x1>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x2>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x3>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
};
l2: l2-cache {
compatible = "cache";
};
};
idle-states {
/*
* PSCI node is not added default, U-boot will add missing
* parts if it determines to use PSCI.
*/
entry-method = "arm,psci";
CPU_PH20: cpu-ph20 {
compatible = "arm,idle-state";
idle-state-name = "PH20";
arm,psci-suspend-param = <0x00010000>;
entry-latency-us = <1000>;
exit-latency-us = <1000>;
min-residency-us = <3000>;
};
};
memory@80000000 {
device_type = "memory";
};
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
};
reboot {
compatible ="syscon-reboot";
regmap = <&dcfg>;
offset = <0xb0>;
mask = <0x02>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
gic: interrupt-controller@1400000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x1410000 0 0x10000>, /* GICD */
<0x0 0x1420000 0 0x20000>, /* GICC */
<0x0 0x1440000 0 0x20000>, /* GICH */
<0x0 0x1460000 0 0x20000>; /* GICV */
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
};
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
};
qspi: quadspi@1550000 {
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
big-endian;
fsl,qspi-has-second-chip;
status = "disabled";
};
esdhc: esdhc@1560000 {
compatible = "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
big-endian;
bus-width = <4>;
};
scfg: scfg@1570000 {
compatible = "fsl,ls1046a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
big-endian;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
};
};
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x10000>;
big-endian;
};
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1046a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
#clock-cells = <2>;
clocks = <&sysclk>;
};
dspi: dspi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 1>;
spi-num-chipselects = <5>;
big-endian;
status = "disabled";
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
dmas = <&edma0 1 39>,
<&edma0 1 38>;
dma-names = "tx", "rx";
status = "disabled";
};
i2c1: i2c@2190000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
i2c2: i2c@21a0000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21a0000 0x0 0x10000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
i2c3: i2c@21b0000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21b0000 0x0 0x10000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
duart2: serial@21d0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0500 0x0 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
duart3: serial@21d0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0600 0x0 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 0>;
clock-names = "ipg";
status = "disabled";
};
lpuart1: serial@2960000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2960000 0x0 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart2: serial@2970000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2970000 0x0 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart3: serial@2980000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2980000 0x0 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart4: serial@2990000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2990000 0x0 0x1000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart5: serial@29a0000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x29a0000 0x0 0x1000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
wdog0: watchdog@2ad0000 {
compatible = "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
big-endian;
};
edma0: edma@2c00000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
reg = <0x0 0x2c00000 0x0 0x10000>,
<0x0 0x2c10000 0x0 0x10000>,
<0x0 0x2c20000 0x0 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
dma-channels = <32>;
big-endian;
clock-names = "dmamux0", "dmamux1";
clocks = <&clockgen 4 1>,
<&clockgen 4 1>;
};
usb0: usb@2f00000 {
compatible = "snps,dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
};
usb1: usb@3000000 {
compatible = "snps,dwc3";
reg = <0x0 0x3000000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
};
usb2: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
};
sata: sata@3200000 {
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
};
};
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
View file @ 482c3e88
......@@ -46,7 +46,7 @@
/dts-v1/;
/include/ "fsl-ls2080a.dtsi"
#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
......
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
View file @ 482c3e88
......@@ -46,7 +46,7 @@
/dts-v1/;
/include/ "fsl-ls2080a.dtsi"
#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a RDB Board";
......
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
View file @ 482c3e88
......@@ -46,7 +46,7 @@
/dts-v1/;
/include/ "fsl-ls2080a.dtsi"
#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a software Simulator model";
......
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View file @ 482c3e88
......@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls2080a";
interrupt-parent = <&gic>;
......@@ -62,15 +64,16 @@ cpus {
*/
/* We have 4 clusters having 2 Cortex-A57 cores each */
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1>;
......@@ -78,15 +81,16 @@ cpu@1 {
next-level-cache = <&cluster0_l2>;
};
cpu@100 {
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>;
};
cpu@101 {
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x101>;
......@@ -94,15 +98,16 @@ cpu@101 {
next-level-cache = <&cluster1_l2>;
};
cpu@200 {
cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
#cooling-cells = <2>;
};
cpu@201 {
cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x201>;
......@@ -110,15 +115,16 @@ cpu@201 {
next-level-cache = <&cluster2_l2>;
};
cpu@300 {
cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
#cooling-cells = <2>;
};
cpu@301 {
cpu7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x301>;
......@@ -222,6 +228,100 @@ dcfg: dcfg@1e00000 {
little-endian;
};
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
fsl,tmu-calibration = <0x00000000 0x00000026
0x00000001 0x0000002d
0x00000002 0x00000032
0x00000003 0x00000039
0x00000004 0x0000003f
0x00000005 0x00000046
0x00000006 0x0000004d
0x00000007 0x00000054
0x00000008 0x0000005a
0x00000009 0x00000061
0x0000000a 0x0000006a
0x0000000b 0x00000071
0x00010000 0x00000025
0x00010001 0x0000002c
0x00010002 0x00000035
0x00010003 0x0000003d
0x00010004 0x00000045
0x00010005 0x0000004e
0x00010006 0x00000057
0x00010007 0x00000061
0x00010008 0x0000006b
0x00010009 0x00000076
0x00020000 0x00000029
0x00020001 0x00000033
0x00020002 0x0000003d
0x00020003 0x00000049
0x00020004 0x00000056
0x00020005 0x00000061
0x00020006 0x0000006d
0x00030000 0x00000021
0x00030001 0x0000002a
0x00030002 0x0000003c
0x00030003 0x0000004e>;
little-endian;
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 4>;
trips {
cpu_alert: cpu-alert {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert>;
cooling-device =
<&cpu2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map2 {
trip = <&cpu_alert>;
cooling-device =
<&cpu4 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map3 {
trip = <&cpu_alert>;
cooling-device =
<&cpu6 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
serial0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
......
arch/arm64/boot/dts/hisilicon/Makefile
View file @ 482c3e88
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/hisilicon/hip06-d03.dts
View file @ 482c3e88
......@@ -41,18 +41,10 @@ &eth3 {
status = "ok";
};
&sas0 {
status = "ok";
};
&sas1 {
status = "ok";
};
&sas2 {
status = "ok";
};
&usb_ohci {
status = "ok";
};
......
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View file @ 482c3e88
......@@ -318,11 +318,17 @@ soc {
#size-cells = <2>;
ranges;
refclk: refclk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
usb_ohci: ohci@a7030000 {
compatible = "generic-ohci";
reg = <0x0 0xa7030000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
interrupts = <64 4>;
interrupts = <640 4>;
dma-coherent;
status = "disabled";
};
......@@ -331,7 +337,7 @@ usb_ehci: ehci@a7020000 {
compatible = "generic-ehci";
reg = <0x0 0xa7020000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
interrupts = <65 4>;
interrupts = <641 4>;
dma-coherent;
status = "disabled";
};
......@@ -508,7 +514,7 @@ port@5 {
};
};
eth0: ethernet@4{
eth0: ethernet-4{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
......@@ -517,7 +523,7 @@ eth0: ethernet@4{
dma-coherent;
};
eth1: ethernet@5{
eth1: ethernet-5{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
......@@ -526,7 +532,7 @@ eth1: ethernet@5{
dma-coherent;
};
eth2: ethernet@0{
eth2: ethernet-0{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
......@@ -535,7 +541,7 @@ eth2: ethernet@0{
dma-coherent;
};
eth3: ethernet@1{
eth3: ethernet-1{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
......@@ -552,6 +558,7 @@ sas0: sas@c3000000 {
ctrl-reset-reg = <0xa60>;
ctrl-reset-sts-reg = <0x5a30>;
ctrl-clock-ena-reg = <0x338>;
clocks = <&refclk 0>;
queue-count = <16>;
phy-count = <8>;
dma-coherent;
......@@ -590,10 +597,11 @@ sas1: sas@a2000000 {
reg = <0 0xa2000000 0 0x10000>;
sas-addr = [50 01 88 20 16 00 00 00];
hisilicon,sas-syscon = <&pcie_subctl>;
am-max-trans;
hip06-sas-v2-quirk-amt;
ctrl-reset-reg = <0xa18>;
ctrl-reset-sts-reg = <0x5a0c>;
ctrl-clock-ena-reg = <0x318>;
clocks = <&refclk 0>;
queue-count = <16>;
phy-count = <8>;
dma-coherent;
......@@ -635,6 +643,7 @@ sas2: sas@a3000000 {
ctrl-reset-reg = <0xae0>;
ctrl-reset-sts-reg = <0x5a70>;
ctrl-clock-ena-reg = <0x3a8>;
clocks = <&refclk 0>;
queue-count = <16>;
phy-count = <9>;
dma-coherent;
......
arch/arm64/boot/dts/hisilicon/hip07-d05.dts 0 → 100644
View file @ 482c3e88
/**
* dts file for Hisilicon D05 Development Board
*
* Copyright (C) 2016 Hisilicon Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*
*/
/dts-v1/;
#include "hip07.dtsi"
/ {
model = "Hisilicon Hip07 D05 Development Board";
compatible = "hisilicon,hip07-d05";
/* the mem node will be updated by UEFI. */
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
numa-node-id = <0>;
};
distance-map {
compatible = "numa-distance-map-v1";
distance-matrix = <0 0 10>,
<0 1 15>,
<0 2 20>,
<0 3 25>,
<1 0 15>,
<1 1 10>,
<1 2 25>,
<1 3 30>,
<2 0 20>,
<2 1 25>,
<2 2 10>,
<2 3 15>,
<3 0 25>,
<3 1 30>,
<3 2 15>,
<3 3 10>;
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "ok";
};
&usb_ohci {
status = "ok";
};
&usb_ehci {
status = "ok";
};
arch/arm64/boot/dts/hisilicon/hip07.dtsi 0 → 100644
View file @ 482c3e88
/**
* dts file for Hisilicon D05 Development Board
*
* Copyright (C) 2016 Hisilicon Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "hisilicon,hip07-d05";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
cluster2 {
core0 {
cpu = <&cpu8>;
};
core1 {
cpu = <&cpu9>;
};
core2 {
cpu = <&cpu10>;
};
core3 {
cpu = <&cpu11>;
};
};
cluster3 {
core0 {
cpu = <&cpu12>;
};
core1 {
cpu = <&cpu13>;
};
core2 {
cpu = <&cpu14>;
};
core3 {
cpu = <&cpu15>;
};
};
cluster4 {
core0 {
cpu = <&cpu16>;
};
core1 {
cpu = <&cpu17>;
};
core2 {
cpu = <&cpu18>;
};
core3 {
cpu = <&cpu19>;
};
};
cluster5 {
core0 {
cpu = <&cpu20>;
};
core1 {
cpu = <&cpu21>;
};
core2 {
cpu = <&cpu22>;
};
core3 {
cpu = <&cpu23>;
};
};
cluster6 {
core0 {
cpu = <&cpu24>;
};
core1 {
cpu = <&cpu25>;
};
core2 {
cpu = <&cpu26>;
};
core3 {
cpu = <&cpu27>;
};
};
cluster7 {
core0 {
cpu = <&cpu28>;
};
core1 {
cpu = <&cpu29>;
};
core2 {
cpu = <&cpu30>;
};
core3 {
cpu = <&cpu31>;
};
};
cluster8 {
core0 {
cpu = <&cpu32>;
};
core1 {
cpu = <&cpu33>;
};
core2 {
cpu = <&cpu34>;
};
core3 {
cpu = <&cpu35>;
};
};
cluster9 {
core0 {
cpu = <&cpu36>;
};
core1 {
cpu = <&cpu37>;
};
core2 {
cpu = <&cpu38>;
};
core3 {
cpu = <&cpu39>;
};
};
cluster10 {
core0 {
cpu = <&cpu40>;
};
core1 {
cpu = <&cpu41>;
};
core2 {
cpu = <&cpu42>;
};
core3 {
cpu = <&cpu43>;
};
};
cluster11 {
core0 {
cpu = <&cpu44>;
};
core1 {
cpu = <&cpu45>;
};
core2 {
cpu = <&cpu46>;
};
core3 {
cpu = <&cpu47>;
};
};
cluster12 {
core0 {
cpu = <&cpu48>;
};
core1 {
cpu = <&cpu49>;
};
core2 {
cpu = <&cpu50>;
};
core3 {
cpu = <&cpu51>;
};
};
cluster13 {
core0 {
cpu = <&cpu52>;
};
core1 {
cpu = <&cpu53>;
};
core2 {
cpu = <&cpu54>;
};
core3 {
cpu = <&cpu55>;
};
};
cluster14 {
core0 {
cpu = <&cpu56>;
};
core1 {
cpu = <&cpu57>;
};
core2 {
cpu = <&cpu58>;
};
core3 {
cpu = <&cpu59>;
};
};
cluster15 {
core0 {
cpu = <&cpu60>;
};
core1 {
cpu = <&cpu61>;
};
core2 {
cpu = <&cpu62>;
};
core3 {
cpu = <&cpu63>;
};
};
};
cpu0: cpu@10000 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10000>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
numa-node-id = <0>;
};
cpu1: cpu@10001 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10001>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
numa-node-id = <0>;
};
cpu2: cpu@10002 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10002>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
numa-node-id = <0>;
};
cpu3: cpu@10003 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10003>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
numa-node-id = <0>;
};
cpu4: cpu@10100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10100>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
numa-node-id = <0>;
};
cpu5: cpu@10101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10101>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
numa-node-id = <0>;
};
cpu6: cpu@10102 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10102>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
numa-node-id = <0>;
};
cpu7: cpu@10103 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10103>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
numa-node-id = <0>;
};
cpu8: cpu@10200 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10200>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
numa-node-id = <0>;
};
cpu9: cpu@10201 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10201>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
numa-node-id = <0>;
};
cpu10: cpu@10202 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10202>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
numa-node-id = <0>;
};
cpu11: cpu@10203 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10203>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
numa-node-id = <0>;
};
cpu12: cpu@10300 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10300>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
numa-node-id = <0>;
};
cpu13: cpu@10301 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10301>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
numa-node-id = <0>;
};
cpu14: cpu@10302 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10302>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
numa-node-id = <0>;
};
cpu15: cpu@10303 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x10303>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
numa-node-id = <0>;
};
cpu16: cpu@30000 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30000>;
enable-method = "psci";
next-level-cache = <&cluster4_l2>;
numa-node-id = <1>;
};
cpu17: cpu@30001 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30001>;
enable-method = "psci";
next-level-cache = <&cluster4_l2>;
numa-node-id = <1>;
};
cpu18: cpu@30002 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30002>;
enable-method = "psci";
next-level-cache = <&cluster4_l2>;
numa-node-id = <1>;
};
cpu19: cpu@30003 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30003>;
enable-method = "psci";
next-level-cache = <&cluster4_l2>;
numa-node-id = <1>;
};
cpu20: cpu@30100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30100>;
enable-method = "psci";
next-level-cache = <&cluster5_l2>;
numa-node-id = <1>;
};
cpu21: cpu@30101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30101>;
enable-method = "psci";
next-level-cache = <&cluster5_l2>;
numa-node-id = <1>;
};
cpu22: cpu@30102 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30102>;
enable-method = "psci";
next-level-cache = <&cluster5_l2>;
numa-node-id = <1>;
};
cpu23: cpu@30103 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30103>;
enable-method = "psci";
next-level-cache = <&cluster5_l2>;
numa-node-id = <1>;
};
cpu24: cpu@30200 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30200>;
enable-method = "psci";
next-level-cache = <&cluster6_l2>;
numa-node-id = <1>;
};
cpu25: cpu@30201 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30201>;
enable-method = "psci";
next-level-cache = <&cluster6_l2>;
numa-node-id = <1>;
};
cpu26: cpu@30202 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30202>;
enable-method = "psci";
next-level-cache = <&cluster6_l2>;
numa-node-id = <1>;
};
cpu27: cpu@30203 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30203>;
enable-method = "psci";
next-level-cache = <&cluster6_l2>;
numa-node-id = <1>;
};
cpu28: cpu@30300 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30300>;
enable-method = "psci";
next-level-cache = <&cluster7_l2>;
numa-node-id = <1>;
};
cpu29: cpu@30301 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30301>;
enable-method = "psci";
next-level-cache = <&cluster7_l2>;
numa-node-id = <1>;
};
cpu30: cpu@30302 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30302>;
enable-method = "psci";
next-level-cache = <&cluster7_l2>;
numa-node-id = <1>;
};
cpu31: cpu@30303 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x30303>;
enable-method = "psci";
next-level-cache = <&cluster7_l2>;
numa-node-id = <1>;
};
cpu32: cpu@50000 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50000>;
enable-method = "psci";
next-level-cache = <&cluster8_l2>;
numa-node-id = <2>;
};
cpu33: cpu@50001 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50001>;
enable-method = "psci";
next-level-cache = <&cluster8_l2>;
numa-node-id = <2>;
};
cpu34: cpu@50002 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50002>;
enable-method = "psci";
next-level-cache = <&cluster8_l2>;
numa-node-id = <2>;
};
cpu35: cpu@50003 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50003>;
enable-method = "psci";
next-level-cache = <&cluster8_l2>;
numa-node-id = <2>;
};
cpu36: cpu@50100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50100>;
enable-method = "psci";
next-level-cache = <&cluster9_l2>;
numa-node-id = <2>;
};
cpu37: cpu@50101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50101>;
enable-method = "psci";
next-level-cache = <&cluster9_l2>;
numa-node-id = <2>;
};
cpu38: cpu@50102 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50102>;
enable-method = "psci";
next-level-cache = <&cluster9_l2>;
numa-node-id = <2>;
};
cpu39: cpu@50103 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50103>;
enable-method = "psci";
next-level-cache = <&cluster9_l2>;
numa-node-id = <2>;
};
cpu40: cpu@50200 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50200>;
enable-method = "psci";
next-level-cache = <&cluster10_l2>;
numa-node-id = <2>;
};
cpu41: cpu@50201 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50201>;
enable-method = "psci";
next-level-cache = <&cluster10_l2>;
numa-node-id = <2>;
};
cpu42: cpu@50202 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50202>;
enable-method = "psci";
next-level-cache = <&cluster10_l2>;
numa-node-id = <2>;
};
cpu43: cpu@50203 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50203>;
enable-method = "psci";
next-level-cache = <&cluster10_l2>;
numa-node-id = <2>;
};
cpu44: cpu@50300 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50300>;
enable-method = "psci";
next-level-cache = <&cluster11_l2>;
numa-node-id = <2>;
};
cpu45: cpu@50301 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50301>;
enable-method = "psci";
next-level-cache = <&cluster11_l2>;
numa-node-id = <2>;
};
cpu46: cpu@50302 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50302>;
enable-method = "psci";
next-level-cache = <&cluster11_l2>;
numa-node-id = <2>;
};
cpu47: cpu@50303 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x50303>;
enable-method = "psci";
next-level-cache = <&cluster11_l2>;
numa-node-id = <2>;
};
cpu48: cpu@70000 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70000>;
enable-method = "psci";
next-level-cache = <&cluster12_l2>;
numa-node-id = <3>;
};
cpu49: cpu@70001 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70001>;
enable-method = "psci";
next-level-cache = <&cluster12_l2>;
numa-node-id = <3>;
};
cpu50: cpu@70002 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70002>;
enable-method = "psci";
next-level-cache = <&cluster12_l2>;
numa-node-id = <3>;
};
cpu51: cpu@70003 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70003>;
enable-method = "psci";
next-level-cache = <&cluster12_l2>;
numa-node-id = <3>;
};
cpu52: cpu@70100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70100>;
enable-method = "psci";
next-level-cache = <&cluster13_l2>;
numa-node-id = <3>;
};
cpu53: cpu@70101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70101>;
enable-method = "psci";
next-level-cache = <&cluster13_l2>;
numa-node-id = <3>;
};
cpu54: cpu@70102 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70102>;
enable-method = "psci";
next-level-cache = <&cluster13_l2>;
numa-node-id = <3>;
};
cpu55: cpu@70103 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70103>;
enable-method = "psci";
next-level-cache = <&cluster13_l2>;
numa-node-id = <3>;
};
cpu56: cpu@70200 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70200>;
enable-method = "psci";
next-level-cache = <&cluster14_l2>;
numa-node-id = <3>;
};
cpu57: cpu@70201 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70201>;
enable-method = "psci";
next-level-cache = <&cluster14_l2>;
numa-node-id = <3>;
};
cpu58: cpu@70202 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70202>;
enable-method = "psci";
next-level-cache = <&cluster14_l2>;
numa-node-id = <3>;
};
cpu59: cpu@70203 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70203>;
enable-method = "psci";
next-level-cache = <&cluster14_l2>;
numa-node-id = <3>;
};
cpu60: cpu@70300 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70300>;
enable-method = "psci";
next-level-cache = <&cluster15_l2>;
numa-node-id = <3>;
};
cpu61: cpu@70301 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70301>;
enable-method = "psci";
next-level-cache = <&cluster15_l2>;
numa-node-id = <3>;
};
cpu62: cpu@70302 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70302>;
enable-method = "psci";
next-level-cache = <&cluster15_l2>;
numa-node-id = <3>;
};
cpu63: cpu@70303 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x70303>;
enable-method = "psci";
next-level-cache = <&cluster15_l2>;
numa-node-id = <3>;
};
cluster0_l2: l2-cache0 {
compatible = "cache";
};
cluster1_l2: l2-cache1 {
compatible = "cache";
};
cluster2_l2: l2-cache2 {
compatible = "cache";
};
cluster3_l2: l2-cache3 {
compatible = "cache";
};
cluster4_l2: l2-cache4 {
compatible = "cache";
};
cluster5_l2: l2-cache5 {
compatible = "cache";
};
cluster6_l2: l2-cache6 {
compatible = "cache";
};
cluster7_l2: l2-cache7 {
compatible = "cache";
};
cluster8_l2: l2-cache8 {
compatible = "cache";
};
cluster9_l2: l2-cache9 {
compatible = "cache";
};
cluster10_l2: l2-cache10 {
compatible = "cache";
};
cluster11_l2: l2-cache11 {
compatible = "cache";
};
cluster12_l2: l2-cache12 {
compatible = "cache";
};
cluster13_l2: l2-cache13 {
compatible = "cache";
};
cluster14_l2: l2-cache14 {
compatible = "cache";
};
cluster15_l2: l2-cache15 {
compatible = "cache";
};
};
gic: interrupt-controller@4d000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
#redistributor-regions = <4>;
redistributor-stride = <0x0 0x40000>;
reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */
<0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */
<0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */
<0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */
<0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */
<0x0 0xfe000000 0x0 0x10000>, /* GICC */
<0x0 0xfe010000 0x0 0x10000>, /* GICH */
<0x0 0xfe020000 0x0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
p0_its_peri_a: interrupt-controller@4c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x4c000000 0x0 0x40000>;
};
p0_its_peri_b: interrupt-controller@6c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x6c000000 0x0 0x40000>;
};
p0_its_dsa_a: interrupt-controller@c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xc6000000 0x0 0x40000>;
};
p0_its_dsa_b: interrupt-controller@8,c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x8 0xc6000000 0x0 0x40000>;
};
p1_its_peri_a: interrupt-controller@400,4c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0x4c000000 0x0 0x40000>;
};
p1_its_peri_b: interrupt-controller@400,6c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0x6c000000 0x0 0x40000>;
};
p1_its_dsa_a: interrupt-controller@400,c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0xc6000000 0x0 0x40000>;
};
p1_its_dsa_b: interrupt-controller@408,c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x408 0xc6000000 0x0 0x40000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
p0_mbigen_peri_b: interrupt-controller@60080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0x60080000 0x0 0x10000>;
mbigen_uart: uart_intc {
msi-parent = <&p0_its_peri_b 0x120c7>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <1>;
};
};
p0_mbigen_pcie_a: interrupt-controller@a0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xa0080000 0x0 0x10000>;
mbigen_usb: intc_usb {
msi-parent = <&p0_its_dsa_a 0x40080>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <2>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
uart0: uart@602b0000 {
compatible = "arm,sbsa-uart";
reg = <0x0 0x602b0000 0x0 0x1000>;
interrupt-parent = <&mbigen_uart>;
interrupts = <807 4>;
current-speed = <115200>;
reg-io-width = <4>;
status = "disabled";
};
usb_ohci: ohci@a7030000 {
compatible = "generic-ohci";
reg = <0x0 0xa7030000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
interrupts = <640 4>;
dma-coherent;
status = "disabled";
};
usb_ehci: ehci@a7020000 {
compatible = "generic-ehci";
reg = <0x0 0xa7020000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
interrupts = <641 4>;
dma-coherent;
status = "disabled";
};
};
};
arch/arm64/boot/dts/marvell/Makefile
View file @ 482c3e88
......@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
# Mvebu SoC Family
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
......
arch/arm64/boot/dts/marvell/armada-3720-db.dts
View file @ 482c3e88
......@@ -56,7 +56,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
......
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts 0 → 100644
View file @ 482c3e88
/*
* Device Tree file for Globalscale Marvell ESPRESSOBin Board
* Copyright (C) 2016 Marvell
*
* Romain Perier <romain.perier@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-372x.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Board";
compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
};
/* J9 */
&pcie0 {
status = "okay";
};
/* J6 */
&sata {
status = "okay";
};
/* Exported on the micro USB connector J5 through an FTDI */
&uart0 {
status = "okay";
};
/* J7 */
&usb3 {
status = "okay";
};
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View file @ 482c3e88
......@@ -91,7 +91,7 @@ soc {
#size-cells = <2>;
ranges;
internal-regs {
internal-regs@d0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
......
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View file @ 482c3e88
......@@ -71,7 +71,7 @@ ap806 {
interrupt-parent = <&gic>;
ranges;
config-space {
config-space@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
......
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
View file @ 482c3e88
......@@ -52,7 +52,7 @@ cp110-master {
interrupt-parent = <&gic>;
ranges;
config-space {
config-space@f2000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
......
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
View file @ 482c3e88
......@@ -52,7 +52,7 @@ cp110-slave {
interrupt-parent = <&gic>;
ranges;
config-space {
config-space@f4000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
......
arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts
View file @ 482c3e88
......@@ -54,7 +54,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@1000000 {
device_type = "memory";
/* the first 16MB is for firmwares' usage */
reg = <0 0x01000000 0 0x7f000000>;
......
arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
View file @ 482c3e88
......@@ -54,7 +54,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@1000000 {
device_type = "memory";
/* the first 16MB is for firmwares' usage */
reg = <0 0x01000000 0 0x7f000000>;
......
arch/arm64/boot/dts/marvell/berlin4ct.dtsi
View file @ 482c3e88
......@@ -142,7 +142,7 @@ timer {
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
soc@f7000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm64/boot/dts/nvidia/Makefile
View file @ 482c3e88
......@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
always := $(dtb-y)
clean-files := *.dtb
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts 0 → 100644
View file @ 482c3e88
/dts-v1/;
#include "tegra186-p3310.dtsi"
/ {
model = "NVIDIA Tegra186 P2771-0000 Development Board";
compatible = "nvidia,p2771-0000", "nvidia,tegra186";
};
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi 0 → 100644
View file @ 482c3e88
#include "tegra186.dtsi"
/ {
model = "NVIDIA Tegra186 P3310 Processor Module";
compatible = "nvidia,p3310", "nvidia,tegra186";
aliases {
serial0 = &uarta;
};
chosen {
bootargs = "earlycon console=ttyS0,115200n8";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x00000000>;
};
serial@3100000 {
status = "okay";
};
hsp@3c00000 {
status = "okay";
};
cpus {
cpu@0 {
enable-method = "psci";
};
cpu@1 {
enable-method = "psci";
};
cpu@2 {
enable-method = "psci";
};
cpu@3 {
enable-method = "psci";
};
cpu@4 {
enable-method = "psci";
};
cpu@5 {
enable-method = "psci";
};
};
bpmp {
status = "okay";
};
psci {
compatible = "arm,psci-1.0";
status = "okay";
method = "smc";
};
};
arch/arm64/boot/dts/nvidia/tegra186.dtsi 0 → 100644
View file @ 482c3e88
#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "nvidia,tegra186";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
gpio: gpio@2200000 {
compatible = "nvidia,tegra186-gpio";
reg-names = "security", "gpio";
reg = <0x0 0x2200000 0x0 0x10000>,
<0x0 0x2210000 0x0 0x10000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
};
uarta: serial@3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 55>;
clock-names = "serial";
resets = <&bpmp 47>;
reset-names = "serial";
status = "disabled";
};
uartb: serial@3110000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03110000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 56>;
clock-names = "serial";
resets = <&bpmp 48>;
reset-names = "serial";
status = "disabled";
};
uartd: serial@3130000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03130000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 77>;
clock-names = "serial";
resets = <&bpmp 50>;
reset-names = "serial";
status = "disabled";
};
uarte: serial@3140000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03140000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 194>;
clock-names = "serial";
resets = <&bpmp 132>;
reset-names = "serial";
status = "disabled";
};
uartf: serial@3150000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03150000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 195>;
clock-names = "serial";
resets = <&bpmp 111>;
reset-names = "serial";
status = "disabled";
};
gen1_i2c: i2c@3160000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x03160000 0x0 0x10000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp 47>;
clock-names = "div-clk";
resets = <&bpmp 19>;
reset-names = "i2c";
status = "disabled";
};
cam_i2c: i2c@3180000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x03180000 0x0 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp 75>;
clock-names = "div-clk";
resets = <&bpmp 21>;
reset-names = "i2c";
status = "disabled";
};
/* shares pads with dpaux1 */
dp_aux_ch1_i2c: i2c@3190000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x03190000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp 86>;
clock-names = "div-clk";
resets = <&bpmp 22>;
reset-names = "i2c";
status = "disabled";
};
/* controlled by BPMP, should not be enabled */
pwr_i2c: i2c@31a0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x031a0000 0x0 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp 48>;
clock-names = "div-clk";
resets = <&bpmp 23>;
reset-names = "i2c";
status = "disabled";
};
/* shares pads with dpaux0 */
dp_aux_ch0_i2c: i2c@31b0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x031b0000 0x0 0x10000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp 125>;
clock-names = "div-clk";
resets = <&bpmp 24>;
reset-names = "i2c";
status = "disabled";
};
gen7_i2c: i2c@31c0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x031c0000 0x0 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp 182>;
clock-names = "div-clk";
resets = <&bpmp 81>;
reset-names = "i2c";
status = "disabled";
};
gen9_i2c: i2c@31e0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x031e0000 0x0 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp 183>;
clock-names = "div-clk";
resets = <&bpmp 83>;
reset-names = "i2c";
status = "disabled";
};
sdmmc1: sdhci@3400000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03400000 0x0 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 52>;
clock-names = "sdhci";
resets = <&bpmp 33>;
reset-names = "sdhci";
status = "disabled";
};
sdmmc2: sdhci@3420000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03420000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 53>;
clock-names = "sdhci";
resets = <&bpmp 34>;
reset-names = "sdhci";
status = "disabled";
};
sdmmc3: sdhci@3440000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03440000 0x0 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 76>;
clock-names = "sdhci";
resets = <&bpmp 35>;
reset-names = "sdhci";
status = "disabled";
};
sdmmc4: sdhci@3460000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03460000 0x0 0x10000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 54>;
clock-names = "sdhci";
resets = <&bpmp 36>;
reset-names = "sdhci";
status = "disabled";
};
gic: interrupt-controller@3881000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x03881000 0x0 0x1000>,
<0x0 0x03882000 0x0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra186-hsp";
reg = <0x0 0x03c00000 0x0 0xa0000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "doorbell";
#mbox-cells = <2>;
status = "disabled";
};
gen2_i2c: i2c@c240000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x0c240000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp 218>;
clock-names = "div-clk";
resets = <&bpmp 20>;
reset-names = "i2c";
status = "disabled";
};
gen8_i2c: i2c@c250000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x0c250000 0x0 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp 219>;
clock-names = "div-clk";
resets = <&bpmp 82>;
reset-names = "i2c";
status = "disabled";
};
uartc: serial@c280000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x0c280000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 215>;
clock-names = "serial";
resets = <&bpmp 49>;
reset-names = "serial";
status = "disabled";
};
uartg: serial@c290000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x0c290000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp 216>;
clock-names = "serial";
resets = <&bpmp 112>;
reset-names = "serial";
status = "disabled";
};
gpio_aon: gpio@c2f0000 {
compatible = "nvidia,tegra186-gpio-aon";
reg-names = "security", "gpio";
reg = <0x0 0xc2f0000 0x0 0x1000>,
<0x0 0xc2f1000 0x0 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sysram@30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
cpu_bpmp_tx: shmem@4e000 {
compatible = "nvidia,tegra186-bpmp-shmem";
reg = <0x0 0x4e000 0x0 0x1000>;
label = "cpu-bpmp-tx";
pool;
};
cpu_bpmp_rx: shmem@4f000 {
compatible = "nvidia,tegra186-bpmp-shmem";
reg = <0x0 0x4f000 0x0 0x1000>;
label = "cpu-bpmp-rx";
pool;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "nvidia,tegra186-denver", "arm,armv8";
device_type = "cpu";
reg = <0x000>;
};
cpu@1 {
compatible = "nvidia,tegra186-denver", "arm,armv8";
device_type = "cpu";
reg = <0x001>;
};
cpu@2 {
compatible = "arm,cortex-a57", "arm,armv8";
device_type = "cpu";
reg = <0x100>;
};
cpu@3 {
compatible = "arm,cortex-a57", "arm,armv8";
device_type = "cpu";
reg = <0x101>;
};
cpu@4 {
compatible = "arm,cortex-a57", "arm,armv8";
device_type = "cpu";
reg = <0x102>;
};
cpu@5 {
compatible = "arm,cortex-a57", "arm,armv8";
device_type = "cpu";
reg = <0x103>;
};
};
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
mboxes = <&hsp_top0 0 19>;
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
#clock-cells = <1>;
#reset-cells = <1>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
nvidia,bpmp-bus-id = <5>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
};
arch/arm64/boot/dts/qcom/Makefile
View file @ 482c3e88
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View file @ 482c3e88
......@@ -15,6 +15,7 @@
#include "pm8916.dtsi"
#include "apq8016-sbc-soc-pins.dtsi"
#include "apq8016-sbc-pmic-pins.dtsi"
#include <dt-bindings/sound/apq8016-lpass.h>
/ {
aliases {
......@@ -251,6 +252,60 @@ dsi-phy@1a98300 {
vddio-supply = <&pm8916_l6>;
};
};
lpass_codec: codec{
status = "okay";
};
/*
Internal Codec
playback - Primary MI2S
capture - Ter MI2S
External Primary:
playback - secondary MI2S
capture - Quat MI2S
External Secondary:
playback - Quat MI2S
capture - Quat MI2S
*/
sound: sound {
compatible = "qcom,apq8016-sbc-sndcard";
reg = <0x07702000 0x4>, <0x07702004 0x4>;
reg-names = "mic-iomux", "spkr-iomux";
status = "okay";
pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
pinctrl-names = "default", "sleep";
qcom,model = "DB410c";
qcom,audio-routing =
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
internal-codec-playback-dai-link@0 { /* I2S - Internal codec */
link-name = "WCD";
cpu { /* PRIMARY */
sound-dai = <&lpass MI2S_PRIMARY>;
};
codec {
sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
};
};
internal-codec-capture-dai-link@0 { /* I2S - Internal codec */
link-name = "WCD-Capture";
cpu { /* PRIMARY */
sound-dai = <&lpass MI2S_TERTIARY>;
};
codec {
sound-dai = <&lpass_codec 1>, <&wcd_codec 1>;
};
};
};
};
usb2513 {
......@@ -278,6 +333,12 @@ hdmi_con: endpoint {
};
};
&wcd_codec {
status = "okay";
clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
clock-names = "mclk";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l5-supply = <&pm8916_s3>;
......@@ -308,8 +369,8 @@ l1 {
};
l2 {
regulator-min-microvolt = <375000>;
regulator-max-microvolt = <1525000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
l3 {
......@@ -328,8 +389,8 @@ l5 {
};
l6 {
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3337000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l7 {
......@@ -388,8 +449,8 @@ l16 {
};
l17 {
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3337000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
l18 {
......
arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi 0 → 100644
View file @ 482c3e88
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
&pm8994_gpios {
pinctrl-names = "default";
pinctrl-0 = <&ls_exp_gpio_f>;
ls_exp_gpio_f: pm8916_mpp4 {
pinconf {
pins = "gpio5";
output-low;
power-source = <2>; // PM8994_GPIO_S4, 1.8V
};
};
};
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
View file @ 482c3e88
......@@ -12,7 +12,9 @@
*/
#include "msm8996.dtsi"
#include "pm8994.dtsi"
#include "apq8096-db820c-pins.dtsi"
#include "apq8096-db820c-pmic-pins.dtsi"
/ {
aliases {
......
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ 482c3e88
......@@ -77,7 +77,7 @@ rfsa@867e00000 {
no-map;
};
mpss@86800000 {
mpss_mem: mpss@86800000 {
reg = <0x0 0x86800000 0x0 0x2b00000>;
no-map;
};
......@@ -504,6 +504,15 @@ lpass: lpass@07708000 {
reg-names = "lpass-lpaif";
};
lpass_codec: codec{
compatible = "qcom,msm8916-wcd-digital-codec";
reg = <0x0771c000 0x400>;
clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
<&gcc GCC_CODEC_DIGCODEC_CLK>;
clock-names = "ahbix-clk", "mclk";
#sound-dai-cells = <1>;
};
sdhc_1: sdhci@07824000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
......@@ -512,8 +521,10 @@ sdhc_1: sdhci@07824000 {
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
<&gcc GCC_SDCC1_AHB_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
mmc-ddr-1_8v;
bus-width = <8>;
non-removable;
status = "disabled";
......@@ -527,8 +538,9 @@ sdhc_2: sdhci@07864000 {
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
<&gcc GCC_SDCC2_AHB_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
bus-width = <4>;
status = "disabled";
};
......@@ -801,6 +813,49 @@ dsi_phy0: dsi-phy@1a98300 {
clock-names = "iface_clk";
};
};
hexagon@4080000 {
compatible = "qcom,q6v5-pil";
reg = <0x04080000 0x100>,
<0x04020000 0x040>;
reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc 0 24 1>,
<&hexagon_smp2p_in 0 0>,
<&hexagon_smp2p_in 1 0>,
<&hexagon_smp2p_in 2 0>,
<&hexagon_smp2p_in 3 0>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
<&gcc GCC_BOOT_ROM_AHB_CLK>;
clock-names = "iface", "bus", "mem";
qcom,smem-states = <&hexagon_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&scm 0>;
reset-names = "mss_restart";
mx-supply = <&pm8916_l3>;
pll-supply = <&pm8916_l7>;
qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
status = "disabled";
mba {
memory-region = <&mba_mem>;
};
mpss {
memory-region = <&mpss_mem>;
};
};
};
smd {
......@@ -848,6 +903,14 @@ smd_rpm_regulators: pm8916-regulators {
};
};
};
hexagon {
interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
qcom,smd-edge = <0>;
qcom,ipc = <&apcs 8 12>;
qcom,remote-pid = <1>;
};
};
hexagon-smp2p {
......
arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts 0 → 100644
View file @ 482c3e88
/* Copyright (c) 2015, LGE Inc. All rights reserved.
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msm8992.dtsi"
/ {
model = "LG Nexus 5X";
compatible = "lg,bullhead", "qcom,msm8992";
/* required for bootloader to select correct board */
qcom,board-id = <0xb64 0>;
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
soc {
serial@f991e000 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
};
};
};
arch/arm64/boot/dts/qcom/msm8992-pins.dtsi 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&msmgpio {
blsp1_uart2_default: blsp1_uart2_default {
pinmux {
function = "blsp_uart2";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <16>;
bias-disable;
};
};
blsp1_uart2_sleep: blsp1_uart2_sleep {
pinmux {
function = "gpio";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-pull-down;
};
};
};
arch/arm64/boot/dts/qcom/msm8992.dtsi 0 → 100644
View file @ 482c3e88
/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
/ {
model = "Qualcomm Technologies, Inc. MSM 8992";
compatible = "qcom,msm8992";
// msm-id needed by bootloader for selecting correct blob
qcom,msm-id = <251 0>, <252 0>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@f9000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0xf9000000 0x1000>,
<0xf9002000 0x1000>;
};
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0xf9020000 0x1000>;
frame@f9021000 {
frame-number = <0>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9021000 0x1000>,
<0xf9022000 0x1000>;
};
frame@f9023000 {
frame-number = <1>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9023000 0x1000>;
status = "disabled";
};
frame@f9024000 {
frame-number = <2>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9024000 0x1000>;
status = "disabled";
};
frame@f9025000 {
frame-number = <3>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9025000 0x1000>;
status = "disabled";
};
frame@f9026000 {
frame-number = <4>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9026000 0x1000>;
status = "disabled";
};
frame@f9027000 {
frame-number = <5>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9027000 0x1000>;
status = "disabled";
};
frame@f9028000 {
frame-number = <6>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9028000 0x1000>;
status = "disabled";
};
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};
msmgpio: pinctrl@fd510000 {
compatible = "qcom,msm8994-pinctrl";
reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
status = "disabled";
clock-names = "core", "iface";
clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
<&clock_gcc GCC_BLSP1_AHB_CLK>;
};
clock_gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8994";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
};
};
memory {
device_type = "memory";
reg = <0 0 0 0>; // bootloader will update
};
};
#include "msm8992-pins.dtsi"
arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts 0 → 100644
View file @ 482c3e88
/* Copyright (c) 2015, Huawei Inc. All rights reserved.
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msm8994.dtsi"
/ {
model = "Huawei Nexus 6P";
compatible = "huawei,angler", "qcom,msm8994";
/* required for bootloader to select correct board */
qcom,board-id = <8026 0>;
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
soc {
serial@f991e000 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
};
};
};
arch/arm64/boot/dts/qcom/msm8994-pins.dtsi 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&msmgpio {
blsp1_uart2_default: blsp1_uart2_default {
pinmux {
function = "blsp_uart2";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <16>;
bias-disable;
};
};
blsp1_uart2_sleep: blsp1_uart2_sleep {
pinmux {
function = "gpio";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-pull-down;
};
};
};
arch/arm64/boot/dts/qcom/msm8994.dtsi 0 → 100644
View file @ 482c3e88
/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
/ {
model = "Qualcomm Technologies, Inc. MSM 8994";
compatible = "qcom,msm8994";
// msm-id and pmic-id are required by bootloader for
// proper selection of dt blob
qcom,msm-id = <207 0x20000>;
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 2 0xff08>,
<1 3 0xff08>,
<1 4 0xff08>,
<1 1 0xff08>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@f9000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0xf9000000 0x1000>,
<0xf9002000 0x1000>;
};
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0xf9020000 0x1000>;
frame@f9021000 {
frame-number = <0>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9021000 0x1000>,
<0xf9022000 0x1000>;
};
frame@f9023000 {
frame-number = <1>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9023000 0x1000>;
status = "disabled";
};
frame@f9024000 {
frame-number = <2>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9024000 0x1000>;
status = "disabled";
};
frame@f9025000 {
frame-number = <3>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9025000 0x1000>;
status = "disabled";
};
frame@f9026000 {
frame-number = <4>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9026000 0x1000>;
status = "disabled";
};
frame@f9027000 {
frame-number = <5>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9027000 0x1000>;
status = "disabled";
};
frame@f9028000 {
frame-number = <6>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9028000 0x1000>;
status = "disabled";
};
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};
msmgpio: pinctrl@fd510000 {
compatible = "qcom,msm8994-pinctrl";
reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clock-names = "core", "iface";
clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
<&clock_gcc GCC_BLSP1_AHB_CLK>;
};
tcsr_mutex_regs: syscon@fd484000 {
compatible = "syscon";
reg = <0xfd484000 0x2000>;
};
clock_gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8994";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
};
};
memory {
device_type = "memory";
// We expect the bootloader to fill in the reg
reg = <0 0 0 0>;
};
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
smem_mem: smem_region@6a00000 {
reg = <0x0 0x6a00000 0x0 0x200000>;
no-map;
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x80>;
#hwlock-cells = <1>;
};
qcom,smem@6a00000 {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
};
#include "msm8994-pins.dtsi"
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file @ 482c3e88
......@@ -30,6 +30,42 @@ memory {
reg = <0 0 0 0>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
mba_region: mba@91500000 {
reg = <0x0 0x91500000 0x0 0x200000>;
no-map;
};
slpi_region: slpi@90b00000 {
reg = <0x0 0x90b00000 0x0 0xa00000>;
no-map;
};
venus_region: venus@90400000 {
reg = <0x0 0x90400000 0x0 0x700000>;
no-map;
};
adsp_region: adsp@8ea00000 {
reg = <0x0 0x8ea00000 0x0 0x1a00000>;
no-map;
};
mpss_region: mpss@88800000 {
reg = <0x0 0x88800000 0x0 0x6200000>;
no-map;
};
smem_mem: smem-mem@86000000 {
reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
......@@ -192,14 +228,14 @@ timer {
};
clocks {
xo_board {
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
sleep_clk {
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
......@@ -212,12 +248,29 @@ psci {
method = "smc";
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
tcsr_mutex_regs: syscon@740000 {
compatible = "syscon";
reg = <0x740000 0x20000>;
};
intc: interrupt-controller@9bc0000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
......@@ -229,6 +282,11 @@ intc: interrupt-controller@9bc0000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
apcs: syscon@9820000 {
compatible = "syscon";
reg = <0x9820000 0x1000>;
};
gcc: clock-controller@300000 {
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
......@@ -347,9 +405,10 @@ sdhc2: sdhci@74a4900 {
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
clock-names = "iface", "core";
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
bus-width = <4>;
};
......@@ -458,5 +517,29 @@ mmcc: clock-controller@8c0000 {
<825000000>;
};
};
adsp-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 16 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
#include "msm8996-pins.dtsi"
arch/arm64/boot/dts/qcom/pm8916.dtsi
View file @ 482c3e88
......@@ -91,9 +91,52 @@ ref_vdd {
};
pm8916_1: pm8916@1 {
compatible = "qcom,spmi-pmic";
compatible = "qcom,pm8916", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
wcd_codec: codec@f000 {
compatible = "qcom,pm8916-wcd-analog-codec";
reg = <0xf000 0x200>;
reg-names = "pmic-codec-core";
clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
clock-names = "mclk";
interrupt-parent = <&spmi_bus>;
interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
<0x1 0xf0 0x1 IRQ_TYPE_NONE>,
<0x1 0xf0 0x2 IRQ_TYPE_NONE>,
<0x1 0xf0 0x3 IRQ_TYPE_NONE>,
<0x1 0xf0 0x4 IRQ_TYPE_NONE>,
<0x1 0xf0 0x5 IRQ_TYPE_NONE>,
<0x1 0xf0 0x6 IRQ_TYPE_NONE>,
<0x1 0xf0 0x7 IRQ_TYPE_NONE>,
<0x1 0xf1 0x0 IRQ_TYPE_NONE>,
<0x1 0xf1 0x1 IRQ_TYPE_NONE>,
<0x1 0xf1 0x2 IRQ_TYPE_NONE>,
<0x1 0xf1 0x3 IRQ_TYPE_NONE>,
<0x1 0xf1 0x4 IRQ_TYPE_NONE>,
<0x1 0xf1 0x5 IRQ_TYPE_NONE>;
interrupt-names = "cdc_spk_cnp_int",
"cdc_spk_clip_int",
"cdc_spk_ocp_int",
"mbhc_ins_rem_det1",
"mbhc_but_rel_det",
"mbhc_but_press_det",
"mbhc_ins_rem_det",
"mbhc_switch_int",
"cdc_ear_ocp_int",
"cdc_hphr_ocp_int",
"cdc_hphl_ocp_det",
"cdc_ear_cnp_int",
"cdc_hphr_cnp_int",
"cdc_hphl_cnp_int";
vdd-cdc-io-supply = <&pm8916_l5>;
vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>;
vdd-micbias-supply = <&pm8916_l13>;
#sound-dai-cells = <1>;
};
};
};
arch/arm64/boot/dts/qcom/pm8994.dtsi
View file @ 482c3e88
......@@ -29,6 +29,7 @@ pm8994_gpios: gpios@c000 {
<0 0xcc 0 IRQ_TYPE_NONE>,
<0 0xcd 0 IRQ_TYPE_NONE>,
<0 0xce 0 IRQ_TYPE_NONE>,
<0 0xcf 0 IRQ_TYPE_NONE>,
<0 0xd0 0 IRQ_TYPE_NONE>,
<0 0xd1 0 IRQ_TYPE_NONE>,
<0 0xd2 0 IRQ_TYPE_NONE>,
......
arch/arm64/boot/dts/renesas/Makefile
View file @ 482c3e88
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
always := $(dtb-y)
clean-files := *.dtb
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
View file @ 482c3e88
/*
* Device Tree Source for the H3ULCB board
* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
......@@ -62,6 +62,24 @@ x12_clk: x12 {
clock-frequency = <24576000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
......@@ -145,18 +163,30 @@ avb_pins: avb {
function = "avb";
};
sdhi0_pins_3v3: sd0_3v3 {
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_1v8: sd0_1v8 {
sdhi0_pins_uhs: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
......@@ -261,8 +291,8 @@ dai0 {
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins_3v3>;
pinctrl-1 = <&sdhi0_pins_1v8>;
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
......@@ -273,6 +303,19 @@ &sdhi0 {
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&ssi1 {
shared-pin;
};
......
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
View file @ 482c3e88
......@@ -62,6 +62,24 @@ x12_clk: x12_clk {
clock-frequency = <24576000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
......@@ -191,6 +209,10 @@ endpoint {
remote-endpoint = <&adv7123_in>;
};
};
port@3 {
lvds_connector: endpoint {
};
};
};
};
......@@ -237,11 +259,37 @@ du_pins: du {
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <3300>;
};
sdhi3_pins_uhs: sd3_uhs {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <1800>;
};
sound_pins: sound {
......@@ -261,8 +309,20 @@ usb0_pins: usb0 {
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
mux {
groups = "usb1";
function = "usb1";
};
ovc {
pins = "GP_6_27";
bias-pull-up;
};
pwen {
pins = "GP_6_26";
bias-pull-down;
};
};
usb2_pins: usb2 {
......@@ -371,25 +431,42 @@ &sata {
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdhi3_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi3>;
vqmmc-supply = <&vccq_sdhi3>;
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
......
arch/arm64/boot/dts/renesas/r8a7795.dtsi
View file @ 482c3e88
......@@ -326,6 +326,11 @@ rst: reset-controller@e6160000 {
reg = <0 0xe6160000 0 0x0200>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7795-sysc";
reg = <0 0xe6180000 0 0x0400>;
......@@ -1311,28 +1316,28 @@ vspbc: vsp@fe920000 {
};
fcpvb1: fcp@fe92f000 {
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
compatible = "renesas,fcpv";
reg = <0 0xfe92f000 0 0x200>;
clocks = <&cpg CPG_MOD 606>;
power-domains = <&sysc R8A7795_PD_A3VP>;
};
fcpf0: fcp@fe950000 {
compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";
compatible = "renesas,fcpf";
reg = <0 0xfe950000 0 0x200>;
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A7795_PD_A3VP>;
};
fcpf1: fcp@fe951000 {
compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";
compatible = "renesas,fcpf";
reg = <0 0xfe951000 0 0x200>;
clocks = <&cpg CPG_MOD 614>;
power-domains = <&sysc R8A7795_PD_A3VP>;
};
fcpf2: fcp@fe952000 {
compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";
compatible = "renesas,fcpf";
reg = <0 0xfe952000 0 0x200>;
clocks = <&cpg CPG_MOD 613>;
power-domains = <&sysc R8A7795_PD_A3VP>;
......@@ -1349,7 +1354,7 @@ vspbd: vsp@fe960000 {
};
fcpvb0: fcp@fe96f000 {
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
compatible = "renesas,fcpv";
reg = <0 0xfe96f000 0 0x200>;
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A7795_PD_A3VP>;
......@@ -1366,7 +1371,7 @@ vspi0: vsp@fe9a0000 {
};
fcpvi0: fcp@fe9af000 {
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
compatible = "renesas,fcpv";
reg = <0 0xfe9af000 0 0x200>;
clocks = <&cpg CPG_MOD 611>;
power-domains = <&sysc R8A7795_PD_A3VP>;
......@@ -1383,7 +1388,7 @@ vspi1: vsp@fe9b0000 {
};
fcpvi1: fcp@fe9bf000 {
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
compatible = "renesas,fcpv";
reg = <0 0xfe9bf000 0 0x200>;
clocks = <&cpg CPG_MOD 610>;
power-domains = <&sysc R8A7795_PD_A3VP>;
......@@ -1400,7 +1405,7 @@ vspi2: vsp@fe9c0000 {
};
fcpvi2: fcp@fe9cf000 {
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
compatible = "renesas,fcpv";
reg = <0 0xfe9cf000 0 0x200>;
clocks = <&cpg CPG_MOD 609>;
power-domains = <&sysc R8A7795_PD_A3VP>;
......@@ -1417,7 +1422,7 @@ vspd0: vsp@fea20000 {
};
fcpvd0: fcp@fea27000 {
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
......@@ -1434,7 +1439,7 @@ vspd1: vsp@fea28000 {
};
fcpvd1: fcp@fea2f000 {
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
......@@ -1451,7 +1456,7 @@ vspd2: vsp@fea30000 {
};
fcpvd2: fcp@fea37000 {
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
compatible = "renesas,fcpv";
reg = <0 0xfea37000 0 0x200>;
clocks = <&cpg CPG_MOD 601>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
......@@ -1468,7 +1473,7 @@ vspd3: vsp@fea38000 {
};
fcpvd3: fcp@fea3f000 {
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
compatible = "renesas,fcpv";
reg = <0 0xfea3f000 0 0x200>;
clocks = <&cpg CPG_MOD 600>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
......
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts 0 → 100644
View file @ 482c3e88
/*
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7796.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Renesas M3ULCB board based on r8a7796";
compatible = "renesas,m3ulcb", "renesas,r8a7796";
aliases {
serial0 = &scif2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
leds {
compatible = "gpio-leds";
led5 {
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
};
led6 {
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
};
};
keyboard {
compatible = "gpio-keys";
key-1 {
linux,code = <KEY_1>;
label = "SW3";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
};
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
View file @ 482c3e88
......@@ -10,6 +10,7 @@
/dts-v1/;
#include "r8a7796.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Salvator-X board based on r8a7796";
......@@ -29,6 +30,72 @@ memory@48000000 {
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi3: regulator-vcc-sdhi3 {
compatible = "regulator-fixed";
regulator-name = "SDHI3 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi3: regulator-vccq-sdhi3 {
compatible = "regulator-gpio";
regulator-name = "SDHI3 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&pfc {
......@@ -43,12 +110,98 @@ scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <3300>;
};
sdhi3_pins_uhs: sd3_uhs {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <1800>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi3>;
vqmmc-supply = <&vccq_sdhi3>;
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
......@@ -60,6 +213,13 @@ &scif_clk {
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
......
arch/arm64/boot/dts/renesas/r8a7796.dtsi
View file @ 482c3e88
......@@ -17,6 +17,16 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
......@@ -238,12 +248,118 @@ rst: reset-controller@e6160000 {
reg = <0 0xe6160000 0 0x0200>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7796-sysc";
reg = <0 0xe6180000 0 0x0400>;
#power-domain-cells = <1>;
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7796";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c1: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7796";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
<&dmac2 0x93>, <&dmac2 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c2: i2c@e6510000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7796";
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c3: i2c@e66d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7796";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c4: i2c@e66d8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7796";
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
dmas = <&dmac0 0x99>, <&dmac0 0x98>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c5: i2c@e66e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7796";
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c6: i2c@e66e8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7796";
reg = <0 0xe66e8000 0 0x40>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
......@@ -256,5 +372,144 @@ scif2: serial@e6e88000 {
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7796",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x10000>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#dma-cells = <1>;
dma-channels = <16>;
};
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a7796",
"renesas,rcar-dmac";
reg = <0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#dma-cells = <1>;
dma-channels = <16>;
};
dmac2: dma-controller@e7310000 {
compatible = "renesas,dmac-r8a7796",
"renesas,rcar-dmac";
reg = <0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 217>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#dma-cells = <1>;
dma-channels = <16>;
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7796";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a7796";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a7796";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a7796";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
};
};
arch/arm64/boot/dts/rockchip/Makefile
View file @ 482c3e88
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
......
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
View file @ 482c3e88
......@@ -344,7 +344,7 @@ &saradc {
&sdmmc {
bus-width = <4>;
clock-frequency = <50000000>;
clock-freq-min-max = <400000 50000000>;
max-frequency = <50000000>;
cap-sd-highspeed;
card-detect-delay = <200>;
num-slots = <1>;
......
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts 0 → 100644
View file @ 482c3e88
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk3368.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Rockchip PX5 EVB";
compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
chosen {
stdout-path = "serial4:115200n8";
};
memory@0 {
reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
};
keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
power {
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
};
&emmc {
status = "okay";
bus-width = <8>;
cap-mmc-highspeed;
clock-frequency = <150000000>;
disable-wp;
keep-power-in-suspend;
mmc-hs200-1_8v;
no-sdio;
no-sd;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc18_flash>;
};
&i2c0 {
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio0>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
rockchip,system-power-controller;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc_io>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc_io>;
clock-output-names = "xin32k", "rk808-clkout2";
#clock-cells = <1>;
regulators {
vdd_cpu: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_cpu";
};
vdd_log: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_log";
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
};
vcc_io: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_io";
};
vcc18_flash: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_flash";
};
vcca_33: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcca_33";
};
vdd_10: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd_10";
};
avdd_33: LDO_REG4 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "avdd_33";
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
};
vdd10_lcd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_lcd";
};
vcc_18: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_18";
};
vcc18_lcd: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_lcd";
};
vcc_sd: SWITCH_REG1 {
regulator-name = "vcc_sd";
};
vcc33_lcd: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc33_lcd";
};
};
};
};
&i2c1 {
status = "okay";
accelerometer@18 {
compatible = "bosch,bma250";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c2 {
status = "okay";
gsl1680: touchscreen@40 {
compatible = "silead,gsl1680";
reg = <0x40>;
interrupt-parent = <&gpio3>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
power-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
silead,max-fingers = <5>;
};
};
&pinctrl {
keys {
pwr_key: pwr-key {
rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_sleep: pmic-sleep {
rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
};
pmic_int: pmic-int {
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&sdmmc {
status = "okay";
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
no-emmc;
no-sdio;
num-slots = <1>;
sd-uhs-sdr12;
sd-uhs-sdr25;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_bus4>, <&sdmmc_cd>;
rockchip,default-sample-phase = <90>;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
};
&tsadc {
status = "okay";
rockchip,hw-tshut-mode = <0>; /* CRU */
rockchip,hw-tshut-polarity = <1>; /* high */
};
&uart4 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_otg {
status = "okay";
};
&wdt {
status = "okay";
};
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View file @ 482c3e88
......@@ -231,7 +231,7 @@ xin24m: oscillator {
sdmmc: dwmmc@ff0c0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
......@@ -243,7 +243,7 @@ sdmmc: dwmmc@ff0c0000 {
sdio0: dwmmc@ff0d0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0d0000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
......@@ -255,7 +255,7 @@ sdio0: dwmmc@ff0d0000 {
emmc: dwmmc@ff0f0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0f0000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
......@@ -315,16 +315,16 @@ spi2: spi@ff130000 {
status = "disabled";
};
i2c1: i2c@ff140000 {
i2c2: i2c@ff140000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff140000 0x0 0x1000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C1>;
clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
......@@ -553,16 +553,16 @@ i2c0: i2c@ff650000 {
status = "disabled";
};
i2c2: i2c@ff660000 {
i2c1: i2c@ff660000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff660000 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C2>;
clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
pinctrl-0 = <&i2c1_xfer>;
status = "disabled";
};
......
arch/arm64/boot/dts/rockchip/rk3399-evb.dts
View file @ 482c3e88
......@@ -49,6 +49,46 @@ / {
compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
"google,rk3399evb-rev2";
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
pwms = <&pwm0 0 25000 0>;
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
......
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View file @ 482c3e88
......@@ -236,7 +236,7 @@ sdio0: dwmmc@fe310000 {
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe310000 0x0 0x4000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
......@@ -249,11 +249,12 @@ sdmmc: dwmmc@fe320000 {
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe320000 0x0 0x4000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
clock-freq-min-max = <400000 150000000>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
power-domains = <&power RK3399_PD_SD>;
status = "disabled";
};
......@@ -270,6 +271,7 @@ sdhci: sdhci@fe330000 {
#clock-cells = <0>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
power-domains = <&power RK3399_PD_EMMC>;
status = "disabled";
};
......@@ -694,6 +696,16 @@ tsadc: tsadc@ff260000 {
status = "disabled";
};
qos_sd: qos@ffa74000 {
compatible = "syscon";
reg = <0x0 0xffa74000 0x0 0x20>;
};
qos_emmc: qos@ffa58000 {
compatible = "syscon";
reg = <0x0 0xffa58000 0x0 0x20>;
};
qos_gmac: qos@ffa5c000 {
compatible = "syscon";
reg = <0x0 0xffa5c000 0x0 0x20>;
......@@ -827,11 +839,23 @@ pd_gpu@RK3399_PD_GPU {
};
/* These power domains are grouped by VD_LOGIC */
pd_emmc@RK3399_PD_EMMC {
reg = <RK3399_PD_EMMC>;
clocks = <&cru ACLK_EMMC>;
pm_qos = <&qos_emmc>;
};
pd_gmac@RK3399_PD_GMAC {
reg = <RK3399_PD_GMAC>;
clocks = <&cru ACLK_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
pm_qos = <&qos_gmac>;
};
pd_sd@RK3399_PD_SD {
reg = <RK3399_PD_SD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sd>;
};
pd_vio@RK3399_PD_VIO {
reg = <RK3399_PD_VIO>;
#address-cells = <1>;
......@@ -1027,6 +1051,9 @@ efuse0: efuse@ff690000 {
clock-names = "pclk_efuse";
/* Data cells */
cpu_id: cpu-id@7 {
reg = <0x07 0x10>;
};
cpub_leakage: cpu-leakage@17 {
reg = <0x17 0x1>;
};
......@@ -1105,6 +1132,16 @@ u2phy0_host: host-port {
interrupt-names = "linestate";
status = "disabled";
};
u2phy0_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
};
u2phy1: usb2-phy@e460 {
......@@ -1122,6 +1159,16 @@ u2phy1_host: host-port {
interrupt-names = "linestate";
status = "disabled";
};
u2phy1_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
};
emmc_phy: phy@f780 {
......@@ -1152,6 +1199,7 @@ tcphy0: phy@ff7c0000 {
clock-names = "tcpdcore", "tcpdphy-ref";
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
assigned-clock-rates = <50000000>;
power-domains = <&power RK3399_PD_TCPD0>;
resets = <&cru SRST_UPHY0>,
<&cru SRST_UPHY0_PIPE_L00>,
<&cru SRST_P_UPHY0_TCPHY>;
......@@ -1180,6 +1228,7 @@ tcphy1: phy@ff800000 {
clock-names = "tcpdcore", "tcpdphy-ref";
assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
assigned-clock-rates = <50000000>;
power-domains = <&power RK3399_PD_TCPD1>;
resets = <&cru SRST_UPHY1>,
<&cru SRST_UPHY1_PIPE_L00>,
<&cru SRST_P_UPHY1_TCPHY>;
......
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
View file @ 482c3e88
......@@ -43,7 +43,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/memreserve/ 0x80000000 0x00080000;
/ {
compatible = "socionext,uniphier-ld11";
......@@ -70,19 +70,60 @@ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
};
cluster0_opp: opp_table {
compatible = "operating-points-v2";
opp-shared;
opp@245000000 {
opp-hz = /bits/ 64 <245000000>;
clock-latency-ns = <300>;
};
opp@250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
opp@490000000 {
opp-hz = /bits/ 64 <490000000>;
clock-latency-ns = <300>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
opp@653334000 {
opp-hz = /bits/ 64 <653334000>;
clock-latency-ns = <300>;
};
opp@666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
opp@980000000 {
opp-hz = /bits/ 64 <980000000>;
clock-latency-ns = <300>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
clocks {
refclk: ref {
compatible = "fixed-clock";
......@@ -233,7 +274,7 @@ smpctrl@59800000 {
};
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
compatible = "socionext,uniphier-ld11-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
......@@ -282,7 +323,7 @@ usb2: usb@5a820100 {
};
mioctrl@5b3e0000 {
compatible = "socionext,uniphier-mioctrl",
compatible = "socionext,uniphier-ld11-mioctrl",
"simple-mfd", "syscon";
reg = <0x5b3e0000 0x800>;
......@@ -299,7 +340,7 @@ mio_rst: reset {
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-soc-glue",
compatible = "socionext,uniphier-ld11-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
......@@ -320,7 +361,7 @@ gic: interrupt-controller@5fe00000 {
sysctrl@61840000 {
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-ld11-clock";
......
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
View file @ 482c3e88
......@@ -43,7 +43,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/memreserve/ 0x80000000 0x00080000;
/ {
compatible = "socionext,uniphier-ld20";
......@@ -79,35 +79,120 @@ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 32>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 32>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster1_opp>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster1_opp>;
};
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp@250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
opp@275000000 {
opp-hz = /bits/ 64 <275000000>;
clock-latency-ns = <300>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
opp@550000000 {
opp-hz = /bits/ 64 <550000000>;
clock-latency-ns = <300>;
};
opp@666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
opp@733334000 {
opp-hz = /bits/ 64 <733334000>;
clock-latency-ns = <300>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <300>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
clock-latency-ns = <300>;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp@250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
opp@275000000 {
opp-hz = /bits/ 64 <275000000>;
clock-latency-ns = <300>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
opp@550000000 {
opp-hz = /bits/ 64 <550000000>;
clock-latency-ns = <300>;
};
opp@666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
opp@733334000 {
opp-hz = /bits/ 64 <733334000>;
clock-latency-ns = <300>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <300>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
clock-latency-ns = <300>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
clocks {
refclk: ref {
compatible = "fixed-clock";
......@@ -274,7 +359,7 @@ sd_rst: reset {
};
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
compatible = "socionext,uniphier-ld20-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
......@@ -290,7 +375,7 @@ peri_rst: reset {
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-soc-glue",
compatible = "socionext,uniphier-ld20-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
......@@ -309,9 +394,9 @@ gic: interrupt-controller@5fe00000 {
};
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl",
compatible = "socionext,uniphier-ld20-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-ld20-clock";
......
arch/arm64/boot/dts/zte/zx296718.dtsi
View file @ 482c3e88
......@@ -277,9 +277,33 @@ dma: dma-controller@1460000 {
dma-requests = <32>;
};
lsp0crm: clock-controller@1420000 {
compatible = "zte,zx296718-lsp0crm";
reg = <0x01420000 0x1000>;
#clock-cells = <1>;
};
lsp1crm: clock-controller@1430000 {
compatible = "zte,zx296718-lsp1crm";
reg = <0x01430000 0x1000>;
#clock-cells = <1>;
};
topcrm: clock-controller@1461000 {
compatible = "zte,zx296718-topcrm";
reg = <0x01461000 0x1000>;
#clock-cells = <1>;
};
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
};
audiocrm: clock-controller@1480000 {
compatible = "zte,zx296718-audiocrm";
reg = <0x01480000 0x1000>;
#clock-cells = <1>;
};
};
};
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