Commit 511d2ffd authored by Dave Airlie's avatar Dave Airlie

Merge tag 'cdns-mhdp-5.10' of...

Merge tag 'cdns-mhdp-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next

Cadence MHDP8546 DisplayPort bridge driver
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Tomi Valkeinen <tomi.valkeinen@ti.com>
Link: https://patchwork.freedesktop.org/patch/msgid/5dd15e3c-51ed-49c0-cf49-88c7af38d6b0@ti.com
parents 1cd0f494 afba7e6c
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Cadence MHDP8546 bridge
maintainers:
- Swapnil Jakhade <sjakhade@cadence.com>
- Yuti Amonkar <yamonkar@cadence.com>
properties:
compatible:
enum:
- cdns,mhdp8546
- ti,j721e-mhdp8546
reg:
minItems: 1
maxItems: 2
items:
- description:
Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
The AUX and PMA registers are not part of this range, they are instead
included in the associated PHY.
- description:
Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
reg-names:
minItems: 1
maxItems: 2
items:
- const: mhdptx
- const: j721e-intg
clocks:
maxItems: 1
description:
DP bridge clock, used by the IP to know how to translate a number of
clock cycles into a time (which is used to comply with DP standard timings
and delays).
phys:
maxItems: 1
description:
phandle to the DisplayPort PHY.
phy-names:
items:
- const: dpphy
power-domains:
maxItems: 1
interrupts:
maxItems: 1
ports:
type: object
description:
Ports as described in Documentation/devicetree/bindings/graph.txt.
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
port@0:
type: object
description:
First input port representing the DP bridge input.
port@1:
type: object
description:
Second input port representing the DP bridge input.
port@2:
type: object
description:
Third input port representing the DP bridge input.
port@3:
type: object
description:
Fourth input port representing the DP bridge input.
port@4:
type: object
description:
Output port representing the DP bridge output.
required:
- port@0
- port@4
- '#address-cells'
- '#size-cells'
allOf:
- if:
properties:
compatible:
contains:
const: ti,j721e-mhdp8546
then:
properties:
reg:
minItems: 2
reg-names:
minItems: 2
else:
properties:
reg:
maxItems: 1
reg-names:
maxItems: 1
required:
- compatible
- clocks
- reg
- reg-names
- phys
- phy-names
- interrupts
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
mhdp: dp-bridge@f0fb000000 {
compatible = "cdns,mhdp8546";
reg = <0xf0 0xfb000000 0x0 0x1000000>;
reg-names = "mhdptx";
clocks = <&mhdp_clock>;
phys = <&dp_phy>;
phy-names = "dpphy";
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp_bridge_input: endpoint {
remote-endpoint = <&xxx_dpi_output>;
};
};
port@4 {
reg = <4>;
dp_bridge_output: endpoint {
remote-endpoint = <&xxx_dp_connector_input>;
};
};
};
};
};
...
......@@ -241,6 +241,8 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig"
source "drivers/gpu/drm/bridge/adv7511/Kconfig"
source "drivers/gpu/drm/bridge/cadence/Kconfig"
source "drivers/gpu/drm/bridge/synopsys/Kconfig"
endmenu
......@@ -25,4 +25,5 @@ obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
obj-y += analogix/
obj-y += cadence/
obj-y += synopsys/
# SPDX-License-Identifier: GPL-2.0-only
config DRM_CDNS_MHDP8546
tristate "Cadence DPI/DP bridge"
select DRM_KMS_HELPER
select DRM_PANEL_BRIDGE
depends on OF
help
Support Cadence DPI to DP bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
It takes a DPI stream as input and outputs it encoded
in DP format.
if DRM_CDNS_MHDP8546
config DRM_CDNS_MHDP8546_J721E
depends on ARCH_K3_J721E_SOC || COMPILE_TEST
bool "J721E Cadence DPI/DP wrapper support"
default y
help
Support J721E Cadence DPI/DP wrapper. This is a wrapper
which adds support for J721E related platform ops. It
initializes the J721E Display Port and sets up the
clock and data muxes.
endif
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
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// SPDX-License-Identifier: GPL-2.0
/*
* TI j721e Cadence MHDP8546 DP wrapper
*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
* Author: Jyri Sarha <jsarha@ti.com>
*/
#include <linux/io.h>
#include <linux/platform_device.h>
#include "cdns-mhdp8546-j721e.h"
#define REVISION 0x00
#define DPTX_IPCFG 0x04
#define ECC_MEM_CFG 0x08
#define DPTX_DSC_CFG 0x0c
#define DPTX_SRC_CFG 0x10
#define DPTX_VIF_SECURE_MODE_CFG 0x14
#define DPTX_VIF_CONN_STATUS 0x18
#define PHY_CLK_STATUS 0x1c
#define DPTX_SRC_AIF_EN BIT(16)
#define DPTX_SRC_VIF_3_IN30B BIT(11)
#define DPTX_SRC_VIF_2_IN30B BIT(10)
#define DPTX_SRC_VIF_1_IN30B BIT(9)
#define DPTX_SRC_VIF_0_IN30B BIT(8)
#define DPTX_SRC_VIF_3_SEL_DPI5 BIT(7)
#define DPTX_SRC_VIF_3_SEL_DPI3 0
#define DPTX_SRC_VIF_2_SEL_DPI4 BIT(6)
#define DPTX_SRC_VIF_2_SEL_DPI2 0
#define DPTX_SRC_VIF_1_SEL_DPI3 BIT(5)
#define DPTX_SRC_VIF_1_SEL_DPI1 0
#define DPTX_SRC_VIF_0_SEL_DPI2 BIT(4)
#define DPTX_SRC_VIF_0_SEL_DPI0 0
#define DPTX_SRC_VIF_3_EN BIT(3)
#define DPTX_SRC_VIF_2_EN BIT(2)
#define DPTX_SRC_VIF_1_EN BIT(1)
#define DPTX_SRC_VIF_0_EN BIT(0)
/* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */
static int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)
{
struct platform_device *pdev = to_platform_device(mhdp->dev);
mhdp->j721e_regs = devm_platform_ioremap_resource(pdev, 1);
return PTR_ERR_OR_ZERO(mhdp->j721e_regs);
}
static void cdns_mhdp_j721e_enable(struct cdns_mhdp_device *mhdp)
{
/*
* Enable VIF_0 and select DPI2 as its input. DSS0 DPI0 is connected
* to eDP DPI2. This is the only supported SST configuration on
* J721E.
*/
writel(DPTX_SRC_VIF_0_EN | DPTX_SRC_VIF_0_SEL_DPI2,
mhdp->j721e_regs + DPTX_SRC_CFG);
}
static void cdns_mhdp_j721e_disable(struct cdns_mhdp_device *mhdp)
{
/* Put everything to defaults */
writel(0, mhdp->j721e_regs + DPTX_DSC_CFG);
}
const struct mhdp_platform_ops mhdp_ti_j721e_ops = {
.init = cdns_mhdp_j721e_init,
.enable = cdns_mhdp_j721e_enable,
.disable = cdns_mhdp_j721e_disable,
};
const struct drm_bridge_timings mhdp_ti_j721e_bridge_timings = {
.input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE |
DRM_BUS_FLAG_DE_HIGH,
};
/* SPDX-License-Identifier: GPL-2.0 */
/*
* TI j721e Cadence MHDP8546 DP wrapper
*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
* Author: Jyri Sarha <jsarha@ti.com>
*/
#ifndef CDNS_MHDP8546_J721E_H
#define CDNS_MHDP8546_J721E_H
#include "cdns-mhdp8546-core.h"
struct mhdp_platform_ops;
extern const struct mhdp_platform_ops mhdp_ti_j721e_ops;
extern const struct drm_bridge_timings mhdp_ti_j721e_bridge_timings;
#endif /* !CDNS_MHDP8546_J721E_H */
......@@ -1852,6 +1852,10 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
cdns_phy->phys[node].num_lanes,
cdns_phy->max_bit_rate / 1000,
cdns_phy->max_bit_rate % 1000);
gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
gphy->attrs.mode = PHY_MODE_DP;
} else {
dev_err(dev, "Driver supports only PHY_TYPE_DP\n");
ret = -ENOTSUPP;
......
......@@ -115,10 +115,12 @@ struct phy_ops {
/**
* struct phy_attrs - represents phy attributes
* @bus_width: Data path width implemented by PHY
* @max_link_rate: Maximum link rate supported by PHY (in Mbps)
* @mode: PHY mode
*/
struct phy_attrs {
u32 bus_width;
u32 max_link_rate;
enum phy_mode mode;
};
......
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