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Commit 5283ecb5 authored by Paul Mundt's avatar Paul Mundt
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sh: Add support for R7780RP and R7780MP boards. 

This adds support for the Renesas SH7780 development boards,
R7780RP and R7780MP.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent d7c30c68
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Showing with 2684 additions and 49 deletions
arch/sh/Kconfig
View file @ 5283ecb5
...@@ -404,6 +404,8 @@ source "arch/sh/boards/renesas/hs7751rvoip/Kconfig" ...@@ -404,6 +404,8 @@ source "arch/sh/boards/renesas/hs7751rvoip/Kconfig"
source "arch/sh/boards/renesas/rts7751r2d/Kconfig" source "arch/sh/boards/renesas/rts7751r2d/Kconfig"
source "arch/sh/boards/renesas/r7780rp/Kconfig"
config SH_PCLK_FREQ config SH_PCLK_FREQ
int "Peripheral clock frequency (in Hz)" int "Peripheral clock frequency (in Hz)"
default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780 default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780
......
arch/sh/Makefile
View file @ 5283ecb5
...@@ -104,6 +104,7 @@ machdir-$(CONFIG_SH_HS7751RVOIP) := renesas/hs7751rvoip ...@@ -104,6 +104,7 @@ machdir-$(CONFIG_SH_HS7751RVOIP) := renesas/hs7751rvoip
machdir-$(CONFIG_SH_RTS7751R2D) := renesas/rts7751r2d machdir-$(CONFIG_SH_RTS7751R2D) := renesas/rts7751r2d
machdir-$(CONFIG_SH_7751_SYSTEMH) := renesas/systemh machdir-$(CONFIG_SH_7751_SYSTEMH) := renesas/systemh
machdir-$(CONFIG_SH_EDOSK7705) := renesas/edosk7705 machdir-$(CONFIG_SH_EDOSK7705) := renesas/edosk7705
machdir-$(CONFIG_SH_R7780RP) := renesas/r7780rp
machdir-$(CONFIG_SH_SH4202_MICRODEV) := superh/microdev machdir-$(CONFIG_SH_SH4202_MICRODEV) := superh/microdev
machdir-$(CONFIG_SH_LANDISK) := landisk machdir-$(CONFIG_SH_LANDISK) := landisk
machdir-$(CONFIG_SH_TITAN) := titan machdir-$(CONFIG_SH_TITAN) := titan
......
arch/sh/boards/renesas/r7780rp/Kconfig 0 → 100644
View file @ 5283ecb5
if SH_R7780RP
menu "R7780RP options"
config SH_R7780MP
bool "R7780MP board support"
default y
help
Selecting this option will enable support for the mass-production
version of the R7780RP. If in doubt, say Y.
endmenu
endif
arch/sh/boards/renesas/r7780rp/Makefile 0 → 100644
View file @ 5283ecb5
#
# Makefile for the R7780RP-1 specific parts of the kernel
#
obj-y := setup.o io.o irq.o
obj-$(CONFIG_HEARTBEAT) += led.o
arch/sh/boards/renesas/r7780rp/io.c 0 → 100644
View file @ 5283ecb5
/*
* linux/arch/sh/kernel/io_r7780rp.c
*
* Copyright (C) 2001 Ian da Silva, Jeremy Siegel
* Based largely on io_se.c.
*
* I/O routine for Renesas Solutions Highlander R7780RP-1
*
* Initial version only to support LAN access; some
* placeholder code from io_r7780rp.c left in with the
* expectation of later SuperIO and PCMCIA access.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/r7780rp/r7780rp.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <linux/module.h>
#include <linux/pci.h>
#include "../../../drivers/pci/pci-sh7780.h"
/*
* The 7780 R7780RP-1 uses the built-in PCI controller (PCIC)
* of the 7780 processor, and has a SuperIO accessible via the PCI.
* The board also includes a PCMCIA controller on its memory bus,
* like the other Solution Engine boards.
*/
#define SH7780_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
#define PCIIOBR (volatile long *)PCI_REG(SH7780_PCIIOBR)
#define PCIMBR (volatile long *)PCI_REG(SH7780_PCIMBR)
#define PCI_IO_AREA SH7780_PCI_IO_BASE
#define PCI_MEM_AREA SH7780_PCI_CONFIG_BASE
#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7780_PCIIOBR_MASK))
static inline void delay(void)
{
ctrl_inw(0xa0000000);
}
static inline unsigned long port2adr(unsigned int port)
{
if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
if (port == 0x3f6)
return (PA_AREA5_IO + 0x80c);
else
return (PA_AREA5_IO + 0x1000 + ((port-0x1f0) << 1));
else
maybebadio((unsigned long)port);
return port;
}
static inline unsigned long port88796l(unsigned int port, int flag)
{
unsigned long addr;
if (flag)
addr = PA_AX88796L + ((port - AX88796L_IO_BASE) << 1);
else
addr = PA_AX88796L + ((port - AX88796L_IO_BASE) << 1) + 0x1000;
return addr;
}
/* The 7780 R7780RP-1 seems to have everything hooked */
/* up pretty normally (nothing on high-bytes only...) so this */
/* shouldn't be needed */
static inline int shifted_port(unsigned long port)
{
/* For IDE registers, value is not shifted */
if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
return 0;
else
return 1;
}
/* In case someone configures the kernel w/o PCI support: in that */
/* scenario, don't ever bother to check for PCI-window addresses */
/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */
#if defined(CONFIG_PCI)
#define CHECK_SH7780_PCIIO(port) \
((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7780_PCI_IO_SIZE)))
#else
#define CHECK_SH7780_PCIIO(port) (0)
#endif
#if defined(CONFIG_NE2000) || defined(CONFIG_NE2000_MODULE)
#define CHECK_AX88796L_PORT(port) \
((port >= AX88796L_IO_BASE) && (port < (AX88796L_IO_BASE+0x20)))
#else
#define CHECK_AX88796L_PORT(port) (0)
#endif
/*
* General outline: remap really low stuff [eventually] to SuperIO,
* stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
* is mapped through the PCI IO window. Stuff with high bits (PXSEG)
* should be way beyond the window, and is used w/o translation for
* compatibility.
*/
u8 r7780rp_inb(unsigned long port)
{
if (CHECK_AX88796L_PORT(port))
return ctrl_inw(port88796l(port, 0)) & 0xff;
else if (PXSEG(port))
return ctrl_inb(port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
return ctrl_inb(PCI_IOMAP(port));
return ctrl_inw(port2adr(port)) & 0xff;
}
u8 r7780rp_inb_p(unsigned long port)
{
u8 v;
if (CHECK_AX88796L_PORT(port))
v = ctrl_inw(port88796l(port, 0)) & 0xff;
else if (PXSEG(port))
v = ctrl_inb(port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
v = ctrl_inb(PCI_IOMAP(port));
else
v = ctrl_inw(port2adr(port)) & 0xff;
delay();
return v;
}
u16 r7780rp_inw(unsigned long port)
{
if (CHECK_AX88796L_PORT(port))
maybebadio(port);
else if (PXSEG(port))
return ctrl_inw(port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
return ctrl_inw(PCI_IOMAP(port));
else
maybebadio(port);
return 0;
}
u32 r7780rp_inl(unsigned long port)
{
if (CHECK_AX88796L_PORT(port))
maybebadio(port);
else if (PXSEG(port))
return ctrl_inl(port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
return ctrl_inl(PCI_IOMAP(port));
else
maybebadio(port);
return 0;
}
void r7780rp_outb(u8 value, unsigned long port)
{
if (CHECK_AX88796L_PORT(port))
ctrl_outw(value, port88796l(port, 0));
else if (PXSEG(port))
ctrl_outb(value, port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
ctrl_outb(value, PCI_IOMAP(port));
else
ctrl_outw(value, port2adr(port));
}
void r7780rp_outb_p(u8 value, unsigned long port)
{
if (CHECK_AX88796L_PORT(port))
ctrl_outw(value, port88796l(port, 0));
else if (PXSEG(port))
ctrl_outb(value, port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
ctrl_outb(value, PCI_IOMAP(port));
else
ctrl_outw(value, port2adr(port));
delay();
}
void r7780rp_outw(u16 value, unsigned long port)
{
if (CHECK_AX88796L_PORT(port))
maybebadio(port);
else if (PXSEG(port))
ctrl_outw(value, port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
ctrl_outw(value, PCI_IOMAP(port));
else
maybebadio(port);
}
void r7780rp_outl(u32 value, unsigned long port)
{
if (CHECK_AX88796L_PORT(port))
maybebadio(port);
else if (PXSEG(port))
ctrl_outl(value, port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
ctrl_outl(value, PCI_IOMAP(port));
else
maybebadio(port);
}
void r7780rp_insb(unsigned long port, void *dst, unsigned long count)
{
volatile u16 *p;
u8 *buf = dst;
if (CHECK_AX88796L_PORT(port)) {
p = (volatile u16 *)port88796l(port, 0);
while (count--)
*buf++ = *p & 0xff;
} else if (PXSEG(port)) {
while (count--)
*buf++ = *(volatile u8 *)port;
} else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);
while (count--)
*buf++ = *bp;
} else {
p = (volatile u16 *)port2adr(port);
while (count--)
*buf++ = *p & 0xff;
}
}
void r7780rp_insw(unsigned long port, void *dst, unsigned long count)
{
volatile u16 *p;
u16 *buf = dst;
if (CHECK_AX88796L_PORT(port))
p = (volatile u16 *)port88796l(port, 1);
else if (PXSEG(port))
p = (volatile u16 *)port;
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
p = (volatile u16 *)PCI_IOMAP(port);
else
p = (volatile u16 *)port2adr(port);
while (count--)
*buf++ = *p;
}
void r7780rp_insl(unsigned long port, void *dst, unsigned long count)
{
u32 *buf = dst;
if (CHECK_AX88796L_PORT(port))
maybebadio(port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);
while (count--)
*buf++ = *p;
} else
maybebadio(port);
}
void r7780rp_outsb(unsigned long port, const void *src, unsigned long count)
{
volatile u16 *p;
const u8 *buf = src;
if (CHECK_AX88796L_PORT(port)) {
p = (volatile u16 *)port88796l(port, 0);
while (count--)
*p = *buf++;
} else if (PXSEG(port))
while (count--)
ctrl_outb(*buf++, port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);
while (count--)
*bp = *buf++;
} else {
p = (volatile u16 *)port2adr(port);
while (count--)
*p = *buf++;
}
}
void r7780rp_outsw(unsigned long port, const void *src, unsigned long count)
{
volatile u16 *p;
const u16 *buf = src;
if (CHECK_AX88796L_PORT(port))
p = (volatile u16 *)port88796l(port, 1);
else if (PXSEG(port))
p = (volatile u16 *)port;
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
p = (volatile u16 *)PCI_IOMAP(port);
else
p = (volatile u16 *)port2adr(port);
while (count--)
*p = *buf++;
}
void r7780rp_outsl(unsigned long port, const void *src, unsigned long count)
{
const u32 *buf = src;
if (CHECK_AX88796L_PORT(port))
maybebadio(port);
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);
while (count--)
*p = *buf++;
} else
maybebadio(port);
}
void __iomem *r7780rp_ioport_map(unsigned long port, unsigned int size)
{
if (CHECK_AX88796L_PORT(port))
return (void __iomem *)port88796l(port, size > 1);
else if (PXSEG(port))
return (void __iomem *)port;
else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
return (void __iomem *)PCI_IOMAP(port);
return (void __iomem *)port2adr(port);
}
arch/sh/boards/renesas/r7780rp/irq.c 0 → 100644
View file @ 5283ecb5
/*
* linux/arch/sh/boards/renesas/r7780rp/irq.c
*
* Copyright (C) 2000 Kazumoto Kojima
*
* Renesas Solutions Highlander R7780RP-1 Support.
*
* Modified for R7780RP-1 by
* Atom Create Engineering Co., Ltd. 2002.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/r7780rp/r7780rp.h>
#ifdef CONFIG_SH_R7780MP
static int mask_pos[] = {12, 11, 9, 14, 15, 8, 13, 6, 5, 4, 3, 2, 0, 0, 1, 0};
#else
static int mask_pos[] = {15, 14, 13, 12, 11, 10, 9, 8, 7, 5, 6, 4, 0, 1, 2, 0};
#endif
static void enable_r7780rp_irq(unsigned int irq);
static void disable_r7780rp_irq(unsigned int irq);
/* shutdown is same as "disable" */
#define shutdown_r7780rp_irq disable_r7780rp_irq
static void ack_r7780rp_irq(unsigned int irq);
static void end_r7780rp_irq(unsigned int irq);
static unsigned int startup_r7780rp_irq(unsigned int irq)
{
enable_r7780rp_irq(irq);
return 0; /* never anything pending */
}
static void disable_r7780rp_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
unsigned short mask = 0xffff ^ (0x0001 << mask_pos[irq]);
/* Set the priority in IPR to 0 */
local_irq_save(flags);
val = ctrl_inw(IRLCNTR1);
val &= mask;
ctrl_outw(val, IRLCNTR1);
local_irq_restore(flags);
}
static void enable_r7780rp_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
unsigned short value = (0x0001 << mask_pos[irq]);
/* Set priority in IPR back to original value */
local_irq_save(flags);
val = ctrl_inw(IRLCNTR1);
val |= value;
ctrl_outw(val, IRLCNTR1);
local_irq_restore(flags);
}
static void ack_r7780rp_irq(unsigned int irq)
{
disable_r7780rp_irq(irq);
}
static void end_r7780rp_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_r7780rp_irq(irq);
}
static struct hw_interrupt_type r7780rp_irq_type = {
.typename = "R7780RP-IRQ",
.startup = startup_r7780rp_irq,
.shutdown = shutdown_r7780rp_irq,
.enable = enable_r7780rp_irq,
.disable = disable_r7780rp_irq,
.ack = ack_r7780rp_irq,
.end = end_r7780rp_irq,
};
static void make_r7780rp_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_desc[irq].handler = &r7780rp_irq_type;
disable_r7780rp_irq(irq);
}
/*
* Initialize IRQ setting
*/
void __init init_r7780rp_IRQ(void)
{
int i;
/* IRL0=PCI Slot #A
* IRL1=PCI Slot #B
* IRL2=PCI Slot #C
* IRL3=PCI Slot #D
* IRL4=CF Card
* IRL5=CF Card Insert
* IRL6=M66596
* IRL7=SD Card
* IRL8=Touch Panel
* IRL9=SCI
* IRL10=Serial
* IRL11=Extention #A
* IRL11=Extention #B
* IRL12=Debug LAN
* IRL13=Push Switch
* IRL14=ZiggBee IO
*/
for (i=0; i<15; i++)
make_r7780rp_irq(i);
}
arch/sh/boards/renesas/r7780rp/led.c 0 → 100644
View file @ 5283ecb5
/*
* Copyright (C) Atom Create Engineering Co., Ltd.
*
* May be copied or modified under the terms of GNU General Public
* License. See linux/COPYING for more information.
*
* This file contains Renesas Solutions HIGHLANDER R7780RP-1 specific LED code.
*/
#include <linux/config.h>
#include <linux/sched.h>
#include <asm/io.h>
#include <asm/r7780rp/r7780rp.h>
/* Cycle the LED's in the clasic Knightriger/Sun pattern */
void heartbeat_r7780rp(void)
{
static unsigned int cnt = 0, period = 0;
volatile unsigned short *p = (volatile unsigned short *)PA_OBLED;
static unsigned bit = 0, up = 1;
unsigned bit_pos[] = {2, 1, 0, 3, 6, 5, 4, 7};
cnt += 1;
if (cnt < period)
return;
cnt = 0;
/* Go through the points (roughly!):
* f(0)=10, f(1)=16, f(2)=20, f(5)=35, f(int)->110
*/
period = 110 - ((300 << FSHIFT)/((avenrun[0]/5) + (3<<FSHIFT)));
*p = 1 << bit_pos[bit];
if (up)
if (bit == 7) {
bit--;
up = 0;
} else
bit++;
else if (bit == 0)
up = 1;
else
bit--;
}
arch/sh/boards/renesas/r7780rp/setup.c 0 → 100644
View file @ 5283ecb5
/*
* arch/sh/boards/renesas/r7780rp/setup.c
*
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
* Copyright (C) 2005, 2006 Paul Mundt
*
* Renesas Solutions Highlander R7780RP-1 Support.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
#include <asm/r7780rp/r7780rp.h>
#include <asm/clock.h>
#include <asm/io.h>
extern void heartbeat_r7780rp(void);
extern void init_r7780rp_IRQ(void);
/*
* The Machine Vector
*/
struct sh_machine_vector mv_r7780rp __initmv = {
.mv_nr_irqs = 109,
.mv_inb = r7780rp_inb,
.mv_inw = r7780rp_inw,
.mv_inl = r7780rp_inl,
.mv_outb = r7780rp_outb,
.mv_outw = r7780rp_outw,
.mv_outl = r7780rp_outl,
.mv_inb_p = r7780rp_inb_p,
.mv_inw_p = r7780rp_inw,
.mv_inl_p = r7780rp_inl,
.mv_outb_p = r7780rp_outb_p,
.mv_outw_p = r7780rp_outw,
.mv_outl_p = r7780rp_outl,
.mv_insb = r7780rp_insb,
.mv_insw = r7780rp_insw,
.mv_insl = r7780rp_insl,
.mv_outsb = r7780rp_outsb,
.mv_outsw = r7780rp_outsw,
.mv_outsl = r7780rp_outsl,
.mv_ioport_map = r7780rp_ioport_map,
.mv_init_irq = init_r7780rp_IRQ,
#ifdef CONFIG_HEARTBEAT
.mv_heartbeat = heartbeat_r7780rp,
#endif
};
ALIAS_MV(r7780rp)
static struct resource m66596_usb_host_resources[] = {
[0] = {
.start = 0xa4800000,
.end = 0xa4ffffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 6, /* irq number */
.end = 6,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device m66596_usb_host_device = {
.name = "m66596-hcd",
.id = 0,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(m66596_usb_host_resources),
.resource = m66596_usb_host_resources,
};
static struct platform_device *r7780rp_devices[] __initdata = {
&m66596_usb_host_device,
};
static int __init r7780rp_devices_setup(void)
{
return platform_add_devices(r7780rp_devices,
ARRAY_SIZE(r7780rp_devices));
}
__initcall(r7780rp_devices_setup);
/*
* Platform specific clocks
*/
static void ivdr_clk_enable(struct clk *clk)
{
ctrl_outw(ctrl_inw(PA_IVDRCTL) | (1 << 8), PA_IVDRCTL);
}
static void ivdr_clk_disable(struct clk *clk)
{
ctrl_outw(ctrl_inw(PA_IVDRCTL) & ~(1 << 8), PA_IVDRCTL);
}
static struct clk_ops ivdr_clk_ops = {
.enable = ivdr_clk_enable,
.disable = ivdr_clk_disable,
};
static struct clk ivdr_clk = {
.name = "ivdr_clk",
.ops = &ivdr_clk_ops,
};
static struct clk *r7780rp_clocks[] = {
&ivdr_clk,
};
const char *get_system_type(void)
{
return "Highlander R7780RP-1";
}
static void r7780rp_power_off(void)
{
#ifdef CONFIG_SH_R7780MP
ctrl_outw(0x0001, PA_POFF);
#endif
}
/*
* Initialize the board
*/
void __init platform_setup(void)
{
u16 ver = ctrl_inw(PA_VERREG);
int i;
printk(KERN_INFO "Renesas Solutions Highlander R7780RP-1 support.\n");
printk(KERN_INFO "Board version: %d (revision %d), "
"FPGA version: %d (revision %d)\n",
(ver >> 12) & 0xf, (ver >> 8) & 0xf,
(ver >> 4) & 0xf, ver & 0xf);
/*
* Enable the important clocks right away..
*/
for (i = 0; i < ARRAY_SIZE(r7780rp_clocks); i++) {
struct clk *clk = r7780rp_clocks[i];
clk_register(clk);
clk_enable(clk);
}
ctrl_outw(0x0000, PA_OBLED); /* Clear LED. */
#ifndef CONFIG_SH_R7780MP
ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */
#endif
ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x0100, PA_IVDRCTL); /* Si13112 */
pm_power_off = r7780rp_power_off;
}
arch/sh/configs/r7780rp_defconfig 0 → 100644
View file @ 5283ecb5
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.15-sh
# Sat Jan 7 19:47:53 2006
#
CONFIG_SUPERH=y
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
CONFIG_HOTPLUG=y
CONFIG_KOBJECT_UEVENT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EMBEDDED=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
CONFIG_SHMEM=y
CONFIG_CC_ALIGN_FUNCTIONS=0
CONFIG_CC_ALIGN_LABELS=0
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# Block layer
#
# CONFIG_LBD is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
#
# System type
#
# CONFIG_SH_SOLUTION_ENGINE is not set
# CONFIG_SH_7751_SOLUTION_ENGINE is not set
# CONFIG_SH_7300_SOLUTION_ENGINE is not set
# CONFIG_SH_73180_SOLUTION_ENGINE is not set
# CONFIG_SH_7751_SYSTEMH is not set
# CONFIG_SH_STB1_HARP is not set
# CONFIG_SH_STB1_OVERDRIVE is not set
# CONFIG_SH_HP6XX is not set
# CONFIG_SH_CQREEK is not set
# CONFIG_SH_DMIDA is not set
# CONFIG_SH_EC3104 is not set
# CONFIG_SH_SATURN is not set
# CONFIG_SH_DREAMCAST is not set
# CONFIG_SH_CAT68701 is not set
# CONFIG_SH_BIGSUR is not set
# CONFIG_SH_SH2000 is not set
# CONFIG_SH_ADX is not set
# CONFIG_SH_MPC1211 is not set
# CONFIG_SH_SH03 is not set
# CONFIG_SH_SECUREEDGE5410 is not set
# CONFIG_SH_HS7751RVOIP is not set
# CONFIG_SH_RTS7751R2D is not set
# CONFIG_SH_R77703DRP is not set
CONFIG_SH_R7780RP=y
# CONFIG_SH_EDOSK7705 is not set
# CONFIG_SH_SH4202_MICRODEV is not set
# CONFIG_SH_LANDISK is not set
# CONFIG_SH_TITAN is not set
# CONFIG_SH_UNKNOWN is not set
#
# Processor selection
#
CONFIG_CPU_SH4=y
CONFIG_CPU_SH4A=y
#
# SH-2 Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7604 is not set
#
# SH-3 Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7300 is not set
# CONFIG_CPU_SUBTYPE_SH7705 is not set
# CONFIG_CPU_SUBTYPE_SH7707 is not set
# CONFIG_CPU_SUBTYPE_SH7708 is not set
# CONFIG_CPU_SUBTYPE_SH7709 is not set
#
# SH-4 Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7750 is not set
# CONFIG_CPU_SUBTYPE_SH7091 is not set
# CONFIG_CPU_SUBTYPE_SH7750R is not set
# CONFIG_CPU_SUBTYPE_SH7750S is not set
# CONFIG_CPU_SUBTYPE_SH7751 is not set
# CONFIG_CPU_SUBTYPE_SH7751R is not set
# CONFIG_CPU_SUBTYPE_SH7760 is not set
# CONFIG_CPU_SUBTYPE_SH4_202 is not set
#
# ST40 Processor Support
#
# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
#
# SH-4A Processor Support
#
# CONFIG_CPU_SUBTYPE_SH73180 is not set
# CONFIG_CPU_SUBTYPE_SH7770 is not set
CONFIG_CPU_SUBTYPE_SH7780=y
#
# Memory management options
#
CONFIG_MMU=y
CONFIG_32BIT=y
CONFIG_HUGETLB_PAGE_SIZE_64K=y
# CONFIG_HUGETLB_PAGE_SIZE_1MB is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
#
# Cache configuration
#
# CONFIG_SH_DIRECT_MAPPED is not set
# CONFIG_SH_WRITETHROUGH is not set
# CONFIG_SH_OCRAM is not set
CONFIG_MEMORY_START=0x08000000
CONFIG_MEMORY_SIZE=0x08000000
#
# Processor features
#
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SH_FPU=y
CONFIG_SH_STORE_QUEUES=y
#
# Timer support
#
CONFIG_SH_TMU=y
CONFIG_SH_PCLK_FREQ_BOOL=y
CONFIG_SH_PCLK_FREQ=32000000
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
#
# DMA support
#
CONFIG_SH_DMA=y
CONFIG_NR_ONCHIP_DMA_CHANNELS=6
# CONFIG_NR_DMA_CHANNELS_BOOL is not set
#
# Companion Chips
#
# CONFIG_HD6446X_SERIES is not set
#
# Kernel features
#
# CONFIG_KEXEC is not set
CONFIG_PREEMPT=y
# CONFIG_SMP is not set
CONFIG_CPU_HAS_INTEVT=y
CONFIG_CPU_HAS_INTC2_IRQ=y
#
# Boot options
#
CONFIG_ZERO_PAGE_OFFSET=0x00001000
CONFIG_BOOT_LINK_OFFSET=0x00800000
# CONFIG_UBC_WAKEUP is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="mem=128M console=ttySC0,115200 root=/dev/hda1"
#
# Bus options
#
CONFIG_PCI=y
CONFIG_SH_PCIDMA_NONCOHERENT=y
CONFIG_PCI_AUTO=y
CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
CONFIG_PCI_LEGACY_PROC=y
# CONFIG_PCI_DEBUG is not set
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# PCI Hotplug Support
#
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_FAKE is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_FLAT is not set
# CONFIG_BINFMT_MISC is not set
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_ASK_IP_FIB_HASH=y
# CONFIG_IP_FIB_TRIE is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_MULTIPLE_TABLES is not set
# CONFIG_IP_ROUTE_MULTIPATH is not set
# CONFIG_IP_ROUTE_VERBOSE is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_BIC=y
# CONFIG_IPV6 is not set
# CONFIG_NETFILTER is not set
#
# DCCP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_DCCP is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
CONFIG_BRIDGE=m
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_IEEE80211 is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=m
# CONFIG_DEBUG_DRIVER is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
#
# ATA/ATAPI/MFM/RLL support
#
CONFIG_IDE=m
CONFIG_IDE_MAX_HWIFS=4
CONFIG_BLK_DEV_IDE=m
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
CONFIG_BLK_DEV_IDE_SATA=y
CONFIG_BLK_DEV_IDEDISK=m
CONFIG_IDEDISK_MULTI_MODE=y
# CONFIG_BLK_DEV_IDECD is not set
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
CONFIG_BLK_DEV_IDESCSI=m
# CONFIG_IDE_TASK_IOCTL is not set
#
# IDE chipset support/bugfixes
#
CONFIG_IDE_GENERIC=m
CONFIG_BLK_DEV_IDEPCI=y
CONFIG_IDEPCI_SHARE_IRQ=y
# CONFIG_BLK_DEV_OFFBOARD is not set
CONFIG_BLK_DEV_GENERIC=m
# CONFIG_BLK_DEV_OPTI621 is not set
CONFIG_BLK_DEV_IDEDMA_PCI=y
# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
CONFIG_IDEDMA_PCI_AUTO=y
# CONFIG_IDEDMA_ONLYDISK is not set
CONFIG_BLK_DEV_AEC62XX=m
# CONFIG_BLK_DEV_ALI15X3 is not set
# CONFIG_BLK_DEV_AMD74XX is not set
# CONFIG_BLK_DEV_CMD64X is not set
# CONFIG_BLK_DEV_TRIFLEX is not set
# CONFIG_BLK_DEV_CY82C693 is not set
# CONFIG_BLK_DEV_CS5520 is not set
# CONFIG_BLK_DEV_CS5530 is not set
# CONFIG_BLK_DEV_HPT34X is not set
# CONFIG_BLK_DEV_HPT366 is not set
# CONFIG_BLK_DEV_SC1200 is not set
# CONFIG_BLK_DEV_PIIX is not set
# CONFIG_BLK_DEV_IT821X is not set
# CONFIG_BLK_DEV_NS87415 is not set
# CONFIG_BLK_DEV_PDC202XX_OLD is not set
CONFIG_BLK_DEV_PDC202XX_NEW=m
# CONFIG_PDC202XX_FORCE is not set
# CONFIG_BLK_DEV_SVWKS is not set
CONFIG_BLK_DEV_SIIMAGE=m
# CONFIG_BLK_DEV_SLC90E66 is not set
# CONFIG_BLK_DEV_TRM290 is not set
# CONFIG_BLK_DEV_VIA82CXXX is not set
CONFIG_IDE_SH=y
# CONFIG_IDE_ARM is not set
CONFIG_BLK_DEV_IDEDMA=y
# CONFIG_IDEDMA_IVB is not set
CONFIG_IDEDMA_AUTO=y
# CONFIG_BLK_DEV_HD is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=m
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=m
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
CONFIG_CHR_DEV_SG=m
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
#
# SCSI Transport Attributes
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
#
# SCSI low-level drivers
#
# CONFIG_ISCSI_TCP is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_SATA is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_FC is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
CONFIG_SCSI_QLA2XXX=m
# CONFIG_SCSI_QLA21XX is not set
# CONFIG_SCSI_QLA22XX is not set
# CONFIG_SCSI_QLA2300 is not set
# CONFIG_SCSI_QLA2322 is not set
# CONFIG_SCSI_QLA6312 is not set
# CONFIG_SCSI_QLA24XX is not set
# CONFIG_SCSI_LPFC is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
# CONFIG_FUSION_SPI is not set
# CONFIG_FUSION_FC is not set
# CONFIG_FUSION_SAS is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
#
# PHY device support
#
# CONFIG_PHYLIB is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_STNIC is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_SMC91X is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
CONFIG_NE2000=y
CONFIG_NET_PCI=y
CONFIG_PCNET32=m
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
# CONFIG_FORCEDETH is not set
# CONFIG_DGRS is not set
# CONFIG_EEPRO100 is not set
# CONFIG_E100 is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
CONFIG_8139CP=m
CONFIG_8139TOO=m
# CONFIG_8139TOO_PIO is not set
# CONFIG_8139TOO_TUNE_TWISTER is not set
CONFIG_8139TOO_8129=y
# CONFIG_8139_OLD_RX_RESET is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
CONFIG_VIA_RHINE=m
CONFIG_VIA_RHINE_MMIO=y
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
CONFIG_E1000=m
# CONFIG_E1000_NAPI is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
CONFIG_R8169=y
# CONFIG_R8169_NAPI is not set
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SK98LIN is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2 is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_CHELSIO_T1 is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
#
# Token Ring devices
#
# CONFIG_TR is not set
#
# Wireless LAN (non-hamradio)
#
CONFIG_NET_RADIO=y
#
# Obsolete Wireless cards support (pre-802.11)
#
# CONFIG_STRIP is not set
#
# Wireless 802.11b ISA/PCI cards support
#
CONFIG_HERMES=m
# CONFIG_PLX_HERMES is not set
# CONFIG_TMD_HERMES is not set
# CONFIG_NORTEL_HERMES is not set
# CONFIG_PCI_HERMES is not set
# CONFIG_ATMEL is not set
#
# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
#
CONFIG_PRISM54=m
# CONFIG_HOSTAP is not set
CONFIG_NET_WIRELESS=y
#
# Wan interfaces
#
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NET_FC is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
# CONFIG_TELCLOCK is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Misc devices
#
#
# Multimedia Capabilities Port drivers
#
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# Graphics support
#
# CONFIG_FB is not set
#
# Sound
#
CONFIG_SOUND=m
#
# Advanced Linux Sound Architecture
#
# CONFIG_SND is not set
#
# Open Sound System
#
CONFIG_SOUND_PRIME=m
# CONFIG_OBSOLETE_OSS_DRIVER is not set
# CONFIG_SOUND_FUSION is not set
# CONFIG_SOUND_ICH is not set
# CONFIG_SOUND_TRIDENT is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
#
# USB support
#
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# InfiniBand support
#
# CONFIG_INFINIBAND is not set
#
# SN Devices
#
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
# CONFIG_EXT3_FS_SECURITY is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
CONFIG_MINIX_FS=y
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
CONFIG_NTFS_FS=y
# CONFIG_NTFS_DEBUG is not set
CONFIG_NTFS_RW=y
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_RAMFS=y
# CONFIG_RELAYFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_V4=y
# CONFIG_NFS_DIRECTIO is not set
CONFIG_NFSD=y
CONFIG_NFSD_V3=y
# CONFIG_NFSD_V3_ACL is not set
CONFIG_NFSD_V4=y
CONFIG_NFSD_TCP=y
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_EXPORTFS=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
CONFIG_NLS_CODEPAGE_932=y
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_MAGIC_SYSRQ is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_DEBUG_SLAB is not set
CONFIG_DEBUG_PREEMPT=y
CONFIG_DEBUG_SPINLOCK=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_INFO is not set
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_VM is not set
CONFIG_FRAME_POINTER=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_SH_STANDARD_BIOS is not set
# CONFIG_EARLY_SCIF_CONSOLE is not set
# CONFIG_KGDB is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
CONFIG_CRYPTO=y
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_TEST is not set
#
# Hardware crypto devices
#
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
arch/sh/drivers/dma/Kconfig
View file @ 5283ecb5
...@@ -11,6 +11,8 @@ config SH_DMA ...@@ -11,6 +11,8 @@ config SH_DMA
config NR_ONCHIP_DMA_CHANNELS config NR_ONCHIP_DMA_CHANNELS
depends on SH_DMA depends on SH_DMA
int "Number of on-chip DMAC channels" int "Number of on-chip DMAC channels"
default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
default "12" if CPU_SUBTYPE_SH7780
default "4" default "4"
help help
This allows you to specify the number of channels that the on-chip This allows you to specify the number of channels that the on-chip
...@@ -52,4 +54,3 @@ config DMA_PAGE_OPS_CHANNEL ...@@ -52,4 +54,3 @@ config DMA_PAGE_OPS_CHANNEL
are dual-address capable. are dual-address capable.
endmenu endmenu
arch/sh/drivers/dma/dma-sh.c
View file @ 5283ecb5
...@@ -11,14 +11,10 @@ ...@@ -11,14 +11,10 @@
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/module.h> #include <linux/module.h>
#include <asm/dreamcast/dma.h> #include <asm/dreamcast/dma.h>
#include <asm/signal.h>
#include <asm/irq.h>
#include <asm/dma.h> #include <asm/dma.h>
#include <asm/io.h> #include <asm/io.h>
#include "dma-sh.h" #include "dma-sh.h"
......
arch/sh/drivers/pci/Makefile
View file @ 5283ecb5
...@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o ...@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o
obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o
obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o
obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \ obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
dma-dreamcast.o dma-dreamcast.o
...@@ -14,4 +15,5 @@ obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o ...@@ -14,4 +15,5 @@ obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o
obj-$(CONFIG_SH_BIGSUR) += ops-bigsur.o obj-$(CONFIG_SH_BIGSUR) += ops-bigsur.o
obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o
obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o
obj-$(CONFIG_SH_R7780RP) += ops-r7780rp.o fixups-r7780rp.o
obj-$(CONFIG_SH_TITAN) += ops-titan.o obj-$(CONFIG_SH_TITAN) += ops-titan.o
arch/sh/drivers/pci/fixups-r7780rp.c 0 → 100644
View file @ 5283ecb5
/*
* arch/sh/drivers/pci/fixups-r7780rp.c
*
* Highlander R7780RP-1 PCI fixups
*
* Copyright (C) 2003 Lineo uSolutions, Inc.
* Copyright (C) 2004 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include "pci-sh7780.h"
#include <asm/io.h>
int pci_fixup_pcic(void)
{
outl(0x000043ff, PCI_REG(SH7780_PCIIMR));
outl(0x0000380f, PCI_REG(SH7780_PCIAINTM));
outl(0xfbb00047, PCI_REG(SH7780_PCICMD));
outl(0x00000000, PCI_REG(SH7780_PCIIBAR));
outl(0x00011912, PCI_REG(SH7780_PCISVID));
outl(0x08000000, PCI_REG(SH7780_PCICSCR0));
outl(0x0000001b, PCI_REG(SH7780_PCICSAR0));
outl(0xfd000000, PCI_REG(SH7780_PCICSCR1));
outl(0x0000000f, PCI_REG(SH7780_PCICSAR1));
outl(0xfd000000, PCI_REG(SH7780_PCIMBR0));
outl(0x00fc0000, PCI_REG(SH7780_PCIMBMR0));
/* Set IOBR for windows containing area specified in pci.h */
outl((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1)), PCI_REG(SH7780_PCIIOBR));
outl(((SH7780_PCI_IO_SIZE-1) & (7<<18)), PCI_REG(SH7780_PCIIOBMR));
return 0;
}
arch/sh/drivers/pci/ops-r7780rp.c 0 → 100644
View file @ 5283ecb5
/*
* Author: Ian DaSilva (idasilva@mvista.com)
*
* Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* PCI initialization for the Renesas SH7780 Highlander R7780RP-1 board
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/module.h>
#include <asm/io.h>
#include "pci-sh7780.h"
#include <asm/r7780rp/r7780rp.h>
int __init pcibios_map_platform_irq(u8 slot, u8 pin)
{
switch (slot) {
case 0: return IRQ_PCISLOT1; /* PCI Interrupt #1 */
case 1: return IRQ_PCISLOT2; /* PCI Interrupt #2 */
case 2: return IRQ_PCISLOT3; /* PCI Interrupt #3 */
case 3: return IRQ_PCISLOT4; /* PCI Interrupt E4 */
default:
printk("PCI: Bad IRQ mapping request for slot %d, func %d\n", slot, pin-1);
return -1;
}
}
static struct resource sh7780_io_resource = {
.name = "SH7780_IO",
.start = 0x2000,
.end = 0x2000 + SH7780_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource sh7780_mem_resource = {
.name = "SH7780_mem",
.start = SH7780_PCI_MEMORY_BASE,
.end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
extern struct pci_ops sh7780_pci_ops;
struct pci_channel board_pci_channels[] = {
{ &sh7780_pci_ops, &sh7780_io_resource, &sh7780_mem_resource, 0, 0xff },
{ NULL, NULL, NULL, 0, 0 },
};
EXPORT_SYMBOL(board_pci_channels);
static struct sh7780_pci_address_map sh7780_pci_map = {
.window0 = {
.base = SH7780_CS2_BASE_ADDR,
.size = 0x04000000,
},
.window1 = {
.base = SH7780_CS3_BASE_ADDR,
.size = 0x04000000,
},
.flags = SH7780_PCIC_NO_RESET,
};
int __init pcibios_init_platform(void)
{
return sh7780_pcic_init(&sh7780_pci_map);
}
arch/sh/drivers/pci/pci-auto.c
View file @ 5283ecb5
...@@ -45,7 +45,7 @@ ...@@ -45,7 +45,7 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/pci.h> #include <linux/pci.h>
#undef DEBUG #define DEBUG
#ifdef DEBUG #ifdef DEBUG
#define DBG(x...) printk(x) #define DBG(x...) printk(x)
#else #else
...@@ -116,7 +116,6 @@ pciauto_setup_bars(struct pci_channel *hose, ...@@ -116,7 +116,6 @@ pciauto_setup_bars(struct pci_channel *hose,
int found_mem64 = 0; int found_mem64 = 0;
for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) { for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
u32 bar_addr; u32 bar_addr;
/* Read the old BAR value */ /* Read the old BAR value */
...@@ -125,7 +124,6 @@ pciauto_setup_bars(struct pci_channel *hose, ...@@ -125,7 +124,6 @@ pciauto_setup_bars(struct pci_channel *hose,
pci_devfn, pci_devfn,
bar, bar,
&bar_addr); &bar_addr);
#endif
/* Tickle the BAR and get the response */ /* Tickle the BAR and get the response */
early_write_config_dword(hose, top_bus, early_write_config_dword(hose, top_bus,
...@@ -140,7 +138,6 @@ pciauto_setup_bars(struct pci_channel *hose, ...@@ -140,7 +138,6 @@ pciauto_setup_bars(struct pci_channel *hose,
bar, bar,
&bar_response); &bar_response);
#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
/* /*
* Write the old BAR value back out, only update the BAR * Write the old BAR value back out, only update the BAR
* if we implicitly want resources to be updated, which * if we implicitly want resources to be updated, which
...@@ -151,7 +148,6 @@ pciauto_setup_bars(struct pci_channel *hose, ...@@ -151,7 +148,6 @@ pciauto_setup_bars(struct pci_channel *hose,
pci_devfn, pci_devfn,
bar, bar,
bar_addr); bar_addr);
#endif
/* If BAR is not implemented go to the next BAR */ /* If BAR is not implemented go to the next BAR */
if (!bar_response) if (!bar_response)
...@@ -362,7 +358,7 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose, ...@@ -362,7 +358,7 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
{ {
u32 temp; u32 temp;
#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D) #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D) && !defined(CONFIG_SH_R7780RP)
/* /*
* [jsun] we always bump up baselines a little, so that if there * [jsun] we always bump up baselines a little, so that if there
* nothing behind P2P bridge, we don't wind up overlapping IO/MEM * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
...@@ -396,7 +392,7 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose, ...@@ -396,7 +392,7 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
* configured by this routine to happily live behind a * configured by this routine to happily live behind a
* P2P bridge in a system. * P2P bridge in a system.
*/ */
#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) #if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_R7780RP)
pciauto_lower_memspc += 0x00400000; pciauto_lower_memspc += 0x00400000;
pciauto_lower_iospc += 0x00004000; pciauto_lower_iospc += 0x00004000;
#endif #endif
...@@ -471,7 +467,7 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus) ...@@ -471,7 +467,7 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) { if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
DBG(" Bridge: primary=%.2x, secondary=%.2x\n", DBG(" Bridge: primary=%.2x, secondary=%.2x\n",
current_bus, sub_bus + 1); current_bus, sub_bus + 1);
#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) #if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_R7780RP)
pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_1); pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_1);
#endif #endif
pciauto_prescan_setup_bridge(hose, top_bus, current_bus, pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
......
arch/sh/drivers/pci/pci-sh7751.c
View file @ 5283ecb5
...@@ -223,7 +223,7 @@ static int __init __area_sdram_check(unsigned int area) ...@@ -223,7 +223,7 @@ static int __init __area_sdram_check(unsigned int area)
word = inl(SH7751_BCR1); word = inl(SH7751_BCR1);
/* check BCR for SDRAM in area */ /* check BCR for SDRAM in area */
if(((word >> area) & 1) == 0) { if (((word >> area) & 1) == 0) {
printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n", printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
area, word); area, word);
return 0; return 0;
...@@ -232,7 +232,7 @@ static int __init __area_sdram_check(unsigned int area) ...@@ -232,7 +232,7 @@ static int __init __area_sdram_check(unsigned int area)
word = (u16)inw(SH7751_BCR2); word = (u16)inw(SH7751_BCR2);
/* check BCR2 for 32bit SDRAM interface*/ /* check BCR2 for 32bit SDRAM interface*/
if(((word >> (area << 1)) & 0x3) != 0x3) { if (((word >> (area << 1)) & 0x3) != 0x3) {
printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n", printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
area, word); area, word);
return 0; return 0;
......
arch/sh/drivers/pci/pci-sh7780.c 0 → 100644
View file @ 5283ecb5
/*
* Low-Level PCI Support for the SH7780
*
* Dustin McIntire (dustin@sensoria.com)
* Derived from arch/i386/kernel/pci-*.c which bore the message:
* (c) 1999--2000 Martin Mares <mj@ucw.cz>
*
* Ported to the new API by Paul Mundt <lethal@linux-sh.org>
* With cleanup by Paul van Gool <pvangool@mimotech.com>
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
*/
#undef DEBUG
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include "pci-sh7780.h"
static unsigned int pci_probe = PCI_PROBE_CONF1;
extern int pci_fixup_pcic(void);
/*
* Direct access to PCI hardware...
*/
#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
/*
* Functions for accessing PCI configuration space with type 1 accesses
*/
static int sh7780_pci_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
unsigned long flags;
u32 data;
/*
* PCIPDR may only be accessed as 32 bit words,
* so we must do byte alignment by hand
*/
local_irq_save(flags);
outl(CONFIG_CMD(bus, devfn, where), PCI_REG(SH7780_PCIPAR));
data = inl(PCI_REG(SH7780_PCIPDR));
local_irq_restore(flags);
switch (size) {
case 1:
*val = (data >> ((where & 3) << 3)) & 0xff;
break;
case 2:
*val = (data >> ((where & 2) << 3)) & 0xffff;
break;
case 4:
*val = data;
break;
default:
return PCIBIOS_FUNC_NOT_SUPPORTED;
}
return PCIBIOS_SUCCESSFUL;
}
/*
* Since SH7780 only does 32bit access we'll have to do a read,
* mask,write operation.
* We'll allow an odd byte offset, though it should be illegal.
*/
static int sh7780_pci_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
unsigned long flags;
int shift;
u32 data;
local_irq_save(flags);
outl(CONFIG_CMD(bus, devfn, where), PCI_REG(SH7780_PCIPAR));
data = inl(PCI_REG(SH7780_PCIPDR));
local_irq_restore(flags);
switch (size) {
case 1:
shift = (where & 3) << 3;
data &= ~(0xff << shift);
data |= ((val & 0xff) << shift);
break;
case 2:
shift = (where & 2) << 3;
data &= ~(0xffff << shift);
data |= ((val & 0xffff) << shift);
break;
case 4:
data = val;
break;
default:
return PCIBIOS_FUNC_NOT_SUPPORTED;
}
outl(data, PCI_REG(SH7780_PCIPDR));
return PCIBIOS_SUCCESSFUL;
}
#undef CONFIG_CMD
struct pci_ops sh7780_pci_ops = {
.read = sh7780_pci_read,
.write = sh7780_pci_write,
};
static int __init pci_check_direct(void)
{
unsigned int tmp, id;
outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
/* check for SH7780/SH7780R hardware */
id = inl(PCI_REG(SH7780_PCIVID));
if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) &&
(id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) {
printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
return -ENODEV;
}
/*
* Check if configuration works.
*/
if (pci_probe & PCI_PROBE_CONF1) {
tmp = inl(PCI_REG(SH7780_PCIPAR));
outl(0x80000000, PCI_REG(SH7780_PCIPAR));
if (inl(PCI_REG(SH7780_PCIPAR)) == 0x80000000) {
outl(tmp, PCI_REG(SH7780_PCIPAR));
printk(KERN_INFO "PCI: Using configuration type 1\n");
request_region(PCI_REG(SH7780_PCIPAR), 8, "PCI conf1");
return 0;
}
outl(tmp, PCI_REG(SH7780_PCIPAR));
}
pr_debug("PCI: pci_check_direct failed\n");
return -EINVAL;
}
/***************************************************************************************/
/*
* Handle bus scanning and fixups ....
*/
static void __init pci_fixup_ide_bases(struct pci_dev *d)
{
int i;
/*
* PCI IDE controllers use non-standard I/O port decoding, respect it.
*/
if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
return;
pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d));
for(i=0; i<4; i++) {
struct resource *r = &d->resource[i];
if ((r->start & ~0x80) == 0x374) {
r->start |= 2;
r->end = r->start;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
/*
* Called after each bus is probed, but before its children
* are examined.
*/
void __init pcibios_fixup_bus(struct pci_bus *b)
{
pci_read_bridge_bases(b);
}
/*
* Initialization. Try all known PCI access methods. Note that we support
* using both PCI BIOS and direct access: in such cases, we use I/O ports
* to access config space.
*
* Note that the platform specific initialization (BSC registers, and memory
* space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it
* exists and via the platform defined function pcibios_init_platform().
* See pci_bigsur.c for implementation;
*
* The BIOS version of the pci functions is not yet implemented but it is left
* in for completeness. Currently an error will be genereated at compile time.
*/
static int __init sh7780_pci_init(void)
{
int ret;
pr_debug("PCI: Starting intialization.\n");
/* Setup the INTC */
ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */
ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */
ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */
ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */
ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */
if ((ret = pci_check_direct()) != 0)
return ret;
return pcibios_init_platform();
}
core_initcall(sh7780_pci_init);
int __init sh7780_pcic_init(struct sh7780_pci_address_map *map)
{
u32 word;
/*
* This code is unused for some boards as it is done in the
* bootloader and doing it here means the MAC addresses loaded
* by the bootloader get lost.
*/
if (!(map->flags & SH7780_PCIC_NO_RESET)) {
/* toggle PCI reset pin */
word = SH7780_PCICR_PREFIX | SH7780_PCICR_PRST;
outl(word,PCI_REG(SH7780_PCICR));
/* Wait for a long time... not 1 sec. but long enough */
mdelay(100);
word = SH7780_PCICR_PREFIX;
outl(word,PCI_REG(SH7780_PCICR));
}
/* set the command/status bits to:
* Wait Cycle Control + Parity Enable + Bus Master +
* Mem space enable
*/
outl(0x00000046, PCI_REG(SH7780_PCICMD));
/* define this host as the host bridge */
word = SH7780_PCI_HOST_BRIDGE << 24;
outl(word, PCI_REG(SH7780_PCIRID));
/* Set IO and Mem windows to local address
* Make PCI and local address the same for easy 1 to 1 mapping
* Window0 = map->window0.size @ non-cached area base = SDRAM
* Window1 = map->window1.size @ cached area base = SDRAM
*/
word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
outl(0x07f00001, PCI_REG(SH7780_PCILSR0));
word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
outl(0x00000001, PCI_REG(SH7780_PCILSR1));
/* Set the values on window 0 PCI config registers */
word = P2SEGADDR(map->window0.base);
outl(0xa8000000, PCI_REG(SH7780_PCILAR0));
outl(0x08000000, PCI_REG(SH7780_PCIMBAR0));
/* Set the values on window 1 PCI config registers */
word = P2SEGADDR(map->window1.base);
outl(0x00000000, PCI_REG(SH7780_PCILAR1));
outl(0x00000000, PCI_REG(SH7780_PCIMBAR1));
/* Map IO space into PCI IO window
* The IO window is 64K-PCIBIOS_MIN_IO in size
* IO addresses will be translated to the
* PCI IO window base address
*/
PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO,
(64*1024), SH7780_PCI_IO_BASE+PCIBIOS_MIN_IO);
/* NOTE: I'm ignoring the PCI error IRQs for now..
* TODO: add support for the internal error interrupts and
* DMA interrupts...
*/
#ifdef CONFIG_SH_R7780RP
pci_fixup_pcic();
#endif
/* SH7780 init done, set central function init complete */
/* use round robin mode to stop a device starving/overruning */
word = SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | /* SH7780_PCICR_ARBM |*/ SH7780_PCICR_FTO;
outl(word, PCI_REG(SH7780_PCICR));
return 1;
}
char * __init pcibios_setup(char *str)
{
if (!strcmp(str, "off")) {
pci_probe = 0;
return NULL;
}
return str;
}
/*
* IRQ functions
*/
static u8 __init sh7780_no_swizzle(struct pci_dev *dev, u8 *pin)
{
/* no swizzling */
return PCI_SLOT(dev->devfn);
}
static int sh7780_pci_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq = -1;
/* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */
irq = pcibios_map_platform_irq(slot,pin);
if( irq < 0 ) {
pr_debug("PCI: Error mapping IRQ on device %s\n", pci_name(dev));
return irq;
}
pr_debug("Setting IRQ for slot %s to %d\n", pci_name(dev), irq);
return irq;
}
void __init pcibios_fixup_irqs(void)
{
pci_fixup_irqs(sh7780_no_swizzle, sh7780_pci_lookup_irq);
}
arch/sh/drivers/pci/pci-sh7780.h 0 → 100644
View file @ 5283ecb5
/*
* Low-Level PCI Support for SH7780 targets
*
* Dustin McIntire (dustin@sensoria.com) (c) 2001
* Paul Mundt (lethal@linux-sh.org) (c) 2003
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
*/
#ifndef _PCI_SH7780_H_
#define _PCI_SH7780_H_
#include <linux/pci.h>
/* set debug level 4=verbose...1=terse */
//#define DEBUG_PCI 3
#undef DEBUG_PCI
#ifdef DEBUG_PCI
#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
#else
#define PCIDBG(n, x...)
#endif
/* startup values */
#define PCI_PROBE_BIOS 1
#define PCI_PROBE_CONF1 2
#define PCI_PROBE_CONF2 4
#define PCI_NO_SORT 0x100
#define PCI_BIOS_SORT 0x200
#define PCI_NO_CHECKS 0x400
#define PCI_ASSIGN_ROMS 0x1000
#define PCI_BIOS_IRQ_SCAN 0x2000
/* Platform Specific Values */
#define SH7780_VENDOR_ID 0x1912
#define SH7780_DEVICE_ID 0x0002
#define SH7781_DEVICE_ID 0x0001
/* SH7780 Control Registers */
#define SH7780_PCI_VCR0 0xFE000000
#define SH7780_PCI_VCR1 0xFE000004
#define SH7780_PCI_VCR2 0xFE000008
/* SH7780 Specific Values */
#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
#define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
#define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
#if 1
#define SH7780_PCI_IO_BASE 0xFE400000 /* IO space base address */
#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */
#else
#define SH7780_PCI_IO_BASE 0xFE200000 /* IO space base address */
#define SH7780_PCI_IO_SIZE 0x00200000 /* Size of IO window */
#endif
#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
#define PCI_REG(n) (SH7780_PCIREG_BASE+n)
/* SH7780 PCI Config Registers */
#define SH7780_PCIVID 0x000 /* Vendor ID */
#define SH7780_PCIDID 0x002 /* Device ID */
#define SH7780_PCICMD 0x004 /* Command */
#define SH7780_PCISTATUS 0x006 /* Status */
#define SH7780_PCIRID 0x008 /* Revision ID */
#define SH7780_PCIPIF 0x009 /* Program Interface */
#define SH7780_PCISUB 0x00a /* Sub class code */
#define SH7780_PCIBCC 0x00b /* Base class code */
#define SH7780_PCICLS 0x00c /* Cache line size */
#define SH7780_PCILTM 0x00d /* latency timer */
#define SH7780_PCIHDR 0x00e /* Header type */
#define SH7780_PCIBIST 0x00f /* BIST */
#define SH7780_PCIIBAR 0x010 /* IO Base address */
#define SH7780_PCIMBAR0 0x014 /* Memory base address0 */
#define SH7780_PCIMBAR1 0x018 /* Memory base address1 */
#define SH7780_PCISVID 0x02c /* Sub system vendor ID */
#define SH7780_PCISID 0x02e /* Sub system ID */
#define SH7780_PCICP 0x034
#define SH7780_PCIINTLINE 0x03c /* Interrupt line */
#define SH7780_PCIINTPIN 0x03d /* Interrupt pin */
#define SH7780_PCIMINGNT 0x03e /* Minumum grand */
#define SH7780_PCIMAXLAT 0x03f /* Maxmum latency */
#define SH7780_PCICID 0x040
#define SH7780_PCINIP 0x041
#define SH7780_PCIPMC 0x042
#define SH7780_PCIPMCSR 0x044
#define SH7780_PCIPMCSR_BSE 0x046
#define SH7780_PCICDD 0x047
/* SH7780 PCI Local Registers */
#define SH7780_PCICR 0x100 /* PCI Control Register */
#define SH7780_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
#define SH7780_PCICR_PFCS 0x00000800 /* TRDY/IRDY Enable */
#define SH7780_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
#define SH7780_PCICR_PFE 0x00000200 /* Target Read Single */
#define SH7780_PCICR_TBS 0x00000100 /* Target Byte Swap */
#define SH7780_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
#define SH7780_PCICR_IOCS 0x00000004 /* INTA output assert */
#define SH7780_PCICR_PRST 0x00000002 /* PCI Reset Assert */
#define SH7780_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
#define SH7780_PCILSR0 0x104 /* PCI Local Space Register0 */
#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
#define SH7780_PCIAIR 0x11C /* Error Address Register */
#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
#define SH7780_PCIPINT 0x1CC /* Power Management Int. Register */
#define SH7780_PCIPINTM 0x1D0 /* Power Management Mask Register */
#define SH7780_PCIMBR0 0x1E0 /* Memory Bank0 Register */
#define SH7780_PCIMBMR0 0x1E4 /* Memory Bank0 Mask Register */
#define SH7780_PCIMBR1 0x1E8 /* Memory Bank1 Register */
#define SH7780_PCIMBMR1 0x1EC /* Memory Bank1 Mask Register */
#define SH7780_PCIMBR2 0x1F0 /* Memory Bank2 Register */
#define SH7780_PCIMBMR2 0x1F4 /* Memory Bank2 Mask Register */
#define SH7780_PCIIOBR 0x1F8 /* Bank Register */
#define SH7780_PCIIOBMR 0x1FC /* Bank Mask Register */
#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */
#define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */
#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */
#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */
#define SH7780_PCIPDR 0x220 /* Port IO Data Register */
/* General Memory Config Addresses */
#define SH7780_CS0_BASE_ADDR 0x0
#define SH7780_MEM_REGION_SIZE 0x04000000
#define SH7780_CS1_BASE_ADDR (SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS2_BASE_ADDR (SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS3_BASE_ADDR (SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS4_BASE_ADDR (SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
#define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)
/* General PCI values */
#define SH7780_PCI_HOST_BRIDGE 0x6
/* Flags */
#define SH7780_PCIC_NO_RESET 0x0001
/* External functions defined per platform i.e. Big Sur, SE... (these could be routed
* through the machine vectors... */
extern int pcibios_init_platform(void);
extern int pcibios_map_platform_irq(u8 slot, u8 pin);
struct sh7780_pci_address_space {
unsigned long base;
unsigned long size;
};
struct sh7780_pci_address_map {
struct sh7780_pci_address_space window0;
struct sh7780_pci_address_space window1;
unsigned long flags;
};
/* arch/sh/drivers/pci/pci-sh7780.c */
extern int sh7780_pcic_init(struct sh7780_pci_address_map *map);
#endif /* _PCI_SH7780_H_ */
arch/sh/kernel/cpu/irq/intc2.c
View file @ 5283ecb5
...@@ -241,9 +241,9 @@ static struct intc2_init { ...@@ -241,9 +241,9 @@ static struct intc2_init {
/* 110-111 reserved/unused */ /* 110-111 reserved/unused */
#elif defined(CONFIG_CPU_SUBTYPE_SH7780) #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
{ TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2}, { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},
#ifdef CONFIG_SH_RTC { 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
{ RTC_IRQ, 4, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY }, { 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
#endif { 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
{ SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY }, { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
{ SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY }, { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
{ SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY }, { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
......
arch/sh/tools/mach-types
View file @ 5283ecb5
...@@ -26,4 +26,6 @@ EDOSK7705 SH_EDOSK7705 ...@@ -26,4 +26,6 @@ EDOSK7705 SH_EDOSK7705
SH4202_MICRODEV SH_SH4202_MICRODEV SH4202_MICRODEV SH_SH4202_MICRODEV
SH03 SH_SH03 SH03 SH_SH03
LANDISK SH_LANDISK LANDISK SH_LANDISK
R7780RP SH_R7780RP
R7780MP SH_R7780MP
TITAN SH_TITAN TITAN SH_TITAN
include/asm-sh/cpu-sh4/addrspace.h
View file @ 5283ecb5
...@@ -22,5 +22,8 @@ ...@@ -22,5 +22,8 @@
#define P4SEG_TLB_DATA 0xf7000000 #define P4SEG_TLB_DATA 0xf7000000
#define P4SEG_REG_BASE 0xff000000 #define P4SEG_REG_BASE 0xff000000
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#endif /* __ASM_CPU_SH4_ADDRSPACE_H */ #endif /* __ASM_CPU_SH4_ADDRSPACE_H */
include/asm-sh/cpu-sh4/dma-sh7780.h 0 → 100644
View file @ 5283ecb5
#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
#define __ASM_SH_CPU_SH4_DMA_SH7780_H
#define REQ_HE 0x000000C0
#define REQ_H 0x00000080
#define REQ_LE 0x00000040
#define TM_BURST 0x0000020
#define TS_8 0x00000000
#define TS_16 0x00000008
#define TS_32 0x00000010
#define TS_16BLK 0x00000018
#define TS_32BLK 0x00100000
/*
* The SuperH DMAC supports a number of transmit sizes, we list them here,
* with their respective values as they appear in the CHCR registers.
*
* Defaults to a 64-bit transfer size.
*/
enum {
XMIT_SZ_8BIT,
XMIT_SZ_16BIT,
XMIT_SZ_32BIT,
XMIT_SZ_128BIT,
XMIT_SZ_256BIT,
};
/*
* The DMA count is defined as the number of bytes to transfer.
*/
static unsigned int __attribute__ ((used)) ts_shift[] = {
[XMIT_SZ_8BIT] = 0,
[XMIT_SZ_16BIT] = 1,
[XMIT_SZ_32BIT] = 2,
[XMIT_SZ_128BIT] = 4,
[XMIT_SZ_256BIT] = 5,
};
#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
include/asm-sh/cpu-sh4/dma.h
View file @ 5283ecb5
#ifndef __ASM_CPU_SH4_DMA_H #ifndef __ASM_CPU_SH4_DMA_H
#define __ASM_CPU_SH4_DMA_H #define __ASM_CPU_SH4_DMA_H
#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
#ifdef CONFIG_CPU_SH4A #ifdef CONFIG_CPU_SH4A
#define SH_DMAC_BASE 0xfc808020 #define SH_DMAC_BASE 0xfc808020
#define CHCR_TS_MASK 0x18
#define CHCR_TS_SHIFT 3
#include <asm/cpu/dma-sh7780.h>
#else #else
#define SH_DMAC_BASE 0xffa00000 #define SH_DMAC_BASE 0xffa00000
#endif
/* Definitions for the SuperH DMAC */ /* Definitions for the SuperH DMAC */
#define TM_BURST 0x0000080 #define TM_BURST 0x0000080
...@@ -19,8 +25,6 @@ ...@@ -19,8 +25,6 @@
#define DMAOR_COD 0x00000008 #define DMAOR_COD 0x00000008
#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
/* /*
* The SuperH DMAC supports a number of transmit sizes, we list them here, * The SuperH DMAC supports a number of transmit sizes, we list them here,
* with their respective values as they appear in the CHCR registers. * with their respective values as they appear in the CHCR registers.
...@@ -45,5 +49,6 @@ static unsigned int ts_shift[] __attribute__ ((used)) = { ...@@ -45,5 +49,6 @@ static unsigned int ts_shift[] __attribute__ ((used)) = {
[XMIT_SZ_32BIT] = 2, [XMIT_SZ_32BIT] = 2,
[XMIT_SZ_256BIT] = 5, [XMIT_SZ_256BIT] = 5,
}; };
#endif
#endif /* __ASM_CPU_SH4_DMA_H */ #endif /* __ASM_CPU_SH4_DMA_H */
include/asm-sh/hs7751rvoip/hs7751rvoip.h
View file @ 5283ecb5
...@@ -19,8 +19,6 @@ ...@@ -19,8 +19,6 @@
#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */ #define PA_OUTPORTR 0xa400000e /* Output Port Reguster */
#define PA_VERREG 0xa4000014 /* FPGA Version Register */ #define PA_VERREG 0xa4000014 /* FPGA Version Register */
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ #define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
......
include/asm-sh/irq-sh7780.h
View file @ 5283ecb5
...@@ -145,11 +145,6 @@ ...@@ -145,11 +145,6 @@
#define TMU_CH5_IPR_POS 1 #define TMU_CH5_IPR_POS 1
#define TMU_CH5_PRIORITY 2 #define TMU_CH5_PRIORITY 2
#define RTC_IRQ 22
#define RTC_IPR_ADDR INTC_INT2PRI1
#define RTC_IPR_POS 0
#define RTC_PRIORITY TIMER_PRIORITY
/* SCIF0 */ /* SCIF0 */
#define SCIF0_ERI_IRQ 40 #define SCIF0_ERI_IRQ 40
#define SCIF0_RXI_IRQ 41 #define SCIF0_RXI_IRQ 41
......
include/asm-sh/irq.h
View file @ 5283ecb5
...@@ -577,7 +577,7 @@ extern int ipr_irq_demux(int irq); ...@@ -577,7 +577,7 @@ extern int ipr_irq_demux(int irq);
#define NR_INTC2_IRQS 64 #define NR_INTC2_IRQS 64
#elif defined(CONFIG_CPU_SUBTYPE_SH7780) #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
#define INTC2_BASE 0xffd40000 #define INTC2_BASE 0xffd40000
#define INTC2_FIRST_IRQ 22 #define INTC2_FIRST_IRQ 21
#define INTC2_INTMSK_OFFSET (0x38) #define INTC2_INTMSK_OFFSET (0x38)
#define INTC2_INTMSKCLR_OFFSET (0x3c) #define INTC2_INTMSKCLR_OFFSET (0x3c)
#define NR_INTC2_IRQS 60 #define NR_INTC2_IRQS 60
......
include/asm-sh/landisk/iodata_landisk.h
View file @ 5283ecb5
...@@ -22,8 +22,6 @@ ...@@ -22,8 +22,6 @@
/* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */ /* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */
#define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */ #define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#define PA_LCD_CLRDSP 0x00 /* LCD Clear Display Offset */ #define PA_LCD_CLRDSP 0x00 /* LCD Clear Display Offset */
#define PA_LCD_RTNHOME 0x00 /* LCD Return Home Offset */ #define PA_LCD_RTNHOME 0x00 /* LCD Return Home Offset */
#define PA_LCD_ENTMODE 0x00 /* LCD Entry Mode Offset */ #define PA_LCD_ENTMODE 0x00 /* LCD Entry Mode Offset */
......
include/asm-sh/r7780rp/ide.h 0 → 100644
View file @ 5283ecb5
#ifndef __ASM_SH_R7780RP_IDE_H
#define __ASM_SH_R7780RP_IDE_H
/* Nothing to see here.. */
#include <asm/mach/r7780rp.h>
#endif /* __ASM_SH_R7780RP_IDE_H */
include/asm-sh/r7780rp/r7780rp.h 0 → 100644
View file @ 5283ecb5
#ifndef __ASM_SH_RENESAS_R7780RP_H
#define __ASM_SH_RENESAS_R7780RP_H
/*
* linux/include/asm-sh/r7780rp.h
*
* Copyright (C) 2000 Atom Create Engineering Co., Ltd.
*
* Renesas Solutions Highlander R7780RP support
*/
/* Box specific addresses. */
#if defined(CONFIG_SH_R7780MP)
#define PA_BCR 0xa4000000 /* FPGA */
#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
#define PA_ICCR (PA_BCR+0x0600) /* Serial control */
#define PA_SAR (PA_BCR+0x0602) /* Serial Slave control */
#define PA_MDR (PA_BCR+0x0604) /* Serial Mode control */
#define PA_ADR1 (PA_BCR+0x0606) /* Serial Address1 control */
#define PA_DAR1 (PA_BCR+0x0646) /* Serial Data1 control */
#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
#define PA_PMR (PA_BCR+0x0900) /* */
#define PA_AX88796L 0xa4100400 /* AX88796L Area */
#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
#define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */
#define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */
#define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */
#define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */
#define IRQ_CFCARD 1 /* CF Card IRQ */
// #define IRQ_CFINST 0 /* CF Card Insert IRQ */
#define IRQ_TP 2 /* Touch Panel IRQ */
#define IRQ_SCI1 3 /* SCI1 IRQ */
#define IRQ_SCI0 4 /* SCI0 IRQ */
#define IRQ_2SERIAL 5 /* Serial IRQ */
#define IRQ_RTC 6 /* RTC A / B IRQ */
#define IRQ_EXTENTION6 7 /* EXT6n IRQ */
#define IRQ_EXTENTION5 8 /* EXT5n IRQ */
#define IRQ_EXTENTION4 9 /* EXT4n IRQ */
#define IRQ_EXTENTION2 10 /* EXT2n IRQ */
#define IRQ_EXTENTION1 11 /* EXT1n IRQ */
#define IRQ_ONETH 13 /* On board Ethernet IRQ */
#define IRQ_PSW 14 /* Push Switch IRQ */
#else /* R7780RP */
#define PA_BCR 0xa5000000 /* FPGA */
#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
#define PA_ICCR (PA_BCR+0x0500) /* Serial control */
#define PA_SAR (PA_BCR+0x0502) /* Serial Slave control */
#define PA_MDR (PA_BCR+0x0504) /* Serial Mode control */
#define PA_ADR1 (PA_BCR+0x0506) /* Serial Address1 control */
#define PA_DAR1 (PA_BCR+0x0546) /* Serial Data1 control */
#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
#define PA_AX88796L 0xa5800400 /* AX88796L Area */
#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
#define IRQ_PCISLOT1 0 /* PCI Slot #1 IRQ */
#define IRQ_PCISLOT2 1 /* PCI Slot #2 IRQ */
#define IRQ_PCISLOT3 2 /* PCI Slot #3 IRQ */
#define IRQ_PCISLOT4 3 /* PCI Slot #4 IRQ */
#define IRQ_CFCARD 4 /* CF Card IRQ */
#define IRQ_CFINST 5 /* CF Card Insert IRQ */
#define IRQ_M66596 6 /* M66596 IRQ */
#define IRQ_SDCARD 7 /* SD Card IRQ */
#define IRQ_TUCHPANEL 8 /* Touch Panel IRQ */
#define IRQ_SCI 9 /* SCI IRQ */
#define IRQ_2SERIAL 10 /* Serial IRQ */
#define IRQ_EXTENTION 11 /* EXTn IRQ */
#define IRQ_ONETH 12 /* On board Ethernet IRQ */
#define IRQ_PSW 13 /* Push Switch IRQ */
#define IRQ_ZIGBEE 14 /* Ziggbee IO IRQ */
#endif /* CONFIG_SH_R7780MP */
#define __IO_PREFIX r7780rp
#include <asm/io_generic.h>
#endif /* __ASM_SH_RENESAS_R7780RP */
include/asm-sh/rts7751r2d/rts7751r2d.h
View file @ 5283ecb5
...@@ -41,8 +41,6 @@ ...@@ -41,8 +41,6 @@
#define PA_AX88796L 0xaa000400 /* AX88796L Area */ #define PA_AX88796L 0xaa000400 /* AX88796L Area */
#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */ #define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ #define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ #define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
......
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