Commit 54e4ff4d authored by Sonic Zhang's avatar Sonic Zhang Committed by Steven Miao

blackfin: adi gpio driver and pinctrl driver support

Remove gpio driver for new gpio controller on BF54x and BF60x.
Build the bfin_gpio driver only when other BF5xx processors are selected.
Replace the prefix of some gpio and peripheral functions with adi.
add portmux platform data in machine portmux.h
Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarSteven Miao <realmz6@gmail.com>
parent 036c5df1
......@@ -317,6 +317,14 @@ config BF53x
depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
default y
config GPIO_ADI
def_bool y
depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
config PINCTRL
def_bool y
depends on BF54x || BF60x
config MEM_MT48LC64M4A2FB_7E
bool
depends on (BFIN533_STAMP)
......
......@@ -25,8 +25,12 @@
#ifndef __ASSEMBLY__
#ifndef CONFIG_PINCTRL
#include <linux/compiler.h>
#include <linux/gpio.h>
#include <asm/blackfin.h>
#include <asm/portmux.h>
#include <asm/irq_handler.h>
/***********************************************************
*
......@@ -45,7 +49,6 @@
* MODIFICATION HISTORY :
**************************************************************/
#if !BFIN_GPIO_PINT
void set_gpio_dir(unsigned, unsigned short);
void set_gpio_inen(unsigned, unsigned short);
void set_gpio_polar(unsigned, unsigned short);
......@@ -115,7 +118,6 @@ struct gpio_port_t {
unsigned short dummy16;
unsigned short inen;
};
#endif
#ifdef BFIN_SPECIAL_GPIO_BANKS
void bfin_special_gpio_free(unsigned gpio);
......@@ -127,25 +129,21 @@ void bfin_special_gpio_pm_hibernate_suspend(void);
#endif
#ifdef CONFIG_PM
int bfin_pm_standby_ctrl(unsigned ctrl);
void bfin_gpio_pm_hibernate_restore(void);
void bfin_gpio_pm_hibernate_suspend(void);
int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
int bfin_gpio_pm_standby_ctrl(unsigned ctrl);
static inline int bfin_pm_standby_setup(void)
{
return bfin_pm_standby_ctrl(1);
return bfin_gpio_pm_standby_ctrl(1);
}
static inline void bfin_pm_standby_restore(void)
{
bfin_pm_standby_ctrl(0);
bfin_gpio_pm_standby_ctrl(0);
}
void bfin_gpio_pm_hibernate_restore(void);
void bfin_gpio_pm_hibernate_suspend(void);
void bfin_pint_suspend(void);
void bfin_pint_resume(void);
# if !BFIN_GPIO_PINT
int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
struct gpio_port_s {
unsigned short data;
......@@ -161,7 +159,6 @@ struct gpio_port_s {
unsigned short reserved;
unsigned short mux;
};
# endif
#endif /*CONFIG_PM*/
/***********************************************************
......@@ -178,35 +175,28 @@ struct gpio_port_s {
*************************************************************
* MODIFICATION HISTORY :
**************************************************************/
int bfin_gpio_request(unsigned gpio, const char *label);
void bfin_gpio_free(unsigned gpio);
int bfin_gpio_irq_request(unsigned gpio, const char *label);
void bfin_gpio_irq_free(unsigned gpio);
int bfin_gpio_direction_input(unsigned gpio);
int bfin_gpio_direction_output(unsigned gpio, int value);
int bfin_gpio_get_value(unsigned gpio);
void bfin_gpio_set_value(unsigned gpio, int value);
void bfin_gpio_irq_prepare(unsigned gpio);
static inline int irq_to_gpio(unsigned irq)
{
return irq - GPIO_IRQ_BASE;
}
#endif /* CONFIG_PINCTRL */
#include <asm/irq.h>
#include <asm/errno.h>
#ifdef CONFIG_GPIOLIB
#include <asm-generic/gpio.h> /* cansleep wrappers */
static inline int gpio_get_value(unsigned int gpio)
{
if (gpio < MAX_BLACKFIN_GPIOS)
return bfin_gpio_get_value(gpio);
else
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned int gpio, int value)
{
if (gpio < MAX_BLACKFIN_GPIOS)
bfin_gpio_set_value(gpio, value);
else
__gpio_set_value(gpio, value);
}
......@@ -219,113 +209,6 @@ static inline int gpio_to_irq(unsigned gpio)
{
return __gpio_to_irq(gpio);
}
#else /* !CONFIG_GPIOLIB */
static inline int gpio_request(unsigned gpio, const char *label)
{
return bfin_gpio_request(gpio, label);
}
static inline void gpio_free(unsigned gpio)
{
return bfin_gpio_free(gpio);
}
static inline int gpio_direction_input(unsigned gpio)
{
return bfin_gpio_direction_input(gpio);
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
return bfin_gpio_direction_output(gpio, value);
}
static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
{
return -EINVAL;
}
static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
{
int err;
err = bfin_gpio_request(gpio, label);
if (err)
return err;
if (flags & GPIOF_DIR_IN)
err = bfin_gpio_direction_input(gpio);
else
err = bfin_gpio_direction_output(gpio,
(flags & GPIOF_INIT_HIGH) ? 1 : 0);
if (err)
bfin_gpio_free(gpio);
return err;
}
static inline int gpio_request_array(const struct gpio *array, size_t num)
{
int i, err;
for (i = 0; i < num; i++, array++) {
err = gpio_request_one(array->gpio, array->flags, array->label);
if (err)
goto err_free;
}
return 0;
err_free:
while (i--)
bfin_gpio_free((--array)->gpio);
return err;
}
static inline void gpio_free_array(const struct gpio *array, size_t num)
{
while (num--)
bfin_gpio_free((array++)->gpio);
}
static inline int __gpio_get_value(unsigned gpio)
{
return bfin_gpio_get_value(gpio);
}
static inline void __gpio_set_value(unsigned gpio, int value)
{
return bfin_gpio_set_value(gpio, value);
}
static inline int gpio_get_value(unsigned gpio)
{
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
return __gpio_set_value(gpio, value);
}
static inline int gpio_to_irq(unsigned gpio)
{
if (likely(gpio < MAX_BLACKFIN_GPIOS))
return gpio + GPIO_IRQ_BASE;
return -EINVAL;
}
#include <asm-generic/gpio.h> /* cansleep wrappers */
#endif /* !CONFIG_GPIOLIB */
static inline int irq_to_gpio(unsigned irq)
{
return (irq - GPIO_IRQ_BASE);
}
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_BLACKFIN_GPIO_H__ */
......@@ -23,8 +23,7 @@
/*
* pm save bfin pint registers
*/
struct bfin_pm_pint_save {
u32 mask_set;
struct adi_pm_pint_save {
u32 assign;
u32 edge_set;
u32 invert_set;
......
......@@ -12,11 +12,11 @@
#include <mach/irq.h>
/* init functions only */
extern int __init init_arch_irq(void);
extern int init_arch_irq(void);
extern void init_exception_vectors(void);
extern void __init program_IAR(void);
extern void program_IAR(void);
#ifdef init_mach_irq
extern void __init init_mach_irq(void);
extern void init_mach_irq(void);
#else
# define init_mach_irq()
#endif
......
......@@ -17,14 +17,29 @@
#define P_MAYSHARE 0x2000
#define P_DONTCARE 0x1000
#ifdef CONFIG_PINCTRL
#include <asm/irq_handler.h>
#define gpio_pint_regs bfin_pint_regs
#define adi_internal_set_wake bfin_internal_set_wake
#define peripheral_request(per, label) 0
#define peripheral_free(per)
#define peripheral_request_list(per, label) \
(pdev ? (IS_ERR(devm_pinctrl_get_select_default(&pdev->dev)) \
? -EINVAL : 0) : 0)
#define peripheral_free_list(per)
#else
int peripheral_request(unsigned short per, const char *label);
void peripheral_free(unsigned short per);
int peripheral_request_list(const unsigned short per[], const char *label);
void peripheral_free_list(const unsigned short per[]);
#endif
#include <asm/gpio.h>
#include <linux/err.h>
#include <linux/pinctrl/pinctrl.h>
#include <mach/portmux.h>
#include <linux/gpio.h>
#ifndef P_SPORT2_TFS
#define P_SPORT2_TFS P_UNDEF
......
......@@ -7,7 +7,7 @@ extra-y := vmlinux.lds
obj-y := \
entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
fixed_code.o reboot.o bfin_gpio.o bfin_dma.o \
fixed_code.o reboot.o bfin_dma.o \
exception.o dumpstack.o
ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
......@@ -16,6 +16,7 @@ else
obj-y += time.o
endif
obj-$(CONFIG_GPIO_ADI) += bfin_gpio.o
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
......
......@@ -11,11 +11,8 @@
#include <linux/err.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <asm/irq_handler.h>
#if ANOMALY_05000311 || ANOMALY_05000323
enum {
......@@ -58,19 +55,6 @@ static struct gpio_port_t * const gpio_array[] = {
(struct gpio_port_t *) FIO0_FLAG_D,
(struct gpio_port_t *) FIO1_FLAG_D,
(struct gpio_port_t *) FIO2_FLAG_D,
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
(struct gpio_port_t *)PORTA_FER,
(struct gpio_port_t *)PORTB_FER,
(struct gpio_port_t *)PORTC_FER,
(struct gpio_port_t *)PORTD_FER,
(struct gpio_port_t *)PORTE_FER,
(struct gpio_port_t *)PORTF_FER,
(struct gpio_port_t *)PORTG_FER,
# if defined(CONFIG_BF54x)
(struct gpio_port_t *)PORTH_FER,
(struct gpio_port_t *)PORTI_FER,
(struct gpio_port_t *)PORTJ_FER,
# endif
#else
# error no gpio arrays defined
#endif
......@@ -169,12 +153,6 @@ DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
inline int check_gpio(unsigned gpio)
{
#if defined(CONFIG_BF54x)
if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
|| gpio == GPIO_PH14 || gpio == GPIO_PH15
|| gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
return -EINVAL;
#endif
if (gpio >= MAX_BLACKFIN_GPIOS)
return -EINVAL;
return 0;
......@@ -212,12 +190,6 @@ static void port_setup(unsigned gpio, unsigned short usage)
else
*port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
SSYNC();
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
if (usage == GPIO_USAGE)
gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
else
gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
SSYNC();
#endif
}
......@@ -306,31 +278,6 @@ static void portmux_setup(unsigned short per)
bfin_write_PORT_MUX(pmux);
}
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
inline void portmux_setup(unsigned short per)
{
u16 ident = P_IDENT(per);
u16 function = P_FUNCT2MUX(per);
u32 pmux;
pmux = gpio_array[gpio_bank(ident)]->port_mux;
pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
gpio_array[gpio_bank(ident)]->port_mux = pmux;
}
inline u16 get_portmux(unsigned short per)
{
u16 ident = P_IDENT(per);
u32 pmux = gpio_array[gpio_bank(ident)]->port_mux;
return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
}
static int portmux_group_check(unsigned short per)
{
return 0;
}
#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
static int portmux_group_check(unsigned short per)
{
......@@ -384,7 +331,6 @@ static int portmux_group_check(unsigned short per)
}
#endif
#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
/***********************************************************
*
* FUNCTIONS: Blackfin General Purpose Ports Access Functions
......@@ -577,7 +523,7 @@ static const unsigned int sic_iwr_irqs[] = {
*************************************************************
* MODIFICATION HISTORY :
**************************************************************/
int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
{
unsigned long flags;
......@@ -596,7 +542,7 @@ int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
return 0;
}
int bfin_pm_standby_ctrl(unsigned ctrl)
int bfin_gpio_pm_standby_ctrl(unsigned ctrl)
{
u16 bank, mask, i;
......@@ -687,53 +633,6 @@ void bfin_gpio_pm_hibernate_restore(void)
#endif
#else /* CONFIG_BF54x || CONFIG_BF60x */
#ifdef CONFIG_PM
int bfin_pm_standby_ctrl(unsigned ctrl)
{
return 0;
}
void bfin_gpio_pm_hibernate_suspend(void)
{
int i, bank;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
bank = gpio_bank(i);
gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
gpio_bank_saved[bank].data = gpio_array[bank]->data;
gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set;
}
}
void bfin_gpio_pm_hibernate_restore(void)
{
int i, bank;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
bank = gpio_bank(i);
gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
gpio_array[bank]->data_set = gpio_bank_saved[bank].data
& gpio_bank_saved[bank].dir;
gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
}
}
#endif
unsigned short get_gpio_dir(unsigned gpio)
{
return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
}
EXPORT_SYMBOL(get_gpio_dir);
#endif /* CONFIG_BF54x || CONFIG_BF60x */
/***********************************************************
*
......@@ -790,11 +689,7 @@ int peripheral_request(unsigned short per, const char *label)
* be requested and used by several drivers
*/
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
#else
if (!(per & P_MAYSHARE)) {
#endif
/*
* Allow that the identical pin function can
* be requested from the same driver twice
......@@ -943,12 +838,9 @@ int bfin_gpio_request(unsigned gpio, const char *label)
if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
" (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
}
#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
else { /* Reset POLAR setting when acquiring a gpio for the first time */
} else { /* Reset POLAR setting when acquiring a gpio for the first time */
set_gpio_polar(gpio, 0);
}
#endif
reserve(gpio, gpio);
set_label(gpio, label);
......@@ -1117,11 +1009,7 @@ void bfin_gpio_irq_free(unsigned gpio)
static inline void __bfin_gpio_direction_input(unsigned gpio)
{
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
#endif
gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
}
......@@ -1145,17 +1033,7 @@ EXPORT_SYMBOL(bfin_gpio_direction_input);
void bfin_gpio_irq_prepare(unsigned gpio)
{
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
unsigned long flags;
#endif
port_setup(gpio, GPIO_USAGE);
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
flags = hard_local_irq_save();
__bfin_gpio_direction_input(gpio);
hard_local_irq_restore(flags);
#endif
}
void bfin_gpio_set_value(unsigned gpio, int arg)
......@@ -1180,11 +1058,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
gpio_set_value(gpio, value);
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
#endif
AWA_DUMMY_READ(dir);
hard_local_irq_restore(flags);
......@@ -1195,9 +1069,6 @@ EXPORT_SYMBOL(bfin_gpio_direction_output);
int bfin_gpio_get_value(unsigned gpio)
{
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
#else
unsigned long flags;
if (unlikely(get_gpio_edge(gpio))) {
......@@ -1210,7 +1081,6 @@ int bfin_gpio_get_value(unsigned gpio)
return ret;
} else
return get_gpio_data(gpio);
#endif
}
EXPORT_SYMBOL(bfin_gpio_get_value);
......
......@@ -377,40 +377,6 @@ config IRQ_PINT3
endmenu
comment "Pin Interrupt to Port Assignment"
menu "Assignment"
config PINTx_REASSIGN
bool "Reprogram PINT Assignment"
default y
help
The interrupt assignment registers controls the pin-to-interrupt
assignment in a byte-wide manner. Each option allows you to select
a set of pins (High/Low Byte) of an specific Port being mapped
to one of the four PIN Interrupts IRQ_PINTx.
You shouldn't change any of these unless you know exactly what you're doing.
Please consult the Blackfin BF54x Processor Hardware Reference Manual.
config PINT0_ASSIGN
hex "PINT0_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT1_ASSIGN
hex "PINT1_ASSIGN"
depends on PINTx_REASSIGN
default 0x01010000
config PINT2_ASSIGN
hex "PINT2_ASSIGN"
depends on PINTx_REASSIGN
default 0x07000101
config PINT3_ASSIGN
hex "PINT3_ASSIGN"
depends on PINTx_REASSIGN
default 0x02020303
endmenu
endmenu
endif
This diff is collapsed.
......@@ -194,14 +194,6 @@ struct gpio_port_t {
unsigned int port_mux;
};
struct gpio_port_s {
unsigned short fer;
unsigned short data;
unsigned short dir;
unsigned short inen;
unsigned int mux;
};
#endif
#include <mach-common/ports-a.h>
......
......@@ -433,7 +433,7 @@
#include <linux/types.h>
/*
* bfin pint registers layout
* gpio pint registers layout
*/
struct bfin_pint_regs {
u32 mask_set;
......
......@@ -7,8 +7,6 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
......
......@@ -9,48 +9,6 @@ source "arch/blackfin/mach-bf609/boards/Kconfig"
menu "BF609 Specific Configuration"
comment "Pin Interrupt to Port Assignment"
menu "Assignment"
config PINTx_REASSIGN
bool "Reprogram PINT Assignment"
default y
help
The interrupt assignment registers controls the pin-to-interrupt
assignment in a byte-wide manner. Each option allows you to select
a set of pins (High/Low Byte) of an specific Port being mapped
to one of the four PIN Interrupts IRQ_PINTx.
You shouldn't change any of these unless you know exactly what you're doing.
Please consult the Blackfin BF60x Processor Hardware Reference Manual.
config PINT0_ASSIGN
hex "PINT0_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT1_ASSIGN
hex "PINT1_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT2_ASSIGN
hex "PINT2_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT3_ASSIGN
hex "PINT3_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT4_ASSIGN
hex "PINT3_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT5_ASSIGN
hex "PINT3_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
endmenu
config SEC_IRQ_PRIORITY_LEVELS
int "SEC interrupt priority levels"
default 7
......
This diff is collapsed.
......@@ -152,14 +152,6 @@ struct gpio_port_t {
unsigned long revid;
};
struct gpio_port_s {
unsigned short fer;
unsigned short data;
unsigned short dir;
unsigned short inen;
unsigned int mux;
};
#endif
#include <mach-common/ports-a.h>
......
......@@ -298,7 +298,7 @@
extern u8 sec_int_priority[];
/*
* bfin pint registers layout
* gpio pint registers layout
*/
struct bfin_pint_regs {
u32 mask_set;
......
......@@ -7,8 +7,6 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
/* EMAC RMII Port Mux */
#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
......@@ -21,6 +19,7 @@
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
#define P_RMII0 {\
P_MII0_ETxD0, \
......@@ -32,6 +31,7 @@
P_MII0_TxCLK, \
P_MII0_PHYINT, \
P_MII0_CRS, \
P_MII0_PTPPPS, \
P_MII0_MDC, \
P_MII0_MDIO, 0}
......@@ -46,6 +46,7 @@
#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
#define P_RMII1 {\
P_MII1_ETxD0, \
......@@ -57,6 +58,7 @@
P_MII1_TxCLK, \
P_MII1_PHYINT, \
P_MII1_CRS, \
P_MII1_PTPPPS, \
P_MII1_MDC, \
P_MII1_MDIO, 0}
......
This diff is collapsed.
......@@ -27,7 +27,7 @@ struct bfin_cpu_pm_fns *bfin_cpu_pm;
void bfin_pm_suspend_standby_enter(void)
{
#ifndef CONFIG_BF60x
#if !BFIN_GPIO_PINT
bfin_pm_standby_setup();
#endif
......@@ -41,7 +41,7 @@ void bfin_pm_suspend_standby_enter(void)
# endif
#endif
#ifndef CONFIG_BF60x
#if !BFIN_GPIO_PINT
bfin_pm_standby_restore();
#endif
......@@ -128,6 +128,7 @@ static void flushinv_all_dcache(void)
if ((status & 0x3) != 0x3)
continue;
/* construct the address using the tag */
addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
......@@ -170,10 +171,8 @@ int bfin_pm_suspend_mem_enter(void)
return ret;
}
#ifdef CONFIG_GPIO_ADI
bfin_gpio_pm_hibernate_suspend();
#if BFIN_GPIO_PINT
bfin_pint_suspend();
#endif
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
......@@ -194,11 +193,9 @@ int bfin_pm_suspend_mem_enter(void)
_enable_icplb();
_enable_dcplb();
#if BFIN_GPIO_PINT
bfin_pint_resume();
#endif
#ifdef CONFIG_GPIO_ADI
bfin_gpio_pm_hibernate_restore();
#endif
blackfin_dma_resume();
kfree(memptr);
......
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