Commit 54f4d1d7 authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Deepak Saxena

[ARM PATCH] 1209/1: PXA250/210 register definition update

parent 2d33b87d
...@@ -262,6 +262,7 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -262,6 +262,7 @@ typedef void (*ExcpHndlr) (void) ;
/* default combinations */ /* default combinations */
#define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4) #define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
...@@ -361,7 +362,7 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -361,7 +362,7 @@ typedef void (*ExcpHndlr) (void) ;
#define LSR_OE (1 << 1) /* Overrun Error */ #define LSR_OE (1 << 1) /* Overrun Error */
#define LSR_DR (1 << 0) /* Data Ready */ #define LSR_DR (1 << 0) /* Data Ready */
#define MCR_LOOP (1 << 4) #define MCR_LOOP (1 << 4) */
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
#define MCR_RTS (1 << 1) /* Request to Send */ #define MCR_RTS (1 << 1) /* Request to Send */
...@@ -376,6 +377,35 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -376,6 +377,35 @@ typedef void (*ExcpHndlr) (void) ;
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
/*
* IrSR (Infrared Selection Register)
*/
#define IrSR_OFFSET 0x20
#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
#define IrSR_RXPL_POS_IS_ZERO 0x0
#define IrSR_TXPL_NEG_IS_ZERO (1<<3)
#define IrSR_TXPL_POS_IS_ZERO 0x0
#define IrSR_XMODE_PULSE_1_6 (1<<2)
#define IrSR_XMODE_PULSE_3_16 0x0
#define IrSR_RCVEIR_IR_MODE (1<<1)
#define IrSR_RCVEIR_UART_MODE 0x0
#define IrSR_XMITIR_IR_MODE (1<<0)
#define IrSR_XMITIR_UART_MODE 0x0
#define IrSR_IR_RECEIVE_ON (\
IrSR_RXPL_NEG_IS_ZERO | \
IrSR_TXPL_POS_IS_ZERO | \
IrSR_XMODE_PULSE_3_16 | \
IrSR_RCVEIR_IR_MODE | \
IrSR_XMITIR_UART_MODE)
#define IrSR_IR_TRANSMIT_ON (\
IrSR_RXPL_NEG_IS_ZERO | \
IrSR_TXPL_POS_IS_ZERO | \
IrSR_XMODE_PULSE_3_16 | \
IrSR_RCVEIR_UART_MODE | \
IrSR_XMITIR_IR_MODE)
/* /*
* I2C registers * I2C registers
...@@ -387,6 +417,37 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -387,6 +417,37 @@ typedef void (*ExcpHndlr) (void) ;
#define ISR __REG(0x40301698) /* I2C Status Register - ISR */ #define ISR __REG(0x40301698) /* I2C Status Register - ISR */
#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
/* ----- Control register bits ---------------------------------------- */
#define ICR_START 0x1 /* start bit */
#define ICR_STOP 0x2 /* stop bit */
#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
#define ICR_TB 0x8 /* transfer byte bit */
#define ICR_MA 0x10 /* master abort */
#define ICR_SCLE 0x20 /* master clock enable */
#define ICR_IUE 0x40 /* unit enable */
#define ICR_GCD 0x80 /* general call disable */
#define ICR_ITEIE 0x100 /* enable tx interrupts */
#define ICR_IRFIE 0x200 /* enable rx interrupts */
#define ICR_BEIE 0x400 /* enable bus error ints */
#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
#define ICR_SADIE 0x2000 /* slave address detected int enable */
#define ICR_UR 0x4000 /* unit reset */
/* ----- Status register bits ----------------------------------------- */
#define ISR_RWM 0x1 /* read/write mode */
#define ISR_ACKNAK 0x2 /* ack/nak status */
#define ISR_UB 0x4 /* unit busy */
#define ISR_IBB 0x8 /* bus busy */
#define ISR_SSD 0x10 /* slave stop detected */
#define ISR_ALD 0x20 /* arbitration loss detected */
#define ISR_ITE 0x40 /* tx buffer empty */
#define ISR_IRF 0x80 /* rx buffer full */
#define ISR_GCAD 0x100 /* general call address detected */
#define ISR_SAD 0x200 /* slave address detected */
#define ISR_BED 0x400 /* bus error no ACK/NAK */
/* /*
* Serial Audio Controller * Serial Audio Controller
...@@ -486,24 +547,92 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -486,24 +547,92 @@ typedef void (*ExcpHndlr) (void) ;
/* /*
* USB Device Controller * USB Device Controller
*/ */
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
#define UDCCR __REG(0x40600000) /* UDC Control Register */ #define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
#define UDCCS0_SST (1 << 4) /* Sent stall */
#define UDCCS0_FST (1 << 5) /* Force stall */
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
#define UDCCS0_SA (1 << 7) /* Setup active */
/* Bulk IN - Endpoint 1,6,11 */
#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
#define UDCCS_BI_FST (1 << 5) /* Force stall */
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
/* Bulk OUT - Endpoint 2,7,12 */
#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
#define UDCCS_BO_FST (1 << 5) /* Force stall */
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
/* Isochronous IN - Endpoint 3,8,13 */
#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
/* Isochronous OUT - Endpoint 4,9,14 */
#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
/* Interrupt IN - Endpoint 5,10,15 */
#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
...@@ -528,11 +657,51 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -528,11 +657,51 @@ typedef void (*ExcpHndlr) (void) ;
#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
/* /*
* Fast Infrared Communication Port * Fast Infrared Communication Port
...@@ -879,6 +1048,22 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -879,6 +1048,22 @@ typedef void (*ExcpHndlr) (void) ;
#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
#define PSSR_RDH (1 << 5) /* Read Disable Hold */
#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
#define PSSR_VFS (1 << 2) /* VDD Fault Status */
#define PSSR_BFS (1 << 1) /* Battery Fault Status */
#define PSSR_SSS (1 << 0) /* Software Sleep Status */
#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
#define RCSR_GPR (1 << 3) /* GPIO Reset */
#define RCSR_SMR (1 << 2) /* Sleep Mode */
#define RCSR_WDR (1 << 1) /* Watchdog Reset */
#define RCSR_HWR (1 << 0) /* Hardware Reset */
/* /*
* SSP Serial Port Registers * SSP Serial Port Registers
...@@ -1035,3 +1220,19 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -1035,3 +1220,19 @@ typedef void (*ExcpHndlr) (void) ;
#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
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