/* MTU + ethernet header + FCS + optional VLAN tag */
lp->rx_buff_len=mtu+ETH_HLEN+8;
lp->options|=OPTION_JUMBO_ENABLE;
}else{
lp->rx_buff_len=PKT_BUFF_SZ;
lp->options&=~OPTION_JUMBO_ENABLE;
}
}
/*
This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
This function will check the ownership of receive buffers and descriptors. It will indicate to kernel up to half the number of maximum receive buffers in the descriptor ring, in a single receive interrupt. It will also replenish the descriptors with new skbs.
*/
staticintamd8111e_rx(structnet_device*dev)
{
structamd8111e_priv*lp=dev->priv;
structsk_buff*skb,*new_skb;
intrx_index=lp->rx_idx&RX_RING_DR_MOD_MASK;
intmin_pkt_len,status;
intnum_rx_pkt=0;
intmax_rx_pkt=NUM_RX_BUFFERS/2;
shortpkt_len;
#if AMD8111E_VLAN_TAG_USED
shortvtag;
#endif
/* If we own the next entry, it's a new packet. Send it up. */
This function will store the original speed to restore later, if autoneg is turned on. This speed will be set later when the autoneg is turned off. If the link status indicates that link is down, that will be indicated to the kernel */
/* Process all the INT event until INTR bit is clear. */
if(!(intr0&INTR))
gotoerr_no_interrupt;
/* Current driver processes 3 interrupts : RINT,TINT,LCINT */
writel(intr0,mmio+INT0);
/* Check if Receive Interrupt has occurred. */
if(intr0&RINT0){
amd8111e_rx(dev);
writel(VAL2|RDMD0,mmio+CMD0);
}
/* Check if Transmit Interrupt has occurred. */
if(intr0&TINT0)
amd8111e_tx(dev);
/* Check if Link Change Interrupt has occurred. */
if(intr0&LCINT)
amd8111e_link_change(dev);
err_no_interrupt:
writel(VAL0|INTREN,mmio+CMD0);
spin_unlock(&lp->lock);
return;
}
/*
This function closes the network interface and copies the new set of statistics into the previous statistics structure so that most recent statistics will be available after the interface is down.
This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA
Module Name:
amd8111e.h
Abstract:
AMD8111 based 10/100 Ethernet Controller driver definitions.
Environment:
Kernel Mode
Revision History:
*/
#ifndef _AMD811E_H
#define _AMD811E_H
/* Hardware definitions */
#define B31_MASK 0x80000000
#define B30_MASK 0X40000000
#define B29_MASK 0x20000000
#define B28_MASK 0x10000000
#define B27_MASK 0x08000000
#define B26_MASK 0x04000000
#define B25_MASK 0x02000000
#define B24_MASK 0x01000000
#define B23_MASK 0x00800000
#define B22_MASK 0x00400000
#define B21_MASK 0x00200000
#define B20_MASK 0x00100000
#define B19_MASK 0x00080000
#define B18_MASK 0x00040000
#define B17_MASK 0x00020000
#define B16_MASK 0x00010000
#define B15_MASK 0x8000
#define B14_MASK 0x4000
#define B13_MASK 0x2000
#define B12_MASK 0x1000
#define B11_MASK 0x0800
#define B10_MASK 0x0400
#define B9_MASK 0x0200
#define B8_MASK 0x0100
#define B7_MASK 0x0080
#define B6_MASK 0x0040
#define B5_MASK 0x0020
#define B4_MASK 0x0010
#define B3_MASK 0x0008
#define B2_MASK 0x0004
#define B1_MASK 0x0002
#define B0_MASK 0x0001
/* PCI register offset */
#define PCI_ID_REG 0x00
#define PCI_COMMAND_REG 0x04
/* #define MEMEN_BIT B1_MASK */
/* #define IOEN_BIT B0_MASK */
#define PCI_REV_ID_REG 0x08
#define PCI_MEM_BASE_REG 0x10
/* #define MEMBASE_MASK 0xFFFFF000 */
/* #define MEMBASE_SIZE 4096 */
#define PCI_INTR_REG 0x3C
#define PCI_STATUS_REG 0x06
#define PCI_CAP_ID_REG_OFFSET 0x34
#define PCI_PMC_REG_OFFSET 0x36
#define PCI_PMCSR_REG_OFFSET 0x38
/* #define NEW_CAP 0x0010 */
#define PME_EN 0x0100
#define PARTID_MASK 0xFFFFF000
#define PARTID_START_BIT 12
/* #define LANCE_DWIO_RESET_PORT 0x18
#define LANCE_WIO_RESET_PORT 0x14 */
#define MIB_OFFSET 0x28
/* Command style register access
Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
