Commit 5a439c56 authored by Linus Torvalds's avatar Linus Torvalds

Merge git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6:
  xtensa: Add config files for Diamond 232L - Rev B processor variant
  xtensa: Fix io regions
  xtensa: Add support for the Sonic Ethernet device for the XT2000 board.
  xtensa: replace remaining __FUNCTION__ occurrences
  xtensa: use newer __SPIN_LOCK_UNLOCKED macro
  XTENSA: warn about including <asm/rwsem.h> directly.
parents 94b6da5a 0025427e
...@@ -64,7 +64,12 @@ choice ...@@ -64,7 +64,12 @@ choice
default XTENSA_VARIANT_FSF default XTENSA_VARIANT_FSF
config XTENSA_VARIANT_FSF config XTENSA_VARIANT_FSF
bool "fsf" bool "fsf - default (not generic) configuration"
config XTENSA_VARIANT_DC232B
bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
help
This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
endchoice endchoice
config MMU config MMU
......
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
# (Use VAR=<xtensa_config> to use another default compiler.) # (Use VAR=<xtensa_config> to use another default compiler.)
variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf
variant-$(CONFIG_XTENSA_VARIANT_DC232B) := dc232b
variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom
VARIANT = $(variant-y) VARIANT = $(variant-y)
......
...@@ -48,7 +48,7 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs) ...@@ -48,7 +48,7 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
if (irq >= NR_IRQS) { if (irq >= NR_IRQS) {
printk(KERN_EMERG "%s: cannot handle IRQ %d\n", printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
__FUNCTION__, irq); __func__, irq);
} }
irq_enter(); irq_enter();
......
...@@ -640,7 +640,7 @@ static int iss_net_configure(int index, char *init) ...@@ -640,7 +640,7 @@ static int iss_net_configure(int index, char *init)
*lp = ((struct iss_net_private) { *lp = ((struct iss_net_private) {
.device_list = LIST_HEAD_INIT(lp->device_list), .device_list = LIST_HEAD_INIT(lp->device_list),
.opened_list = LIST_HEAD_INIT(lp->opened_list), .opened_list = LIST_HEAD_INIT(lp->opened_list),
.lock = SPIN_LOCK_UNLOCKED, .lock = __SPIN_LOCK_UNLOCKED(lp.lock),
.dev = dev, .dev = dev,
.index = index, .index = index,
//.fd = -1, //.fd = -1,
......
...@@ -464,6 +464,12 @@ config MIPS_JAZZ_SONIC ...@@ -464,6 +464,12 @@ config MIPS_JAZZ_SONIC
This is the driver for the onboard card of MIPS Magnum 4000, This is the driver for the onboard card of MIPS Magnum 4000,
Acer PICA, Olivetti M700-10 and a few other identical OEM systems. Acer PICA, Olivetti M700-10 and a few other identical OEM systems.
config XTENSA_XT2000_SONIC
tristate "Xtensa XT2000 onboard SONIC Ethernet support"
depends on XTENSA_PLATFORM_XT2000
help
This is the driver for the onboard card of the Xtensa XT2000 board.
config MIPS_AU1X00_ENET config MIPS_AU1X00_ENET
bool "MIPS AU1000 Ethernet support" bool "MIPS AU1000 Ethernet support"
depends on SOC_AU1X00 depends on SOC_AU1X00
......
...@@ -227,6 +227,8 @@ pasemi_mac_driver-objs := pasemi_mac.o pasemi_mac_ethtool.o ...@@ -227,6 +227,8 @@ pasemi_mac_driver-objs := pasemi_mac.o pasemi_mac_ethtool.o
obj-$(CONFIG_MLX4_CORE) += mlx4/ obj-$(CONFIG_MLX4_CORE) += mlx4/
obj-$(CONFIG_ENC28J60) += enc28j60.o obj-$(CONFIG_ENC28J60) += enc28j60.o
obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_ARM) += arm/ obj-$(CONFIG_ARM) += arm/
......
/*
* xtsonic.c
*
* (C) 2001 - 2007 Tensilica Inc.
* Kevin Chea <kchea@yahoo.com>
* Marc Gauthier <marc@linux-xtensa.org>
* Chris Zankel <chris@zankel.net>
*
* (C) 1996,1998 by Thomas Bogendoerfer (tsbogend@alpha.franken.de)
*
* This driver is based on work from Andreas Busse, but most of
* the code is rewritten.
*
* (C) 1995 by Andreas Busse (andy@waldorf-gmbh.de)
*
* A driver for the onboard Sonic ethernet controller on the XT2000.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/in.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/dma.h>
static char xtsonic_string[] = "xtsonic";
extern unsigned xtboard_nvram_valid(void);
extern void xtboard_get_ether_addr(unsigned char *buf);
#include "sonic.h"
/*
* According to the documentation for the Sonic ethernet controller,
* EOBC should be 760 words (1520 bytes) for 32-bit applications, and,
* as such, 2 words less than the buffer size. The value for RBSIZE
* defined in sonic.h, however is only 1520.
*
* (Note that in 16-bit configurations, EOBC is 759 words (1518 bytes) and
* RBSIZE 1520 bytes)
*/
#undef SONIC_RBSIZE
#define SONIC_RBSIZE 1524
/*
* The chip provides 256 byte register space.
*/
#define SONIC_MEM_SIZE 0x100
/*
* Macros to access SONIC registers
*/
#define SONIC_READ(reg) \
(0xffff & *((volatile unsigned int *)dev->base_addr+reg))
#define SONIC_WRITE(reg,val) \
*((volatile unsigned int *)dev->base_addr+reg) = val
/* Use 0 for production, 1 for verification, and >2 for debug */
#ifdef SONIC_DEBUG
static unsigned int sonic_debug = SONIC_DEBUG;
#else
static unsigned int sonic_debug = 1;
#endif
/*
* We cannot use station (ethernet) address prefixes to detect the
* sonic controller since these are board manufacturer depended.
* So we check for known Silicon Revision IDs instead.
*/
static unsigned short known_revisions[] =
{
0x101, /* SONIC 83934 */
0xffff /* end of list */
};
static int xtsonic_open(struct net_device *dev)
{
if (request_irq(dev->irq,&sonic_interrupt,IRQF_DISABLED,"sonic",dev)) {
printk(KERN_ERR "%s: unable to get IRQ %d.\n",
dev->name, dev->irq);
return -EAGAIN;
}
return sonic_open(dev);
}
static int xtsonic_close(struct net_device *dev)
{
int err;
err = sonic_close(dev);
free_irq(dev->irq, dev);
return err;
}
static int __init sonic_probe1(struct net_device *dev)
{
static unsigned version_printed = 0;
unsigned int silicon_revision;
struct sonic_local *lp = netdev_priv(dev);
unsigned int base_addr = dev->base_addr;
int i;
int err = 0;
if (!request_mem_region(base_addr, 0x100, xtsonic_string))
return -EBUSY;
/*
* get the Silicon Revision ID. If this is one of the known
* one assume that we found a SONIC ethernet controller at
* the expected location.
*/
silicon_revision = SONIC_READ(SONIC_SR);
if (sonic_debug > 1)
printk("SONIC Silicon Revision = 0x%04x\n",silicon_revision);
i = 0;
while ((known_revisions[i] != 0xffff) &&
(known_revisions[i] != silicon_revision))
i++;
if (known_revisions[i] == 0xffff) {
printk("SONIC ethernet controller not found (0x%4x)\n",
silicon_revision);
return -ENODEV;
}
if (sonic_debug && version_printed++ == 0)
printk(version);
/*
* Put the sonic into software reset, then retrieve ethernet address.
* Note: we are assuming that the boot-loader has initialized the cam.
*/
SONIC_WRITE(SONIC_CMD,SONIC_CR_RST);
SONIC_WRITE(SONIC_DCR,
SONIC_DCR_WC0|SONIC_DCR_DW|SONIC_DCR_LBR|SONIC_DCR_SBUS);
SONIC_WRITE(SONIC_CEP,0);
SONIC_WRITE(SONIC_IMR,0);
SONIC_WRITE(SONIC_CMD,SONIC_CR_RST);
SONIC_WRITE(SONIC_CEP,0);
for (i=0; i<3; i++) {
unsigned int val = SONIC_READ(SONIC_CAP0-i);
dev->dev_addr[i*2] = val;
dev->dev_addr[i*2+1] = val >> 8;
}
/* Initialize the device structure. */
lp->dma_bitmode = SONIC_BITMODE32;
/*
* Allocate local private descriptor areas in uncached space.
* The entire structure must be located within the same 64kb segment.
* A simple way to ensure this is to allocate twice the
* size of the structure -- given that the structure is
* much less than 64 kB, at least one of the halves of
* the allocated area will be contained entirely in 64 kB.
* We also allocate extra space for a pointer to allow freeing
* this structure later on (in xtsonic_cleanup_module()).
*/
lp->descriptors =
dma_alloc_coherent(lp->device,
SIZEOF_SONIC_DESC * SONIC_BUS_SCALE(lp->dma_bitmode),
&lp->descriptors_laddr, GFP_KERNEL);
if (lp->descriptors == NULL) {
printk(KERN_ERR "%s: couldn't alloc DMA memory for "
" descriptors.\n", lp->device->bus_id);
goto out;
}
lp->cda = lp->descriptors;
lp->tda = lp->cda + (SIZEOF_SONIC_CDA
* SONIC_BUS_SCALE(lp->dma_bitmode));
lp->rda = lp->tda + (SIZEOF_SONIC_TD * SONIC_NUM_TDS
* SONIC_BUS_SCALE(lp->dma_bitmode));
lp->rra = lp->rda + (SIZEOF_SONIC_RD * SONIC_NUM_RDS
* SONIC_BUS_SCALE(lp->dma_bitmode));
/* get the virtual dma address */
lp->cda_laddr = lp->descriptors_laddr;
lp->tda_laddr = lp->cda_laddr + (SIZEOF_SONIC_CDA
* SONIC_BUS_SCALE(lp->dma_bitmode));
lp->rda_laddr = lp->tda_laddr + (SIZEOF_SONIC_TD * SONIC_NUM_TDS
* SONIC_BUS_SCALE(lp->dma_bitmode));
lp->rra_laddr = lp->rda_laddr + (SIZEOF_SONIC_RD * SONIC_NUM_RDS
* SONIC_BUS_SCALE(lp->dma_bitmode));
dev->open = xtsonic_open;
dev->stop = xtsonic_close;
dev->hard_start_xmit = sonic_send_packet;
dev->get_stats = sonic_get_stats;
dev->set_multicast_list = &sonic_multicast_list;
dev->tx_timeout = sonic_tx_timeout;
dev->watchdog_timeo = TX_TIMEOUT;
/*
* clear tally counter
*/
SONIC_WRITE(SONIC_CRCT,0xffff);
SONIC_WRITE(SONIC_FAET,0xffff);
SONIC_WRITE(SONIC_MPT,0xffff);
return 0;
out:
release_region(dev->base_addr, SONIC_MEM_SIZE);
return err;
}
/*
* Probe for a SONIC ethernet controller on an XT2000 board.
* Actually probing is superfluous but we're paranoid.
*/
int __init xtsonic_probe(struct platform_device *pdev)
{
struct net_device *dev;
struct sonic_local *lp;
struct resource *resmem, *resirq;
int err = 0;
DECLARE_MAC_BUF(mac);
if ((resmem = platform_get_resource(pdev, IORESOURCE_MEM, 0)) == NULL)
return -ENODEV;
if ((resirq = platform_get_resource(pdev, IORESOURCE_IRQ, 0)) == NULL)
return -ENODEV;
if ((dev = alloc_etherdev(sizeof(struct sonic_local))) == NULL)
return -ENOMEM;
lp = netdev_priv(dev);
lp->device = &pdev->dev;
SET_NETDEV_DEV(dev, &pdev->dev);
netdev_boot_setup_check(dev);
dev->base_addr = resmem->start;
dev->irq = resirq->start;
if ((err = sonic_probe1(dev)))
goto out;
if ((err = register_netdev(dev)))
goto out1;
printk("%s: SONIC ethernet @%08lx, MAC %s, IRQ %d\n", dev->name,
dev->base_addr, print_mac(mac, dev->dev_addr), dev->irq);
return 0;
out1:
release_region(dev->base_addr, SONIC_MEM_SIZE);
out:
free_netdev(dev);
return err;
}
MODULE_DESCRIPTION("Xtensa XT2000 SONIC ethernet driver");
module_param(sonic_debug, int, 0);
MODULE_PARM_DESC(sonic_debug, "xtsonic debug level (1-4)");
#include "sonic.c"
static int __devexit xtsonic_device_remove (struct platform_device *pdev)
{
struct net_device *dev = platform_get_drvdata(pdev);
struct sonic_local *lp = netdev_priv(dev);
unregister_netdev(dev);
dma_free_coherent(lp->device,
SIZEOF_SONIC_DESC * SONIC_BUS_SCALE(lp->dma_bitmode),
lp->descriptors, lp->descriptors_laddr);
release_region (dev->base_addr, SONIC_MEM_SIZE);
free_netdev(dev);
return 0;
}
static struct platform_driver xtsonic_driver = {
.probe = xtsonic_probe,
.remove = __devexit_p(xtsonic_device_remove),
.driver = {
.name = xtsonic_string,
},
};
static int __init xtsonic_init(void)
{
return platform_driver_register(&xtsonic_driver);
}
static void __exit xtsonic_cleanup(void)
{
platform_driver_unregister(&xtsonic_driver);
}
module_init(xtsonic_init);
module_exit(xtsonic_cleanup);
...@@ -18,10 +18,12 @@ ...@@ -18,10 +18,12 @@
#include <linux/types.h> #include <linux/types.h>
#define XCHAL_KIO_CACHED_VADDR 0xf0000000 #define XCHAL_KIO_CACHED_VADDR 0xe0000000
#define XCHAL_KIO_BYPASS_VADDR 0xf8000000 #define XCHAL_KIO_BYPASS_VADDR 0xf0000000
#define XCHAL_KIO_PADDR 0xf0000000 #define XCHAL_KIO_PADDR 0xf0000000
#define XCHAL_KIO_SIZE 0x08000000 #define XCHAL_KIO_SIZE 0x10000000
#define IOADDR(x) (XCHAL_KIO_BYPASS_VADDR + (x))
/* /*
* swap functions to change byte order from little-endian to big-endian and * swap functions to change byte order from little-endian to big-endian and
......
...@@ -13,6 +13,10 @@ ...@@ -13,6 +13,10 @@
#ifndef _XTENSA_RWSEM_H #ifndef _XTENSA_RWSEM_H
#define _XTENSA_RWSEM_H #define _XTENSA_RWSEM_H
#ifndef _LINUX_RWSEM_H
#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
#endif
#include <linux/list.h> #include <linux/list.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <asm/atomic.h> #include <asm/atomic.h>
......
This diff is collapsed.
/*
* This header file contains assembly-language definitions (assembly
* macros, etc.) for this specific Xtensa processor's TIE extensions
* and options. It is customized to this Xtensa processor configuration.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999-2007 Tensilica Inc.
*/
#ifndef _XTENSA_CORE_TIE_ASM_H
#define _XTENSA_CORE_TIE_ASM_H
/* Selection parameter values for save-area save/restore macros: */
/* Option vs. TIE: */
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
/* Whether used automatically by compiler: */
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
/* ABI handling across function calls: */
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
/* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
/* Macro to save all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Save area ptr (clobbered): ptr (1 byte aligned)
* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
*/
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
xchal_sa_start \continue, \ofs
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 1024-8, 4, 4
rsr \at1, ACCLO // MAC16 accumulator
rsr \at2, ACCHI
s32i \at1, \ptr, .Lxchal_ofs_ + 0
s32i \at2, \ptr, .Lxchal_ofs_ + 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 1024-16, 4, 4
rsr \at1, M0 // MAC16 registers
rsr \at2, M1
s32i \at1, \ptr, .Lxchal_ofs_ + 0
s32i \at2, \ptr, .Lxchal_ofs_ + 4
rsr \at1, M2
rsr \at2, M3
s32i \at1, \ptr, .Lxchal_ofs_ + 8
s32i \at2, \ptr, .Lxchal_ofs_ + 12
.set .Lxchal_ofs_, .Lxchal_ofs_ + 16
.endif
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 1024-4, 4, 4
rsr \at1, SCOMPARE1 // conditional store option
s32i \at1, \ptr, .Lxchal_ofs_ + 0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
xchal_sa_align \ptr, 0, 1024-4, 4, 4
rur \at1, THREADPTR // threadptr option
s32i \at1, \ptr, .Lxchal_ofs_ + 0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.endm // xchal_ncp_store
/* Macro to save all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Save area ptr (clobbered): ptr (1 byte aligned)
* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
*/
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
xchal_sa_start \continue, \ofs
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 1024-8, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_ + 0
l32i \at2, \ptr, .Lxchal_ofs_ + 4
wsr \at1, ACCLO // MAC16 accumulator
wsr \at2, ACCHI
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 1024-16, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_ + 0
l32i \at2, \ptr, .Lxchal_ofs_ + 4
wsr \at1, M0 // MAC16 registers
wsr \at2, M1
l32i \at1, \ptr, .Lxchal_ofs_ + 8
l32i \at2, \ptr, .Lxchal_ofs_ + 12
wsr \at1, M2
wsr \at2, M3
.set .Lxchal_ofs_, .Lxchal_ofs_ + 16
.endif
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 1024-4, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_ + 0
wsr \at1, SCOMPARE1 // conditional store option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
xchal_sa_align \ptr, 0, 1024-4, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_ + 0
wur \at1, THREADPTR // threadptr option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.endm // xchal_ncp_load
#define XCHAL_NCP_NUM_ATMPS 2
#define XCHAL_SA_NUM_ATMPS 2
#endif /*_XTENSA_CORE_TIE_ASM_H*/
/*
* This header file describes this specific Xtensa processor's TIE extensions
* that extend basic Xtensa core functionality. It is customized to this
* Xtensa processor configuration.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999-2007 Tensilica Inc.
*/
#ifndef _XTENSA_CORE_TIE_H
#define _XTENSA_CORE_TIE_H
#define XCHAL_CP_NUM 1 /* number of coprocessors */
#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
#define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
/* Basic parameters of each coprocessor: */
#define XCHAL_CP7_NAME "XTIOP"
#define XCHAL_CP7_IDENT XTIOP
#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_CP0_SA_SIZE 0
#define XCHAL_CP0_SA_ALIGN 1
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP6_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 32
#define XCHAL_NCP_SA_ALIGN 4
/* Total save area for optional and custom state (NCP + CPn): */
#define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
/*
* Detailed contents of save areas.
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
* before expanding the XCHAL_xxx_SA_LIST() macros.
*
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
*
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
* ccused = set if used by compiler without special options or code
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
* name = lowercase reg name (no quotes)
* galign = group byte alignment (power of 2) (galign >= align)
* align = register byte alignment (power of 2)
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
* (not including any pad bytes required to galign this or next reg)
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
* regnum = reg index in regfile, or special/TIE-user reg number
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
* gapsz = intervening bits, if bitsz bits not stored contiguously
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
* reset = register reset value (or 0 if undefined at reset)
* x = reserved for future use (0 until then)
*
* To filter out certain registers, e.g. to expand only the non-global
* registers used by the compiler, you can do something like this:
*
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* ...what you want to expand...
*/
#define XCHAL_NCP_SA_NUM 8
#define XCHAL_NCP_SA_LIST(s) \
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
#define XCHAL_CP0_SA_NUM 0
#define XCHAL_CP0_SA_LIST(s) /* empty */
#define XCHAL_CP1_SA_NUM 0
#define XCHAL_CP1_SA_LIST(s) /* empty */
#define XCHAL_CP2_SA_NUM 0
#define XCHAL_CP2_SA_LIST(s) /* empty */
#define XCHAL_CP3_SA_NUM 0
#define XCHAL_CP3_SA_LIST(s) /* empty */
#define XCHAL_CP4_SA_NUM 0
#define XCHAL_CP4_SA_LIST(s) /* empty */
#define XCHAL_CP5_SA_NUM 0
#define XCHAL_CP5_SA_LIST(s) /* empty */
#define XCHAL_CP6_SA_NUM 0
#define XCHAL_CP6_SA_LIST(s) /* empty */
#define XCHAL_CP7_SA_NUM 0
#define XCHAL_CP7_SA_LIST(s) /* empty */
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_XTENSA_CORE_TIE_H*/
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment