Commit 5ce5fe14 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Michael Ellerman

powerpc/mm/radix: Improve _tlbiel_pid to be usable for PWC flushes

The PWC flush only needs a single set call, just like the
full (RIC=2) flush.

This will allow us to get rid of the dedicated _tlbiel_pwc()
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 75f327c6
...@@ -54,12 +54,15 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) ...@@ -54,12 +54,15 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
*/ */
__tlbiel_pid(pid, 0, ric); __tlbiel_pid(pid, 0, ric);
if (ric == RIC_FLUSH_ALL) /* For PWC, only one flush is needed */
/* For the remaining sets, just flush the TLB */ if (ric == RIC_FLUSH_PWC) {
ric = RIC_FLUSH_TLB; asm volatile("ptesync": : :"memory");
return;
}
/* For the remaining sets, just flush the TLB */
for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++) for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
__tlbiel_pid(pid, set, ric); __tlbiel_pid(pid, set, RIC_FLUSH_TLB);
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory"); asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
......
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