Commit 5e27cb68 authored by Dave Jones's avatar Dave Jones

Merge tetrachloride.(none):/mnt/raid/src/kernel/2.5/bk-linus

into tetrachloride.(none):/mnt/raid/src/kernel/2.5/agpgart
parents 162132e0 0b1640a1
agpgart-y := backend.o frontend.o generic.o generic-3.0.o agpgart-y := backend.o frontend.o generic.o isoch.o
obj-$(CONFIG_AGP) += agpgart.o obj-$(CONFIG_AGP) += agpgart.o
obj-$(CONFIG_AGP_ALI) += ali-agp.o obj-$(CONFIG_AGP_ALI) += ali-agp.o
......
...@@ -139,6 +139,8 @@ struct agp_bridge_data { ...@@ -139,6 +139,8 @@ struct agp_bridge_data {
int max_memory_agp; /* in number of pages */ int max_memory_agp; /* in number of pages */
int aperture_size_idx; int aperture_size_idx;
int capndx; int capndx;
char major_version;
char minor_version;
}; };
#define OUTREG64(mmap, addr, val) __raw_writeq((val), (mmap)+(addr)) #define OUTREG64(mmap, addr, val) __raw_writeq((val), (mmap)+(addr))
...@@ -388,27 +390,38 @@ void agp_free_key(int key); ...@@ -388,27 +390,38 @@ void agp_free_key(int key);
int agp_num_entries(void); int agp_num_entries(void);
u32 agp_collect_device_status(u32 mode, u32 command); u32 agp_collect_device_status(u32 mode, u32 command);
void agp_device_command(u32 command, int agp_v3); void agp_device_command(u32 command, int agp_v3);
int agp_3_0_node_enable(struct agp_bridge_data *bridge, u32 mode, u32 minor); int agp_3_0_enable(struct agp_bridge_data *bridge, u32 mode);
int agp_3_5_enable(struct agp_bridge_data *bridge, u32 mode);
void global_cache_flush(void); void global_cache_flush(void);
void get_agp_version(struct agp_bridge_data *bridge);
/* Standard agp registers */ /* Standard agp registers */
#define AGPSTAT 0x4 #define AGPSTAT 0x4
#define AGPCMD 0x8 #define AGPCMD 0x8
#define AGPNISTAT 0xc
#define AGPNEPG 0x16 #define AGPNEPG 0x16
#define AGPNICMD 0x20
#define AGP_MAJOR_VERSION_SHIFT (20) #define AGP_MAJOR_VERSION_SHIFT (20)
#define AGP_MINOR_VERSION_SHIFT (16) #define AGP_MINOR_VERSION_SHIFT (16)
#define AGPSTAT_RQ_DEPTH (0xff000000) #define AGPSTAT_RQ_DEPTH (0xff000000)
#define AGPSTAT_CAL_MASK (1<<12|1<<11|1<<10)
#define AGPSTAT_ARQSZ (1<<15|1<<14|1<<13)
#define AGPSTAT_ARQSZ_SHIFT 13 #define AGPSTAT_ARQSZ_SHIFT 13
#define AGPSTAT_AGP_ENABLE (1<<8)
#define AGPSTAT_SBA (1<<9) #define AGPSTAT_SBA (1<<9)
#define AGPSTAT_AGP_ENABLE (1<<8)
#define AGPSTAT_FW (1<<4)
#define AGPSTAT_MODE_3_0 (1<<3)
#define AGPSTAT2_1X (1<<0) #define AGPSTAT2_1X (1<<0)
#define AGPSTAT2_2X (1<<1) #define AGPSTAT2_2X (1<<1)
#define AGPSTAT2_4X (1<<2) #define AGPSTAT2_4X (1<<2)
#define AGPSTAT_FW (1<<4)
#define AGPSTAT3_RSVD (1<<2)
#define AGPSTAT3_8X (1<<1)
#define AGPSTAT3_4X (1)
#endif /* _AGP_BACKEND_PRIV_H */ #endif /* _AGP_BACKEND_PRIV_H */
...@@ -253,8 +253,10 @@ static int __init agp_amdk8_probe(struct pci_dev *pdev, ...@@ -253,8 +253,10 @@ static int __init agp_amdk8_probe(struct pci_dev *pdev,
{ {
struct agp_bridge_data *bridge; struct agp_bridge_data *bridge;
struct pci_dev *loop_dev; struct pci_dev *loop_dev;
u8 rev_id;
u8 cap_ptr; u8 cap_ptr;
int i = 0; int i = 0;
char *revstring=" ";
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
if (!cap_ptr) if (!cap_ptr)
...@@ -266,14 +268,38 @@ static int __init agp_amdk8_probe(struct pci_dev *pdev, ...@@ -266,14 +268,38 @@ static int __init agp_amdk8_probe(struct pci_dev *pdev,
if (!bridge) if (!bridge)
return -ENOMEM; return -ENOMEM;
/* Assume here we have an 8151. (Later this assumption will be fixed). */
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
switch (rev_id) {
case 0x01: revstring="A0";
break;
case 0x02: revstring="A1";
break;
case 0x11: revstring="B0";
break;
case 0x12: revstring="B1";
break;
case 0x13: revstring="B2";
break;
default: revstring="??";
break;
}
printk ("Detected AMD 8151 AGP Bridge rev %s", revstring);
/*
* Work around errata.
* Chips before B2 stepping incorrectly reporting v3.5
*/
if (rev_id < 0x13) {
bridge->major_version = 3;
bridge->minor_version = 0;
}
bridge->driver = &amd_8151_driver; bridge->driver = &amd_8151_driver;
bridge->dev = pdev; bridge->dev = pdev;
bridge->capndx = cap_ptr; bridge->capndx = cap_ptr;
/* Fill in the mode register */ /* Fill in the mode register */
pci_read_config_dword(pdev, pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
bridge->capndx+PCI_AGP_STATUS,
&bridge->mode);
/* cache pci_devs of northbridges. */ /* cache pci_devs of northbridges. */
pci_for_each_dev(loop_dev) { pci_for_each_dev(loop_dev) {
...@@ -290,7 +316,7 @@ static int __init agp_amdk8_probe(struct pci_dev *pdev, ...@@ -290,7 +316,7 @@ static int __init agp_amdk8_probe(struct pci_dev *pdev,
pci_set_drvdata(pdev, bridge); pci_set_drvdata(pdev, bridge);
return agp_add_bridge(bridge); return agp_add_bridge(bridge);
out_free: out_free:
agp_put_bridge(bridge); agp_put_bridge(bridge);
return -ENOMEM; return -ENOMEM;
} }
......
...@@ -270,14 +270,16 @@ EXPORT_SYMBOL_GPL(agp_num_entries); ...@@ -270,14 +270,16 @@ EXPORT_SYMBOL_GPL(agp_num_entries);
int agp_copy_info(agp_kern_info * info) int agp_copy_info(agp_kern_info * info)
{ {
memset(info, 0, sizeof(agp_kern_info)); memset(info, 0, sizeof(agp_kern_info));
if (agp_bridge->type == NOT_SUPPORTED) { if (!agp_bridge || agp_bridge->type == NOT_SUPPORTED ||
info->chipset = agp_bridge->type; !agp_bridge->version) {
info->chipset = NOT_SUPPORTED;
return -EIO; return -EIO;
} }
info->version.major = agp_bridge->version->major; info->version.major = agp_bridge->version->major;
info->version.minor = agp_bridge->version->minor; info->version.minor = agp_bridge->version->minor;
info->device = agp_bridge->dev;
info->chipset = agp_bridge->type; info->chipset = agp_bridge->type;
info->device = agp_bridge->dev;
info->mode = agp_bridge->mode; info->mode = agp_bridge->mode;
info->aper_base = agp_bridge->gart_bus_addr; info->aper_base = agp_bridge->gart_bus_addr;
info->aper_size = agp_return_size(); info->aper_size = agp_return_size();
...@@ -366,60 +368,106 @@ EXPORT_SYMBOL(agp_unbind_memory); ...@@ -366,60 +368,106 @@ EXPORT_SYMBOL(agp_unbind_memory);
/* Generic Agp routines - Start */ /* Generic Agp routines - Start */
static void agp_v2_parse_one(u32 *mode, u32 *cmd, u32 *tmp)
{
/* disable SBA if it's not supported */
if (!((*cmd & AGPSTAT_SBA) && (*tmp & AGPSTAT_SBA) && (*mode & AGPSTAT_SBA)))
*cmd &= ~AGPSTAT_SBA;
/* disable FW if it's not supported */
if (!((*cmd & AGPSTAT_FW) && (*tmp & AGPSTAT_FW) && (*mode & AGPSTAT_FW)))
*cmd &= ~AGPSTAT_FW;
/* Set speed */
if (!((*cmd & AGPSTAT2_4X) && (*tmp & AGPSTAT2_4X) && (*mode & AGPSTAT2_4X)))
*cmd &= ~AGPSTAT2_4X;
if (!((*cmd & AGPSTAT2_2X) && (*tmp & AGPSTAT2_2X) && (*mode & AGPSTAT2_2X)))
*cmd &= ~AGPSTAT2_2X;
if (!((*cmd & AGPSTAT2_1X) && (*tmp & AGPSTAT2_1X) && (*mode & AGPSTAT2_1X)))
*cmd &= ~AGPSTAT2_1X;
/* Now we know what mode it should be, clear out the unwanted bits. */
if (*cmd & AGPSTAT2_4X)
*cmd &= ~(AGPSTAT2_1X | AGPSTAT2_2X); /* 4X */
if (*cmd & AGPSTAT2_2X)
*cmd &= ~(AGPSTAT2_1X | AGPSTAT2_4X); /* 2X */
if (*cmd & AGPSTAT2_1X)
*cmd &= ~(AGPSTAT2_2X | AGPSTAT2_4X); /* 1Xf */
}
u32 agp_collect_device_status(u32 mode, u32 command)
static void agp_v3_parse_one(u32 *mode, u32 *cmd, u32 *tmp)
{
/* ARQSZ - Set the value to the maximum one.
* Don't allow the mode register to override values. */
*cmd = ((*cmd & ~AGPSTAT_ARQSZ) |
max_t(u32,(*cmd & AGPSTAT_ARQSZ),(*tmp & AGPSTAT_ARQSZ)));
/* Calibration cycle.
* Don't allow the mode register to override values. */
*cmd = ((*cmd & ~AGPSTAT_CAL_MASK) |
min_t(u32,(*cmd & AGPSTAT_CAL_MASK),(*tmp & AGPSTAT_CAL_MASK)));
/* SBA *must* be supported for AGP v3 */
*cmd |= AGPSTAT_SBA;
/* disable FW if it's not supported */
if (!((*cmd & AGPSTAT_FW) && (*tmp & AGPSTAT_FW) && (*mode & AGPSTAT_FW)))
*cmd &= ~AGPSTAT_FW;
/* Set speed. */
if (!((*cmd & AGPSTAT3_8X) && (*tmp & AGPSTAT3_8X) && (*mode & AGPSTAT3_8X)))
*cmd &= ~AGPSTAT3_8X;
if (!((*cmd & AGPSTAT3_4X) && (*tmp & AGPSTAT3_4X) && (*mode & AGPSTAT3_4X)))
*cmd &= ~AGPSTAT3_4X;
/* Clear out unwanted bits. */
if (*cmd & AGPSTAT3_8X)
*cmd *= ~(AGPSTAT3_4X | AGPSTAT3_RSVD);
if (*cmd & AGPSTAT3_4X)
*cmd *= ~(AGPSTAT3_8X | AGPSTAT3_RSVD);
}
//FIXME: This doesn't smell right.
//We need a function we pass an agp_device to.
u32 agp_collect_device_status(u32 mode, u32 cmd)
{ {
struct pci_dev *device; struct pci_dev *device;
u8 agp; u8 cap_ptr;
u32 scratch; u32 tmp;
u32 agp3;
pci_for_each_dev(device) { pci_for_each_dev(device) {
agp = pci_find_capability(device, PCI_CAP_ID_AGP); cap_ptr = pci_find_capability(device, PCI_CAP_ID_AGP);
if (!agp) if (!cap_ptr)
continue; continue;
/* /*
* Ok, here we have a AGP device. Disable impossible * Ok, here we have a AGP device. Disable impossible
* settings, and adjust the readqueue to the minimum. * settings, and adjust the readqueue to the minimum.
*/ */
pci_read_config_dword(device, agp + PCI_AGP_STATUS, &scratch); pci_read_config_dword(device, cap_ptr+PCI_AGP_STATUS, &tmp);
/* adjust RQ depth */ /* adjust RQ depth */
command = ((command & ~AGPSTAT_RQ_DEPTH) | cmd = ((cmd & ~AGPSTAT_RQ_DEPTH) |
min_t(u32, (mode & AGPSTAT_RQ_DEPTH), min_t(u32, (mode & AGPSTAT_RQ_DEPTH),
min_t(u32, (command & AGPSTAT_RQ_DEPTH), min_t(u32, (cmd & AGPSTAT_RQ_DEPTH), (tmp & AGPSTAT_RQ_DEPTH))));
(scratch & AGPSTAT_RQ_DEPTH))));
/* disable SBA if it's not supported */
if (!((command & AGPSTAT_SBA) && (scratch & AGPSTAT_SBA) && (mode & AGPSTAT_SBA)))
command &= ~AGPSTAT_SBA;
/* disable FW if it's not supported */
if (!((command & AGPSTAT_FW) && (scratch & AGPSTAT_FW) && (mode & AGPSTAT_FW)))
command &= ~AGPSTAT_FW;
/* Set speed */
if (!((command & AGPSTAT2_4X) && (scratch & AGPSTAT2_4X) && (mode & AGPSTAT2_4X)))
command &= ~AGPSTAT2_4X;
if (!((command & AGPSTAT2_2X) && (scratch & AGPSTAT2_2X) && (mode & AGPSTAT2_2X))) pci_read_config_dword(device, cap_ptr+AGPSTAT, &agp3);
command &= ~AGPSTAT2_2X;
if (!((command & AGPSTAT2_1X) && (scratch & AGPSTAT2_1X) && (mode & AGPSTAT2_1X))) /* Check to see if we are operating in 3.0 mode */
command &= ~AGPSTAT2_1X; if (agp3 & AGPSTAT_MODE_3_0) {
agp_v3_parse_one(&mode, &cmd, &tmp);
} else {
agp_v2_parse_one(&mode, &cmd, &tmp);
} }
}
/* Now we know what mode it should be, clear out the unwanted bits. */ return cmd;
if (command & AGPSTAT2_4X)
command &= ~(AGPSTAT2_1X | AGPSTAT2_2X); /* 4X */
if (command & AGPSTAT2_2X)
command &= ~(AGPSTAT2_1X | AGPSTAT2_4X); /* 2X */
if (command & AGPSTAT2_1X)
command &= ~(AGPSTAT2_2X | AGPSTAT2_4X); /* 1Xf */
return command;
} }
EXPORT_SYMBOL(agp_collect_device_status); EXPORT_SYMBOL(agp_collect_device_status);
...@@ -446,29 +494,33 @@ void agp_device_command(u32 command, int agp_v3) ...@@ -446,29 +494,33 @@ void agp_device_command(u32 command, int agp_v3)
EXPORT_SYMBOL(agp_device_command); EXPORT_SYMBOL(agp_device_command);
void agp_generic_enable(u32 mode) void get_agp_version(struct agp_bridge_data *bridge)
{ {
u32 command, ncapid, major, minor; u32 ncapid;
/* Exit early if already set by errata workarounds. */
if (agp_bridge->major_version != 0)
return;
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx, &ncapid); pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx, &ncapid);
major = (ncapid >> 20) & 0xf; agp_bridge->major_version = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf;
minor = (ncapid >> 16) & 0xf; agp_bridge->minor_version = (ncapid >> AGP_MINOR_VERSION_SHIFT) & 0xf;
printk(KERN_INFO PFX "Found an AGP %d.%d compliant device.\n",major, minor); }
EXPORT_SYMBOL(get_agp_version);
if(major >= 3) {
u32 agp_3_0;
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x4, &agp_3_0); void agp_generic_enable(u32 mode)
/* Check to see if we are operating in 3.0 mode */ {
if((agp_3_0 >> 3) & 0x1) { u32 command;
agp_3_0_node_enable(agp_bridge, mode, minor); u32 agp3;
return;
} else { get_agp_version(agp_bridge);
printk (KERN_INFO PFX "not in AGP 3.0 mode, falling back to 2.x\n");
} printk(KERN_INFO PFX "Found an AGP %d.%d compliant device at %s.\n",
} agp_bridge->major_version,
agp_bridge->minor_version,
agp_bridge->dev->slot_name);
/* AGP v<3 */
pci_read_config_dword(agp_bridge->dev, pci_read_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_STATUS, &command); agp_bridge->capndx + PCI_AGP_STATUS, &command);
...@@ -477,7 +529,27 @@ void agp_generic_enable(u32 mode) ...@@ -477,7 +529,27 @@ void agp_generic_enable(u32 mode)
pci_write_config_dword(agp_bridge->dev, pci_write_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_COMMAND, command); agp_bridge->capndx + PCI_AGP_COMMAND, command);
agp_device_command(command, 0);
/* Do AGP version specific frobbing. */
if(agp_bridge->major_version >= 3) {
pci_read_config_dword(agp_bridge->dev,
agp_bridge->capndx+AGPSTAT, &agp3);
/* Check to see if we are operating in 3.0 mode */
if (agp3 & AGPSTAT_MODE_3_0) {
/* If we have 3.5, we can do the isoch stuff. */
if (agp_bridge->minor_version >= 5)
agp_3_5_enable(agp_bridge, mode);
agp_device_command(command, TRUE);
return;
} else {
printk (KERN_INFO PFX "Device is in legacy mode,"
" falling back to 2.x\n");
}
}
/* AGP v<3 */
agp_device_command(command, FALSE);
} }
EXPORT_SYMBOL(agp_generic_enable); EXPORT_SYMBOL(agp_generic_enable);
...@@ -831,6 +903,7 @@ void agp_enable(u32 mode) ...@@ -831,6 +903,7 @@ void agp_enable(u32 mode)
} }
EXPORT_SYMBOL(agp_enable); EXPORT_SYMBOL(agp_enable);
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
static void ipi_handler(void *null) static void ipi_handler(void *null)
{ {
......
...@@ -49,7 +49,7 @@ config DRM_RADEON ...@@ -49,7 +49,7 @@ config DRM_RADEON
config DRM_I810 config DRM_I810
tristate "Intel I810" tristate "Intel I810"
depends on DRM && AGP depends on DRM && AGP && AGP_INTEL
help help
Choose this option if you have an Intel I810 graphics card. If M is Choose this option if you have an Intel I810 graphics card. If M is
selected, the module will be called i810. AGP support is required selected, the module will be called i810. AGP support is required
...@@ -57,7 +57,7 @@ config DRM_I810 ...@@ -57,7 +57,7 @@ config DRM_I810
config DRM_I830 config DRM_I830
tristate "Intel 830M, 845G, 852GM, 855GM, 865G" tristate "Intel 830M, 845G, 852GM, 855GM, 865G"
depends on DRM && AGP depends on DRM && AGP && AGP_INTEL
help help
Choose this option if you have a system that has Intel 830M, 845G, Choose this option if you have a system that has Intel 830M, 845G,
852GM, 855GM or 865G integrated graphics. If M is selected, the 852GM, 855GM or 865G integrated graphics. If M is selected, the
......
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