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nexedi
linux
Commits
5f6e0070
Commit
5f6e0070
authored
Apr 09, 2017
by
Christoffer Dall
Browse files
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Merge remote-tracking branch 'rutland/kvm/common-sysreg' into next-fix
parents
f7214e60
7606e078
Changes
6
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6 changed files
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284 additions
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334 deletions
+284
-334
arch/arm64/include/asm/arch_gicv3.h
arch/arm64/include/asm/arch_gicv3.h
+13
-68
arch/arm64/include/asm/sysreg.h
arch/arm64/include/asm/sysreg.h
+155
-7
arch/arm64/kernel/head.S
arch/arm64/kernel/head.S
+4
-4
arch/arm64/kvm/sys_regs.c
arch/arm64/kvm/sys_regs.c
+106
-252
arch/arm64/kvm/sys_regs.h
arch/arm64/kvm/sys_regs.h
+5
-0
arch/arm64/kvm/sys_regs_generic_v8.c
arch/arm64/kvm/sys_regs_generic_v8.c
+1
-3
No files found.
arch/arm64/include/asm/arch_gicv3.h
View file @
5f6e0070
...
@@ -20,69 +20,14 @@
...
@@ -20,69 +20,14 @@
#include <asm/sysreg.h>
#include <asm/sysreg.h>
#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
#define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
#define ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
/*
* System register definitions
*/
#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
#define ICH_LR0_EL2 __LR0_EL2(0)
#define ICH_LR1_EL2 __LR0_EL2(1)
#define ICH_LR2_EL2 __LR0_EL2(2)
#define ICH_LR3_EL2 __LR0_EL2(3)
#define ICH_LR4_EL2 __LR0_EL2(4)
#define ICH_LR5_EL2 __LR0_EL2(5)
#define ICH_LR6_EL2 __LR0_EL2(6)
#define ICH_LR7_EL2 __LR0_EL2(7)
#define ICH_LR8_EL2 __LR8_EL2(0)
#define ICH_LR9_EL2 __LR8_EL2(1)
#define ICH_LR10_EL2 __LR8_EL2(2)
#define ICH_LR11_EL2 __LR8_EL2(3)
#define ICH_LR12_EL2 __LR8_EL2(4)
#define ICH_LR13_EL2 __LR8_EL2(5)
#define ICH_LR14_EL2 __LR8_EL2(6)
#define ICH_LR15_EL2 __LR8_EL2(7)
#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
#include <linux/stringify.h>
#include <asm/barrier.h>
#include <asm/barrier.h>
#include <asm/cacheflush.h>
#include <asm/cacheflush.h>
#define read_gicreg
read_sysreg_s
#define read_gicreg
(r) read_sysreg_s(SYS_ ## r)
#define write_gicreg
write_sysreg_s
#define write_gicreg
(v, r) write_sysreg_s(v, SYS_ ## r)
/*
/*
* Low-level accessors
* Low-level accessors
...
@@ -93,13 +38,13 @@
...
@@ -93,13 +38,13 @@
static
inline
void
gic_write_eoir
(
u32
irq
)
static
inline
void
gic_write_eoir
(
u32
irq
)
{
{
write_sysreg_s
(
irq
,
ICC_EOIR1_EL1
);
write_sysreg_s
(
irq
,
SYS_
ICC_EOIR1_EL1
);
isb
();
isb
();
}
}
static
inline
void
gic_write_dir
(
u32
irq
)
static
inline
void
gic_write_dir
(
u32
irq
)
{
{
write_sysreg_s
(
irq
,
ICC_DIR_EL1
);
write_sysreg_s
(
irq
,
SYS_
ICC_DIR_EL1
);
isb
();
isb
();
}
}
...
@@ -107,7 +52,7 @@ static inline u64 gic_read_iar_common(void)
...
@@ -107,7 +52,7 @@ static inline u64 gic_read_iar_common(void)
{
{
u64
irqstat
;
u64
irqstat
;
irqstat
=
read_sysreg_s
(
ICC_IAR1_EL1
);
irqstat
=
read_sysreg_s
(
SYS_
ICC_IAR1_EL1
);
dsb
(
sy
);
dsb
(
sy
);
return
irqstat
;
return
irqstat
;
}
}
...
@@ -124,7 +69,7 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
...
@@ -124,7 +69,7 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
u64
irqstat
;
u64
irqstat
;
nops
(
8
);
nops
(
8
);
irqstat
=
read_sysreg_s
(
ICC_IAR1_EL1
);
irqstat
=
read_sysreg_s
(
SYS_
ICC_IAR1_EL1
);
nops
(
4
);
nops
(
4
);
mb
();
mb
();
...
@@ -133,40 +78,40 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
...
@@ -133,40 +78,40 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
static
inline
void
gic_write_pmr
(
u32
val
)
static
inline
void
gic_write_pmr
(
u32
val
)
{
{
write_sysreg_s
(
val
,
ICC_PMR_EL1
);
write_sysreg_s
(
val
,
SYS_
ICC_PMR_EL1
);
}
}
static
inline
void
gic_write_ctlr
(
u32
val
)
static
inline
void
gic_write_ctlr
(
u32
val
)
{
{
write_sysreg_s
(
val
,
ICC_CTLR_EL1
);
write_sysreg_s
(
val
,
SYS_
ICC_CTLR_EL1
);
isb
();
isb
();
}
}
static
inline
void
gic_write_grpen1
(
u32
val
)
static
inline
void
gic_write_grpen1
(
u32
val
)
{
{
write_sysreg_s
(
val
,
ICC_GRPEN1_EL1
);
write_sysreg_s
(
val
,
SYS_
ICC_GRPEN1_EL1
);
isb
();
isb
();
}
}
static
inline
void
gic_write_sgi1r
(
u64
val
)
static
inline
void
gic_write_sgi1r
(
u64
val
)
{
{
write_sysreg_s
(
val
,
ICC_SGI1R_EL1
);
write_sysreg_s
(
val
,
SYS_
ICC_SGI1R_EL1
);
}
}
static
inline
u32
gic_read_sre
(
void
)
static
inline
u32
gic_read_sre
(
void
)
{
{
return
read_sysreg_s
(
ICC_SRE_EL1
);
return
read_sysreg_s
(
SYS_
ICC_SRE_EL1
);
}
}
static
inline
void
gic_write_sre
(
u32
val
)
static
inline
void
gic_write_sre
(
u32
val
)
{
{
write_sysreg_s
(
val
,
ICC_SRE_EL1
);
write_sysreg_s
(
val
,
SYS_
ICC_SRE_EL1
);
isb
();
isb
();
}
}
static
inline
void
gic_write_bpr1
(
u32
val
)
static
inline
void
gic_write_bpr1
(
u32
val
)
{
{
asm
volatile
(
"msr_s "
__stringify
(
ICC_BPR1_EL1
)
", %0"
:
:
"r"
(
val
)
);
write_sysreg_s
(
val
,
SYS_ICC_BPR1_EL1
);
}
}
#define gic_read_typer(c) readq_relaxed(c)
#define gic_read_typer(c) readq_relaxed(c)
...
...
arch/arm64/include/asm/sysreg.h
View file @
5f6e0070
...
@@ -48,6 +48,8 @@
...
@@ -48,6 +48,8 @@
((crn) << CRn_shift) | ((crm) << CRm_shift) | \
((crn) << CRn_shift) | ((crm) << CRm_shift) | \
((op2) << Op2_shift))
((op2) << Op2_shift))
#define sys_insn sys_reg
#define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
#define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
#define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
#define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
#define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
#define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
...
@@ -81,6 +83,41 @@
...
@@ -81,6 +83,41 @@
#endif
/* CONFIG_BROKEN_GAS_INST */
#endif
/* CONFIG_BROKEN_GAS_INST */
#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
(!!x)<<8 | 0x1f)
#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
(!!x)<<8 | 0x1f)
#define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
#define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
#define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
#define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
#define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
#define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
#define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
#define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
#define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
#define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
#define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
#define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
#define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
#define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
#define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
#define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
#define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
#define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
#define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
...
@@ -88,6 +125,7 @@
...
@@ -88,6 +125,7 @@
#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
...
@@ -118,17 +156,127 @@
...
@@ -118,17 +156,127 @@
#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
#define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
#define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
#define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
#define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
#define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
#define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
#define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
#define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
#define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
#define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
#define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
#define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
(!!x)<<8 | 0x1f)
#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
(!!x)<<8 | 0x1f)
#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
#define __PMEV_op2(n) ((n) & 0x7)
#define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
#define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
#define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7)
#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
#define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
#define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
#define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
#define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
#define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
#define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
#define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
#define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
#define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
#define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
#define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
#define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
#define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
#define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
#define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
#define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
#define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
#define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
#define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
/* Common SCTLR_ELx flags. */
/* Common SCTLR_ELx flags. */
#define SCTLR_ELx_EE (1 << 25)
#define SCTLR_ELx_EE (1 << 25)
...
...
arch/arm64/kernel/head.S
View file @
5f6e0070
...
@@ -594,14 +594,14 @@ set_hcr:
...
@@ -594,14 +594,14 @@ set_hcr:
cmp
x0
,
#
1
cmp
x0
,
#
1
b.ne
3
f
b.ne
3
f
mrs_s
x0
,
ICC_SRE_EL2
mrs_s
x0
,
SYS_
ICC_SRE_EL2
orr
x0
,
x0
,
#
ICC_SRE_EL2_SRE
//
Set
ICC_SRE_EL2
.
SRE
==
1
orr
x0
,
x0
,
#
ICC_SRE_EL2_SRE
//
Set
ICC_SRE_EL2
.
SRE
==
1
orr
x0
,
x0
,
#
ICC_SRE_EL2_ENABLE
//
Set
ICC_SRE_EL2
.
Enable
==
1
orr
x0
,
x0
,
#
ICC_SRE_EL2_ENABLE
//
Set
ICC_SRE_EL2
.
Enable
==
1
msr_s
ICC_SRE_EL2
,
x0
msr_s
SYS_
ICC_SRE_EL2
,
x0
isb
//
Make
sure
SRE
is
now
set
isb
//
Make
sure
SRE
is
now
set
mrs_s
x0
,
ICC_SRE_EL2
//
Read
SRE
back
,
mrs_s
x0
,
SYS_ICC_SRE_EL2
//
Read
SRE
back
,
tbz
x0
,
#
0
,
3
f
//
and
check
that
it
sticks
tbz
x0
,
#
0
,
3
f
//
and
check
that
it
sticks
msr_s
ICH_HCR_EL2
,
xzr
//
Reset
ICC_HCR_EL2
to
defaults
msr_s
SYS_
ICH_HCR_EL2
,
xzr
//
Reset
ICC_HCR_EL2
to
defaults
3
:
3
:
#endif
#endif
...
...
arch/arm64/kvm/sys_regs.c
View file @
5f6e0070
...
@@ -807,31 +807,23 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
...
@@ -807,31 +807,23 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */
\
{ SYS_DESC(SYS_DBGBVRn_EL1(n)), \
{ Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \
trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \
/* DBGBCRn_EL1 */
\
{ SYS_DESC(SYS_DBGBCRn_EL1(n)), \
{ Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \
trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \
/* DBGWVRn_EL1 */
\
{ SYS_DESC(SYS_DBGWVRn_EL1(n)), \
{ Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \
trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \
/* DBGWCRn_EL1 */
\
{ SYS_DESC(SYS_DBGWCRn_EL1(n)), \
{ Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
/* Macro to expand the PMEVCNTRn_EL0 register */
/* Macro to expand the PMEVCNTRn_EL0 register */
#define PMU_PMEVCNTR_EL0(n) \
#define PMU_PMEVCNTR_EL0(n) \
/* PMEVCNTRn_EL0 */
\
{ SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \
{ Op0(0b11), Op1(0b011), CRn(0b1110), \
CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
/* Macro to expand the PMEVTYPERn_EL0 register */
/* Macro to expand the PMEVTYPERn_EL0 register */
#define PMU_PMEVTYPER_EL0(n) \
#define PMU_PMEVTYPER_EL0(n) \
/* PMEVTYPERn_EL0 */
\
{ SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
{ Op0(0b11), Op1(0b011), CRn(0b1110), \
CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
static
bool
access_cntp_tval
(
struct
kvm_vcpu
*
vcpu
,
static
bool
access_cntp_tval
(
struct
kvm_vcpu
*
vcpu
,
...
@@ -901,24 +893,14 @@ static bool access_cntp_cval(struct kvm_vcpu *vcpu,
...
@@ -901,24 +893,14 @@ static bool access_cntp_cval(struct kvm_vcpu *vcpu,
* more demanding guest...
* more demanding guest...
*/
*/
static
const
struct
sys_reg_desc
sys_reg_descs
[]
=
{
static
const
struct
sys_reg_desc
sys_reg_descs
[]
=
{
/* DC ISW */
{
SYS_DESC
(
SYS_DC_ISW
),
access_dcsw
},
{
Op0
(
0
b01
),
Op1
(
0
b000
),
CRn
(
0
b0111
),
CRm
(
0
b0110
),
Op2
(
0
b010
),
{
SYS_DESC
(
SYS_DC_CSW
),
access_dcsw
},
access_dcsw
},
{
SYS_DESC
(
SYS_DC_CISW
),
access_dcsw
},
/* DC CSW */
{
Op0
(
0
b01
),
Op1
(
0
b000
),
CRn
(
0
b0111
),
CRm
(
0
b1010
),
Op2
(
0
b010
),
access_dcsw
},
/* DC CISW */
{
Op0
(
0
b01
),
Op1
(
0
b000
),
CRn
(
0
b0111
),
CRm
(
0
b1110
),
Op2
(
0
b010
),
access_dcsw
},
DBG_BCR_BVR_WCR_WVR_EL1
(
0
),
DBG_BCR_BVR_WCR_WVR_EL1
(
0
),
DBG_BCR_BVR_WCR_WVR_EL1
(
1
),
DBG_BCR_BVR_WCR_WVR_EL1
(
1
),
/* MDCCINT_EL1 */
{
SYS_DESC
(
SYS_MDCCINT_EL1
),
trap_debug_regs
,
reset_val
,
MDCCINT_EL1
,
0
},
{
Op0
(
0
b10
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0010
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_MDSCR_EL1
),
trap_debug_regs
,
reset_val
,
MDSCR_EL1
,
0
},
trap_debug_regs
,
reset_val
,
MDCCINT_EL1
,
0
},
/* MDSCR_EL1 */
{
Op0
(
0
b10
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0010
),
Op2
(
0
b010
),
trap_debug_regs
,
reset_val
,
MDSCR_EL1
,
0
},
DBG_BCR_BVR_WCR_WVR_EL1
(
2
),
DBG_BCR_BVR_WCR_WVR_EL1
(
2
),
DBG_BCR_BVR_WCR_WVR_EL1
(
3
),
DBG_BCR_BVR_WCR_WVR_EL1
(
3
),
DBG_BCR_BVR_WCR_WVR_EL1
(
4
),
DBG_BCR_BVR_WCR_WVR_EL1
(
4
),
...
@@ -934,179 +916,77 @@ static const struct sys_reg_desc sys_reg_descs[] = {
...
@@ -934,179 +916,77 @@ static const struct sys_reg_desc sys_reg_descs[] = {
DBG_BCR_BVR_WCR_WVR_EL1
(
14
),
DBG_BCR_BVR_WCR_WVR_EL1
(
14
),
DBG_BCR_BVR_WCR_WVR_EL1
(
15
),
DBG_BCR_BVR_WCR_WVR_EL1
(
15
),
/* MDRAR_EL1 */
{
SYS_DESC
(
SYS_MDRAR_EL1
),
trap_raz_wi
},
{
Op0
(
0
b10
),
Op1
(
0
b000
),
CRn
(
0
b0001
),
CRm
(
0
b0000
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_OSLAR_EL1
),
trap_raz_wi
},
trap_raz_wi
},
{
SYS_DESC
(
SYS_OSLSR_EL1
),
trap_oslsr_el1
},
/* OSLAR_EL1 */
{
SYS_DESC
(
SYS_OSDLR_EL1
),
trap_raz_wi
},
{
Op0
(
0
b10
),
Op1
(
0
b000
),
CRn
(
0
b0001
),
CRm
(
0
b0000
),
Op2
(
0
b100
),
{
SYS_DESC
(
SYS_DBGPRCR_EL1
),
trap_raz_wi
},
trap_raz_wi
},
{
SYS_DESC
(
SYS_DBGCLAIMSET_EL1
),
trap_raz_wi
},
/* OSLSR_EL1 */
{
SYS_DESC
(
SYS_DBGCLAIMCLR_EL1
),
trap_raz_wi
},
{
Op0
(
0
b10
),
Op1
(
0
b000
),
CRn
(
0
b0001
),
CRm
(
0
b0001
),
Op2
(
0
b100
),
{
SYS_DESC
(
SYS_DBGAUTHSTATUS_EL1
),
trap_dbgauthstatus_el1
},
trap_oslsr_el1
},
/* OSDLR_EL1 */
{
SYS_DESC
(
SYS_MDCCSR_EL0
),
trap_raz_wi
},
{
Op0
(
0
b10
),
Op1
(
0
b000
),
CRn
(
0
b0001
),
CRm
(
0
b0011
),
Op2
(
0
b100
),
{
SYS_DESC
(
SYS_DBGDTR_EL0
),
trap_raz_wi
},
trap_raz_wi
},
// DBGDTR[TR]X_EL0 share the same encoding
/* DBGPRCR_EL1 */
{
SYS_DESC
(
SYS_DBGDTRTX_EL0
),
trap_raz_wi
},
{
Op0
(
0
b10
),
Op1
(
0
b000
),
CRn
(
0
b0001
),
CRm
(
0
b0100
),
Op2
(
0
b100
),
trap_raz_wi
},
{
SYS_DESC
(
SYS_DBGVCR32_EL2
),
NULL
,
reset_val
,
DBGVCR32_EL2
,
0
},
/* DBGCLAIMSET_EL1 */
{
Op0
(
0
b10
),
Op1
(
0
b000
),
CRn
(
0
b0111
),
CRm
(
0
b1000
),
Op2
(
0
b110
),
{
SYS_DESC
(
SYS_MPIDR_EL1
),
NULL
,
reset_mpidr
,
MPIDR_EL1
},
trap_raz_wi
},
{
SYS_DESC
(
SYS_SCTLR_EL1
),
access_vm_reg
,
reset_val
,
SCTLR_EL1
,
0x00C50078
},
/* DBGCLAIMCLR_EL1 */
{
SYS_DESC
(
SYS_CPACR_EL1
),
NULL
,
reset_val
,
CPACR_EL1
,
0
},
{
Op0
(
0
b10
),
Op1
(
0
b000
),
CRn
(
0
b0111
),
CRm
(
0
b1001
),
Op2
(
0
b110
),
{
SYS_DESC
(
SYS_TTBR0_EL1
),
access_vm_reg
,
reset_unknown
,
TTBR0_EL1
},
trap_raz_wi
},
{
SYS_DESC
(
SYS_TTBR1_EL1
),
access_vm_reg
,
reset_unknown
,
TTBR1_EL1
},
/* DBGAUTHSTATUS_EL1 */
{
SYS_DESC
(
SYS_TCR_EL1
),
access_vm_reg
,
reset_val
,
TCR_EL1
,
0
},
{
Op0
(
0
b10
),
Op1
(
0
b000
),
CRn
(
0
b0111
),
CRm
(
0
b1110
),
Op2
(
0
b110
),
trap_dbgauthstatus_el1
},
{
SYS_DESC
(
SYS_AFSR0_EL1
),
access_vm_reg
,
reset_unknown
,
AFSR0_EL1
},
{
SYS_DESC
(
SYS_AFSR1_EL1
),
access_vm_reg
,
reset_unknown
,
AFSR1_EL1
},
/* MDCCSR_EL1 */
{
SYS_DESC
(
SYS_ESR_EL1
),
access_vm_reg
,
reset_unknown
,
ESR_EL1
},
{
Op0
(
0
b10
),
Op1
(
0
b011
),
CRn
(
0
b0000
),
CRm
(
0
b0001
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_FAR_EL1
),
access_vm_reg
,
reset_unknown
,
FAR_EL1
},
trap_raz_wi
},
{
SYS_DESC
(
SYS_PAR_EL1
),
NULL
,
reset_unknown
,
PAR_EL1
},
/* DBGDTR_EL0 */
{
Op0
(
0
b10
),
Op1
(
0
b011
),
CRn
(
0
b0000
),
CRm
(
0
b0100
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_PMINTENSET_EL1
),
access_pminten
,
reset_unknown
,
PMINTENSET_EL1
},
trap_raz_wi
},
{
SYS_DESC
(
SYS_PMINTENCLR_EL1
),
access_pminten
,
NULL
,
PMINTENSET_EL1
},
/* DBGDTR[TR]X_EL0 */
{
Op0
(
0
b10
),
Op1
(
0
b011
),
CRn
(
0
b0000
),
CRm
(
0
b0101
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_MAIR_EL1
),
access_vm_reg
,
reset_unknown
,
MAIR_EL1
},
trap_raz_wi
},
{
SYS_DESC
(
SYS_AMAIR_EL1
),
access_vm_reg
,
reset_amair_el1
,
AMAIR_EL1
},
/* DBGVCR32_EL2 */
{
SYS_DESC
(
SYS_VBAR_EL1
),
NULL
,
reset_val
,
VBAR_EL1
,
0
},
{
Op0
(
0
b10
),
Op1
(
0
b100
),
CRn
(
0
b0000
),
CRm
(
0
b0111
),
Op2
(
0
b000
),
NULL
,
reset_val
,
DBGVCR32_EL2
,
0
},
{
SYS_DESC
(
SYS_ICC_SGI1R_EL1
),
access_gic_sgi
},
{
SYS_DESC
(
SYS_ICC_SRE_EL1
),
access_gic_sre
},
/* MPIDR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0000
),
Op2
(
0
b101
),
{
SYS_DESC
(
SYS_CONTEXTIDR_EL1
),
access_vm_reg
,
reset_val
,
CONTEXTIDR_EL1
,
0
},
NULL
,
reset_mpidr
,
MPIDR_EL1
},
{
SYS_DESC
(
SYS_TPIDR_EL1
),
NULL
,
reset_unknown
,
TPIDR_EL1
},
/* SCTLR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0001
),
CRm
(
0
b0000
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_CNTKCTL_EL1
),
NULL
,
reset_val
,
CNTKCTL_EL1
,
0
},
access_vm_reg
,
reset_val
,
SCTLR_EL1
,
0x00C50078
},
/* CPACR_EL1 */
{
SYS_DESC
(
SYS_CSSELR_EL1
),
NULL
,
reset_unknown
,
CSSELR_EL1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0001
),
CRm
(
0
b0000
),
Op2
(
0
b010
),
NULL
,
reset_val
,
CPACR_EL1
,
0
},
{
SYS_DESC
(
SYS_PMCR_EL0
),
access_pmcr
,
reset_pmcr
,
},
/* TTBR0_EL1 */
{
SYS_DESC
(
SYS_PMCNTENSET_EL0
),
access_pmcnten
,
reset_unknown
,
PMCNTENSET_EL0
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0010
),
CRm
(
0
b0000
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_PMCNTENCLR_EL0
),
access_pmcnten
,
NULL
,
PMCNTENSET_EL0
},
access_vm_reg
,
reset_unknown
,
TTBR0_EL1
},
{
SYS_DESC
(
SYS_PMOVSCLR_EL0
),
access_pmovs
,
NULL
,
PMOVSSET_EL0
},
/* TTBR1_EL1 */
{
SYS_DESC
(
SYS_PMSWINC_EL0
),
access_pmswinc
,
reset_unknown
,
PMSWINC_EL0
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0010
),
CRm
(
0
b0000
),
Op2
(
0
b001
),
{
SYS_DESC
(
SYS_PMSELR_EL0
),
access_pmselr
,
reset_unknown
,
PMSELR_EL0
},
access_vm_reg
,
reset_unknown
,
TTBR1_EL1
},
{
SYS_DESC
(
SYS_PMCEID0_EL0
),
access_pmceid
},
/* TCR_EL1 */
{
SYS_DESC
(
SYS_PMCEID1_EL0
),
access_pmceid
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0010
),
CRm
(
0
b0000
),
Op2
(
0
b010
),
{
SYS_DESC
(
SYS_PMCCNTR_EL0
),
access_pmu_evcntr
,
reset_unknown
,
PMCCNTR_EL0
},
access_vm_reg
,
reset_val
,
TCR_EL1
,
0
},
{
SYS_DESC
(
SYS_PMXEVTYPER_EL0
),
access_pmu_evtyper
},
{
SYS_DESC
(
SYS_PMXEVCNTR_EL0
),
access_pmu_evcntr
},
/* AFSR0_EL1 */
/*
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0101
),
CRm
(
0
b0001
),
Op2
(
0
b000
),
* PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
access_vm_reg
,
reset_unknown
,
AFSR0_EL1
},
/* AFSR1_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0101
),
CRm
(
0
b0001
),
Op2
(
0
b001
),
access_vm_reg
,
reset_unknown
,
AFSR1_EL1
},
/* ESR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0101
),
CRm
(
0
b0010
),
Op2
(
0
b000
),
access_vm_reg
,
reset_unknown
,
ESR_EL1
},
/* FAR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0110
),
CRm
(
0
b0000
),
Op2
(
0
b000
),
access_vm_reg
,
reset_unknown
,
FAR_EL1
},
/* PAR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0111
),
CRm
(
0
b0100
),
Op2
(
0
b000
),
NULL
,
reset_unknown
,
PAR_EL1
},
/* PMINTENSET_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b1001
),
CRm
(
0
b1110
),
Op2
(
0
b001
),
access_pminten
,
reset_unknown
,
PMINTENSET_EL1
},
/* PMINTENCLR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b1001
),
CRm
(
0
b1110
),
Op2
(
0
b010
),
access_pminten
,
NULL
,
PMINTENSET_EL1
},
/* MAIR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b1010
),
CRm
(
0
b0010
),
Op2
(
0
b000
),
access_vm_reg
,
reset_unknown
,
MAIR_EL1
},
/* AMAIR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b1010
),
CRm
(
0
b0011
),
Op2
(
0
b000
),
access_vm_reg
,
reset_amair_el1
,
AMAIR_EL1
},
/* VBAR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b1100
),
CRm
(
0
b0000
),
Op2
(
0
b000
),
NULL
,
reset_val
,
VBAR_EL1
,
0
},
/* ICC_SGI1R_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b1100
),
CRm
(
0
b1011
),
Op2
(
0
b101
),
access_gic_sgi
},
/* ICC_SRE_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b1100
),
CRm
(
0
b1100
),
Op2
(
0
b101
),
access_gic_sre
},
/* CONTEXTIDR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b1101
),
CRm
(
0
b0000
),
Op2
(
0
b001
),
access_vm_reg
,
reset_val
,
CONTEXTIDR_EL1
,
0
},
/* TPIDR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b1101
),
CRm
(
0
b0000
),
Op2
(
0
b100
),
NULL
,
reset_unknown
,
TPIDR_EL1
},
/* CNTKCTL_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b1110
),
CRm
(
0
b0001
),
Op2
(
0
b000
),
NULL
,
reset_val
,
CNTKCTL_EL1
,
0
},
/* CSSELR_EL1 */
{
Op0
(
0
b11
),
Op1
(
0
b010
),
CRn
(
0
b0000
),
CRm
(
0
b0000
),
Op2
(
0
b000
),
NULL
,
reset_unknown
,
CSSELR_EL1
},
/* PMCR_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1100
),
Op2
(
0
b000
),
access_pmcr
,
reset_pmcr
,
},
/* PMCNTENSET_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1100
),
Op2
(
0
b001
),
access_pmcnten
,
reset_unknown
,
PMCNTENSET_EL0
},
/* PMCNTENCLR_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1100
),
Op2
(
0
b010
),
access_pmcnten
,
NULL
,
PMCNTENSET_EL0
},
/* PMOVSCLR_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1100
),
Op2
(
0
b011
),
access_pmovs
,
NULL
,
PMOVSSET_EL0
},
/* PMSWINC_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1100
),
Op2
(
0
b100
),
access_pmswinc
,
reset_unknown
,
PMSWINC_EL0
},
/* PMSELR_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1100
),
Op2
(
0
b101
),
access_pmselr
,
reset_unknown
,
PMSELR_EL0
},
/* PMCEID0_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1100
),
Op2
(
0
b110
),
access_pmceid
},
/* PMCEID1_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1100
),
Op2
(
0
b111
),
access_pmceid
},
/* PMCCNTR_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1101
),
Op2
(
0
b000
),
access_pmu_evcntr
,
reset_unknown
,
PMCCNTR_EL0
},
/* PMXEVTYPER_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1101
),
Op2
(
0
b001
),
access_pmu_evtyper
},
/* PMXEVCNTR_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1101
),
Op2
(
0
b010
),
access_pmu_evcntr
},
/* PMUSERENR_EL0
* This register resets as unknown in 64bit mode while it resets as zero
* in 32bit mode. Here we choose to reset it as zero for consistency.
* in 32bit mode. Here we choose to reset it as zero for consistency.
*/
*/
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1110
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_PMUSERENR_EL0
),
access_pmuserenr
,
reset_val
,
PMUSERENR_EL0
,
0
},
access_pmuserenr
,
reset_val
,
PMUSERENR_EL0
,
0
},
{
SYS_DESC
(
SYS_PMOVSSET_EL0
),
access_pmovs
,
reset_unknown
,
PMOVSSET_EL0
},
/* PMOVSSET_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1001
),
CRm
(
0
b1110
),
Op2
(
0
b011
),
{
SYS_DESC
(
SYS_TPIDR_EL0
),
NULL
,
reset_unknown
,
TPIDR_EL0
},
access_pmovs
,
reset_unknown
,
PMOVSSET_EL0
},
{
SYS_DESC
(
SYS_TPIDRRO_EL0
),
NULL
,
reset_unknown
,
TPIDRRO_EL0
},
/* TPIDR_EL0 */
{
SYS_DESC
(
SYS_CNTP_TVAL_EL0
),
access_cntp_tval
},
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1101
),
CRm
(
0
b0000
),
Op2
(
0
b010
),
{
SYS_DESC
(
SYS_CNTP_CTL_EL0
),
access_cntp_ctl
},
NULL
,
reset_unknown
,
TPIDR_EL0
},
{
SYS_DESC
(
SYS_CNTP_CVAL_EL0
),
access_cntp_cval
},
/* TPIDRRO_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1101
),
CRm
(
0
b0000
),
Op2
(
0
b011
),
NULL
,
reset_unknown
,
TPIDRRO_EL0
},
/* CNTP_TVAL_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1110
),
CRm
(
0
b0010
),
Op2
(
0
b000
),
access_cntp_tval
},
/* CNTP_CTL_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1110
),
CRm
(
0
b0010
),
Op2
(
0
b001
),
access_cntp_ctl
},
/* CNTP_CVAL_EL0 */
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1110
),
CRm
(
0
b0010
),
Op2
(
0
b010
),
access_cntp_cval
},
/* PMEVCNTRn_EL0 */
/* PMEVCNTRn_EL0 */
PMU_PMEVCNTR_EL0
(
0
),
PMU_PMEVCNTR_EL0
(
0
),
...
@@ -1172,22 +1052,15 @@ static const struct sys_reg_desc sys_reg_descs[] = {
...
@@ -1172,22 +1052,15 @@ static const struct sys_reg_desc sys_reg_descs[] = {
PMU_PMEVTYPER_EL0
(
28
),
PMU_PMEVTYPER_EL0
(
28
),
PMU_PMEVTYPER_EL0
(
29
),
PMU_PMEVTYPER_EL0
(
29
),
PMU_PMEVTYPER_EL0
(
30
),
PMU_PMEVTYPER_EL0
(
30
),
/*
PMCCFILTR_EL0
/*
*
This register
resets as unknown in 64bit mode while it resets as zero
*
PMCCFILTR_EL0
resets as unknown in 64bit mode while it resets as zero
* in 32bit mode. Here we choose to reset it as zero for consistency.
* in 32bit mode. Here we choose to reset it as zero for consistency.
*/
*/
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b1110
),
CRm
(
0
b1111
),
Op2
(
0
b111
),
{
SYS_DESC
(
SYS_PMCCFILTR_EL0
),
access_pmu_evtyper
,
reset_val
,
PMCCFILTR_EL0
,
0
},
access_pmu_evtyper
,
reset_val
,
PMCCFILTR_EL0
,
0
},
{
SYS_DESC
(
SYS_DACR32_EL2
),
NULL
,
reset_unknown
,
DACR32_EL2
},
/* DACR32_EL2 */
{
SYS_DESC
(
SYS_IFSR32_EL2
),
NULL
,
reset_unknown
,
IFSR32_EL2
},
{
Op0
(
0
b11
),
Op1
(
0
b100
),
CRn
(
0
b0011
),
CRm
(
0
b0000
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_FPEXC32_EL2
),
NULL
,
reset_val
,
FPEXC32_EL2
,
0x70
},
NULL
,
reset_unknown
,
DACR32_EL2
},
/* IFSR32_EL2 */
{
Op0
(
0
b11
),
Op1
(
0
b100
),
CRn
(
0
b0101
),
CRm
(
0
b0000
),
Op2
(
0
b001
),
NULL
,
reset_unknown
,
IFSR32_EL2
},
/* FPEXC32_EL2 */
{
Op0
(
0
b11
),
Op1
(
0
b100
),
CRn
(
0
b0101
),
CRm
(
0
b0011
),
Op2
(
0
b000
),
NULL
,
reset_val
,
FPEXC32_EL2
,
0x70
},
};
};
static
bool
trap_dbgidr
(
struct
kvm_vcpu
*
vcpu
,
static
bool
trap_dbgidr
(
struct
kvm_vcpu
*
vcpu
,
...
@@ -1942,44 +1815,25 @@ FUNCTION_INVARIANT(aidr_el1)
...
@@ -1942,44 +1815,25 @@ FUNCTION_INVARIANT(aidr_el1)
/* ->val is filled in by kvm_sys_reg_table_init() */
/* ->val is filled in by kvm_sys_reg_table_init() */
static
struct
sys_reg_desc
invariant_sys_regs
[]
=
{
static
struct
sys_reg_desc
invariant_sys_regs
[]
=
{
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0000
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_MIDR_EL1
),
NULL
,
get_midr_el1
},
NULL
,
get_midr_el1
},
{
SYS_DESC
(
SYS_REVIDR_EL1
),
NULL
,
get_revidr_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0000
),
Op2
(
0
b110
),
{
SYS_DESC
(
SYS_ID_PFR0_EL1
),
NULL
,
get_id_pfr0_el1
},
NULL
,
get_revidr_el1
},
{
SYS_DESC
(
SYS_ID_PFR1_EL1
),
NULL
,
get_id_pfr1_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0001
),
Op2
(
0
b000
),
{
SYS_DESC
(
SYS_ID_DFR0_EL1
),
NULL
,
get_id_dfr0_el1
},
NULL
,
get_id_pfr0_el1
},
{
SYS_DESC
(
SYS_ID_AFR0_EL1
),
NULL
,
get_id_afr0_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0001
),
Op2
(
0
b001
),
{
SYS_DESC
(
SYS_ID_MMFR0_EL1
),
NULL
,
get_id_mmfr0_el1
},
NULL
,
get_id_pfr1_el1
},
{
SYS_DESC
(
SYS_ID_MMFR1_EL1
),
NULL
,
get_id_mmfr1_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0001
),
Op2
(
0
b010
),
{
SYS_DESC
(
SYS_ID_MMFR2_EL1
),
NULL
,
get_id_mmfr2_el1
},
NULL
,
get_id_dfr0_el1
},
{
SYS_DESC
(
SYS_ID_MMFR3_EL1
),
NULL
,
get_id_mmfr3_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0001
),
Op2
(
0
b011
),
{
SYS_DESC
(
SYS_ID_ISAR0_EL1
),
NULL
,
get_id_isar0_el1
},
NULL
,
get_id_afr0_el1
},
{
SYS_DESC
(
SYS_ID_ISAR1_EL1
),
NULL
,
get_id_isar1_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0001
),
Op2
(
0
b100
),
{
SYS_DESC
(
SYS_ID_ISAR2_EL1
),
NULL
,
get_id_isar2_el1
},
NULL
,
get_id_mmfr0_el1
},
{
SYS_DESC
(
SYS_ID_ISAR3_EL1
),
NULL
,
get_id_isar3_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0001
),
Op2
(
0
b101
),
{
SYS_DESC
(
SYS_ID_ISAR4_EL1
),
NULL
,
get_id_isar4_el1
},
NULL
,
get_id_mmfr1_el1
},
{
SYS_DESC
(
SYS_ID_ISAR5_EL1
),
NULL
,
get_id_isar5_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0001
),
Op2
(
0
b110
),
{
SYS_DESC
(
SYS_CLIDR_EL1
),
NULL
,
get_clidr_el1
},
NULL
,
get_id_mmfr2_el1
},
{
SYS_DESC
(
SYS_AIDR_EL1
),
NULL
,
get_aidr_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0001
),
Op2
(
0
b111
),
{
SYS_DESC
(
SYS_CTR_EL0
),
NULL
,
get_ctr_el0
},
NULL
,
get_id_mmfr3_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0010
),
Op2
(
0
b000
),
NULL
,
get_id_isar0_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0010
),
Op2
(
0
b001
),
NULL
,
get_id_isar1_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0010
),
Op2
(
0
b010
),
NULL
,
get_id_isar2_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0010
),
Op2
(
0
b011
),
NULL
,
get_id_isar3_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0010
),
Op2
(
0
b100
),
NULL
,
get_id_isar4_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0000
),
CRm
(
0
b0010
),
Op2
(
0
b101
),
NULL
,
get_id_isar5_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b001
),
CRn
(
0
b0000
),
CRm
(
0
b0000
),
Op2
(
0
b001
),
NULL
,
get_clidr_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b001
),
CRn
(
0
b0000
),
CRm
(
0
b0000
),
Op2
(
0
b111
),
NULL
,
get_aidr_el1
},
{
Op0
(
0
b11
),
Op1
(
0
b011
),
CRn
(
0
b0000
),
CRm
(
0
b0000
),
Op2
(
0
b001
),
NULL
,
get_ctr_el0
},
};
};
static
int
reg_from_user
(
u64
*
val
,
const
void
__user
*
uaddr
,
u64
id
)
static
int
reg_from_user
(
u64
*
val
,
const
void
__user
*
uaddr
,
u64
id
)
...
...
arch/arm64/kvm/sys_regs.h
View file @
5f6e0070
...
@@ -129,4 +129,9 @@ const struct sys_reg_desc *find_reg_by_id(u64 id,
...
@@ -129,4 +129,9 @@ const struct sys_reg_desc *find_reg_by_id(u64 id,
#define CRm(_x) .CRm = _x
#define CRm(_x) .CRm = _x
#define Op2(_x) .Op2 = _x
#define Op2(_x) .Op2 = _x
#define SYS_DESC(reg) \
Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \
Op2(sys_reg_Op2(reg))
#endif
/* __ARM64_KVM_SYS_REGS_LOCAL_H__ */
#endif
/* __ARM64_KVM_SYS_REGS_LOCAL_H__ */
arch/arm64/kvm/sys_regs_generic_v8.c
View file @
5f6e0070
...
@@ -52,9 +52,7 @@ static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
...
@@ -52,9 +52,7 @@ static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
*/
*/
static
const
struct
sys_reg_desc
genericv8_sys_regs
[]
=
{
static
const
struct
sys_reg_desc
genericv8_sys_regs
[]
=
{
/* ACTLR_EL1 */
{
SYS_DESC
(
SYS_ACTLR_EL1
),
access_actlr
,
reset_actlr
,
ACTLR_EL1
},
{
Op0
(
0
b11
),
Op1
(
0
b000
),
CRn
(
0
b0001
),
CRm
(
0
b0000
),
Op2
(
0
b001
),
access_actlr
,
reset_actlr
,
ACTLR_EL1
},
};
};
static
const
struct
sys_reg_desc
genericv8_cp15_regs
[]
=
{
static
const
struct
sys_reg_desc
genericv8_cp15_regs
[]
=
{
...
...
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