Commit 60b3df9c authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Ingo Molnar

perf_counter: add comment to barrier

We need to ensure the enabled=0 write happens before we
start disabling the actual counters, so that a pcm_amd_enable()
will not enable one underneath us.

I think the race is impossible anyway, we always balance the
ops within any one context and perform enable() with IRQs disabled.
Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 75564232
...@@ -247,6 +247,10 @@ static u64 pmc_amd_save_disable_all(void) ...@@ -247,6 +247,10 @@ static u64 pmc_amd_save_disable_all(void)
enabled = cpuc->enabled; enabled = cpuc->enabled;
cpuc->enabled = 0; cpuc->enabled = 0;
/*
* ensure we write the disable before we start disabling the
* counters proper, so that pcm_amd_enable() does the right thing.
*/
barrier(); barrier();
for (idx = 0; idx < nr_counters_generic; idx++) { for (idx = 0; idx < nr_counters_generic; idx++) {
......
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