Commit 62a3213a authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher

drm/amd/display: Rename DCN TG specific function prefixes to tg

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c3aa1d67
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
#define DCN10TG_FROM_TG(tg)\ #define DCN10TG_FROM_TG(tg)\
container_of(tg, struct dcn10_timing_generator, base) container_of(tg, struct dcn10_timing_generator, base)
#define TG_COMMON_REG_LIST_DCN1_0(inst) \ #define TG_COMMON_REG_LIST_DCN(inst) \
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
SRI(OTG_VUPDATE_PARAM, OTG, inst),\ SRI(OTG_VUPDATE_PARAM, OTG, inst),\
SRI(OTG_VREADY_PARAM, OTG, inst),\ SRI(OTG_VREADY_PARAM, OTG, inst),\
...@@ -64,9 +64,6 @@ ...@@ -64,9 +64,6 @@
SRI(OTG_STATUS_POSITION, OTG, inst),\ SRI(OTG_STATUS_POSITION, OTG, inst),\
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
SRI(OTG_BLACK_COLOR, OTG, inst),\ SRI(OTG_BLACK_COLOR, OTG, inst),\
SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
SRI(OTG_CLOCK_CONTROL, OTG, inst),\ SRI(OTG_CLOCK_CONTROL, OTG, inst),\
SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
...@@ -76,7 +73,14 @@ ...@@ -76,7 +73,14 @@
SR(D1VGA_CONTROL),\ SR(D1VGA_CONTROL),\
SR(D2VGA_CONTROL),\ SR(D2VGA_CONTROL),\
SR(D3VGA_CONTROL),\ SR(D3VGA_CONTROL),\
SR(D4VGA_CONTROL),\ SR(D4VGA_CONTROL)
#define TG_COMMON_REG_LIST_DCN1_0(inst) \
TG_COMMON_REG_LIST_DCN(inst),\
SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
SRI(OTG_TEST_PATTERN_COLOR, OTG, inst)
struct dcn_tg_registers { struct dcn_tg_registers {
uint32_t OTG_VSTARTUP_PARAM; uint32_t OTG_VSTARTUP_PARAM;
...@@ -127,7 +131,7 @@ struct dcn_tg_registers { ...@@ -127,7 +131,7 @@ struct dcn_tg_registers {
uint32_t D4VGA_CONTROL; uint32_t D4VGA_CONTROL;
}; };
#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
...@@ -192,17 +196,6 @@ struct dcn_tg_registers { ...@@ -192,17 +196,6 @@ struct dcn_tg_registers {
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\ SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\ SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\ SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
...@@ -210,12 +203,26 @@ struct dcn_tg_registers { ...@@ -210,12 +203,26 @@ struct dcn_tg_registers {
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\
SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\ SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh)
#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh)
#define TG_REG_FIELD_LIST(type) \ #define TG_REG_FIELD_LIST(type) \
type VSTARTUP_START;\ type VSTARTUP_START;\
...@@ -300,11 +307,12 @@ struct dcn_tg_registers { ...@@ -300,11 +307,12 @@ struct dcn_tg_registers {
type OPTC_INPUT_CLK_ON;\ type OPTC_INPUT_CLK_ON;\
type OPTC_INPUT_CLK_GATE_DIS;\ type OPTC_INPUT_CLK_GATE_DIS;\
type OPTC_SRC_SEL;\ type OPTC_SRC_SEL;\
type OPTC_SEG0_SRC_SEL;\
type OPPBUF_ACTIVE_WIDTH;\ type OPPBUF_ACTIVE_WIDTH;\
type OPPBUF_3D_VACT_SPACE1_SIZE;\ type OPPBUF_3D_VACT_SPACE1_SIZE;\
type VTG0_ENABLE;\ type VTG0_ENABLE;\
type VTG0_FP2;\ type VTG0_FP2;\
type VTG0_VCOUNT_INIT;\ type VTG0_VCOUNT_INIT;
struct dcn_tg_shift { struct dcn_tg_shift {
TG_REG_FIELD_LIST(uint8_t) TG_REG_FIELD_LIST(uint8_t)
...@@ -336,9 +344,4 @@ struct dcn10_timing_generator { ...@@ -336,9 +344,4 @@ struct dcn10_timing_generator {
void dcn10_timing_generator_init(struct dcn10_timing_generator *tg); void dcn10_timing_generator_init(struct dcn10_timing_generator *tg);
void dcn10_timing_generator_set_drr(struct timing_generator *tg,
const struct drr_params *params);
void dcn10_unlock(struct timing_generator *tg);
void dcn10_lock(struct timing_generator *tg);
#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
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