Commit 662c6ecb authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter

drm/i915/vlv: fix up broken precision in vlv_crtc_clock_get

With some divider values we end up with the wrong result.  So remove the
intermediates (like Ville suggested in the first place) to get the right
answer.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent acbec814
...@@ -5084,7 +5084,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, ...@@ -5084,7 +5084,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
int pipe = pipe_config->cpu_transcoder; int pipe = pipe_config->cpu_transcoder;
intel_clock_t clock; intel_clock_t clock;
u32 mdiv; u32 mdiv;
int refclk = 100000, fastclk, update_rate; int refclk = 100000;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->dpio_lock);
mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe)); mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
...@@ -5096,10 +5096,8 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, ...@@ -5096,10 +5096,8 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
update_rate = refclk / clock.n; clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
clock.vco = update_rate * clock.m1 * clock.m2; clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
fastclk = clock.vco / clock.p1 / clock.p2;
clock.dot = (2 * fastclk);
pipe_config->port_clock = clock.dot / 10; pipe_config->port_clock = clock.dot / 10;
} }
......
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