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Commit 67e06f62 authored by Tony Lindgren's avatar Tony Lindgren Committed by Russell King
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[ARM PATCH] 2195/1: Updates to OMAP clock framework 

Patch from Tony Lindgren

This patch by Tuukka Tikkanen updates the OMAP clock framework.
It also contains a patch by Juha Yrjölä to enable 216MHz rate
on 16xx.

Signed-off-by: Tony Lindgren 
Signed-off-by: Russell King
parent 3f6b53b0
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Inline Side-by-side
Showing with 72 additions and 64 deletions
arch/arm/mach-omap/clock.c
View file @ 67e06f62
...@@ -33,6 +33,9 @@ struct mpu_rate rate_table[] = { ...@@ -33,6 +33,9 @@ struct mpu_rate rate_table[] = {
/* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
* armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
*/ */
#if defined(CONFIG_OMAP_ARM_216MHZ) && defined(CONFIG_ARCH_OMAP16XX)
{ 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
#endif
#if defined(CONFIG_OMAP_ARM_195MHZ) && defined(CONFIG_ARCH_OMAP730) #if defined(CONFIG_OMAP_ARM_195MHZ) && defined(CONFIG_ARCH_OMAP730)
{ 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
#endif #endif
...@@ -95,19 +98,21 @@ static void watchdog_recalc(struct clk * clk) ...@@ -95,19 +98,21 @@ static void watchdog_recalc(struct clk * clk)
static struct clk ck_ref = { static struct clk ck_ref = {
.name = "ck_ref", .name = "ck_ref",
.rate = 12000000, .rate = 12000000,
.flags = ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
ALWAYS_ENABLED,
}; };
static struct clk ck_dpll1 = { static struct clk ck_dpll1 = {
.name = "ck_dpll1", .name = "ck_dpll1",
.parent = &ck_ref, .parent = &ck_ref,
.flags = RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_PROPAGATES | ALWAYS_ENABLED,
}; };
static struct clk ck_dpll1out = { static struct clk ck_dpll1out = {
.name = "ck_dpll1out", .name = "ck_dpll1out",
.parent = &ck_dpll1, .parent = &ck_dpll1,
.flags = DOES_NOT_EXIST_ON_1510, .flags = CLOCK_IN_OMAP16XX,
.enable_reg = ARM_IDLECT2, .enable_reg = ARM_IDLECT2,
.enable_bit = EN_CKOUT_ARM, .enable_bit = EN_CKOUT_ARM,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -116,7 +121,8 @@ static struct clk ck_dpll1out = { ...@@ -116,7 +121,8 @@ static struct clk ck_dpll1out = {
static struct clk arm_ck = { static struct clk arm_ck = {
.name = "arm_ck", .name = "arm_ck",
.parent = &ck_dpll1, .parent = &ck_dpll1,
.flags = RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
.rate_offset = CKCTL_ARMDIV_OFFSET, .rate_offset = CKCTL_ARMDIV_OFFSET,
.recalc = &ckctl_recalc, .recalc = &ckctl_recalc,
}; };
...@@ -124,7 +130,8 @@ static struct clk arm_ck = { ...@@ -124,7 +130,8 @@ static struct clk arm_ck = {
static struct clk armper_ck = { static struct clk armper_ck = {
.name = "armper_ck", .name = "armper_ck",
.parent = &ck_dpll1, .parent = &ck_dpll1,
.flags = RATE_CKCTL, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_CKCTL,
.enable_reg = ARM_IDLECT2, .enable_reg = ARM_IDLECT2,
.enable_bit = EN_PERCK, .enable_bit = EN_PERCK,
.rate_offset = CKCTL_PERDIV_OFFSET, .rate_offset = CKCTL_PERDIV_OFFSET,
...@@ -134,7 +141,7 @@ static struct clk armper_ck = { ...@@ -134,7 +141,7 @@ static struct clk armper_ck = {
static struct clk arm_gpio_ck = { static struct clk arm_gpio_ck = {
.name = "arm_gpio_ck", .name = "arm_gpio_ck",
.parent = &ck_dpll1, .parent = &ck_dpll1,
.flags = DOES_NOT_EXIST_ON_1610, .flags = CLOCK_IN_OMAP1510,
.enable_reg = ARM_IDLECT2, .enable_reg = ARM_IDLECT2,
.enable_bit = EN_GPIOCK, .enable_bit = EN_GPIOCK,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -143,6 +150,7 @@ static struct clk arm_gpio_ck = { ...@@ -143,6 +150,7 @@ static struct clk arm_gpio_ck = {
static struct clk armxor_ck = { static struct clk armxor_ck = {
.name = "armxor_ck", .name = "armxor_ck",
.parent = &ck_ref, .parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
.enable_reg = ARM_IDLECT2, .enable_reg = ARM_IDLECT2,
.enable_bit = EN_XORPCK, .enable_bit = EN_XORPCK,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -151,6 +159,7 @@ static struct clk armxor_ck = { ...@@ -151,6 +159,7 @@ static struct clk armxor_ck = {
static struct clk armtim_ck = { static struct clk armtim_ck = {
.name = "armtim_ck", .name = "armtim_ck",
.parent = &ck_ref, .parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
.enable_reg = ARM_IDLECT2, .enable_reg = ARM_IDLECT2,
.enable_bit = EN_TIMCK, .enable_bit = EN_TIMCK,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -159,6 +168,7 @@ static struct clk armtim_ck = { ...@@ -159,6 +168,7 @@ static struct clk armtim_ck = {
static struct clk armwdt_ck = { static struct clk armwdt_ck = {
.name = "armwdt_ck", .name = "armwdt_ck",
.parent = &ck_ref, .parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
.enable_reg = ARM_IDLECT2, .enable_reg = ARM_IDLECT2,
.enable_bit = EN_WDTCK, .enable_bit = EN_WDTCK,
.recalc = &watchdog_recalc, .recalc = &watchdog_recalc,
...@@ -167,7 +177,7 @@ static struct clk armwdt_ck = { ...@@ -167,7 +177,7 @@ static struct clk armwdt_ck = {
static struct clk arminth_ck1610 = { static struct clk arminth_ck1610 = {
.name = "arminth_ck", .name = "arminth_ck",
.parent = &arm_ck, .parent = &arm_ck,
.flags = DOES_NOT_EXIST_ON_1510, .flags = CLOCK_IN_OMAP16XX,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
/* Note: On 1610/1710 frequency can be divided by 2 by programming /* Note: On 1610/1710 frequency can be divided by 2 by programming
* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
...@@ -179,7 +189,8 @@ static struct clk arminth_ck1610 = { ...@@ -179,7 +189,8 @@ static struct clk arminth_ck1610 = {
static struct clk dsp_ck = { static struct clk dsp_ck = {
.name = "dsp_ck", .name = "dsp_ck",
.parent = &ck_dpll1, .parent = &ck_dpll1,
.flags = RATE_CKCTL, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_CKCTL,
.enable_reg = ARM_CKCTL, .enable_reg = ARM_CKCTL,
.enable_bit = EN_DSPCK, .enable_bit = EN_DSPCK,
.rate_offset = CKCTL_DSPDIV_OFFSET, .rate_offset = CKCTL_DSPDIV_OFFSET,
...@@ -189,7 +200,8 @@ static struct clk dsp_ck = { ...@@ -189,7 +200,8 @@ static struct clk dsp_ck = {
static struct clk dspmmu_ck = { static struct clk dspmmu_ck = {
.name = "dspmmu_ck", .name = "dspmmu_ck",
.parent = &ck_dpll1, .parent = &ck_dpll1,
.flags = RATE_CKCTL | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_CKCTL | ALWAYS_ENABLED,
.rate_offset = CKCTL_DSPMMUDIV_OFFSET, .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
.recalc = &ckctl_recalc, .recalc = &ckctl_recalc,
}; };
...@@ -197,7 +209,8 @@ static struct clk dspmmu_ck = { ...@@ -197,7 +209,8 @@ static struct clk dspmmu_ck = {
static struct clk tc_ck = { static struct clk tc_ck = {
.name = "tc_ck", .name = "tc_ck",
.parent = &ck_dpll1, .parent = &ck_dpll1,
.flags = RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
.rate_offset = CKCTL_TCDIV_OFFSET, .rate_offset = CKCTL_TCDIV_OFFSET,
.recalc = &ckctl_recalc, .recalc = &ckctl_recalc,
}; };
...@@ -205,7 +218,7 @@ static struct clk tc_ck = { ...@@ -205,7 +218,7 @@ static struct clk tc_ck = {
static struct clk arminth_ck1510 = { static struct clk arminth_ck1510 = {
.name = "arminth_ck", .name = "arminth_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = DOES_NOT_EXIST_ON_1610, .flags = CLOCK_IN_OMAP1510,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
/* Note: On 1510 frequency follows TC_CK /* Note: On 1510 frequency follows TC_CK
* *
...@@ -216,14 +229,14 @@ static struct clk arminth_ck1510 = { ...@@ -216,14 +229,14 @@ static struct clk arminth_ck1510 = {
static struct clk tipb_ck = { static struct clk tipb_ck = {
.name = "tibp_ck", .name = "tibp_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = DOES_NOT_EXIST_ON_1610, .flags = CLOCK_IN_OMAP1510,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk l3_ocpi_ck = { static struct clk l3_ocpi_ck = {
.name = "l3_ocpi_ck", .name = "l3_ocpi_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = DOES_NOT_EXIST_ON_1510, .flags = CLOCK_IN_OMAP16XX,
.enable_reg = ARM_IDLECT3, .enable_reg = ARM_IDLECT3,
.enable_bit = EN_OCPI_CK, .enable_bit = EN_OCPI_CK,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -232,7 +245,7 @@ static struct clk l3_ocpi_ck = { ...@@ -232,7 +245,7 @@ static struct clk l3_ocpi_ck = {
static struct clk tc1_ck = { static struct clk tc1_ck = {
.name = "tc1_ck", .name = "tc1_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = DOES_NOT_EXIST_ON_1510, .flags = CLOCK_IN_OMAP16XX,
.enable_reg = ARM_IDLECT3, .enable_reg = ARM_IDLECT3,
.enable_bit = EN_TC1_CK, .enable_bit = EN_TC1_CK,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -241,7 +254,7 @@ static struct clk tc1_ck = { ...@@ -241,7 +254,7 @@ static struct clk tc1_ck = {
static struct clk tc2_ck = { static struct clk tc2_ck = {
.name = "tc2_ck", .name = "tc2_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = DOES_NOT_EXIST_ON_1510, .flags = CLOCK_IN_OMAP16XX,
.enable_reg = ARM_IDLECT3, .enable_reg = ARM_IDLECT3,
.enable_bit = EN_TC2_CK, .enable_bit = EN_TC2_CK,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -250,19 +263,21 @@ static struct clk tc2_ck = { ...@@ -250,19 +263,21 @@ static struct clk tc2_ck = {
static struct clk dma_ck = { static struct clk dma_ck = {
.name = "dma_ck", .name = "dma_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk dma_lcdfree_ck = { static struct clk dma_lcdfree_ck = {
.name = "dma_lcdfree_ck", .name = "dma_lcdfree_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = DOES_NOT_EXIST_ON_1510, .flags = CLOCK_IN_OMAP16XX,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk api_ck = { static struct clk api_ck = {
.name = "api_ck", .name = "api_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
.enable_reg = ARM_IDLECT2, .enable_reg = ARM_IDLECT2,
.enable_bit = EN_APICK, .enable_bit = EN_APICK,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -271,7 +286,7 @@ static struct clk api_ck = { ...@@ -271,7 +286,7 @@ static struct clk api_ck = {
static struct clk lb_ck = { static struct clk lb_ck = {
.name = "lb_ck", .name = "lb_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = DOES_NOT_EXIST_ON_1610, .flags = CLOCK_IN_OMAP1510,
.enable_reg = ARM_IDLECT2, .enable_reg = ARM_IDLECT2,
.enable_bit = EN_LBCK, .enable_bit = EN_LBCK,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
...@@ -280,21 +295,22 @@ static struct clk lb_ck = { ...@@ -280,21 +295,22 @@ static struct clk lb_ck = {
static struct clk rhea1_ck = { static struct clk rhea1_ck = {
.name = "rhea1_ck", .name = "rhea1_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = DOES_NOT_EXIST_ON_1510, .flags = CLOCK_IN_OMAP16XX,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk rhea2_ck = { static struct clk rhea2_ck = {
.name = "rhea2_ck", .name = "rhea2_ck",
.parent = &tc_ck, .parent = &tc_ck,
.flags = DOES_NOT_EXIST_ON_1510, .flags = CLOCK_IN_OMAP16XX,
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk lcd_ck = { static struct clk lcd_ck = {
.name = "lcd_ck", .name = "lcd_ck",
.parent = &ck_dpll1, .parent = &ck_dpll1,
.flags = RATE_CKCTL, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_CKCTL,
.enable_reg = ARM_IDLECT2, .enable_reg = ARM_IDLECT2,
.enable_bit = EN_LCDCK, .enable_bit = EN_LCDCK,
.rate_offset = CKCTL_LCDDIV_OFFSET, .rate_offset = CKCTL_LCDDIV_OFFSET,
...@@ -305,7 +321,8 @@ static struct clk uart1_ck = { ...@@ -305,7 +321,8 @@ static struct clk uart1_ck = {
.name = "uart1_ck", .name = "uart1_ck",
/* Direct from ULPD, no parent */ /* Direct from ULPD, no parent */
.rate = 48000000, .rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = MOD_CONF_CTRL_0, .enable_reg = MOD_CONF_CTRL_0,
.enable_bit = 29, .enable_bit = 29,
/* (Only on 1510) /* (Only on 1510)
...@@ -317,7 +334,8 @@ static struct clk uart2_ck = { ...@@ -317,7 +334,8 @@ static struct clk uart2_ck = {
.name = "uart2_ck", .name = "uart2_ck",
/* Direct from ULPD, no parent */ /* Direct from ULPD, no parent */
.rate = 48000000, .rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = MOD_CONF_CTRL_0, .enable_reg = MOD_CONF_CTRL_0,
.enable_bit = 30, .enable_bit = 30,
/* (1510/1610/1710) /* (1510/1610/1710)
...@@ -329,7 +347,8 @@ static struct clk uart3_ck = { ...@@ -329,7 +347,8 @@ static struct clk uart3_ck = {
.name = "uart3_ck", .name = "uart3_ck",
/* Direct from ULPD, no parent */ /* Direct from ULPD, no parent */
.rate = 48000000, .rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = MOD_CONF_CTRL_0, .enable_reg = MOD_CONF_CTRL_0,
.enable_bit = 31, .enable_bit = 31,
/* (Only on 1510) /* (Only on 1510)
...@@ -341,8 +360,8 @@ static struct clk usb_ck1610 = { ...@@ -341,8 +360,8 @@ static struct clk usb_ck1610 = {
.name = "usb_ck", .name = "usb_ck",
/* Direct from ULPD, no parent */ /* Direct from ULPD, no parent */
.rate = 48000000, .rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT | .flags = CLOCK_IN_OMAP16XX |
DOES_NOT_EXIST_ON_1510, RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = ULPD_CLOCK_CTRL, .enable_reg = ULPD_CLOCK_CTRL,
.enable_bit = USB_MCLK_EN, .enable_bit = USB_MCLK_EN,
}; };
...@@ -351,14 +370,15 @@ static struct clk usb_ck1510 = { ...@@ -351,14 +370,15 @@ static struct clk usb_ck1510 = {
.name = "usb_ck", .name = "usb_ck",
/* Direct from ULPD, no parent */ /* Direct from ULPD, no parent */
.rate = 48000000, .rate = 48000000,
.flags = RATE_FIXED | DOES_NOT_EXIST_ON_1610, .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
}; };
static struct clk usb_hhc_ck = { static struct clk usb_hhc_ck = {
.name = "usb_hhc_ck", .name = "usb_hhc_ck",
/* Direct from ULPD, no parent */ /* Direct from ULPD, no parent */
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
.flags = RATE_FIXED | ENABLE_REG_32BIT, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = MOD_CONF_CTRL_0, .enable_reg = MOD_CONF_CTRL_0,
.enable_bit = USB_HOST_HHC_UHOST_EN, .enable_bit = USB_HOST_HHC_UHOST_EN,
}; };
...@@ -373,39 +393,32 @@ static struct clk bclk = { ...@@ -373,39 +393,32 @@ static struct clk bclk = {
}; };
-- to be done */ -- to be done */
static struct clk mmc_ck = {
.name = "mmc1_ck",
.parent = &armxor_ck, /* (1510) */
.rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT |
DOES_NOT_EXIST_ON_1610,
.enable_reg = MOD_CONF_CTRL_0,
.enable_bit = 23,
};
static struct clk mmc1_ck = { static struct clk mmc1_ck = {
.name = "mmc1_ck", .name = "mmc1_ck",
/* Direct from ULPD, no parent (1610/1710) */ /* Functional clock is direct from ULPD, interface clock is ARMPER */
.parent = &armper_ck,
.rate = 48000000, .rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
DOES_NOT_EXIST_ON_1510, RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = MOD_CONF_CTRL_0, .enable_reg = MOD_CONF_CTRL_0,
.enable_bit = 23, .enable_bit = 23,
}; };
static struct clk mmc2_ck = { static struct clk mmc2_ck = {
.name = "mmc2_ck", .name = "mmc2_ck",
/* Direct from ULPD, no parent */ /* Functional clock is direct from ULPD, interface clock is ARMPER */
.parent = &armper_ck,
.rate = 48000000, .rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT | .flags = CLOCK_IN_OMAP16XX |
DOES_NOT_EXIST_ON_1510, RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = MOD_CONF_CTRL_0, .enable_reg = MOD_CONF_CTRL_0,
.enable_bit = 20, .enable_bit = 20,
}; };
static struct clk virtual_ck_mpu = { static struct clk virtual_ck_mpu = {
.name = "mpu", .name = "mpu",
.flags = VIRTUAL_CLOCK | ALWAYS_ENABLED, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
VIRTUAL_CLOCK | ALWAYS_ENABLED,
.parent = &arm_ck, /* Is smarter alias for */ .parent = &arm_ck, /* Is smarter alias for */
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
.set_rate = &select_table_rate, .set_rate = &select_table_rate,
...@@ -454,8 +467,7 @@ static struct clk * onchip_clks[] = { ...@@ -454,8 +467,7 @@ static struct clk * onchip_clks[] = {
&mclk, &mclk,
&bclk, &bclk,
-- to be done */ -- to be done */
&mmc_ck, /* 1510 */ &mmc1_ck,
&mmc1_ck, /* 1610/1710 */
&mmc2_ck, &mmc2_ck,
/* Virtual clocks */ /* Virtual clocks */
&virtual_ck_mpu, &virtual_ck_mpu,
...@@ -496,7 +508,8 @@ int __clk_enable(struct clk *clk) ...@@ -496,7 +508,8 @@ int __clk_enable(struct clk *clk)
return 0; return 0;
if (unlikely(clk->enable_reg == 0)) { if (unlikely(clk->enable_reg == 0)) {
printk("Enable for %s without enable enabled\n", clk->name); printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
clk->name);
return 0; return 0;
} }
...@@ -618,10 +631,6 @@ EXPORT_SYMBOL(clk_unuse); ...@@ -618,10 +631,6 @@ EXPORT_SYMBOL(clk_unuse);
unsigned long clk_get_rate(struct clk *clk) unsigned long clk_get_rate(struct clk *clk)
{ {
if (clk->rate == 0) {
printk("Get rate for %s without cached clock\n", clk->name);
}
return clk->rate; return clk->rate;
} }
EXPORT_SYMBOL(clk_get_rate); EXPORT_SYMBOL(clk_get_rate);
...@@ -869,14 +878,15 @@ int __init clk_init(void) ...@@ -869,14 +878,15 @@ int __init clk_init(void)
int crystal_type = 0; /* Default 12 MHz */ int crystal_type = 0; /* Default 12 MHz */
for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
if ((((*clkp)->flags & DOES_NOT_EXIST_ON_1510) && if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
cpu_is_omap1510()) || clk_register(*clkp);
(((*clkp)->flags & DOES_NOT_EXIST_ON_1610) && continue;
(cpu_is_omap1610() || cpu_is_omap1710()))) { }
(*clkp)->parent = 0;
if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
clk_register(*clkp);
continue; continue;
} }
clk_register(*clkp);
} }
info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
...@@ -897,14 +907,14 @@ int __init clk_init(void) ...@@ -897,14 +907,14 @@ int __init clk_init(void)
/* Find the highest supported frequency and enable it */ /* Find the highest supported frequency and enable it */
if (select_table_rate(~0)) { if (select_table_rate(~0)) {
printk("System frequencies not set. Check your config.\n"); printk(KERN_ERR "System frequencies not set. Check your config.\n");
/* Guess sane values (60MHz) */ /* Guess sane values (60MHz) */
omap_writew(0x2290, DPLL_CTL); omap_writew(0x2290, DPLL_CTL);
omap_writew(0x1005, ARM_CKCTL); omap_writew(0x1005, ARM_CKCTL);
ck_dpll1.rate = 60000000; ck_dpll1.rate = 60000000;
propagate_rate(&ck_dpll1); propagate_rate(&ck_dpll1);
printk("Clocking rate (xtal/DPLL1/MPU): %ld/%ld/%ld\n", printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld/%ld/%ld\n",
ck_ref.rate, ck_dpll1.rate, arm_ck.rate); ck_ref.rate, ck_dpll1.rate, arm_ck.rate);
} }
/* Cache rates for clocks connected to ck_ref (not dpll1) */ /* Cache rates for clocks connected to ck_ref (not dpll1) */
...@@ -941,7 +951,5 @@ int __init clk_init(void) ...@@ -941,7 +951,5 @@ int __init clk_init(void)
if (cpu_is_omap1510()) if (cpu_is_omap1510())
clk_enable(&arm_gpio_ck); clk_enable(&arm_gpio_ck);
start_mputimer1(0xffffffff);
return 0; return 0;
} }
arch/arm/mach-omap/clock.h
View file @ 67e06f62
...@@ -48,8 +48,8 @@ struct mpu_rate { ...@@ -48,8 +48,8 @@ struct mpu_rate {
#define VIRTUAL_CLOCK 8 #define VIRTUAL_CLOCK 8
#define ALWAYS_ENABLED 16 #define ALWAYS_ENABLED 16
#define ENABLE_REG_32BIT 32 #define ENABLE_REG_32BIT 32
#define DOES_NOT_EXIST_ON_1510 64 #define CLOCK_IN_OMAP16XX 64
#define DOES_NOT_EXIST_ON_1610 128 /* Including 1710 */ #define CLOCK_IN_OMAP1510 128
/* ARM_CKCTL bit shifts */ /* ARM_CKCTL bit shifts */
#define CKCTL_PERDIV_OFFSET 0 #define CKCTL_PERDIV_OFFSET 0
......
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