[E1000] whitespace fix from previous patches

* Corrected indentation from previous patches

drivers/net/e1000/e1000_hw.c

@@ -718,7 +718,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
     }
     DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
 
-if (hw->phy_type == e1000_phy_igp) {
+    if (hw->phy_type == e1000_phy_igp) {
 
         ret_val = e1000_phy_reset(hw);
         if(ret_val < 0) {
@@ -744,12 +744,14 @@ if (hw->phy_type == e1000_phy_igp) {
 
         if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
             /* Disable SmartSpeed */
-        if(e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data) < 0) {
+            if(e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                  &phy_data) < 0) {
                 DEBUGOUT("PHY Read Error\n");
                 return -E1000_ERR_PHY;
             }
             phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-        if(e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data) < 0) {
+            if(e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                   phy_data) < 0) {
                 DEBUGOUT("PHY Write Error\n");
                 return -E1000_ERR_PHY;
             }
@@ -771,7 +773,8 @@ if (hw->phy_type == e1000_phy_igp) {
         }
 
         /* Force MDI for IGP PHY */
-    phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
+        phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
+                      IGP01E1000_PSCR_FORCE_MDI_MDIX);
 
         hw->mdix = 1;
 
@@ -780,7 +783,7 @@ if (hw->phy_type == e1000_phy_igp) {
             return -E1000_ERR_PHY;
         }
 
-} else {
+    } else {
         /* Enable CRS on TX. This must be set for half-duplex operation. */
         if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
             DEBUGOUT("PHY Read Error\n");
@@ -842,7 +845,8 @@ if (hw->phy_type == e1000_phy_igp) {
                           M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
             phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
                          M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
-        if(e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
+            if(e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+                                   phy_data) < 0) {
                 DEBUGOUT("PHY Write Error\n");
                 return -E1000_ERR_PHY;
             }
@@ -854,7 +858,7 @@ if (hw->phy_type == e1000_phy_igp) {
             DEBUGOUT("Error Resetting the PHY\n");
             return ret_val;
         }
-}
+    }
 
     /* Options:
      *   autoneg = 1 (default)
@@ -1193,7 +1197,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
     /* Write the configured values back to the Device Control Reg. */
     E1000_WRITE_REG(hw, CTRL, ctrl);
 
-if (hw->phy_type == e1000_phy_m88) {
+    if (hw->phy_type == e1000_phy_m88) {
         if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
             DEBUGOUT("PHY Read Error\n");
             return -E1000_ERR_PHY;
@@ -1211,7 +1215,7 @@ if (hw->phy_type == e1000_phy_m88) {
 
         /* Need to reset the PHY or these changes will be ignored */
         mii_ctrl_reg |= MII_CR_RESET;
-} else {
+    } else {
         /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
          * forced whenever speed or duplex are forced.
          */
@@ -1227,7 +1231,7 @@ if (hw->phy_type == e1000_phy_m88) {
             DEBUGOUT("PHY Write Error\n");
             return -E1000_ERR_PHY;
         }
-}
+    }
 
     /* Write back the modified PHY MII control register. */
     if(e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) {
@@ -1291,7 +1295,7 @@ if (hw->phy_type == e1000_phy_m88) {
         }
     }
 
-if (hw->phy_type == e1000_phy_m88) {
+    if (hw->phy_type == e1000_phy_m88) {
         /* Because we reset the PHY above, we need to re-force TX_CLK in the
          * Extended PHY Specific Control Register to 25MHz clock.  This value
          * defaults back to a 2.5MHz clock when the PHY is reset.
@@ -1318,7 +1322,7 @@ if (hw->phy_type == e1000_phy_m88) {
             DEBUGOUT("PHY Write Error\n");
             return -E1000_ERR_PHY;
         }
-}
+    }
     return 0;
 }
 
@@ -1373,7 +1377,7 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
     /* Set up duplex in the Device Control and Transmit Control
      * registers depending on negotiated values.
      */
-if (hw->phy_type == e1000_phy_igp) {
+    if (hw->phy_type == e1000_phy_igp) {
         if(e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0) {
             DEBUGOUT("PHY Read Error\n");
             return -E1000_ERR_PHY;
@@ -1392,7 +1396,7 @@ if (hw->phy_type == e1000_phy_igp) {
         else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
                 IGP01E1000_PSSR_SPEED_100MBPS)
             ctrl |= E1000_CTRL_SPD_100;
-} else {
+    } else {
         if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
             DEBUGOUT("PHY Read Error\n");
             return -E1000_ERR_PHY;
@@ -1409,7 +1413,7 @@ if (hw->phy_type == e1000_phy_igp) {
             ctrl |= E1000_CTRL_SPD_1000;
         else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
             ctrl |= E1000_CTRL_SPD_100;
-}
+    }
     /* Write the configured values back to the Device Control Reg. */
     E1000_WRITE_REG(hw, CTRL, ctrl);
     return 0;