Commit 69fc4053 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller

tg3: Remove unused cfgspc device members

This patch removes the pci_bist and pci_hdr_type members from the
device structure and removes the code that references them.  They are
not really used.

The patch rounds out the changes by moving the pci_cmd member to plug
a structure hole that would have been created.  On 32-bit systems, this
movement removes a subsequent structure hole later in the structure. On
64-bit systems though, the movement merely consolidates two holes into
one larger hole.
Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarBenjamin Li <benli@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 027455ad
...@@ -12160,7 +12160,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) ...@@ -12160,7 +12160,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
{ }, { },
}; };
u32 misc_ctrl_reg; u32 misc_ctrl_reg;
u32 cacheline_sz_reg;
u32 pci_state_reg, grc_misc_cfg; u32 pci_state_reg, grc_misc_cfg;
u32 val; u32 val;
u16 pci_cmd; u16 pci_cmd;
...@@ -12330,14 +12329,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) ...@@ -12330,14 +12329,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
tp->misc_host_ctrl); tp->misc_host_ctrl);
pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
&cacheline_sz_reg);
tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
tp->pdev_peer = tg3_find_peer(tp); tp->pdev_peer = tg3_find_peer(tp);
...@@ -12447,17 +12438,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) ...@@ -12447,17 +12438,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
&tp->pci_cacheline_sz);
pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
&tp->pci_lat_timer);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
tp->pci_lat_timer < 64) { tp->pci_lat_timer < 64) {
tp->pci_lat_timer = 64; tp->pci_lat_timer = 64;
pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0); tp->pci_lat_timer);
cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
cacheline_sz_reg);
} }
if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
......
...@@ -2676,10 +2676,9 @@ struct tg3 { ...@@ -2676,10 +2676,9 @@ struct tg3 {
/* PCI block */ /* PCI block */
u32 pci_chip_rev_id; u32 pci_chip_rev_id;
u16 pci_cmd;
u8 pci_cacheline_sz; u8 pci_cacheline_sz;
u8 pci_lat_timer; u8 pci_lat_timer;
u8 pci_hdr_type;
u8 pci_bist;
int pm_cap; int pm_cap;
int msi_cap; int msi_cap;
...@@ -2730,7 +2729,6 @@ struct tg3 { ...@@ -2730,7 +2729,6 @@ struct tg3 {
u32 led_ctrl; u32 led_ctrl;
u32 phy_otp; u32 phy_otp;
u16 pci_cmd;
char board_part_number[24]; char board_part_number[24];
#define TG3_VER_SIZE 32 #define TG3_VER_SIZE 32
......
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