drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part3

[Why]
In DCN we want direct DAL to SMU calls, with as little as
possible interference by pplib. The reason for each pp_smu interface
mapping to 1 SMU message is so we can have the sequencing of different
SMU message in dal and shared across different OS. This will also
simplify debugging as DAL owns this interaction and there's no
confusion about division of ownership.

[How]
Separate the set_hard_min_fclk_by_freq message from the
SMU messages that are sent as part of pp_rv_set_display_requirement.
directly notify min dcfclk to smu part 2
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c

@@ -196,6 +196,24 @@ static void notify_hard_min_dcfclk_to_smu(
 	pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, min_dcf_clk_mhz);
 }
 
+static void notify_hard_min_fclk_to_smu(
+		struct pp_smu_funcs_rv *pp_smu, int min_f_clk_khz)
+{
+	int min_f_clk_mhz; //minimum required F clock in mhz
+
+	/*
+	 * if function pointer not set up, this message is
+	 * sent as part of pplib_apply_display_requirements.
+	 * So just return.
+	 */
+	if (!pp_smu || !pp_smu->set_hard_min_fclk_by_freq)
+		return;
+
+	min_f_clk_mhz = min_f_clk_khz / 1000;
+
+	pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, min_f_clk_mhz);
+}
+
 static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
 			struct dc_state *context,
 			bool safe_to_lower)
@@ -250,7 +268,8 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
 		clock_voltage_req.clocks_in_khz = new_clocks->fclk_khz;
 		smu_req.hard_min_fclk_khz = new_clocks->fclk_khz;
 
-		dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
+		notify_hard_min_fclk_to_smu(pp_smu, new_clocks->fclk_khz);
+
 		send_request_to_lower = true;
 	}
 
@@ -279,6 +298,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
 		clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
 
 		notify_hard_min_dcfclk_to_smu(pp_smu, clock_voltage_req.clocks_in_khz);
+
 		if (pp_smu->set_display_requirement)
 			pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
 

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

@@ -103,6 +103,12 @@ struct pp_smu_funcs_rv {
 	void (*set_display_count)(struct pp_smu *pp, int count);
 
 	/* which SMU message?  are reader and writer WM separate SMU msg? */
+	/*
+	 * PPSMC_MSG_SetDriverDramAddrHigh
+	 * PPSMC_MSG_SetDriverDramAddrLow
+	 * PPSMC_MSG_TransferTableDram2Smu
+	 *
+	 * */
 	void (*set_wm_ranges)(struct pp_smu *pp,
 			struct pp_smu_wm_range_sets *ranges);