Commit 6aba2ae7 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman

Merge tag 'for-3.16' of...

Merge tag 'for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next

Kishon writes:

for 3.16 merge window

Bunch of fixes and a new driver for Exynos5 USB 3.0 PHY.
parents cea35899 eadd4312
......@@ -114,3 +114,50 @@ Example:
compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
Samsung Exynos5 SoC series USB DRD PHY controller
--------------------------------------------------
Required properties:
- compatible : Should be set to one of the following supported values:
- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
- reg : Register offset and length of USB DRD PHY register set;
- clocks: Clock IDs array as required by the controller
- clock-names: names of clocks correseponding to IDs in the clock property;
Required clocks:
- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
used for register access.
- ref: PHY's reference clock (usually crystal clock), used for
PHY operations, associated by phy name. It is used to
determine bit values for clock settings register.
For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
- samsung,pmu-syscon: phandle for PMU system controller interface, used to
control pmu registers for power isolation.
- #phy-cells : from the generic PHY bindings, must be 1;
For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
compatible PHYs, the second cell in the PHY specifier identifies the
PHY id, which is interpreted as follows:
0 - UTMI+ type phy,
1 - PIPE3 type phy,
Example:
usbdrd_phy: usbphy@12100000 {
compatible = "samsung,exynos5250-usbdrd-phy";
reg = <0x12100000 0x100>;
clocks = <&clock 286>, <&clock 1>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
'usbdrd_phy' nodes should have numbered alias in the aliases node,
in the form of usbdrdphyN, N = 0, 1... (depending on number of
controllers).
Example:
aliases {
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
......@@ -2,15 +2,26 @@ Allwinner sun4i USB PHY
-----------------------
Required properties:
- compatible : should be one of "allwinner,sun4i-a10-usb-phy",
"allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"
- compatible : should be one of
* allwinner,sun4i-a10-usb-phy
* allwinner,sun5i-a13-usb-phy
* allwinner,sun6i-a31-usb-phy
* allwinner,sun7i-a20-usb-phy
- reg : a list of offset + length pairs
- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"
- reg-names :
* "phy_ctrl"
* "pmu1"
* "pmu2" for sun4i, sun6i or sun7i
- #phy-cells : from the generic phy bindings, must be 1
- clocks : phandle + clock specifier for the phy clock
- clock-names : "usb_phy"
- clocks : phandle + clock specifier for the phy clocks
- clock-names :
* "usb_phy" for sun4i, sun5i or sun7i
* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
- resets : a list of phandle + reset specifier pairs
- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"
- reset-names :
* "usb0_reset"
* "usb1_reset"
* "usb2_reset" for sun4i, sun6i or sun7i
Example:
usbphy: phy@0x01c13400 {
......
......@@ -32,6 +32,11 @@ Required properties:
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
- clocks: a list of phandles and clock-specifier pairs, one for each entry in
clock-names.
- clock-names: should include:
* "wkupclk" - wakeup clock.
* "refclk" - reference clock (optional).
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
......@@ -44,6 +49,8 @@ usb2phy@4a0ad080 {
reg = <0x4a0ad080 0x58>;
ctrl-module = <&omap_control_usb>;
#phy-cells = <0>;
clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
clock-names = "wkupclk", "refclk";
};
TI PIPE3 PHY
......
......@@ -89,8 +89,8 @@ config PHY_EXYNOS_DP_VIDEO
config BCM_KONA_USB2_PHY
tristate "Broadcom Kona USB2 PHY Driver"
depends on GENERIC_PHY
depends on HAS_IOMEM
select GENERIC_PHY
help
Enable this to support the Broadcom Kona USB 2.0 PHY.
......@@ -160,6 +160,17 @@ config PHY_EXYNOS5250_USB2
particular SoC is compiled in the driver. In case of Exynos 5250 four
phys are available - device, host, HSIC0 and HSIC.
config PHY_EXYNOS5_USBDRD
tristate "Exynos5 SoC series USB DRD PHY driver"
depends on ARCH_EXYNOS5 && OF
depends on HAS_IOMEM
select GENERIC_PHY
select MFD_SYSCON
help
Enable USB DRD PHY support for Exynos 5 SoC series.
This driver provides PHY interface for USB 3.0 DRD controller
present on Exynos5 SoC series.
config PHY_XGENE
tristate "APM X-Gene 15Gbps PHY support"
depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
......
......@@ -18,4 +18,5 @@ phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
......@@ -101,7 +101,7 @@ static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
{
struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
if (WARN_ON(args->args[0] > EXYNOS_MIPI_PHYS_NUM))
if (WARN_ON(args->args[0] >= EXYNOS_MIPI_PHYS_NUM))
return ERR_PTR(-ENODEV);
return state->phys[args->args[0]].phy;
......
This diff is collapsed.
......@@ -246,6 +246,6 @@ static struct platform_driver exynos_sata_phy_driver = {
module_platform_driver(exynos_sata_phy_driver);
MODULE_DESCRIPTION("Samsung SerDes PHY driver");
MODULE_LICENSE("GPL V2");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
MODULE_AUTHOR("Yuvaraj C D <yuvaraj.cd@samsung.com>");
......@@ -275,18 +275,34 @@ static int omap_usb2_probe(struct platform_device *pdev)
if (IS_ERR(phy_provider))
return PTR_ERR(phy_provider);
phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
if (IS_ERR(phy->wkupclk)) {
dev_warn(&pdev->dev, "unable to get wkupclk, trying old name\n");
phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
if (IS_ERR(phy->wkupclk)) {
dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
return PTR_ERR(phy->wkupclk);
} else {
dev_warn(&pdev->dev,
"found usb_phy_cm_clk32k, please fix DTS\n");
}
}
clk_prepare(phy->wkupclk);
phy->optclk = devm_clk_get(phy->dev, "refclk");
if (IS_ERR(phy->optclk)) {
dev_dbg(&pdev->dev, "unable to get refclk, trying old name\n");
phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
if (IS_ERR(phy->optclk))
dev_vdbg(&pdev->dev, "unable to get refclk960m\n");
else
if (IS_ERR(phy->optclk)) {
dev_dbg(&pdev->dev,
"unable to get usb_otg_ss_refclk960m\n");
} else {
dev_warn(&pdev->dev,
"found usb_otg_ss_refclk960m, please fix DTS\n");
}
} else {
clk_prepare(phy->optclk);
}
usb_add_phy_dev(&phy->phy);
......
......@@ -61,7 +61,6 @@
#define MAX_PHYS 3
struct sun4i_usb_phy_data {
struct clk *clk;
void __iomem *base;
struct mutex mutex;
int num_phys;
......@@ -71,6 +70,7 @@ struct sun4i_usb_phy_data {
void __iomem *pmu;
struct regulator *vbus;
struct reset_control *reset;
struct clk *clk;
int index;
} phys[MAX_PHYS];
};
......@@ -146,13 +146,13 @@ static int sun4i_usb_phy_init(struct phy *_phy)
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
int ret;
ret = clk_prepare_enable(data->clk);
ret = clk_prepare_enable(phy->clk);
if (ret)
return ret;
ret = reset_control_deassert(phy->reset);
if (ret) {
clk_disable_unprepare(data->clk);
clk_disable_unprepare(phy->clk);
return ret;
}
......@@ -170,11 +170,10 @@ static int sun4i_usb_phy_init(struct phy *_phy)
static int sun4i_usb_phy_exit(struct phy *_phy)
{
struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
sun4i_usb_phy_passby(phy, 0);
reset_control_assert(phy->reset);
clk_disable_unprepare(data->clk);
clk_disable_unprepare(phy->clk);
return 0;
}
......@@ -224,13 +223,9 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
struct sun4i_usb_phy_data *data;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
void __iomem *pmu = NULL;
struct phy_provider *phy_provider;
struct reset_control *reset;
struct regulator *vbus;
bool dedicated_clocks;
struct resource *res;
struct phy *phy;
char name[16];
int i;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
......@@ -249,55 +244,64 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
else
data->disc_thresh = 2;
if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy"))
dedicated_clocks = true;
else
dedicated_clocks = false;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
data->base = devm_ioremap_resource(dev, res);
if (IS_ERR(data->base))
return PTR_ERR(data->base);
data->clk = devm_clk_get(dev, "usb_phy");
if (IS_ERR(data->clk)) {
dev_err(dev, "could not get usb_phy clock\n");
return PTR_ERR(data->clk);
}
/* Skip 0, 0 is the phy for otg which is not yet supported. */
for (i = 1; i < data->num_phys; i++) {
struct sun4i_usb_phy *phy = data->phys + i;
char name[16];
snprintf(name, sizeof(name), "usb%d_vbus", i);
vbus = devm_regulator_get_optional(dev, name);
if (IS_ERR(vbus)) {
if (PTR_ERR(vbus) == -EPROBE_DEFER)
phy->vbus = devm_regulator_get_optional(dev, name);
if (IS_ERR(phy->vbus)) {
if (PTR_ERR(phy->vbus) == -EPROBE_DEFER)
return -EPROBE_DEFER;
vbus = NULL;
phy->vbus = NULL;
}
if (dedicated_clocks)
snprintf(name, sizeof(name), "usb%d_phy", i);
else
strlcpy(name, "usb_phy", sizeof(name));
phy->clk = devm_clk_get(dev, name);
if (IS_ERR(phy->clk)) {
dev_err(dev, "failed to get clock %s\n", name);
return PTR_ERR(phy->clk);
}
snprintf(name, sizeof(name), "usb%d_reset", i);
reset = devm_reset_control_get(dev, name);
if (IS_ERR(reset)) {
phy->reset = devm_reset_control_get(dev, name);
if (IS_ERR(phy->reset)) {
dev_err(dev, "failed to get reset %s\n", name);
return PTR_ERR(reset);
return PTR_ERR(phy->reset);
}
if (i) { /* No pmu for usbc0 */
snprintf(name, sizeof(name), "pmu%d", i);
res = platform_get_resource_byname(pdev,
IORESOURCE_MEM, name);
pmu = devm_ioremap_resource(dev, res);
if (IS_ERR(pmu))
return PTR_ERR(pmu);
phy->pmu = devm_ioremap_resource(dev, res);
if (IS_ERR(phy->pmu))
return PTR_ERR(phy->pmu);
}
phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL);
if (IS_ERR(phy)) {
phy->phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL);
if (IS_ERR(phy->phy)) {
dev_err(dev, "failed to create PHY %d\n", i);
return PTR_ERR(phy);
return PTR_ERR(phy->phy);
}
data->phys[i].phy = phy;
data->phys[i].pmu = pmu;
data->phys[i].vbus = vbus;
data->phys[i].reset = reset;
data->phys[i].index = i;
phy_set_drvdata(phy, &data->phys[i]);
phy->index = i;
phy_set_drvdata(phy->phy, &data->phys[i]);
}
dev_set_drvdata(dev, data);
......@@ -311,6 +315,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy" },
{ .compatible = "allwinner,sun5i-a13-usb-phy" },
{ .compatible = "allwinner,sun6i-a31-usb-phy" },
{ .compatible = "allwinner,sun7i-a20-usb-phy" },
{ },
};
......
/*
* Exynos5 SoC series Power Management Unit (PMU) register offsets
* and bit definitions.
*
* Copyright (C) 2014 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_
#define _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_
/* Exynos5 PMU register definitions */
#define EXYNOS5_HDMI_PHY_CONTROL (0x700)
#define EXYNOS5_USBDRD_PHY_CONTROL (0x704)
/* Exynos5250 specific register definitions */
#define EXYNOS5_USBHOST_PHY_CONTROL (0x708)
#define EXYNOS5_EFNAND_PHY_CONTROL (0x70c)
#define EXYNOS5_MIPI_PHY0_CONTROL (0x710)
#define EXYNOS5_MIPI_PHY1_CONTROL (0x714)
#define EXYNOS5_ADC_PHY_CONTROL (0x718)
#define EXYNOS5_MTCADC_PHY_CONTROL (0x71c)
#define EXYNOS5_DPTX_PHY_CONTROL (0x720)
#define EXYNOS5_SATA_PHY_CONTROL (0x724)
/* Exynos5420 specific register definitions */
#define EXYNOS5420_USBDRD1_PHY_CONTROL (0x708)
#define EXYNOS5420_USBHOST_PHY_CONTROL (0x70c)
#define EXYNOS5420_MIPI_PHY0_CONTROL (0x714)
#define EXYNOS5420_MIPI_PHY1_CONTROL (0x718)
#define EXYNOS5420_MIPI_PHY2_CONTROL (0x71c)
#define EXYNOS5420_ADC_PHY_CONTROL (0x720)
#define EXYNOS5420_MTCADC_PHY_CONTROL (0x724)
#define EXYNOS5420_DPTX_PHY_CONTROL (0x728)
#define EXYNOS5_PHY_ENABLE BIT(0)
#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1)
#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2)
#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */
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