Commit 6af632be authored by Jaroslav Kysela's avatar Jaroslav Kysela

ALSA CVS update - Takashi Iwai <tiwai@suse.de>

Documentation,PCI drivers,au88x0 driver
added the au88x0 drivers for Aureal soundcards by Manuel Jander <mjander@embedded.cl>
parent d4ab9ef9
......@@ -112,7 +112,8 @@ Module parameters
- value is used for /proc/asound filesystem
- this value can be used by applications for identification
of card if user does not want identify card with index number
enable - enable card (only first card is enabled by default)
enable - enable card. (all cards enabled for PCI and ISA PnP cards
as default.)
Module snd-ad1816a
------------------
......@@ -178,6 +179,32 @@ Module parameters
Module supports up to 8 cards, autoprobe and PnP.
Module snd-au8810, snd-au8820, snd-au8830
-----------------------------------------
Module for Aureal Vortex, Vortex2 and Advantage device.
pcifix - Control PCI workarounds
0 = Disable all workarounds
1 = Force the PCI latency of the Aureal card to 0xff
2 = Force the Extend PCI#2 Internal Master for Efficient
Handling of Dummy Requests on the VIA KT133 AGP Bridge
3 = Force both settings
255 = Autodetect what is required (default)
This module supports all ADB PCM channels, ac97 mixer, SPDIF, hardware
EQ, mpu401, gameport. A3D and wavetable support are still in development.
Development and reverse engineering work is being coordinated at
http://savannah.nongnu.org/projects/openvortex/
SPDIF output has a copy of the AC97 codec output, unless you use the
"spdif" pcm device, which allows raw data passthru.
The hardware EQ hardware and SPDIF is only present in the Vortex2 and
Advantage.
Note: Some ALSA mixer applicactions don't handle the SPDIF samplerate
control correctly. If you have problems regarding this, try
another ALSA compliant mixer (alsamixer works).
Module snd-azt2320
------------------
......@@ -608,6 +635,7 @@ Module parameters
1 = use headphone control as master
2 = swap headphone and master controls
3 = for AD1985, turn on OMS bit and use headphone
4 = for ALC65x, turn on the jack sense mode
Module supports autoprobe and multiple bus-master chips (max 8).
......
......@@ -15,6 +15,30 @@ config SND_ALI5451
help
Say 'Y' or 'M' to include support for ALI PCI Audio M5451 sound core.
config SND_AU8810
tristate "Aureal Advantage"
depends on SND
select SND_MPU401_UART
select SND_AC97_CODEC
help
Say 'Y' or 'M' to include support for Aureal Advantage soundcards.
config SND_AU8820
tristate "Aureal Vortex"
depends on SND
select SND_MPU401_UART
select SND_AC97_CODEC
help
Say 'Y' or 'M' to include support for Aureal Vortex soundcards.
config SND_AU8830
tristate "Aureal Vortex 2"
depends on SND
select SND_MPU401_UART
select SND_AC97_CODEC
help
Say 'Y' or 'M' to include support for Aureal Vortex 2 soundcards.
config SND_AZT3328
tristate "Aztech AZF3328 / PCI168 (EXPERIMENTAL)"
depends on SND && EXPERIMENTAL
......
......@@ -41,6 +41,7 @@ obj-$(CONFIG_SND_VIA82XX) += snd-via82xx.o
obj-$(CONFIG_SND) += \
ac97/ \
ali5451/ \
au88x0/ \
cs46xx/ \
emu10k1/ \
ice1712/ \
......
snd-au8810-objs := au8810.o
snd-au8820-objs := au8820.o
snd-au8830-objs := au8830.o
obj-$(CONFIG_SND_AU8810) += snd-au8810.o
obj-$(CONFIG_SND_AU8820) += snd-au8820.o
obj-$(CONFIG_SND_AU8830) += snd-au8830.o
#include "au8810.h"
#include "au88x0.h"
static struct pci_device_id snd_vortex_ids[] = {
{PCI_VENDOR_ID_AUREAL, PCI_DEVICE_ID_AUREAL_ADVANTAGE,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1,},
{0,}
};
#include "au88x0_core.c"
#include "au88x0_pcm.c"
#include "au88x0_mixer.c"
#include "au88x0_mpu401.c"
#include "au88x0_game.c"
#include "au88x0_eq.c"
#include "au88x0_a3d.c"
#include "au88x0_xtalk.c"
#include "au88x0.c"
/*
Aureal Advantage Soundcard driver.
*/
#define CHIP_AU8810
#define CARD_NAME "Aureal Advantage 3D Sound Processor"
#define CARD_NAME_SHORT "au8810"
#ifndef PCI_VENDOR_ID_AUREAL
#define PCI_VENDOR_ID_AUREAL 0x12eb
#endif
#ifndef PCI_VENDOR_ID_AUREAL_ADVANTAGE
#define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003
#endif
#define hwread(x,y) readl((x)+((y)>>2))
#define hwwrite(x,y,z) writel((z),(x)+((y)>>2))
#define NR_ADB 0x20
#define NR_WT 0x00
#define NR_SRC 0x10
#define NR_A3D 0x10
#define NR_MIXIN 0x20
#define NR_MIXOUT 0x10
/* ADBDMA */
#define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
#define POS_MASK 0x00000fff
#define POS_SHIFT 0x0
#define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
#define ADB_SUBBUF_SHIFT 0xc /* ADB only. */
#define VORTEX_ADBDMA_CTRL 0x27180 /* write only; format, flags, DMA pos */
#define OFFSET_MASK 0x00000fff
#define OFFSET_SHIFT 0x0
#define IE_MASK 0x00001000 /* interrupt enable. */
#define IE_SHIFT 0xc
#define DIR_MASK 0x00002000 /* Direction */
#define DIR_SHIFT 0xd
#define FMT_MASK 0x0003c000
#define FMT_SHIFT 0xe
// The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
#define VORTEX_ADBDMA_BUFCFG0 0x27100
#define VORTEX_ADBDMA_BUFCFG1 0x27104
#define VORTEX_ADBDMA_BUFBASE 0x27000
#define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */
#define VORTEX_ADBDMA_STATUS 0x27A90 /* stored at AdbDma->this_10 / 2 DWORD in size. */
/* WTDMA */
#define VORTEX_WTDMA_CTRL 0x27fd8 /* format, DMA pos */
#define VORTEX_WTDMA_STAT 0x27fe8 /* DMA subbuf, DMA pos */
#define WT_SUBBUF_MASK 0x3
#define WT_SUBBUF_SHIFT 0xc
#define VORTEX_WTDMA_BUFBASE 0x27fc0
#define VORTEX_WTDMA_BUFCFG0 0x27fd0
#define VORTEX_WTDMA_BUFCFG1 0x27fd4
#define VORTEX_WTDMA_START 0x27fe4 /* which subbuffer is first */
/* ADB */
#define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */
#define VORTEX_ADB_RTBASE 0x28000
#define VORTEX_ADB_RTBASE_SIZE (VORTEX_ADB_CHNBASE - VORTEX_ADB_RTBASE)
#define VORTEX_ADB_CHNBASE 0x282b4
#define VORTEX_ADB_CHNBASE_SIZE (ADB_MASK - VORTEX_ADB_RTBASE_SIZE)
#define ROUTE_MASK 0xffff
#define SOURCE_MASK 0xff00
#define ADB_MASK 0xff
#define ADB_SHIFT 0x8
/* ADB address */
#define OFFSET_ADBDMA 0x00
#define OFFSET_SRCIN 0x40
#define OFFSET_SRCOUT 0x20
#define OFFSET_MIXIN 0x50
#define OFFSET_MIXOUT 0x30
#define OFFSET_CODECIN 0x70
#define OFFSET_CODECOUT 0x88
#define OFFSET_SPORTIN 0x78 /* ch 0x13 */
#define OFFSET_SPORTOUT 0x90
#define OFFSET_SPDIFOUT 0x92 /* ch 0x14 check this! */
#define OFFSET_EQIN 0xa0
#define OFFSET_EQOUT 0x7e /* 2 routes on ch 0x11 */
#define OFFSET_XTALKOUT 0x66 /* crosstalk canceller (source) */
#define OFFSET_XTALKIN 0x96 /* crosstalk canceller (sink) */
#define OFFSET_EFXIN 0x80 /* ADB sink. */
#define OFFSET_EFXOUT 0x68 /* ADB source. */
/* ADB route translate helper */
#define ADB_DMA(x) (x)
#define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
#define ADB_SRCIN(x) (x + OFFSET_SRCIN)
#define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
#define ADB_MIXIN(x) (x + OFFSET_MIXIN)
#define ADB_CODECIN(x) (x + OFFSET_CODECIN)
#define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
#define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)
#define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
#define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT)
#define ADB_EQIN(x) (x + OFFSET_EQIN)
#define ADB_EQOUT(x) (x + OFFSET_EQOUT)
#define ADB_A3DOUT(x) (x + 0x50) /* A3D blocks */
#define ADB_A3DIN(x) (x + 0x70)
#define ADB_XTALKIN(x) (x + OFFSET_XTALKIN)
#define ADB_XTALKOUT(x) (x + OFFSET_XTALKOUT)
#define MIX_OUTL 0xe
#define MIX_OUTR 0xf
#define MIX_INL 0x1e
#define MIX_INR 0x1f
#define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */
#define MIX_DEFOGAIN 0x08
/* MIXER */
#define VORTEX_MIXER_SR 0x21f00
#define VORTEX_MIXER_CLIP 0x21f80
#define VORTEX_MIXER_CHNBASE 0x21e40
#define VORTEX_MIXER_RTBASE 0x21e00
#define MIXER_RTBASE_SIZE 0x38
#define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */
#define VORTEX_MIX_SMP 0x21c00 /* AU8820: 0x9c00 */
/* MIX */
#define VORTEX_MIX_INVOL_A 0x21000 /* in? */
#define VORTEX_MIX_INVOL_B 0x20000 /* out? */
#define VORTEX_MIX_VOL_A 0x21800
#define VORTEX_MIX_VOL_B 0x20800
#define VOL_MIN 0x80 /* Input volume when muted. */
#define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */
/* SRC */
#define VORTEX_SRCBLOCK_SR 0x26cc0
#define VORTEX_SRC_CHNBASE 0x26c40
#define VORTEX_SRC_RTBASE 0x26c00
#define VORTEX_SRC_SOURCE 0x26cc4
#define VORTEX_SRC_SOURCESIZE 0x26cc8
#define VORTEX_SRC_CONVRATIO 0x26e40
#define VORTEX_SRC_DRIFT0 0x26e80
#define VORTEX_SRC_DRIFT1 0x26ec0
#define VORTEX_SRC_DRIFT2 0x26f40
#define VORTEX_SRC_U0 0x26e00
#define VORTEX_SRC_U1 0x26f00
#define VORTEX_SRC_U2 0x26f80
#define VORTEX_SRC_DATA 0x26800 /* 0xc800 */
#define VORTEX_SRC_DATA0 0x26000
/* FIFO */
#define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */
#define VORTEX_FIFO_WTCTRL 0x16000
#define FIFO_RDONLY 0x00000001
#define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */
#define FIFO_VALID 0x00000010
#define FIFO_EMPTY 0x00000020
#define FIFO_U0 0x00001000 /* Unknown. */
#define FIFO_U1 0x00010000
#define FIFO_SIZE_BITS 5
#define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20
#define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */
//#define FIFO_MASK 0x1f /* at shift left 0xb */
//#define FIFO_SIZE 0x20
#define FIFO_BITS 0x03880000
#define VORTEX_FIFO_ADBDATA 0x14000
#define VORTEX_FIFO_WTDATA 0x10000
/* CODEC */
#define VORTEX_CODEC_CTRL 0x29184
#define VORTEX_CODEC_EN 0x29190
#define EN_CODEC0 0x00000300
#define EN_CODEC1 0x00003000
#define EN_CODEC (EN_CODEC0 | EN_CODEC1)
#define EN_SPORT 0x00030000
#define EN_SPDIF 0x000c0000
#define VORTEX_CODEC_CHN 0x29080
#define VORTEX_CODEC_WRITE 0x00800000
#define VORTEX_CODEC_ADDSHIFT 16
#define VORTEX_CODEC_ADDMASK 0x7f0000 /* 0x000f0000 */
#define VORTEX_CODEC_DATSHIFT 0
#define VORTEX_CODEC_DATMASK 0xffff
#define VORTEX_CODEC_IO 0x29188
/* SPDIF */
#define VORTEX_SPDIF_FLAGS 0x2205c
#define VORTEX_SPDIF_CFG0 0x291D0
#define VORTEX_SPDIF_CFG1 0x291D4
#define VORTEX_SPDIF_SMPRATE 0x29194
/* Sample timer */
#define VORTEX_SMP_TIME 0x29198
/* IRQ */
#define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */
#define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */
#define VORTEX_STAT 0x2a008 /* Status */
#define VORTEX_CTRL 0x2a00c
#define CTRL_MIDI_EN 0x00000001
#define CTRL_MIDI_PORT 0x00000060
#define CTRL_GAME_EN 0x00000008
#define CTRL_GAME_PORT 0x00000e00
//#define CTRL_IRQ_ENABLE 0x01004000
#define CTRL_IRQ_ENABLE 0x00004000
/* write: Timer period config / read: TIMER IRQ ack. */
#define VORTEX_IRQ_STAT 0x2919c
/* DMA */
#define VORTEX_ENGINE_CTRL 0x27ae8
#define ENGINE_INIT 0x1380000
/* MIDI *//* GAME. */
#define VORTEX_MIDI_DATA 0x28800
#define VORTEX_MIDI_CMD 0x28804 /* Write command / Read status */
#define VORTEX_CTRL2 0x2880c
#define CTRL2_GAME_ADCMODE 0x40
#define VORTEX_GAME_LEGACY 0x28808
#define VORTEX_GAME_AXIS 0x28810
#define AXIS_SIZE 4
#define AXIS_RANGE 0x1fff
#include "au8820.h"
#include "au88x0.h"
static struct pci_device_id snd_vortex_ids[] = {
{PCI_VENDOR_ID_AUREAL, PCI_DEVICE_ID_AUREAL_VORTEX,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
{0,}
};
#include "au88x0_synth.c"
#include "au88x0_core.c"
#include "au88x0_pcm.c"
#include "au88x0_mpu401.c"
#include "au88x0_game.c"
#include "au88x0_mixer.c"
#include "au88x0.c"
/*
Aureal Vortex Soundcard driver.
IO addr collected from asp4core.vxd:
function address
0005D5A0 13004
00080674 14004
00080AFF 12818
*/
#define CHIP_AU8820
#define CARD_NAME "Aureal Vortex 3D Sound Processor"
#define CARD_NAME_SHORT "au8820"
#ifndef PCI_VENDOR_ID_AUREAL
#define PCI_VENDOR_ID_AUREAL 0x12eb
#endif
#ifndef PCI_VENDOR_ID_AUREAL_VORTEX
#define PCI_DEVICE_ID_AUREAL_VORTEX 0x0001
#endif
/* Number of ADB and WT channels */
#define NR_ADB 0x10
#define NR_WT 0x20
#define NR_SRC 0x10
#define NR_A3D 0x00
#define NR_MIXIN 0x10
#define NR_MIXOUT 0x10
/* ADBDMA */
#define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */
#define POS_MASK 0x00000fff
#define POS_SHIFT 0x0
#define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
#define ADB_SUBBUF_SHIFT 0xc /* ADB only. */
#define VORTEX_ADBDMA_CTRL 0x10580 /* write only, format, flags, DMA pos */
#define OFFSET_MASK 0x00000fff
#define OFFSET_SHIFT 0x0
#define IE_MASK 0x00001000 /* interrupt enable. */
#define IE_SHIFT 0xc
#define DIR_MASK 0x00002000 /* Direction. */
#define DIR_SHIFT 0xd
#define FMT_MASK 0x0003c000
#define FMT_SHIFT 0xe
// The masks and shift also work for the wtdma, if not specified otherwise.
#define VORTEX_ADBDMA_BUFCFG0 0x10400
#define VORTEX_ADBDMA_BUFCFG1 0x10404
#define VORTEX_ADBDMA_BUFBASE 0x10200
#define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */
#define VORTEX_ADBDMA_STATUS 0x10600 /* stored at AdbDma->this_10 / 2 DWORD in size. */
/* ADB */
#define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */
#define VORTEX_ADB_RTBASE 0x10800
#define VORTEX_ADB_RTBASE_SIZE (VORTEX_ADB_CHNBASE - VORTEX_ADB_RTBASE)
#define VORTEX_ADB_CHNBASE 0x1099c
#define VORTEX_ADB_CHNBASE_SIZE (ADB_MASK - VORTEX_ADB_RTBASE_SIZE)
#define ROUTE_MASK 0x3fff
#define ADB_MASK 0x7f
#define ADB_SHIFT 0x7
//#define ADB_MIX_MASK 0xf
/* ADB address */
#define OFFSET_ADBDMA 0x00
#define OFFSET_SRCOUT 0x10 /* on channel 0x11 */
#define OFFSET_SRCIN 0x10 /* on channel < 0x11 */
#define OFFSET_MIXOUT 0x20 /* source */
#define OFFSET_MIXIN 0x30 /* sink */
#define OFFSET_CODECIN 0x48 /* ADB source */
#define OFFSET_CODECOUT 0x58 /* ADB sink/target */
#define OFFSET_SPORTOUT 0x60 /* sink */
#define OFFSET_SPORTIN 0x50 /* source */
#define OFFSET_EFXOUT 0x50 /* sink */
#define OFFSET_EFXIN 0x40 /* source */
#define OFFSET_A3DOUT 0x00 /* This card has no HRTF :( */
#define OFFSET_A3DIN 0x00
#define OFFSET_WTOUT 0x58 /* */
/* ADB route translate helper */
#define ADB_DMA(x) (x + OFFSET_ADBDMA)
#define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
#define ADB_SRCIN(x) (x + OFFSET_SRCIN)
#define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
#define ADB_MIXIN(x) (x + OFFSET_MIXIN)
#define ADB_CODECIN(x) (x + OFFSET_CODECIN)
#define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
#define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
#define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* */
#define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */
#define ADB_A3DIN(x) (x + OFFSET_A3DIN)
#define ADB_WTOUT(x,y) (y + OFFSET_WTOUT)
/* WTDMA */
#define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */
#define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */
#define WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT)
#define WT_SUBBUF_SHIFT 0x15
#define VORTEX_WTDMA_BUFBASE 0x10000
#define VORTEX_WTDMA_BUFCFG0 0x10300
#define VORTEX_WTDMA_BUFCFG1 0x10304
#define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */
#define VORTEX_WT_BASE 0x9000
/* MIXER */
#define VORTEX_MIXER_SR 0x9f00
#define VORTEX_MIXER_CLIP 0x9f80
#define VORTEX_MIXER_CHNBASE 0x9e40
#define VORTEX_MIXER_RTBASE 0x9e00
#define MIXER_RTBASE_SIZE 0x26
#define VORTEX_MIX_ENIN 0x9a00 /* Input enable bits. 4 bits wide. */
#define VORTEX_MIX_SMP 0x9c00
/* MIX */
#define VORTEX_MIX_INVOL_A 0x9000 /* in? */
#define VORTEX_MIX_INVOL_B 0x8000 /* out? */
#define VORTEX_MIX_VOL_A 0x9800
#define VORTEX_MIX_VOL_B 0x8800
#define VOL_MIN 0x80 /* Input volume when muted. */
#define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */
//#define MIX_OUTL 0xe
//#define MIX_OUTR 0xf
//#define MIX_INL 0xe
//#define MIX_INR 0xf
#define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */
#define MIX_DEFOGAIN 0x08
/* SRC */
#define VORTEX_SRCBLOCK_SR 0xccc0
#define VORTEX_SRC_CHNBASE 0xcc40
#define VORTEX_SRC_RTBASE 0xcc00
#define VORTEX_SRC_SOURCE 0xccc4
#define VORTEX_SRC_SOURCESIZE 0xccc8
#define VORTEX_SRC_U0 0xce00
#define VORTEX_SRC_DRIFT0 0xce80
#define VORTEX_SRC_DRIFT1 0xcec0
#define VORTEX_SRC_U1 0xcf00
#define VORTEX_SRC_DRIFT2 0xcf40
#define VORTEX_SRC_U2 0xcf80
#define VORTEX_SRC_DATA 0xc800
#define VORTEX_SRC_DATA0 0xc000
#define VORTEX_SRC_CONVRATIO 0xce40
//#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */
//#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */
/* FIFO */
#define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */
#define VORTEX_FIFO_WTCTRL 0xf840
#define FIFO_RDONLY 0x00000001
#define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */
#define FIFO_VALID 0x00000010
#define FIFO_EMPTY 0x00000020
#define FIFO_U0 0x00001000 /* Unknown. */
#define FIFO_U1 0x00010000
#define FIFO_SIZE_BITS 5
#define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20
#define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */
#define VORTEX_FIFO_ADBDATA 0xe000
#define VORTEX_FIFO_WTDATA 0xe800
/* CODEC */
#define VORTEX_CODEC_CTRL 0x11984
#define VORTEX_CODEC_EN 0x11990
#define EN_CODEC 0x00000300
#define EN_SPORT 0x00030000
#define EN_SPDIF 0x000c0000
#define VORTEX_CODEC_CHN 0x11880
#define VORTEX_CODEC_WRITE 0x00800000
#define VORTEX_CODEC_ADDSHIFT 16
#define VORTEX_CODEC_ADDMASK 0x7f0000 /* 0x000f0000 */
#define VORTEX_CODEC_DATSHIFT 0
#define VORTEX_CODEC_DATMASK 0xffff
#define VORTEX_CODEC_IO 0x11988
#define VORTEX_SPDIF_FLAGS 0x1005c /* FIXME */
#define VORTEX_SPDIF_CFG0 0x119D0
#define VORTEX_SPDIF_CFG1 0x119D4
#define VORTEX_SPDIF_SMPRATE 0x11994
/* Sample timer */
#define VORTEX_SMP_TIME 0x11998
/* IRQ */
#define VORTEX_IRQ_SOURCE 0x12800 /* Interrupt source flags. */
#define VORTEX_IRQ_CTRL 0x12804 /* Interrupt source mask. */
#define VORTEX_STAT 0x12808 /* ?? */
#define VORTEX_CTRL 0x1280c
#define CTRL_MIDI_EN 0x00000001
#define CTRL_MIDI_PORT 0x00000060
#define CTRL_GAME_EN 0x00000008
#define CTRL_GAME_PORT 0x00000e00
#define CTRL_IRQ_ENABLE 0x4000
/* write: Timer period config / read: TIMER IRQ ack. */
#define VORTEX_IRQ_STAT 0x1199c
/* DMA */
#define VORTEX_DMA_BUFFER 0x10200
#define VORTEX_ENGINE_CTRL 0x1060c
#define ENGINE_INIT 0x0L
/* MIDI *//* GAME. */
#define VORTEX_MIDI_DATA 0x11000
#define VORTEX_MIDI_CMD 0x11004 /* Write command / Read status */
#define VORTEX_GAME_LEGACY 0x11008
#define VORTEX_CTRL2 0x1100c
#define CTRL2_GAME_ADCMODE 0x40
#define VORTEX_GAME_AXIS 0x11010
#define AXIS_SIZE 4
#define AXIS_RANGE 0x1fff
#include "au8830.h"
#include "au88x0.h"
static struct pci_device_id snd_vortex_ids[] = {
{PCI_VENDOR_ID_AUREAL, PCI_DEVICE_ID_AUREAL_VORTEX2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
{0,}
};
#include "au88x0_synth.c"
#include "au88x0_core.c"
#include "au88x0_pcm.c"
#include "au88x0_mixer.c"
#include "au88x0_mpu401.c"
#include "au88x0_game.c"
#include "au88x0_eq.c"
#include "au88x0_a3d.c"
#include "au88x0_xtalk.c"
#include "au88x0.c"
/*
Aureal Vortex Soundcard driver.
IO addr collected from asp4core.vxd:
function address
0005D5A0 13004
00080674 14004
00080AFF 12818
*/
#define CHIP_AU8830
#define CARD_NAME "Aureal Vortex 2 3D Sound Processor"
#define CARD_NAME_SHORT "au8830"
#ifndef PCI_VENDOR_ID_AUREAL
#define PCI_VENDOR_ID_AUREAL 0x12eb
#endif
#ifndef PCI_VENDOR_ID_AUREAL_VORTEX2
#define PCI_DEVICE_ID_AUREAL_VORTEX2 0x0002
#endif
#define hwread(x,y) readl((x)+((y)>>2))
#define hwwrite(x,y,z) writel((z),(x)+((y)>>2))
#define NR_ADB 0x20
#define NR_SRC 0x10
#define NR_A3D 0x10
#define NR_MIXIN 0x20
#define NR_MIXOUT 0x10
#define NR_WT 0x40
/* ADBDMA */
#define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
#define POS_MASK 0x00000fff
#define POS_SHIFT 0x0
#define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
#define ADB_SUBBUF_SHIFT 0xc /* ADB only. */
#define VORTEX_ADBDMA_CTRL 0x27a00 /* write only; format, flags, DMA pos */
#define OFFSET_MASK 0x00000fff
#define OFFSET_SHIFT 0x0
#define IE_MASK 0x00001000 /* interrupt enable. */
#define IE_SHIFT 0xc
#define DIR_MASK 0x00002000 /* Direction. */
#define DIR_SHIFT 0xd
#define FMT_MASK 0x0003c000
#define FMT_SHIFT 0xe
#define ADB_FIFO_EN_SHIFT 0x15
#define ADB_FIFO_EN (1 << 0x15)
// The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
#define VORTEX_ADBDMA_BUFCFG0 0x27800
#define VORTEX_ADBDMA_BUFCFG1 0x27804
#define VORTEX_ADBDMA_BUFBASE 0x27400
#define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */
#define VORTEX_ADBDMA_STATUS 0x27A90 /* stored at AdbDma->this_10 / 2 DWORD in size. */
/* Starting at MSB, each pair seem to be the current DMA page. */
/* This current page bits are consistent (same value) with VORTEX_ADBDMA_STAT) */
/* DMA */
#define VORTEX_ENGINE_CTRL 0x27ae8
#define ENGINE_INIT 0x1380000
/* WTDMA */
#define VORTEX_WTDMA_CTRL 0x27900 /* format, DMA pos */
#define VORTEX_WTDMA_STAT 0x27d00 /* DMA subbuf, DMA pos */
#define WT_SUBBUF_MASK 0x3
#define WT_SUBBUF_SHIFT 0xc
#define VORTEX_WTDMA_BUFBASE 0x27000
#define VORTEX_WTDMA_BUFCFG0 0x27600
#define VORTEX_WTDMA_BUFCFG1 0x27604
#define VORTEX_WTDMA_START 0x27b00 /* which subbuffer is first */
/* ADB */
#define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */
#define VORTEX_ADB_RTBASE 0x28000
#define VORTEX_ADB_RTBASE_SIZE (VORTEX_ADB_CHNBASE - VORTEX_ADB_RTBASE)
#define VORTEX_ADB_CHNBASE 0x282b4
#define VORTEX_ADB_CHNBASE_SIZE (ADB_MASK - VORTEX_ADB_RTBASE_SIZE)
#define ROUTE_MASK 0xffff
#define SOURCE_MASK 0xff00
#define ADB_MASK 0xff
#define ADB_SHIFT 0x8
/* ADB address */
#define OFFSET_ADBDMA 0x00
#define OFFSET_ADBDMAB 0x20
#define OFFSET_SRCIN 0x40
#define OFFSET_SRCOUT 0x20 /* ch 0x11 */
#define OFFSET_MIXIN 0x50 /* ch 0x11 */
#define OFFSET_MIXOUT 0x30 /* ch 0x11 */
#define OFFSET_CODECIN 0x70 /* ch 0x11 */ /* adb source */
#define OFFSET_CODECOUT 0x88 /* ch 0x11 */ /* adb target */
#define OFFSET_SPORTIN 0x78 /* ch 0x13 ADB source. 2 routes. */
#define OFFSET_SPORTOUT 0x90 /* ch 0x13 ADB sink. 2 routes. */
#define OFFSET_SPDIFIN 0x7A /* ch 0x14 ADB source. */
#define OFFSET_SPDIFOUT 0x92 /* ch 0x14 ADB sink. */
#define OFFSET_AC98IN 0x7c /* ch 0x14 ADB source. */
#define OFFSET_AC98OUT 0x94 /* ch 0x14 ADB sink. */
#define OFFSET_EQIN 0xa0 /* ch 0x11 */
#define OFFSET_EQOUT 0x7e /* ch 0x11 */ /* 2 routes on ch 0x11 */
#define OFFSET_A3DIN 0x70 /* ADB sink. */
#define OFFSET_A3DOUT 0xA6 /* ADB source. 2 routes per slice = 8 */
#define OFFSET_WT0 0x40 /* WT bank 0 output. 0x40 - 0x65 */
#define OFFSET_WT1 0x80 /* WT bank 1 output. 0x80 - 0xA5 */
/* WT sources offset : 0x00-0x1f Direct stream. */
/* WT sources offset : 0x20-0x25 Mixed Output. */
#define OFFSET_XTALKOUT 0x66 /* crosstalk canceller (source) 2 routes */
#define OFFSET_XTALKIN 0x96 /* crosstalk canceller (sink). 10 routes */
#define OFFSET_EFXOUT 0x68 /* ADB source. 8 routes. */
#define OFFSET_EFXIN 0x80 /* ADB sink. 8 routes. */
/* ADB route translate helper */
#define ADB_DMA(x) (x)
#define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
#define ADB_SRCIN(x) (x + OFFSET_SRCIN)
#define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
#define ADB_MIXIN(x) (x + OFFSET_MIXIN)
#define ADB_CODECIN(x) (x + OFFSET_CODECIN)
#define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
#define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)
#define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
#define ADB_SPDIFIN(x) (x + OFFSET_SPDIFIN)
#define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT)
#define ADB_EQIN(x) (x + OFFSET_EQIN)
#define ADB_EQOUT(x) (x + OFFSET_EQOUT)
#define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 0x10 A3D blocks */
#define ADB_A3DIN(x) (x + OFFSET_A3DIN)
//#define ADB_WTOUT(x) ((x<x20)?(x + OFFSET_WT0):(x + OFFSET_WT1))
#define ADB_WTOUT(x,y) (((x)==0)?((y) + OFFSET_WT0):((y) + OFFSET_WT1))
#define ADB_XTALKIN(x) ((x) + OFFSET_XTALKIN)
#define ADB_XTALKOUT(x) ((x) + OFFSET_XTALKOUT)
#define MIX_DEFIGAIN 0x08
#define MIX_DEFOGAIN 0x08 /* 0x8->6dB (6dB = x4) 16 to 18 bit conversion? */
/* MIXER */
#define VORTEX_MIXER_SR 0x21f00
#define VORTEX_MIXER_CLIP 0x21f80
#define VORTEX_MIXER_CHNBASE 0x21e40
#define VORTEX_MIXER_RTBASE 0x21e00
#define MIXER_RTBASE_SIZE 0x38
#define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */
#define VORTEX_MIX_SMP 0x21c00 /* wave data buffers. AU8820: 0x9c00 */
/* MIX */
#define VORTEX_MIX_INVOL_B 0x20000 /* Input volume current */
#define VORTEX_MIX_VOL_B 0x20800 /* Output Volume current */
#define VORTEX_MIX_INVOL_A 0x21000 /* Input Volume target */
#define VORTEX_MIX_VOL_A 0x21800 /* Output Volume target */
#define VOL_MIN 0x80 /* Input volume when muted. */
#define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */
/* SRC */
#define VORTEX_SRC_CHNBASE 0x26c40
#define VORTEX_SRC_RTBASE 0x26c00
#define VORTEX_SRCBLOCK_SR 0x26cc0
#define VORTEX_SRC_SOURCE 0x26cc4
#define VORTEX_SRC_SOURCESIZE 0x26cc4
/* Params
0x26e00 : 1 U0
0x26e40 : 2 CR
0x26e80 : 3 U3
0x26ec0 : 4 DRIFT1
0x26f00 : 5 U1
0x26f40 : 6 DRIFT2
0x26f80 : 7 U2 : Target rate, direction
*/
#define VORTEX_SRC_CONVRATIO 0x26e40
#define VORTEX_SRC_DRIFT0 0x26e80
#define VORTEX_SRC_DRIFT1 0x26ec0
#define VORTEX_SRC_DRIFT2 0x26f40
#define VORTEX_SRC_U0 0x26e00
#define U0_SLOWLOCK 0x200
#define VORTEX_SRC_U1 0x26f00
#define VORTEX_SRC_U2 0x26f80
#define VORTEX_SRC_DATA 0x26800 /* 0xc800 */
#define VORTEX_SRC_DATA0 0x26000
/* FIFO */
#define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */
#define VORTEX_FIFO_WTCTRL 0x16000
#define FIFO_RDONLY 0x00000001
#define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */
#define FIFO_VALID 0x00000010
#define FIFO_EMPTY 0x00000020
#define FIFO_U0 0x00002000 /* Unknown. */
#define FIFO_U1 0x00040000
#define FIFO_SIZE_BITS 6
#define FIFO_SIZE (1<<(FIFO_SIZE_BITS)) // 0x40
#define FIFO_MASK (FIFO_SIZE-1) //0x3f /* at shift left 0xc */
#define FIFO_BITS 0x1c400000
#define VORTEX_FIFO_ADBDATA 0x14000
#define VORTEX_FIFO_WTDATA 0x10000
#define VORTEX_FIFO_GIRT 0x17000 /* wt0, wt1, adb */
#define GIRT_COUNT 3
/* CODEC */
#define VORTEX_CODEC_CHN 0x29080 /* The name "CHN" is wrong. */
#define VORTEX_CODEC_CTRL 0x29184
#define VORTEX_CODEC_IO 0x29188
#define VORTEX_CODEC_WRITE 0x00800000
#define VORTEX_CODEC_ADDSHIFT 16
#define VORTEX_CODEC_ADDMASK 0x7f0000 /* 0x000f0000 */
#define VORTEX_CODEC_DATSHIFT 0
#define VORTEX_CODEC_DATMASK 0xffff
#define VORTEX_CODEC_SPORTCTRL 0x2918c
#define VORTEX_CODEC_EN 0x29190
#define EN_AUDIO0 0x00000300
#define EN_MODEM 0x00000c00
#define EN_AUDIO1 0x00003000
#define EN_SPORT 0x00030000
#define EN_SPDIF 0x000c0000
#define EN_CODEC (EN_AUDIO1 | EN_AUDIO0)
#define VORTEX_SPDIF_SMPRATE 0x29194
#define VORTEX_SPDIF_FLAGS 0x2205c
#define VORTEX_SPDIF_CFG0 0x291D0 /* status data */
#define VORTEX_SPDIF_CFG1 0x291D4
#define VORTEX_SMP_TIME 0x29198 /* Sample counter/timer */
#define VORTEX_SMP_TIMER 0x2919c
#define VORTEX_CODEC2_CTRL 0x291a0
#define VORTEX_MODEM_CTRL 0x291ac
/* IRQ */
#define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */
#define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */
//#define VORTEX_IRQ_U0 0x2a008 /* ?? */
#define VORTEX_STAT 0x2a008 /* Some sort of status */
#define STAT_IRQ 0x00000001 /* This bitis set if the IRQ is valid. */
#define VORTEX_CTRL 0x2a00c
#define CTRL_MIDI_EN 0x00000001
#define CTRL_MIDI_PORT 0x00000060
#define CTRL_GAME_EN 0x00000008
#define CTRL_GAME_PORT 0x00000e00
#define CTRL_IRQ_ENABLE 0x00004000
#define CTRL_SPDIF 0x00000000 /* unknown. Please find this value */
#define CTRL_SPORT 0x00200000
#define CTRL_RST 0x00800000
#define CTRL_UNKNOWN 0x01000000
/* write: Timer period config / read: TIMER IRQ ack. */
#define VORTEX_IRQ_STAT 0x2919c
/* MIDI *//* GAME. */
#define VORTEX_MIDI_DATA 0x28800
#define VORTEX_MIDI_CMD 0x28804 /* Write command / Read status */
#define VORTEX_GAME_LEGACY 0x28808
#define VORTEX_CTRL2 0x2880c
#define CTRL2_GAME_ADCMODE 0x40
#define VORTEX_GAME_AXIS 0x28810 /* Axis base register. 4 axis's */
#define AXIS_SIZE 4
#define AXIS_RANGE 0x1fff
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/*
Aureal Vortex Soundcard driver.
IO addr collected from asp4core.vxd:
function address
0005D5A0 13004
00080674 14004
00080AFF 12818
*/
#ifndef __SOUND_AU88X0_H
#define __SOUND_AU88X0_H
#ifdef __KERNEL__
#include <sound/driver.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/rawmidi.h>
#include <sound/mpu401.h>
#include <sound/hwdep.h>
#include <sound/ac97_codec.h>
/*
#ifndef PCI_VENDOR_ID_AUREAL
#define PCI_VENDOR_ID_AUREAL 0x12eb
#endif
#ifndef PCI_VENDOR_ID_AUREAL_VORTEX
#define PCI_DEVICE_ID_AUREAL_VORTEX 0x0001
#endif
#ifndef PCI_VENDOR_ID_AUREAL_VORTEX2
#define PCI_DEVICE_ID_AUREAL_VORTEX2 0x0002
#endif
#ifndef PCI_VENDOR_ID_AUREAL_ADVANTAGE
#define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003
#endif
*/
#endif
#ifndef CHIP_AU8820
#include "au88x0_eq.h"
#include "au88x0_a3d.h"
#endif
#ifndef CHIP_AU8810
#include "au88x0_wt.h"
#endif
#define VORTEX_DMA_MASK 0xffffffff
#define hwread(x,y) readl((x)+((y)>>2))
#define hwwrite(x,y,z) writel((z),(x)+((y)>>2))
/* Vortex MPU401 defines. */
#define MIDI_CLOCK_DIV 0x61
/* Standart MPU401 defines. */
#define MPU401_RESET 0xff
#define MPU401_ENTER_UART 0x3f
#define MPU401_ACK 0xfe
// Get src register value to convert from x to y.
#define SRC_RATIO(x,y) ((((x<<15)/y) + 1)/2)
/* FIFO software state constants. */
#define FIFO_STOP 0
#define FIFO_START 1
#define FIFO_PAUSE 2
/* IRQ flags */
#define IRQ_ERR_MASK 0x00ff
#define IRQ_FATAL 0x0001
#define IRQ_PARITY 0x0002
#define IRQ_REG 0x0004
#define IRQ_FIFO 0x0008
#define IRQ_DMA 0x0010
#define IRQ_PCMOUT 0x0020 /* PCM OUT page crossing */
#define IRQ_TIMER 0x1000
#define IRQ_MIDI 0x2000
#define IRQ_MODEM 0x4000
/* ADB Resource */
#define VORTEX_RESOURCE_DMA 0x00000000
#define VORTEX_RESOURCE_SRC 0x00000001
#define VORTEX_RESOURCE_MIXIN 0x00000002
#define VORTEX_RESOURCE_MIXOUT 0x00000003
#define VORTEX_RESOURCE_A3D 0x00000004
#define VORTEX_RESOURCE_LAST 0x00000005
/* Check for SDAC bit in "Extended audio ID" AC97 register */
#define VORTEX_IS_QUAD(x) ((x->codec == NULL) ? 0 : (x->codec->ext_id|0x80))
/* PCM devices */
#define VORTEX_PCM_ADB 0
#define VORTEX_PCM_SPDIF 1
#define VORTEX_PCM_A3D 2
#define VORTEX_PCM_WT 3
#define VORTEX_PCM_I2S 4
#define VORTEX_PCM_LAST 5
#define MIX_CAPT(x) (vortex->mixcapt[x])
#define MIX_PLAYB(x) (vortex->mixplayb[x])
#define MIX_SPDIF(x) (vortex->mixspdif[x])
#define NR_WTPB 0x20 /* WT channels per eahc bank. */
/* Structs */
typedef struct {
//int this_08; /* Still unknown */
int fifo_enabled; /* this_24 */
int fifo_status; /* this_1c */
int dma_ctrl; /* this_78 (ADB), this_7c (WT) */
int dma_unknown; /* this_74 (ADB), this_78 (WT). WDM: +8 */
int cfg0;
int cfg1;
int nr_ch; /* Nr of PCM channels in use */
int type; /* Output type (ac97, a3d, spdif, i2s, dsp) */
int dma; /* Hardware DMA index. */
int dir; /* Stream Direction. */
u32 resources[5];
/* Virtual page extender stuff */
int nr_periods;
int period_bytes;
snd_pcm_sgbuf_t *sgbuf; /* DMA Scatter Gather struct */
int period_real;
int period_virt;
snd_pcm_substream_t *substream;
} stream_t;
typedef struct snd_vortex vortex_t;
struct snd_vortex {
/* ALSA structs. */
snd_card_t *card;
snd_pcm_t *pcm[VORTEX_PCM_LAST];
snd_rawmidi_t *rmidi; /* Legacy Midi interface. */
ac97_t *codec;
/* Stream structs. */
stream_t dma_adb[NR_ADB];
int spdif_sr;
#ifndef CHIP_AU8810
stream_t dma_wt[NR_WT];
wt_voice_t wt_voice[NR_WT]; /* WT register cache. */
char mixwt[(NR_WT / NR_WTPB) * 6]; /* WT mixin objects */
#endif
/* Global resources */
char mixcapt[2];
char mixplayb[4];
#ifndef CHIP_AU8820
char mixspdif[2];
char mixa3d[2]; /* mixers which collect all a3d streams. */
char mixxtlk[2]; /* crosstalk canceler mixer inputs. */
#endif
u32 fixed_res[5];
#ifndef CHIP_AU8820
/* Hardware equalizer structs */
eqlzr_t eq;
/* A3D structs */
a3dsrc_t a3d[NR_A3D];
/* Xtalk canceler */
int xt_mode; /* 1: speakers, 0:headphones. */
#endif
/* Gameport stuff. */
struct gameport *gameport;
/* PCI hardware resources */
unsigned long io;
unsigned long *mmio;
unsigned int irq;
spinlock_t lock;
/* PCI device */
struct pci_dev *pci_dev;
u16 vendor;
u16 device;
u8 rev;
};
#define chip_t vortex_t
/* Functions. */
/* SRC */
static void vortex_adb_setsrc(vortex_t * vortex, int adbdma,
unsigned int cvrt, int dir);
/* DMA Engines. */
static void vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma,
snd_pcm_sgbuf_t * sgbuf, int size,
int count);
static void vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie,
int dir, int fmt, int d,
unsigned long offset);
static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb);
#ifndef CHIP_AU8810
static void vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma,
snd_pcm_sgbuf_t * sgbuf, int size,
int count);
static void vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d, /*int e, */
unsigned long offset);
static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb);
#endif
static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma);
//static void vortex_adbdma_stopfifo(vortex_t *vortex, int adbdma);
static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma);
static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma);
static int inline vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma);
#ifndef CHIP_AU8810
static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma);
static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma);
static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma);
static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma);
static int inline vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma);
#endif
/* global stuff. */
static void vortex_codec_init(vortex_t * vortex);
static void vortex_codec_write(ac97_t * codec, unsigned short addr,
unsigned short data);
static unsigned short vortex_codec_read(ac97_t * codec, unsigned short addr);
static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode);
static int vortex_core_init(vortex_t * card);
static int vortex_core_shutdown(vortex_t * card);
static void vortex_enable_int(vortex_t * card);
static irqreturn_t vortex_interrupt(int irq, void *dev_id,
struct pt_regs *regs);
static int vortex_alsafmt_aspfmt(int alsafmt);
/* Connection stuff. */
static void vortex_connect_default(vortex_t * vortex, int en);
static int vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch,
int dir, int type);
static char vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out,
int restype);
#ifndef CHIP_AU8810
static int vortex_wt_allocroute(vortex_t * vortex, int dma, int nr_ch);
static void vortex_wt_connect(vortex_t * vortex, int en);
static void vortex_wt_init(vortex_t * vortex);
#endif
static void vortex_route(vortex_t * vortex, int en, unsigned char channel,
unsigned char source, unsigned char dest);
#if 0
static void vortex_routes(vortex_t * vortex, int en, unsigned char channel,
unsigned char source, unsigned char dest0,
unsigned char dest1);
#endif
static void vortex_connection_mixin_mix(vortex_t * vortex, int en,
unsigned char mixin,
unsigned char mix, int a);
static void vortex_mix_setinputvolumebyte(vortex_t * vortex,
unsigned char mix, int mixin,
unsigned char vol);
static void vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix,
unsigned char vol);
/* A3D functions. */
#ifndef CHIP_AU8820
static void vortex_Vort3D(vortex_t * v, int en);
static void vortex_Vort3D_connect(vortex_t * vortex, int en);
static void vortex_Vort3D_InitializeSource(a3dsrc_t * a, int en);
#endif
/* Driver stuff. */
static int __devinit vortex_gameport_register(vortex_t * card);
static int __devexit vortex_gameport_unregister(vortex_t * card);
#ifndef CHIP_AU8820
static int __devinit vortex_eq_init(vortex_t * vortex);
static int __devexit vortex_eq_free(vortex_t * vortex);
#endif
/* ALSA stuff. */
static int __devinit snd_vortex_new_pcm(vortex_t * vortex, int idx, int nr);
static int __devinit snd_vortex_mixer(vortex_t * vortex);
static int __devinit snd_vortex_midi(vortex_t * vortex);
#endif
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/***************************************************************************
* au88x0_a3d.h
*
* Fri Jul 18 14:16:03 2003
* Copyright 2003 mjander
* mjander@users.sourceforge.net
****************************************************************************/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Library General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _AU88X0_A3D_H
#define _AU88X0_A3D_H
//#include <openal.h>
#define HRTF_SZ 0x38
#define DLINE_SZ 0x28
#define CTRLID_HRTF 1
#define CTRLID_ITD 2
#define CTRLID_ILD 4
#define CTRLID_FILTER 8
#define CTRLID_GAINS 16
/* 3D parameter structs */
typedef unsigned short int a3d_Hrtf_t[HRTF_SZ];
typedef unsigned short int a3d_ItdDline_t[DLINE_SZ];
typedef unsigned short int a3d_atmos_t[5];
typedef unsigned short int a3d_LRGains_t[2];
typedef unsigned short int a3d_Itd_t[2];
typedef unsigned short int a3d_Ild_t[2];
typedef struct {
void *vortex; // Formerly CAsp4HwIO*, now vortex_t*.
unsigned int source; /* this_04 */
unsigned int slice; /* this_08 */
a3d_Hrtf_t hrtf[2];
a3d_Itd_t itd;
a3d_Ild_t ild;
a3d_ItdDline_t dline;
a3d_atmos_t filter;
} a3dsrc_t;
/* First Register bank */
#define A3D_A_HrtfCurrent 0x18000 /* 56 ULONG */
#define A3D_A_GainCurrent 0x180E0
#define A3D_A_GainTarget 0x180E4
#define A3D_A_A12Current 0x180E8 /* Atmospheric current. */
#define A3D_A_A21Target 0x180EC /* Atmospheric target */
#define A3D_A_B01Current 0x180F0 /* Atmospheric current */
#define A3D_A_B10Target 0x180F4 /* Atmospheric target */
#define A3D_A_B2Current 0x180F8 /* Atmospheric current */
#define A3D_A_B2Target 0x180FC /* Atmospheric target */
#define A3D_A_HrtfTarget 0x18100 /* 56 ULONG */
#define A3D_A_ITDCurrent 0x181E0
#define A3D_A_ITDTarget 0x181E4
#define A3D_A_HrtfDelayLine 0x181E8 /* 56 ULONG */
#define A3D_A_ITDDelayLine 0x182C8 /* 40/45 ULONG */
#define A3D_A_HrtfTrackTC 0x1837C /* Time Constants */
#define A3D_A_GainTrackTC 0x18380
#define A3D_A_CoeffTrackTC 0x18384
#define A3D_A_ITDTrackTC 0x18388
#define A3D_A_x1 0x1838C
#define A3D_A_x2 0x18390
#define A3D_A_y1 0x18394
#define A3D_A_y2 0x18398
#define A3D_A_HrtfOutL 0x1839C
#define A3D_A_HrtfOutR 0x183A0
#define A3D_A_TAIL 0x183A4
/* Second register bank */
#define A3D_B_HrtfCurrent 0x19000 /* 56 ULONG */
#define A3D_B_GainCurrent 0x190E0
#define A3D_B_GainTarget 0x190E4
#define A3D_B_A12Current 0x190E8
#define A3D_B_A21Target 0x190EC
#define A3D_B_B01Current 0x190F0
#define A3D_B_B10Target 0x190F4
#define A3D_B_B2Current 0x190F8
#define A3D_B_B2Target 0x190FC
#define A3D_B_HrtfTarget 0x19100 /* 56 ULONG */
#define A3D_B_ITDCurrent 0x191E0
#define A3D_B_ITDTarget 0x191E4
#define A3D_B_HrtfDelayLine 0x191E8 /* 56 ULONG */
#define A3D_B_TAIL 0x192C8
/* There are 4 slices, 4 a3d each = 16 a3d sources. */
#define A3D_SLICE_BANK_A 0x18000 /* 4 sources */
#define A3D_SLICE_BANK_B 0x19000 /* 4 sources */
#define A3D_SLICE_VDBDest 0x19C00 /* 8 ULONG */
#define A3D_SLICE_VDBSource 0x19C20 /* 4 ULONG */
#define A3D_SLICE_ABReg 0x19C30
#define A3D_SLICE_CReg 0x19C34
#define A3D_SLICE_Control 0x19C38
#define A3D_SLICE_DebugReserved 0x19C3c /* Dangerous! */
#define A3D_SLICE_Pointers 0x19C40
#define A3D_SLICE_TAIL 0x1A000
// Slice size: 0x2000
// Source size: 0x3A4, 0x2C8
/* Address generator macro. */
#define a3d_addrA(slice,source,reg) (((slice)<<0xd)+((source)*0x3A4)+(reg))
#define a3d_addrB(slice,source,reg) (((slice)<<0xd)+((source)*0x2C8)+(reg))
#define a3d_addrS(slice,reg) (((slice)<<0xd)+(reg))
//#define a3d_addr(slice,source,reg) (((reg)>=0x19000) ? a3d_addr2((slice),(source),(reg)) : a3d_addr1((slice),(source),(reg)))
#endif /* _AU88X0_A3D_H */
/***************************************************************************
* au88x0_a3ddata.c
*
* Wed Nov 19 21:11:32 2003
* Copyright 2003 mjander
* mjander@users.sourceforge.org
****************************************************************************/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Library General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* Constant initializer values. */
static const a3d_Hrtf_t A3dHrirZeros = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0,
0, 0, 0
};
static const a3d_Hrtf_t A3dHrirImpulse = {
0x7fff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0,
0, 0, 0
};
static const a3d_Hrtf_t A3dHrirOnes = {
0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
0x7fff,
0x7fff,
0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
0x7fff,
0x7fff,
0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
0x7fff,
0x7fff,
0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
0x7fff,
0x7fff,
0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff
};
static const a3d_Hrtf_t A3dHrirSatTest = {
0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
0x7fff,
0x7fff,
0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001,
0x8001,
0x8001,
0x7fff, 0x0000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
static const a3d_Hrtf_t A3dHrirDImpulse = {
0, 0x7fff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0,
0, 0, 0
};
static const a3d_ItdDline_t A3dItdDlineZeros = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
static short const GainTCDefault = 0x300;
static short const ItdTCDefault = 0x0C8;
static short const HrtfTCDefault = 0x147;
static short const CoefTCDefault = 0x300;
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#ifndef AU88X0_EQ_H
#define AU88X0_EQ_H
/***************************************************************************
* au88x0_eq.h
*
* Definitions and constant data for the Aureal Hardware EQ.
*
* Sun Jun 8 18:23:38 2003
* Author: Manuel Jander (mjander@users.sourceforge.net)
****************************************************************************/
typedef struct {
u16 LeftCoefs[50]; //0x4
u16 RightCoefs[50]; // 0x68
u16 LeftGains[20]; //0xd0
u16 RightGains[20]; //0xe4
} auxxEqCoeffSet_t;
typedef struct {
unsigned int *this00; /*CAsp4HwIO */
long this04; /* How many filters for each side (default = 10) */
long this08; /* inited to cero. Stereo flag? */
} eqhw_t;
typedef struct {
unsigned int *this00; /*CAsp4Core */
eqhw_t this04; /* CHwEq */
short this08; /* Bad codec flag ? SetBypassGain: bypass gain */
short this0a;
short this0c; /* SetBypassGain: bypass gain when this28 is not set. */
short this0e;
long this10; /* How many gains are used for each side (right or left). */
u16 this14[32]; /* SetLeftGainsTarget: Left (and right?) EQ gains */
long this24;
long this28; /* flag related to EQ enabled or not. Gang flag ? */
long this54; /* SetBypass */
long this58;
long this5c;
/*0x60 */ auxxEqCoeffSet_t coefset;
/* 50 u16 word each channel. */
u16 this130[20]; /* Left and Right gains */
} eqlzr_t;
#endif
/* Data structs */
static u16 asEqCoefsZeros[50] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};
static u16 asEqCoefsPipes[64] = {
0x0000, 0x0000,
0x0000, 0x0666, 0x0000, 0x0000, 0x0666,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0666, 0x0000, 0x0000, 0x0666,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0666, 0x0000, 0x0000, 0x0666,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0666, 0x0000, 0x0000, 0x0666,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0666, 0x0000, 0x0000, 0x066a,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000
};
/* More coef sets can be found in the win2k "inf" file. */
static auxxEqCoeffSet_t asEqCoefsNormal = {
.LeftCoefs = {
0x7e60, 0xc19e, 0x0001, 0x0002, 0x0001,
0x7fa0, 0xc05f, 0x004f, 0x0000, 0xffb1,
0x7f3f, 0xc0bc, 0x00c2, 0x0000, 0xff3e,
0x7e78, 0xc177, 0x011f, 0x0000, 0xfee1,
0x7cd6, 0xc2e5, 0x025c, 0x0000, 0xfda4,
0x7949, 0xc5aa, 0x0467, 0x0000, 0xfb99,
0x7120, 0xcadf, 0x0864, 0x0000, 0xf79c,
0x5d33, 0xd430, 0x0f7e, 0x0000, 0xf082,
0x2beb, 0xe3ca, 0x1bd3, 0x0000, 0xe42d,
0xd740, 0xf01d, 0x2ac5, 0x0000, 0xd53b},
.RightCoefs = {
0x7e60, 0xc19e, 0x0001, 0x0002, 0x0001,
0x7fa0, 0xc05f, 0x004f, 0x0000, 0xffb1,
0x7f3f, 0xc0bc, 0x00c2, 0x0000, 0xff3e,
0x7e78, 0xc177, 0x011f, 0x0000, 0xfee1,
0x7cd6, 0xc2e5, 0x025c, 0x0000, 0xfda4,
0x7949, 0xc5aa, 0x0467, 0x0000, 0xfb99,
0x7120, 0xcadf, 0x0864, 0x0000, 0xf79c,
0x5d33, 0xd430, 0x0f7e, 0x0000, 0xf082,
0x2beb, 0xe3ca, 0x1bd3, 0x0000, 0xe42d,
0xd740, 0xf01d, 0x2ac5, 0x0000, 0xd53b},
.LeftGains = {
0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96,
0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96},
.RightGains = {
0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96,
0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96}
};
static u16 eq_gains_normal[20] = {
0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96,
0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96,
0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96,
0x3e96, 0x3e96, 0x3e96, 0x3e96, 0x3e96
};
/* _rodatab60 */
static u16 eq_gains_zero[10] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};
/* _rodatab7c: ProgramPipe */
static u16 eq_gains_current[12] = {
0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
0x7fff,
0x7fff, 0x7fff, 0x7fff
};
/* _rodatab78 */
static u16 eq_states_zero[2] = { 0x0000, 0x0000 };
static u16 asEqOutStateZeros[48] = {
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000
};
/*_rodataba0:*/
static long eq_levels[32] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};
/*
* $Id: au88x0_game.c,v 1.9 2003/09/22 03:51:28 mjander Exp $
*
* Manuel Jander.
*
* Based on the work of:
* Vojtech Pavlik
* Raymond Ingles
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Should you need to contact me, the author, you can do so either by
* e-mail - mail your message to <vojtech@suse.cz>, or by paper mail:
* Vojtech Pavlik, Ucitelska 1576, Prague 8, 182 00 Czech Republic
*
* Based 90% on Vojtech Pavlik pcigame driver.
* Merged and modified by Manuel Jander, for the OpenVortex
* driver. (email: mjander@embedded.cl).
*/
#include <sound/driver.h>
#include <linux/time.h>
#include <linux/init.h>
#include <sound/core.h>
#include "au88x0.h"
#include <linux/gameport.h>
#define VORTEX_GAME_DWAIT 20 /* 20 ms */
static struct gameport gameport;
static unsigned char vortex_game_read(struct gameport *gameport)
{
vortex_t *vortex = gameport->driver;
return hwread(vortex->mmio, VORTEX_GAME_LEGACY);
}
static void vortex_game_trigger(struct gameport *gameport)
{
vortex_t *vortex = gameport->driver;
hwwrite(vortex->mmio, VORTEX_GAME_LEGACY, 0xff);
}
static int
vortex_game_cooked_read(struct gameport *gameport, int *axes, int *buttons)
{
vortex_t *vortex = gameport->driver;
int i;
*buttons = (~hwread(vortex->mmio, VORTEX_GAME_LEGACY) >> 4) & 0xf;
for (i = 0; i < 4; i++) {
axes[i] =
hwread(vortex->mmio, VORTEX_GAME_AXIS + (i * AXIS_SIZE));
if (axes[i] == AXIS_RANGE)
axes[i] = -1;
}
return 0;
}
static int vortex_game_open(struct gameport *gameport, int mode)
{
vortex_t *vortex = gameport->driver;
switch (mode) {
case GAMEPORT_MODE_COOKED:
hwwrite(vortex->mmio, VORTEX_CTRL2,
hwread(vortex->mmio,
VORTEX_CTRL2) | CTRL2_GAME_ADCMODE);
wait_ms(VORTEX_GAME_DWAIT);
return 0;
case GAMEPORT_MODE_RAW:
hwwrite(vortex->mmio, VORTEX_CTRL2,
hwread(vortex->mmio,
VORTEX_CTRL2) & ~CTRL2_GAME_ADCMODE);
return 0;
default:
return -1;
}
return 0;
}
static int vortex_gameport_register(vortex_t * vortex)
{
vortex->gameport = &gameport;
vortex->gameport->driver = vortex;
vortex->gameport->fuzz = 64;
vortex->gameport->read = vortex_game_read;
vortex->gameport->trigger = vortex_game_trigger;
vortex->gameport->cooked_read = vortex_game_cooked_read;
vortex->gameport->open = vortex_game_open;
gameport_register_port((struct gameport *)vortex->gameport);
/* printk(KERN_INFO "gameport%d: %s at speed %d kHz\n",
vortex->gameport->number, vortex->pci_dev->name, vortex->gameport->speed);
*/
return 0;
}
static int vortex_gameport_unregister(vortex_t * vortex)
{
if (vortex->gameport != NULL)
gameport_unregister_port(vortex->gameport);
return 0;
}
/*
* Vortex Mixer support.
*
* There is much more than just the AC97 mixer...
*
*/
#include <sound/driver.h>
#include <linux/time.h>
#include <linux/init.h>
#include <sound/core.h>
#include "au88x0.h"
static int __devinit snd_vortex_mixer(vortex_t * vortex)
{
ac97_bus_t bus, *pbus;
ac97_t ac97;
int err;
memset(&bus, 0, sizeof(bus));
bus.write = vortex_codec_write;
bus.read = vortex_codec_read;
if ((err = snd_ac97_bus(vortex->card, &bus, &pbus)) < 0)
return err;
memset(&ac97, 0, sizeof(ac97));
// Intialize AC97 codec stuff.
ac97.private_data = vortex;
return snd_ac97_mixer(pbus, &ac97, &vortex->codec);
}
/*
* Copyright (c) by Jaroslav Kysela <perex@suse.cz>
* Routines for control of MPU-401 in UART mode
*
* Modified for the Aureal Vortex based Soundcards
* by Manuel Jander (mjande@embedded.cl).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <linux/time.h>
#include <linux/init.h>
#include <sound/core.h>
#include <sound/mpu401.h>
#include "au88x0.h"
/* Check for mpu401 mmio support. */
/* MPU401 legacy support is only provided as a emergency fallback *
* for older versions of ALSA. Its usage is strongly discouraged. */
#ifndef MPU401_HW_AUREAL
#define VORTEX_MPU401_LEGACY
#endif
/* Vortex MPU401 defines. */
#define MIDI_CLOCK_DIV 0x61
/* Standart MPU401 defines. */
#define MPU401_RESET 0xff
#define MPU401_ENTER_UART 0x3f
#define MPU401_ACK 0xfe
static int __devinit snd_vortex_midi(vortex_t * vortex)
{
snd_rawmidi_t *rmidi;
int temp, mode;
mpu401_t *mpu;
int port;
#ifdef VORTEX_MPU401_LEGACY
/* EnableHardCodedMPU401Port() */
/* Enable Legacy MIDI Interface port. */
port = (0x03 << 5); /* FIXME: static address. 0x330 */
temp =
(hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) |
CTRL_MIDI_EN | port;
hwwrite(vortex->mmio, VORTEX_CTRL, temp);
#else
/* Disable Legacy MIDI Interface port. */
temp =
(hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) &
~CTRL_MIDI_EN;
hwwrite(vortex->mmio, VORTEX_CTRL, temp);
#endif
/* Mpu401UartInit() */
mode = 1;
temp = hwread(vortex->mmio, VORTEX_CTRL2) & 0xffff00cf;
temp |= (MIDI_CLOCK_DIV << 8) | ((mode >> 24) & 0xff) << 4;
hwwrite(vortex->mmio, VORTEX_CTRL2, temp);
hwwrite(vortex->mmio, VORTEX_MIDI_CMD, MPU401_RESET);
/* Set some kind of mode */
if (mode)
hwwrite(vortex->mmio, VORTEX_MIDI_CMD, MPU401_ENTER_UART);
/* Check if anything is OK. */
temp = hwread(vortex->mmio, VORTEX_MIDI_DATA);
if (temp != MPU401_ACK /*0xfe */ ) {
printk(KERN_ERR "midi port doesn't acknowledge!\n");
return -ENODEV;
}
/* Enable MPU401 interrupts. */
hwwrite(vortex->mmio, VORTEX_IRQ_CTRL,
hwread(vortex->mmio, VORTEX_IRQ_CTRL) | IRQ_MIDI);
/* Create MPU401 instance. */
#ifdef VORTEX_MPU401_LEGACY
if ((temp =
snd_mpu401_uart_new(vortex->card, 0, MPU401_HW_MPU401, 0x330,
0, 0, 0, &rmidi)) != 0) {
hwwrite(vortex->mmio, VORTEX_CTRL,
(hwread(vortex->mmio, VORTEX_CTRL) &
~CTRL_MIDI_PORT) & ~CTRL_MIDI_EN);
return temp;
}
#else
port = (unsigned long)(vortex->mmio + (VORTEX_MIDI_DATA >> 2));
if ((temp =
snd_mpu401_uart_new(vortex->card, 0, MPU401_HW_AUREAL, port,
1, 0, 0, &rmidi)) != 0) {
hwwrite(vortex->mmio, VORTEX_CTRL,
(hwread(vortex->mmio, VORTEX_CTRL) &
~CTRL_MIDI_PORT) & ~CTRL_MIDI_EN);
return temp;
}
mpu = snd_magic_cast(mpu401_t, rmidi->private_data, return -ENOMEM);
mpu->cport = (unsigned long)(vortex->mmio + (VORTEX_MIDI_CMD >> 2));
#endif
vortex->rmidi = rmidi;
return 0;
}
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/***************************************************************************
* au88x0_sb.h
*
* Wed Oct 29 22:10:42 2003
*
****************************************************************************/
#ifdef CHIP_AU8820
/* AU8820 starting @ 64KiB offset */
#define SBEMU_BASE 0x10000
#else
/* AU8810? and AU8830 starting @ 164KiB offset */
#define SBEMU_BASE 0x29000
#endif
#define FM_A_STATUS (SBEMU_BASE + 0x00) /* read */
#define FM_A_ADDRESS (SBEMU_BASE + 0x00) /* write */
#define FM_A_DATA (SBEMU_BASE + 0x04)
#define FM_B_STATUS (SBEMU_BASE + 0x08)
#define FM_B_ADDRESS (SBEMU_BASE + 0x08)
#define FM_B_DATA (SBEMU_BASE + 0x0C)
#define SB_MIXER_ADDR (SBEMU_BASE + 0x10)
#define SB_MIXER_DATA (SBEMU_BASE + 0x14)
#define SB_RESET (SBEMU_BASE + 0x18)
#define SB_RESET_ALIAS (SBEMU_BASE + 0x1C)
#define FM_STATUS2 (SBEMU_BASE + 0x20)
#define FM_ADDR2 (SBEMU_BASE + 0x20)
#define FM_DATA2 (SBEMU_BASE + 0x24)
#define SB_DSP_READ (SBEMU_BASE + 0x28)
#define SB_DSP_WRITE (SBEMU_BASE + 0x30)
#define SB_DSP_WRITE_STATUS (SBEMU_BASE + 0x30) /* bit 7 */
#define SB_DSP_READ_STATUS (SBEMU_BASE + 0x38) /* bit 7 */
#define SB_LACR (SBEMU_BASE + 0x40) /* ? */
#define SB_LADCR (SBEMU_BASE + 0x44) /* ? */
#define SB_LAMR (SBEMU_BASE + 0x48) /* ? */
#define SB_LARR (SBEMU_BASE + 0x4C) /* ? */
#define SB_VERSION (SBEMU_BASE + 0x50)
#define SB_CTRLSTAT (SBEMU_BASE + 0x54)
#define SB_TIMERSTAT (SBEMU_BASE + 0x58)
#define FM_RAM (SBEMU_BASE + 0x100) /* 0x40 ULONG */
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/***************************************************************************
* WT register offsets.
*
* Wed Oct 22 13:50:20 2003
* Copyright 2003 mjander
* mjander@users.sourceforge.org
****************************************************************************/
#ifndef _AU88X0_WT_H
#define _AU88X0_WT_H
/* WT channels are grouped in banks. Each bank has 0x20 channels. */
/* Bank register address boundary is 0x8000 */
#define NR_WT_PB 0x20
/* WT bank base register (as dword address). */
#define WT_BAR(x) (((x)&0xffe0)<<0x8)
#define WT_BANK(x) (x>>5)
/* WT Bank registers */
#define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */
#define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */
#define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */
#define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */
#define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */
#define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */
/* WT Voice registers */
#define WT_STEREO(voice) ((WT_BAR(voice)+ 0x20 +(((voice)&0x1f)>>1))<<2) /* 0x0080 */
#define WT_MUTE(voice) ((WT_BAR(voice)+ 0x40 +((voice)&0x1f))<<2) /* 0x0100 */
#define WT_RUN(voice) ((WT_BAR(voice)+ 0x60 +((voice)&0x1f))<<2) /* 0x0180 */
/* Some kind of parameters. */
/* PARM0, PARM1 : Filter (0xFF000000), SampleRate (0x0000FFFF) */
/* PARM2, PARM3 : Still unknown */
#define WT_PARM(x,y) (((WT_BAR(x))+ 0x80 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0200 */
#define WT_DELAY(x,y) (((WT_BAR(x))+ 0x100 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0400 */
/* Numeric indexes used by SetReg() and GetReg() */
#if 0
enum {
run = 0, /* 0 W 1:run 0:stop */
parm0, /* 1 W filter, samplerate */
parm1, /* 2 W filter, samplerate */
parm2, /* 3 W */
parm3, /* 4 RW volume. This value is calculated using floating point ops. */
sramp, /* 5 W */
mute, /* 6 W 1:mute, 0:unmute */
gmode, /* 7 RO Looks like only bit0 is used. */
aramp, /* 8 W */
mramp, /* 9 W */
ctrl, /* a W */
delay, /* b W All 4 values are written at once with same value. */
dsreg, /* c (R)W */
} wt_reg;
#endif
typedef struct {
unsigned int parm0; /* this_1E4 */
unsigned int parm1; /* this_1E8 */
unsigned int parm2; /* this_1EC */
unsigned int parm3; /* this_1F0 */
unsigned int this_1D0;
} wt_voice_t;
#endif /* _AU88X0_WT_H */
/* End of file */
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/***************************************************************************
* au88x0_cxtalk.h
*
* Wed Nov 19 19:07:17 2003
* Copyright 2003 mjander
* mjander@users.sourceforge.org
****************************************************************************/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Library General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* The crosstalk canceler supports 5 stereo input channels. The result is
available at one single output route pair (stereo). */
#ifndef _AU88X0_CXTALK_H
#define _AU88X0_CXTALK_H
#include "au88x0.h"
#define XTDLINE_SZ 32
#define XTGAINS_SZ 10
#define XTINST_SZ 4
#define XT_HEADPHONE 1
#define XT_SPEAKER0 2
#define XT_SPEAKER1 3
#define XT_DIAMOND 4
typedef long xtalk_dline_t[XTDLINE_SZ];
typedef short xtalk_gains_t[XTGAINS_SZ];
typedef short xtalk_instate_t[XTINST_SZ];
typedef short xtalk_coefs_t[5][5];
typedef short xtalk_state_t[5][4];
extern xtalk_gains_t const asXtalkGainsAllChan;
static void vortex_XtalkHw_SetGains(vortex_t * vortex,
xtalk_gains_t const gains);
static void vortex_XtalkHw_SetSampleRate(vortex_t * vortex, int sr);
static void vortex_XtalkHw_ProgramPipe(vortex_t * vortex);
static void vortex_XtalkHw_ProgramPipe(vortex_t * vortex);
static void vortex_XtalkHw_ProgramXtalkWide(vortex_t * vortex);
static void vortex_XtalkHw_ProgramXtalkNarrow(vortex_t * vortex);
static void vortex_XtalkHw_ProgramDiamondXtalk(vortex_t * vortex);
static void vortex_XtalkHw_Enable(vortex_t * vortex);
static void vortex_XtalkHw_Disable(vortex_t * vortex);
static void vortex_XtalkHw_init(vortex_t * vortex);
#endif /* _AU88X0_CXTALK_H */
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