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Commit 6d1e66bb authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'omap-for-v4.10/legacy-signed' of... 

Merge tag 'omap-for-v4.10/legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

Legacy platform_data removal for omaps for v4.10 merge window.
We've dropped the last legacy boot board-*.c files for mach-omap2
for v4.9 so now we can start removing the unused platform_data.

All of the below has been unused since v4.9 merge window:

- Drop legacy pmic init code
- Apply seq_puts() fixes for legacy mux code, then drop it
- Drop legacy serial init
- Drop legacy i2c init
- Drop legacy PM init
- Drop legacy twl4030 platform init
- Drop legacy USB host init
- Drop legacy muxing for tusb6010, n8x0 is still using it's
  platform init via pdata-quirks.c
- Drop legacy musb init
- Drop hwmod related legacy mux code
- Drop legacy hwmod data for omap3
- Drop legacy smsc911x and smc91x init
- Drop legacy board flash init
- Drop legacy ads7846 init
- Drop legacy sdram timings

* tag 'omap-for-v4.10/legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
  ARM: OMAP2+: Drop legacy sdram timings
  ARM: OMAP2+: Drop legacy ads7846 init
  ARM: OMAP2+: Remove legacy board-flash.c
  ARM: OMAP2+: Remove legacy smsc911x and smc91x GPMC support
  ARM: OMAP2+: Remove legacy data from hwmod for omap3
  ARM: OMAP2+: Remove legacy mux code
  ARM: OMAP2+: Remove legacy hwmod mux code
  ARM: OMAP2+: Remove legacy usb-musb.c platform init code
  ARM: OMAP2+: Remove legacy muxing for usb-tusb6010.c
  ARM: OMAP2+: Remove legacy usb-host.c platform init code
  ARM: OMAP2+: Remove legacy twl4030 platform init code
  ARM: OMAP2+: Remove legacy PM init
  ARM: OMAP2+: Remove legacy i2c.c platform init code
  ARM: OMAP2+: Remove legacy serial.c
  ARM: OMAP2+: mux: Use seq_putc() in omap_mux_dbg_signal_show()
  ARM: OMAP2+: mux: Replace three seq_printf() calls by seq_puts()
  ARM: OMAP: kill omap_pmic_init
  ARM: OMAP2: kill omap2_pmic_init
  ARM: OMAP3: kill omap3_pmic_init
  ARM: OMAP3: kill omap3_pmic_get_config and twl_{get,set}_voltage
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents a9fa1f7c 19944b3a
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arch/arm/mach-omap1/Kconfig
View file @ 6d1e66bb
...@@ -31,6 +31,32 @@ config ARCH_OMAP16XX ...@@ -31,6 +31,32 @@ config ARCH_OMAP16XX
select ARCH_OMAP_OTG select ARCH_OMAP_OTG
select CPU_ARM926T select CPU_ARM926T
config OMAP_MUX
bool "OMAP multiplexing support"
depends on ARCH_OMAP
default y
help
Pin multiplexing support for OMAP boards. If your bootloader
sets the multiplexing correctly, say N. Otherwise, or if unsure,
say Y.
config OMAP_MUX_DEBUG
bool "Multiplexing debug output"
depends on OMAP_MUX
help
Makes the multiplexing functions print out a lot of debug info.
This is useful if you want to find out the correct values of the
multiplexing registers.
config OMAP_MUX_WARNINGS
bool "Warn about pins the bootloader didn't set up"
depends on OMAP_MUX
default y
help
Choose Y here to warn whenever driver initialization logic needs
to change the pin multiplexing setup. When there are no warnings
printed, it's safe to deselect OMAP_MUX for your product.
comment "OMAP Board Type" comment "OMAP Board Type"
depends on ARCH_OMAP1 depends on ARCH_OMAP1
......
arch/arm/mach-omap1/i2c.c
View file @ 6d1e66bb
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
* *
*/ */
#include <linux/i2c.h>
#include <linux/i2c-omap.h> #include <linux/i2c-omap.h>
#include <mach/mux.h> #include <mach/mux.h>
#include "soc.h" #include "soc.h"
...@@ -91,6 +92,88 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata, ...@@ -91,6 +92,88 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
return platform_device_register(pdev); return platform_device_register(pdev);
} }
#define OMAP_I2C_MAX_CONTROLLERS 4
static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
/**
* omap_i2c_bus_setup - Process command line options for the I2C bus speed
* @str: String of options
*
* This function allow to override the default I2C bus speed for given I2C
* bus with a command line option.
*
* Format: i2c_bus=bus_id,clkrate (in kHz)
*
* Returns 1 on success, 0 otherwise.
*/
static int __init omap_i2c_bus_setup(char *str)
{
int ints[3];
get_options(str, 3, ints);
if (ints[0] < 2 || ints[1] < 1 ||
ints[1] > OMAP_I2C_MAX_CONTROLLERS)
return 0;
i2c_pdata[ints[1] - 1].clkrate = ints[2];
i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
return 1;
}
__setup("i2c_bus=", omap_i2c_bus_setup);
/*
* Register busses defined in command line but that are not registered with
* omap_register_i2c_bus from board initialization code.
*/
int __init omap_register_i2c_bus_cmdline(void)
{
int i, err = 0;
for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
err = omap_i2c_add_bus(&i2c_pdata[i], i + 1);
if (err)
goto out;
}
out:
return err;
}
/**
* omap_register_i2c_bus - register I2C bus with device descriptors
* @bus_id: bus id counting from number 1
* @clkrate: clock rate of the bus in kHz
* @info: pointer into I2C device descriptor table or NULL
* @len: number of descriptors in the table
*
* Returns 0 on success or an error code.
*/
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
int err;
BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
if (info) {
err = i2c_register_board_info(bus_id, info, len);
if (err)
return err;
}
if (!i2c_pdata[bus_id - 1].clkrate)
i2c_pdata[bus_id - 1].clkrate = clkrate;
i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id);
}
static int __init omap_i2c_cmdline(void) static int __init omap_i2c_cmdline(void)
{ {
return omap_register_i2c_bus_cmdline(); return omap_register_i2c_bus_cmdline();
......
arch/arm/mach-omap2/Makefile
View file @ 6d1e66bb
...@@ -6,7 +6,7 @@ ccflags-y := -I$(srctree)/$(src)/include \ ...@@ -6,7 +6,7 @@ ccflags-y := -I$(srctree)/$(src)/include \
-I$(srctree)/arch/arm/plat-omap/include -I$(srctree)/arch/arm/plat-omap/include
# Common support # Common support
obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \ obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \
common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
omap_device.o omap-headsmp.o sram.o drm.o omap_device.o omap-headsmp.o sram.o drm.o
...@@ -63,9 +63,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o ...@@ -63,9 +63,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
# Pin multiplexing
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
# SMS/SDRC # SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
...@@ -235,26 +232,15 @@ obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o ...@@ -235,26 +232,15 @@ obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
# Platform specific device init code # Platform specific device init code
omap-flash-$(CONFIG_MTD_NAND_OMAP2) := board-flash.o
omap-flash-$(CONFIG_MTD_ONENAND_OMAP2) := board-flash.o
obj-y += $(omap-flash-y) $(omap-flash-m)
omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
obj-y += usb-musb.o
obj-y += omap_phy_internal.o obj-y += omap_phy_internal.o
obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
obj-y += usb-host.o
onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
obj-y += $(onenand-m) $(onenand-y) obj-y += $(onenand-m) $(onenand-y)
nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o
obj-y += $(nand-m) $(nand-y) obj-y += $(nand-m) $(nand-y)
smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
obj-y += $(smsc911x-m) $(smsc911x-y)
obj-y += common-board-devices.o twl-common.o dss-common.o
arch/arm/mach-omap2/board-flash.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* board-flash.c
* Modified from mach-omap2/board-3430sdp-flash.c
*
* Copyright (C) 2009 Nokia Corporation
* Copyright (C) 2009 Texas Instruments
*
* Vimal Singh <vimalsingh@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/omap-gpmc.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <linux/platform_data/mtd-nand-omap2.h>
#include <linux/platform_data/mtd-onenand-omap2.h>
#include "soc.h"
#include "common.h"
#include "board-flash.h"
#define REG_FPGA_REV 0x10
#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
#define MAX_SUPPORTED_GPMC_CONFIG 3
#define DEBUG_BASE 0x08000000 /* debug board */
/* various memory sizes */
#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */
#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */
static struct physmap_flash_data board_nor_data = {
.width = 2,
};
static struct resource board_nor_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device board_nor_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &board_nor_data,
},
.num_resources = 1,
.resource = &board_nor_resource,
};
static void
__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
{
int err;
board_nor_data.parts = nor_parts;
board_nor_data.nr_parts = nr_parts;
/* Configure start address and size of NOR device */
if (omap_rev() >= OMAP3430_REV_ES1_0) {
err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
(unsigned long *)&board_nor_resource.start);
board_nor_resource.end = board_nor_resource.start
+ FLASH_SIZE_SDPV2 - 1;
} else {
err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
(unsigned long *)&board_nor_resource.start);
board_nor_resource.end = board_nor_resource.start
+ FLASH_SIZE_SDPV1 - 1;
}
if (err < 0) {
pr_err("NOR: Can't request GPMC CS\n");
return;
}
if (platform_device_register(&board_nor_device) < 0)
pr_err("Unable to register NOR device\n");
}
#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
static struct omap_onenand_platform_data board_onenand_data = {
.dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
};
void
__init board_onenand_init(struct mtd_partition *onenand_parts,
u8 nr_parts, u8 cs)
{
board_onenand_data.cs = cs;
board_onenand_data.parts = onenand_parts;
board_onenand_data.nr_parts = nr_parts;
gpmc_onenand_init(&board_onenand_data);
}
#endif /* IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) */
#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
/* Note that all values in this struct are in nanoseconds */
struct gpmc_timings nand_default_timings[1] = {
{
.sync_clk = 0,
.cs_on = 0,
.cs_rd_off = 36,
.cs_wr_off = 36,
.we_on = 6,
.oe_on = 6,
.adv_on = 6,
.adv_rd_off = 24,
.adv_wr_off = 36,
.we_off = 30,
.oe_off = 48,
.access = 54,
.rd_cycle = 72,
.wr_cycle = 72,
.wr_access = 30,
.wr_data_mux_bus = 0,
},
};
static struct omap_nand_platform_data board_nand_data;
void
__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
int nand_type, struct gpmc_timings *gpmc_t)
{
board_nand_data.cs = cs;
board_nand_data.parts = nand_parts;
board_nand_data.nr_parts = nr_parts;
board_nand_data.devsize = nand_type;
board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
gpmc_nand_init(&board_nand_data, gpmc_t);
}
#endif /* IS_ENABLED(CONFIG_MTD_NAND_OMAP2) */
/**
* get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
* the various cs values.
*/
static u8 get_gpmc0_type(void)
{
u8 cs = 0;
void __iomem *fpga_map_addr;
fpga_map_addr = ioremap(DEBUG_BASE, 4096);
if (!fpga_map_addr)
return -ENOMEM;
if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
/* we dont have an DEBUG FPGA??? */
/* Depend on #defines!! default to strata boot return param */
goto unmap;
/* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
/* ES2.0 SDP's onwards 4 dip switches are provided for CS */
if (omap_rev() >= OMAP3430_REV_ES1_0)
/* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
((cs & 2) << 1) | ((cs & 1) << 3);
else
/* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
unmap:
iounmap(fpga_map_addr);
return cs;
}
/**
* board_flash_init - Identify devices connected to GPMC and register.
*
* @return - void.
*/
void __init board_flash_init(struct flash_partitions partition_info[],
char chip_sel_board[][GPMC_CS_NUM], int nand_type)
{
u8 cs = 0;
u8 norcs = GPMC_CS_NUM + 1;
u8 nandcs = GPMC_CS_NUM + 1;
u8 onenandcs = GPMC_CS_NUM + 1;
u8 idx;
unsigned char *config_sel = NULL;
/* REVISIT: Is this return correct idx for 2430 SDP?
* for which cs configuration matches for 2430 SDP?
*/
idx = get_gpmc0_type();
if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
pr_err("%s: Invalid chip select: %d\n", __func__, cs);
return;
}
config_sel = (unsigned char *)(chip_sel_board[idx]);
while (cs < GPMC_CS_NUM) {
switch (config_sel[cs]) {
case PDC_NOR:
if (norcs > GPMC_CS_NUM)
norcs = cs;
break;
case PDC_NAND:
if (nandcs > GPMC_CS_NUM)
nandcs = cs;
break;
case PDC_ONENAND:
if (onenandcs > GPMC_CS_NUM)
onenandcs = cs;
break;
}
cs++;
}
if (norcs > GPMC_CS_NUM)
pr_err("NOR: Unable to find configuration in GPMC\n");
else
board_nor_init(partition_info[0].parts,
partition_info[0].nr_parts, norcs);
if (onenandcs > GPMC_CS_NUM)
pr_err("OneNAND: Unable to find configuration in GPMC\n");
else
board_onenand_init(partition_info[1].parts,
partition_info[1].nr_parts, onenandcs);
if (nandcs > GPMC_CS_NUM)
pr_err("NAND: Unable to find configuration in GPMC\n");
else
board_nand_init(partition_info[2].parts,
partition_info[2].nr_parts, nandcs,
nand_type, nand_default_timings);
}
arch/arm/mach-omap2/board-flash.h deleted 100644 → 0
View file @ a9fa1f7c
/*
* board-sdp.h
*
* Information structures for SDP-specific board config data
*
* Copyright (C) 2009 Nokia Corporation
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#define PDC_NOR 1
#define PDC_NAND 2
#define PDC_ONENAND 3
#define DBG_MPDB 4
struct flash_partitions {
struct mtd_partition *parts;
int nr_parts;
};
#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) || IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
extern void board_flash_init(struct flash_partitions [],
char chip_sel[][GPMC_CS_NUM], int nand_type);
#else
static inline void board_flash_init(struct flash_partitions part[],
char chip_sel[][GPMC_CS_NUM], int nand_type)
{
}
#endif
#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
extern void board_nand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
extern struct gpmc_timings nand_default_timings[];
#else
static inline void board_nand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
{
}
#define nand_default_timings NULL
#endif
#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
extern void board_onenand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs);
#else
static inline void board_onenand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs)
{
}
#endif
arch/arm/mach-omap2/common-board-devices.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* common-board-devices.c
*
* Copyright (C) 2011 CompuLab, Ltd.
* Author: Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include "common.h"
#include "common-board-devices.h"
#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
static struct omap2_mcspi_device_config ads7846_mcspi_config = {
.turbo_mode = 0,
};
static struct ads7846_platform_data ads7846_config = {
.x_max = 0x0fff,
.y_max = 0x0fff,
.x_plate_ohms = 180,
.pressure_max = 255,
.debounce_max = 10,
.debounce_tol = 3,
.debounce_rep = 1,
.gpio_pendown = -EINVAL,
.keep_vref_on = 1,
};
static struct spi_board_info ads7846_spi_board_info __initdata = {
.modalias = "ads7846",
.bus_num = -EINVAL,
.chip_select = 0,
.max_speed_hz = 1500000,
.controller_data = &ads7846_mcspi_config,
.irq = -EINVAL,
.platform_data = &ads7846_config,
};
void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
struct ads7846_platform_data *board_pdata)
{
struct spi_board_info *spi_bi = &ads7846_spi_board_info;
int err;
/*
* If a board defines get_pendown_state() function, request the pendown
* GPIO and set the GPIO debounce time.
* If a board does not define the get_pendown_state() function, then
* the ads7846 driver will setup the pendown GPIO itself.
*/
if (board_pdata && board_pdata->get_pendown_state) {
err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
if (err) {
pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
return;
}
if (gpio_debounce)
gpio_set_debounce(gpio_pendown, gpio_debounce);
gpio_export(gpio_pendown, 0);
}
spi_bi->bus_num = bus_num;
spi_bi->irq = gpio_to_irq(gpio_pendown);
ads7846_config.gpio_pendown = gpio_pendown;
if (board_pdata) {
board_pdata->gpio_pendown = gpio_pendown;
board_pdata->gpio_pendown_debounce = gpio_debounce;
spi_bi->platform_data = board_pdata;
}
spi_register_board_info(&ads7846_spi_board_info, 1);
}
#else
void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
struct ads7846_platform_data *board_pdata)
{
}
#endif
arch/arm/mach-omap2/common-board-devices.h
View file @ 6d1e66bb
...@@ -3,15 +3,7 @@ ...@@ -3,15 +3,7 @@
#include <sound/tlv320aic3x.h> #include <sound/tlv320aic3x.h>
#include <linux/mfd/menelaus.h> #include <linux/mfd/menelaus.h>
#include "twl-common.h"
#define NAND_BLOCK_SIZE SZ_128K
struct mtd_partition;
struct ads7846_platform_data;
void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
struct ads7846_platform_data *board_pdata);
void *n8x0_legacy_init(void); void *n8x0_legacy_init(void);
extern struct menelaus_platform_data n8x0_menelaus_platform_data; extern struct menelaus_platform_data n8x0_menelaus_platform_data;
......
arch/arm/mach-omap2/common.h
View file @ 6d1e66bb
...@@ -77,15 +77,6 @@ static inline int omap4_pm_init_early(void) ...@@ -77,15 +77,6 @@ static inline int omap4_pm_init_early(void)
} }
#endif #endif
#ifdef CONFIG_OMAP_MUX
int omap_mux_late_init(void);
#else
static inline int omap_mux_late_init(void)
{
return 0;
}
#endif
extern void omap2_init_common_infrastructure(void); extern void omap2_init_common_infrastructure(void);
extern void omap_init_time(void); extern void omap_init_time(void);
......
arch/arm/mach-omap2/devices.c
View file @ 6d1e66bb
...@@ -30,7 +30,6 @@ ...@@ -30,7 +30,6 @@
#include "soc.h" #include "soc.h"
#include "common.h" #include "common.h"
#include "mux.h"
#include "control.h" #include "control.h"
#include "display.h" #include "display.h"
......
arch/arm/mach-omap2/dss-common.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* Copyright (C) 2012 Texas Instruments, Inc..
* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
/*
* NOTE: this is a transitional file to help with DT adaptation.
* This file will be removed when DSS supports DT.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/platform_data/omapdss.h>
#include <video/omap-panel-data.h>
#include "soc.h"
#include "dss-common.h"
#include "mux.h"
#include "display.h"
arch/arm/mach-omap2/dss-common.h deleted 100644 → 0
View file @ a9fa1f7c
#ifndef __OMAP_DSS_COMMON__
#define __OMAP_DSS_COMMON__
/*
* NOTE: this is a transitional file to help with DT adaptation.
* This file will be removed when DSS supports DT.
*/
void __init omap4_panda_display_init_of(void);
void __init omap_4430sdp_display_init_of(void);
void __init omap3_igep2_display_init_of(void);
#endif
arch/arm/mach-omap2/gpmc-smsc911x.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* linux/arch/arm/mach-omap2/gpmc-smsc911x.c
*
* Copyright (C) 2009 Li-Pro.Net
* Stephan Linz <linz@li-pro.net>
*
* Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/smsc911x.h>
#include "gpmc.h"
#include "gpmc-smsc911x.h"
static struct resource gpmc_smsc911x_resources[] = {
[0] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
static struct smsc911x_platform_config gpmc_smsc911x_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
};
/*
* Initialize smsc911x device connected to the GPMC. Note that we
* assume that pin multiplexing is done in the board-*.c file,
* or in the bootloader.
*/
void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *gpmc_cfg)
{
struct platform_device *pdev;
unsigned long cs_mem_base;
int ret;
if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
pr_err("Failed to request GPMC mem region\n");
return;
}
gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0;
gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff;
if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "smsc911x irq")) {
pr_err("Failed to request IRQ GPIO%d\n", gpmc_cfg->gpio_irq);
goto free1;
}
gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
if (gpio_is_valid(gpmc_cfg->gpio_reset)) {
ret = gpio_request_one(gpmc_cfg->gpio_reset,
GPIOF_OUT_INIT_HIGH, "smsc911x reset");
if (ret) {
pr_err("Failed to request reset GPIO%d\n",
gpmc_cfg->gpio_reset);
goto free2;
}
gpio_set_value(gpmc_cfg->gpio_reset, 0);
msleep(100);
gpio_set_value(gpmc_cfg->gpio_reset, 1);
}
gpmc_smsc911x_config.flags = gpmc_cfg->flags ? : SMSC911X_USE_16BIT;
pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id,
gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
&gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));
if (IS_ERR(pdev)) {
pr_err("Unable to register platform device\n");
gpio_free(gpmc_cfg->gpio_reset);
goto free2;
}
return;
free2:
gpio_free(gpmc_cfg->gpio_irq);
free1:
gpmc_cs_free(gpmc_cfg->cs);
pr_err("Could not initialize smsc911x device\n");
}
arch/arm/mach-omap2/gpmc-smsc911x.h deleted 100644 → 0
View file @ a9fa1f7c
/*
* arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
*
* Copyright (C) 2009 Li-Pro.Net
* Stephan Linz <linz@li-pro.net>
*
* Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
struct omap_smsc911x_platform_data {
int id;
int cs;
int gpio_irq;
int gpio_reset;
u32 flags;
};
#if IS_ENABLED(CONFIG_SMSC911X)
extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
#else
static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
{
}
#endif
#endif
arch/arm/mach-omap2/hsmmc.c
View file @ 6d1e66bb
...@@ -22,7 +22,6 @@ ...@@ -22,7 +22,6 @@
#include "omap_device.h" #include "omap_device.h"
#include "omap-pm.h" #include "omap-pm.h"
#include "mux.h"
#include "hsmmc.h" #include "hsmmc.h"
#include "control.h" #include "control.h"
...@@ -147,91 +146,6 @@ static int nop_mmc_set_power(struct device *dev, int power_on, int vdd) ...@@ -147,91 +146,6 @@ static int nop_mmc_set_power(struct device *dev, int power_on, int vdd)
return 0; return 0;
} }
static inline void omap_hsmmc_mux(struct omap_hsmmc_platform_data
*mmc_controller, int controller_nr)
{
if (gpio_is_valid(mmc_controller->gpio_cd) &&
(mmc_controller->gpio_cd < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->gpio_cd,
OMAP_PIN_INPUT_PULLUP);
if (gpio_is_valid(mmc_controller->gpio_cod) &&
(mmc_controller->gpio_cod < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->gpio_cod,
OMAP_PIN_INPUT_PULLUP);
if (gpio_is_valid(mmc_controller->gpio_wp) &&
(mmc_controller->gpio_wp < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->gpio_wp,
OMAP_PIN_INPUT_PULLUP);
if (cpu_is_omap34xx()) {
if (controller_nr == 0) {
omap_mux_init_signal("sdmmc1_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat0",
OMAP_PIN_INPUT_PULLUP);
if (mmc_controller->caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc1_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc1_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
if (controller_nr == 1) {
/* MMC2 */
omap_mux_init_signal("sdmmc2_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat0",
OMAP_PIN_INPUT_PULLUP);
/*
* For 8 wire configurations, Lines DAT4, 5, 6 and 7
* need to be muxed in the board-*.c files
*/
if (mmc_controller->caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc2_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
/*
* For MMC3 the pins need to be muxed in the board-*.c files
*/
}
}
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
struct omap_hsmmc_platform_data *mmc) struct omap_hsmmc_platform_data *mmc)
{ {
...@@ -410,8 +324,6 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo, ...@@ -410,8 +324,6 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
if (res < 0) if (res < 0)
goto free_mmc; goto free_mmc;
omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
name = "omap_hsmmc"; name = "omap_hsmmc";
res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
"mmc%d", ctrl_nr); "mmc%d", ctrl_nr);
......
arch/arm/mach-omap2/i2c.c
View file @ 6d1e66bb
...@@ -26,7 +26,6 @@ ...@@ -26,7 +26,6 @@
#include "prm.h" #include "prm.h"
#include "common.h" #include "common.h"
#include "mux.h"
#include "i2c.h" #include "i2c.h"
/* In register I2C_CON, Bit 15 is the I2C enable bit */ /* In register I2C_CON, Bit 15 is the I2C enable bit */
...@@ -36,20 +35,6 @@ ...@@ -36,20 +35,6 @@
#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16 #define MAX_OMAP_I2C_HWMOD_NAME_LEN 16
static void __init omap2_i2c_mux_pins(int bus_id)
{
char mux_name[sizeof("i2c2_scl.i2c2_scl")];
/* First I2C bus is not muxable */
if (bus_id == 1)
return;
sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
}
/** /**
* omap_i2c_reset - reset the omap i2c module. * omap_i2c_reset - reset the omap i2c module.
* @oh: struct omap_hwmod * * @oh: struct omap_hwmod *
...@@ -107,85 +92,3 @@ int omap_i2c_reset(struct omap_hwmod *oh) ...@@ -107,85 +92,3 @@ int omap_i2c_reset(struct omap_hwmod *oh)
return 0; return 0;
} }
static int __init omap_i2c_nr_ports(void)
{
int ports = 0;
if (cpu_is_omap24xx())
ports = 2;
else if (cpu_is_omap34xx())
ports = 3;
else if (cpu_is_omap44xx())
ports = 4;
return ports;
}
/*
* XXX This function is a temporary compatibility wrapper - only
* needed until the I2C driver can be converted to call
* omap_pm_set_max_dev_wakeup_lat() and handle a return code.
*/
static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
{
omap_pm_set_max_mpu_wakeup_lat(dev, t);
}
static const char name[] = "omap_i2c";
int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
int bus_id)
{
int l;
struct omap_hwmod *oh;
struct platform_device *pdev;
char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
struct omap_i2c_bus_platform_data *pdata;
struct omap_i2c_dev_attr *dev_attr;
if (bus_id > omap_i2c_nr_ports())
return -EINVAL;
omap2_i2c_mux_pins(bus_id);
l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
"String buffer overflow in I2C%d device setup\n", bus_id);
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
return -EEXIST;
}
pdata = i2c_pdata;
/*
* pass the hwmod class's CPU-specific knowledge of I2C IP revision in
* use, and functionality implementation flags, up to the OMAP I2C
* driver via platform data
*/
pdata->rev = oh->class->rev;
dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
pdata->flags = dev_attr->flags;
/*
* When waiting for completion of a i2c transfer, we need to
* set a wake up latency constraint for the MPU. This is to
* ensure quick enough wakeup from idle, when transfer
* completes.
* Only omap3 has support for constraints
*/
if (cpu_is_omap34xx())
pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
pdev = omap_device_build(name, bus_id, oh, pdata,
sizeof(struct omap_i2c_bus_platform_data));
WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
return PTR_ERR_OR_ZERO(pdev);
}
static int __init omap_i2c_cmdline(void)
{
return omap_register_i2c_bus_cmdline();
}
omap_subsys_initcall(omap_i2c_cmdline);
arch/arm/mach-omap2/io.c
View file @ 6d1e66bb
...@@ -427,7 +427,6 @@ static void __init omap_hwmod_init_postsetup(void) ...@@ -427,7 +427,6 @@ static void __init omap_hwmod_init_postsetup(void)
static void __init __maybe_unused omap_common_late_init(void) static void __init __maybe_unused omap_common_late_init(void)
{ {
omap_mux_late_init();
omap2_common_pm_late_init(); omap2_common_pm_late_init();
omap_soc_device_init(); omap_soc_device_init();
} }
......
arch/arm/mach-omap2/msdi.c
View file @ 6d1e66bb
...@@ -30,7 +30,6 @@ ...@@ -30,7 +30,6 @@
#include "control.h" #include "control.h"
#include "omap_hwmod.h" #include "omap_hwmod.h"
#include "omap_device.h" #include "omap_device.h"
#include "mux.h"
#include "mmc.h" #include "mmc.h"
/* /*
......
arch/arm/mach-omap2/mux.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* linux/arch/arm/mach-omap2/mux.c
*
* OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
*
* Copyright (C) 2004 - 2010 Texas Instruments Inc.
* Copyright (C) 2003 - 2008 Nokia Corporation
*
* Written by Tony Lindgren
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/uaccess.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include "omap_hwmod.h"
#include "soc.h"
#include "control.h"
#include "mux.h"
#include "prm.h"
#include "common.h"
#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
#define OMAP_MUX_BASE_SZ 0x5ca
struct omap_mux_entry {
struct omap_mux mux;
struct list_head node;
};
static LIST_HEAD(mux_partitions);
static DEFINE_MUTEX(muxmode_mutex);
struct omap_mux_partition *omap_mux_get(const char *name)
{
struct omap_mux_partition *partition;
list_for_each_entry(partition, &mux_partitions, node) {
if (!strcmp(name, partition->name))
return partition;
}
return NULL;
}
u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
{
if (partition->flags & OMAP_MUX_REG_8BIT)
return readb_relaxed(partition->base + reg);
else
return readw_relaxed(partition->base + reg);
}
void omap_mux_write(struct omap_mux_partition *partition, u16 val,
u16 reg)
{
if (partition->flags & OMAP_MUX_REG_8BIT)
writeb_relaxed(val, partition->base + reg);
else
writew_relaxed(val, partition->base + reg);
}
void omap_mux_write_array(struct omap_mux_partition *partition,
struct omap_board_mux *board_mux)
{
if (!board_mux)
return;
while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
omap_mux_write(partition, board_mux->value,
board_mux->reg_offset);
board_mux++;
}
}
#ifdef CONFIG_OMAP_MUX
static char *omap_mux_options;
static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
int gpio, int val)
{
struct omap_mux_entry *e;
struct omap_mux *gpio_mux = NULL;
u16 old_mode;
u16 mux_mode;
int found = 0;
struct list_head *muxmodes = &partition->muxmodes;
if (!gpio)
return -EINVAL;
list_for_each_entry(e, muxmodes, node) {
struct omap_mux *m = &e->mux;
if (gpio == m->gpio) {
gpio_mux = m;
found++;
}
}
if (found == 0) {
pr_err("%s: Could not set gpio%i\n", __func__, gpio);
return -ENODEV;
}
if (found > 1) {
pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
found, gpio);
return -EINVAL;
}
old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
mux_mode |= partition->gpio;
pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
return 0;
}
int __init omap_mux_init_gpio(int gpio, int val)
{
struct omap_mux_partition *partition;
int ret;
list_for_each_entry(partition, &mux_partitions, node) {
ret = _omap_mux_init_gpio(partition, gpio, val);
if (!ret)
return ret;
}
return -ENODEV;
}
static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
const char *muxname,
struct omap_mux **found_mux)
{
struct omap_mux *mux = NULL;
struct omap_mux_entry *e;
const char *mode_name;
int found = 0, found_mode = 0, mode0_len = 0;
struct list_head *muxmodes = &partition->muxmodes;
mode_name = strchr(muxname, '.');
if (mode_name) {
mode0_len = strlen(muxname) - strlen(mode_name);
mode_name++;
} else {
mode_name = muxname;
}
list_for_each_entry(e, muxmodes, node) {
char *m0_entry;
int i;
mux = &e->mux;
m0_entry = mux->muxnames[0];
/* First check for full name in mode0.muxmode format */
if (mode0_len)
if (strncmp(muxname, m0_entry, mode0_len) ||
(strlen(m0_entry) != mode0_len))
continue;
/* Then check for muxmode only */
for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
char *mode_cur = mux->muxnames[i];
if (!mode_cur)
continue;
if (!strcmp(mode_name, mode_cur)) {
*found_mux = mux;
found++;
found_mode = i;
}
}
}
if (found == 1) {
return found_mode;
}
if (found > 1) {
pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
found, muxname);
return -EINVAL;
}
return -ENODEV;
}
int __init omap_mux_get_by_name(const char *muxname,
struct omap_mux_partition **found_partition,
struct omap_mux **found_mux)
{
struct omap_mux_partition *partition;
list_for_each_entry(partition, &mux_partitions, node) {
struct omap_mux *mux = NULL;
int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux);
if (mux_mode < 0)
continue;
*found_partition = partition;
*found_mux = mux;
return mux_mode;
}
pr_err("%s: Could not find signal %s\n", __func__, muxname);
return -ENODEV;
}
int __init omap_mux_init_signal(const char *muxname, int val)
{
struct omap_mux_partition *partition = NULL;
struct omap_mux *mux = NULL;
u16 old_mode;
int mux_mode;
mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
if (mux_mode < 0 || !mux)
return mux_mode;
old_mode = omap_mux_read(partition, mux->reg_offset);
mux_mode |= val;
pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n",
__func__, muxname, old_mode, mux_mode);
omap_mux_write(partition, mux_mode, mux->reg_offset);
return 0;
}
struct omap_hwmod_mux_info * __init
omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
{
struct omap_hwmod_mux_info *hmux;
int i, nr_pads_dynamic = 0;
if (!bpads || nr_pads < 1)
return NULL;
hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL);
if (!hmux)
goto err1;
hmux->nr_pads = nr_pads;
hmux->pads = kzalloc(sizeof(struct omap_device_pad) *
nr_pads, GFP_KERNEL);
if (!hmux->pads)
goto err2;
for (i = 0; i < hmux->nr_pads; i++) {
struct omap_mux_partition *partition;
struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i];
struct omap_mux *mux;
int mux_mode;
mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux);
if (mux_mode < 0)
goto err3;
if (!pad->partition)
pad->partition = partition;
if (!pad->mux)
pad->mux = mux;
pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL);
if (!pad->name) {
int j;
for (j = i - 1; j >= 0; j--)
kfree(hmux->pads[j].name);
goto err3;
}
strcpy(pad->name, bpad->name);
pad->flags = bpad->flags;
pad->enable = bpad->enable;
pad->idle = bpad->idle;
pad->off = bpad->off;
if (pad->flags &
(OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
nr_pads_dynamic++;
pr_debug("%s: Initialized %s\n", __func__, pad->name);
}
if (!nr_pads_dynamic)
return hmux;
/*
* Add pads that need dynamic muxing into a separate list
*/
hmux->nr_pads_dynamic = nr_pads_dynamic;
hmux->pads_dynamic = kzalloc(sizeof(struct omap_device_pad *) *
nr_pads_dynamic, GFP_KERNEL);
if (!hmux->pads_dynamic) {
pr_err("%s: Could not allocate dynamic pads\n", __func__);
return hmux;
}
nr_pads_dynamic = 0;
for (i = 0; i < hmux->nr_pads; i++) {
struct omap_device_pad *pad = &hmux->pads[i];
if (pad->flags &
(OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
pr_debug("%s: pad %s tagged dynamic\n",
__func__, pad->name);
hmux->pads_dynamic[nr_pads_dynamic] = pad;
nr_pads_dynamic++;
}
}
return hmux;
err3:
kfree(hmux->pads);
err2:
kfree(hmux);
err1:
pr_err("%s: Could not allocate device mux entry\n", __func__);
return NULL;
}
/**
* omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
* @hmux: Pads for a hwmod
* @mpu_irqs: MPU irq array for a hwmod
*
* Scans the wakeup status of pads for a single hwmod. If an irq
* array is defined for this mux, the parser will call the registered
* ISRs for corresponding pads, otherwise the parser will stop at the
* first wakeup active pad and return. Returns true if there is a
* pending and non-served wakeup event for the mux, otherwise false.
*/
static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
struct omap_hwmod_irq_info *mpu_irqs)
{
int i, irq;
unsigned int val;
u32 handled_irqs = 0;
for (i = 0; i < hmux->nr_pads_dynamic; i++) {
struct omap_device_pad *pad = hmux->pads_dynamic[i];
if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
!(pad->idle & OMAP_WAKEUP_EN))
continue;
val = omap_mux_read(pad->partition, pad->mux->reg_offset);
if (!(val & OMAP_WAKEUP_EVENT))
continue;
if (!hmux->irqs)
return true;
irq = hmux->irqs[i];
/* make sure we only handle each irq once */
if (handled_irqs & 1 << irq)
continue;
handled_irqs |= 1 << irq;
generic_handle_irq(mpu_irqs[irq].irq);
}
return false;
}
/**
* _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
*
* Checks a single hwmod for every wakeup capable pad to see if there is an
* active wakeup event. If this is the case, call the corresponding ISR.
*/
static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
{
if (!oh->mux || !oh->mux->enabled)
return 0;
if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
generic_handle_irq(oh->mpu_irqs[0].irq);
return 0;
}
/**
* omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
*
* Calls a function for each registered omap_hwmod to check
* pad wakeup statuses.
*/
static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
{
omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
return IRQ_HANDLED;
}
/* Assumes the calling function takes care of locking */
void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
{
int i;
/* Runtime idling of dynamic pads */
if (state == _HWMOD_STATE_IDLE && hmux->enabled) {
for (i = 0; i < hmux->nr_pads_dynamic; i++) {
struct omap_device_pad *pad = hmux->pads_dynamic[i];
int val = -EINVAL;
val = pad->idle;
omap_mux_write(pad->partition, val,
pad->mux->reg_offset);
}
return;
}
/* Runtime enabling of dynamic pads */
if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic
&& hmux->enabled) {
for (i = 0; i < hmux->nr_pads_dynamic; i++) {
struct omap_device_pad *pad = hmux->pads_dynamic[i];
int val = -EINVAL;
val = pad->enable;
omap_mux_write(pad->partition, val,
pad->mux->reg_offset);
}
return;
}
/* Enabling or disabling of all pads */
for (i = 0; i < hmux->nr_pads; i++) {
struct omap_device_pad *pad = &hmux->pads[i];
int flags, val = -EINVAL;
flags = pad->flags;
switch (state) {
case _HWMOD_STATE_ENABLED:
val = pad->enable;
pr_debug("%s: Enabling %s %x\n", __func__,
pad->name, val);
break;
case _HWMOD_STATE_DISABLED:
/* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
if (flags & OMAP_DEVICE_PAD_REMUX)
val = pad->off;
else
val = OMAP_MUX_MODE7;
pr_debug("%s: Disabling %s %x\n", __func__,
pad->name, val);
break;
default:
/* Nothing to be done */
break;
}
if (val >= 0) {
omap_mux_write(pad->partition, val,
pad->mux->reg_offset);
pad->flags = flags;
}
}
if (state == _HWMOD_STATE_ENABLED)
hmux->enabled = true;
else
hmux->enabled = false;
}
#ifdef CONFIG_DEBUG_FS
#define OMAP_MUX_MAX_NR_FLAGS 10
#define OMAP_MUX_TEST_FLAG(val, mask) \
if (((val) & (mask)) == (mask)) { \
i++; \
flags[i] = #mask; \
}
/* REVISIT: Add checking for non-optimal mux settings */
static inline void omap_mux_decode(struct seq_file *s, u16 val)
{
char *flags[OMAP_MUX_MAX_NR_FLAGS];
char mode[sizeof("OMAP_MUX_MODE") + 1];
int i = -1;
sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
i++;
flags[i] = mode;
OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
if (val & OMAP_OFF_EN) {
if (!(val & OMAP_OFFOUT_EN)) {
if (!(val & OMAP_OFF_PULL_UP)) {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_INPUT_PULLDOWN);
} else {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_INPUT_PULLUP);
}
} else {
if (!(val & OMAP_OFFOUT_VAL)) {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_OUTPUT_LOW);
} else {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_OUTPUT_HIGH);
}
}
}
if (val & OMAP_INPUT_EN) {
if (val & OMAP_PULL_ENA) {
if (!(val & OMAP_PULL_UP)) {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_INPUT_PULLDOWN);
} else {
OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
}
} else {
OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
}
} else {
i++;
flags[i] = "OMAP_PIN_OUTPUT";
}
do {
seq_printf(s, "%s", flags[i]);
if (i > 0)
seq_printf(s, " | ");
} while (i-- > 0);
}
#define OMAP_MUX_DEFNAME_LEN 32
static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
{
struct omap_mux_partition *partition = s->private;
struct omap_mux_entry *e;
u8 omap_gen = omap_rev() >> 28;
list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
char m0_def[OMAP_MUX_DEFNAME_LEN];
char *m0_name = m->muxnames[0];
u16 val;
int i, mode;
if (!m0_name)
continue;
/* REVISIT: Needs to be updated if mode0 names get longer */
for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
if (m0_name[i] == '\0') {
m0_def[i] = m0_name[i];
break;
}
m0_def[i] = toupper(m0_name[i]);
}
val = omap_mux_read(partition, m->reg_offset);
mode = val & OMAP_MUX_MODE7;
if (mode != 0)
seq_printf(s, "/* %s */\n", m->muxnames[mode]);
/*
* XXX: Might be revisited to support differences across
* same OMAP generation.
*/
seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
omap_mux_decode(s, val);
seq_printf(s, "),\n");
}
return 0;
}
static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
{
return single_open(file, omap_mux_dbg_board_show, inode->i_private);
}
static const struct file_operations omap_mux_dbg_board_fops = {
.open = omap_mux_dbg_board_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
{
struct omap_mux_partition *partition;
list_for_each_entry(partition, &mux_partitions, node) {
struct list_head *muxmodes = &partition->muxmodes;
struct omap_mux_entry *e;
list_for_each_entry(e, muxmodes, node) {
struct omap_mux *m = &e->mux;
if (m == mux)
return partition;
}
}
return NULL;
}
static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
{
struct omap_mux *m = s->private;
struct omap_mux_partition *partition;
const char *none = "NA";
u16 val;
int mode;
partition = omap_mux_get_partition(m);
if (!partition)
return 0;
val = omap_mux_read(partition, m->reg_offset);
mode = val & OMAP_MUX_MODE7;
seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
m->muxnames[0], m->muxnames[mode],
partition->phys + m->reg_offset, m->reg_offset, val,
m->balls[0] ? m->balls[0] : none,
m->balls[1] ? m->balls[1] : none);
seq_printf(s, "mode: ");
omap_mux_decode(s, val);
seq_printf(s, "\n");
seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
m->muxnames[0] ? m->muxnames[0] : none,
m->muxnames[1] ? m->muxnames[1] : none,
m->muxnames[2] ? m->muxnames[2] : none,
m->muxnames[3] ? m->muxnames[3] : none,
m->muxnames[4] ? m->muxnames[4] : none,
m->muxnames[5] ? m->muxnames[5] : none,
m->muxnames[6] ? m->muxnames[6] : none,
m->muxnames[7] ? m->muxnames[7] : none);
return 0;
}
#define OMAP_MUX_MAX_ARG_CHAR 7
static ssize_t omap_mux_dbg_signal_write(struct file *file,
const char __user *user_buf,
size_t count, loff_t *ppos)
{
struct seq_file *seqf;
struct omap_mux *m;
u16 val;
int ret;
struct omap_mux_partition *partition;
if (count > OMAP_MUX_MAX_ARG_CHAR)
return -EINVAL;
ret = kstrtou16_from_user(user_buf, count, 0x10, &val);
if (ret < 0)
return ret;
seqf = file->private_data;
m = seqf->private;
partition = omap_mux_get_partition(m);
if (!partition)
return -ENODEV;
omap_mux_write(partition, val, m->reg_offset);
*ppos += count;
return count;
}
static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
{
return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
}
static const struct file_operations omap_mux_dbg_signal_fops = {
.open = omap_mux_dbg_signal_open,
.read = seq_read,
.write = omap_mux_dbg_signal_write,
.llseek = seq_lseek,
.release = single_release,
};
static struct dentry *mux_dbg_dir;
static void __init omap_mux_dbg_create_entry(
struct omap_mux_partition *partition,
struct dentry *mux_dbg_dir)
{
struct omap_mux_entry *e;
list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
(void)debugfs_create_file(m->muxnames[0], S_IWUSR | S_IRUGO,
mux_dbg_dir, m,
&omap_mux_dbg_signal_fops);
}
}
static void __init omap_mux_dbg_init(void)
{
struct omap_mux_partition *partition;
static struct dentry *mux_dbg_board_dir;
mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
if (!mux_dbg_dir)
return;
mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
if (!mux_dbg_board_dir)
return;
list_for_each_entry(partition, &mux_partitions, node) {
omap_mux_dbg_create_entry(partition, mux_dbg_dir);
(void)debugfs_create_file(partition->name, S_IRUGO,
mux_dbg_board_dir, partition,
&omap_mux_dbg_board_fops);
}
}
#else
static inline void omap_mux_dbg_init(void)
{
}
#endif /* CONFIG_DEBUG_FS */
static void __init omap_mux_free_names(struct omap_mux *m)
{
int i;
for (i = 0; i < OMAP_MUX_NR_MODES; i++)
kfree(m->muxnames[i]);
#ifdef CONFIG_DEBUG_FS
for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
kfree(m->balls[i]);
#endif
}
/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
int __init omap_mux_late_init(void)
{
struct omap_mux_partition *partition;
int ret;
list_for_each_entry(partition, &mux_partitions, node) {
struct omap_mux_entry *e, *tmp;
list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
u16 mode = omap_mux_read(partition, m->reg_offset);
if (OMAP_MODE_GPIO(partition, mode))
continue;
#ifndef CONFIG_DEBUG_FS
mutex_lock(&muxmode_mutex);
list_del(&e->node);
mutex_unlock(&muxmode_mutex);
omap_mux_free_names(m);
kfree(m);
#endif
}
}
omap_mux_dbg_init();
/* see pinctrl-single-omap for the wake-up interrupt handling */
if (of_have_populated_dt())
return 0;
ret = request_irq(omap_prcm_event_to_irq("io"),
omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
"hwmod_io", omap_mux_late_init);
if (ret)
pr_warn("mux: Failed to setup hwmod io irq %d\n", ret);
return 0;
}
static void __init omap_mux_package_fixup(struct omap_mux *p,
struct omap_mux *superset)
{
while (p->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *s = superset;
int found = 0;
while (s->reg_offset != OMAP_MUX_TERMINATOR) {
if (s->reg_offset == p->reg_offset) {
*s = *p;
found++;
break;
}
s++;
}
if (!found)
pr_err("%s: Unknown entry offset 0x%x\n", __func__,
p->reg_offset);
p++;
}
}
#ifdef CONFIG_DEBUG_FS
static void __init omap_mux_package_init_balls(struct omap_ball *b,
struct omap_mux *superset)
{
while (b->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *s = superset;
int found = 0;
while (s->reg_offset != OMAP_MUX_TERMINATOR) {
if (s->reg_offset == b->reg_offset) {
s->balls[0] = b->balls[0];
s->balls[1] = b->balls[1];
found++;
break;
}
s++;
}
if (!found)
pr_err("%s: Unknown ball offset 0x%x\n", __func__,
b->reg_offset);
b++;
}
}
#else /* CONFIG_DEBUG_FS */
static inline void omap_mux_package_init_balls(struct omap_ball *b,
struct omap_mux *superset)
{
}
#endif /* CONFIG_DEBUG_FS */
static int __init omap_mux_setup(char *options)
{
if (!options)
return 0;
omap_mux_options = options;
return 1;
}
__setup("omap_mux=", omap_mux_setup);
/*
* Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
* cmdline options only override the bootloader values.
* During development, please enable CONFIG_DEBUG_FS, and use the
* signal specific entries under debugfs.
*/
static void __init omap_mux_set_cmdline_signals(void)
{
char *options, *next_opt, *token;
if (!omap_mux_options)
return;
options = kstrdup(omap_mux_options, GFP_KERNEL);
if (!options)
return;
next_opt = options;
while ((token = strsep(&next_opt, ",")) != NULL) {
char *keyval, *name;
u16 val;
keyval = token;
name = strsep(&keyval, "=");
if (name) {
int res;
res = kstrtou16(keyval, 0x10, &val);
if (res < 0)
continue;
omap_mux_init_signal(name, (u16)val);
}
}
kfree(options);
}
static int __init omap_mux_copy_names(struct omap_mux *src,
struct omap_mux *dst)
{
int i;
for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
if (src->muxnames[i]) {
dst->muxnames[i] = kstrdup(src->muxnames[i],
GFP_KERNEL);
if (!dst->muxnames[i])
goto free;
}
}
#ifdef CONFIG_DEBUG_FS
for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
if (src->balls[i]) {
dst->balls[i] = kstrdup(src->balls[i], GFP_KERNEL);
if (!dst->balls[i])
goto free;
}
}
#endif
return 0;
free:
omap_mux_free_names(dst);
return -ENOMEM;
}
#endif /* CONFIG_OMAP_MUX */
static struct omap_mux *omap_mux_get_by_gpio(
struct omap_mux_partition *partition,
int gpio)
{
struct omap_mux_entry *e;
struct omap_mux *ret = NULL;
list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
if (m->gpio == gpio) {
ret = m;
break;
}
}
return ret;
}
/* Needed for dynamic muxing of GPIO pins for off-idle */
u16 omap_mux_get_gpio(int gpio)
{
struct omap_mux_partition *partition;
struct omap_mux *m = NULL;
list_for_each_entry(partition, &mux_partitions, node) {
m = omap_mux_get_by_gpio(partition, gpio);
if (m)
return omap_mux_read(partition, m->reg_offset);
}
if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
pr_err("%s: Could not get gpio%i\n", __func__, gpio);
return OMAP_MUX_TERMINATOR;
}
/* Needed for dynamic muxing of GPIO pins for off-idle */
void omap_mux_set_gpio(u16 val, int gpio)
{
struct omap_mux_partition *partition;
struct omap_mux *m = NULL;
list_for_each_entry(partition, &mux_partitions, node) {
m = omap_mux_get_by_gpio(partition, gpio);
if (m) {
omap_mux_write(partition, val, m->reg_offset);
return;
}
}
if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
pr_err("%s: Could not set gpio%i\n", __func__, gpio);
}
static struct omap_mux * __init omap_mux_list_add(
struct omap_mux_partition *partition,
struct omap_mux *src)
{
struct omap_mux_entry *entry;
struct omap_mux *m;
entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
if (!entry)
return NULL;
m = &entry->mux;
entry->mux = *src;
#ifdef CONFIG_OMAP_MUX
if (omap_mux_copy_names(src, m)) {
kfree(entry);
return NULL;
}
#endif
mutex_lock(&muxmode_mutex);
list_add_tail(&entry->node, &partition->muxmodes);
mutex_unlock(&muxmode_mutex);
return m;
}
/*
* Note if CONFIG_OMAP_MUX is not selected, we will only initialize
* the GPIO to mux offset mapping that is needed for dynamic muxing
* of GPIO pins for off-idle.
*/
static void __init omap_mux_init_list(struct omap_mux_partition *partition,
struct omap_mux *superset)
{
while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *entry;
#ifdef CONFIG_OMAP_MUX
if (!superset->muxnames[0]) {
superset++;
continue;
}
#else
/* Skip pins that are not muxed as GPIO by bootloader */
if (!OMAP_MODE_GPIO(partition, omap_mux_read(partition,
superset->reg_offset))) {
superset++;
continue;
}
#endif
entry = omap_mux_list_add(partition, superset);
if (!entry) {
pr_err("%s: Could not add entry\n", __func__);
return;
}
superset++;
}
}
#ifdef CONFIG_OMAP_MUX
static void omap_mux_init_package(struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_ball *package_balls)
{
if (package_subset)
omap_mux_package_fixup(package_subset, superset);
if (package_balls)
omap_mux_package_init_balls(package_balls, superset);
}
static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
struct omap_board_mux *board_mux)
{
omap_mux_set_cmdline_signals();
omap_mux_write_array(partition, board_mux);
}
#else
static void omap_mux_init_package(struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_ball *package_balls)
{
}
static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
struct omap_board_mux *board_mux)
{
}
#endif
static u32 mux_partitions_cnt;
int __init omap_mux_init(const char *name, u32 flags,
u32 mux_pbase, u32 mux_size,
struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_board_mux *board_mux,
struct omap_ball *package_balls)
{
struct omap_mux_partition *partition;
partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
if (!partition)
return -ENOMEM;
partition->name = name;
partition->flags = flags;
partition->gpio = flags & OMAP_MUX_MODE7;
partition->size = mux_size;
partition->phys = mux_pbase;
partition->base = ioremap(mux_pbase, mux_size);
if (!partition->base) {
pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
__func__, partition->phys);
kfree(partition);
return -ENODEV;
}
INIT_LIST_HEAD(&partition->muxmodes);
list_add_tail(&partition->node, &mux_partitions);
mux_partitions_cnt++;
pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
mux_partitions_cnt, partition->name, partition->flags);
omap_mux_init_package(superset, package_subset, package_balls);
omap_mux_init_list(partition, superset);
omap_mux_init_signals(partition, board_mux);
return 0;
}
arch/arm/mach-omap2/mux.h deleted 100644 → 0
View file @ a9fa1f7c
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009-2010 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "mux34xx.h"
#define OMAP_MUX_TERMINATOR 0xffff
/* 34xx mux mode options for each pin. See TRM for options */
#define OMAP_MUX_MODE0 0
#define OMAP_MUX_MODE1 1
#define OMAP_MUX_MODE2 2
#define OMAP_MUX_MODE3 3
#define OMAP_MUX_MODE4 4
#define OMAP_MUX_MODE5 5
#define OMAP_MUX_MODE6 6
#define OMAP_MUX_MODE7 7
/* 24xx/34xx mux bit defines */
#define OMAP_PULL_ENA (1 << 3)
#define OMAP_PULL_UP (1 << 4)
#define OMAP_ALTELECTRICALSEL (1 << 5)
/* omap3/4/5 specific mux bit defines */
#define OMAP_INPUT_EN (1 << 8)
#define OMAP_OFF_EN (1 << 9)
#define OMAP_OFFOUT_EN (1 << 10)
#define OMAP_OFFOUT_VAL (1 << 11)
#define OMAP_OFF_PULL_EN (1 << 12)
#define OMAP_OFF_PULL_UP (1 << 13)
#define OMAP_WAKEUP_EN (1 << 14)
#define OMAP_WAKEUP_EVENT (1 << 15)
/* Active pin states */
#define OMAP_PIN_OUTPUT 0
#define OMAP_PIN_INPUT OMAP_INPUT_EN
#define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \
| OMAP_PULL_UP)
#define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN)
/* Off mode states */
#define OMAP_PIN_OFF_NONE 0
#define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \
| OMAP_OFFOUT_VAL)
#define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN)
#define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
| OMAP_OFF_PULL_UP)
#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
#define OMAP_MODE_GPIO(partition, x) (((x) & OMAP_MUX_MODE7) == \
partition->gpio)
#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0)
/* Flags for omapX_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CBC 3 /* 515-pin 0.50 0.65 */
#define OMAP_MUX_NR_MODES 8 /* Available modes */
#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
/*
* omap_mux_init flags definition:
*
* OMAP_GPIO_MUX_MODE, bits 0-2: gpio muxing mode, same like pad control
* register which includes values from 0-7.
* OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
* The default value is 16 bits.
*/
#define OMAP_MUX_GPIO_IN_MODE0 OMAP_MUX_MODE0
#define OMAP_MUX_GPIO_IN_MODE1 OMAP_MUX_MODE1
#define OMAP_MUX_GPIO_IN_MODE2 OMAP_MUX_MODE2
#define OMAP_MUX_GPIO_IN_MODE3 OMAP_MUX_MODE3
#define OMAP_MUX_GPIO_IN_MODE4 OMAP_MUX_MODE4
#define OMAP_MUX_GPIO_IN_MODE5 OMAP_MUX_MODE5
#define OMAP_MUX_GPIO_IN_MODE6 OMAP_MUX_MODE6
#define OMAP_MUX_GPIO_IN_MODE7 OMAP_MUX_MODE7
#define OMAP_MUX_REG_8BIT (1 << 3)
/**
* struct omap_board_data - board specific device data
* @id: instance id
* @flags: additional flags for platform init code
* @pads: array of device specific pads
* @pads_cnt: ARRAY_SIZE() of pads
*/
struct omap_board_data {
int id;
u32 flags;
struct omap_device_pad *pads;
int pads_cnt;
};
/**
* struct mux_partition - contain partition related information
* @name: name of the current partition
* @flags: flags specific to this partition
* @gpio: gpio mux mode
* @phys: physical address
* @size: partition size
* @base: virtual address after ioremap
* @muxmodes: list of nodes that belong to a partition
* @node: list node for the partitions linked list
*/
struct omap_mux_partition {
const char *name;
u32 flags;
u32 gpio;
u32 phys;
u32 size;
void __iomem *base;
struct list_head muxmodes;
struct list_head node;
};
/**
* struct omap_mux - data for omap mux register offset and it's value
* @reg_offset: mux register offset from the mux base
* @gpio: GPIO number
* @muxnames: available signal modes for a ball
* @balls: available balls on the package
*/
struct omap_mux {
u16 reg_offset;
u16 gpio;
#ifdef CONFIG_OMAP_MUX
char *muxnames[OMAP_MUX_NR_MODES];
#ifdef CONFIG_DEBUG_FS
char *balls[OMAP_MUX_NR_SIDES];
#endif
#endif
};
/**
* struct omap_ball - data for balls on omap package
* @reg_offset: mux register offset from the mux base
* @balls: available balls on the package
*/
struct omap_ball {
u16 reg_offset;
char *balls[OMAP_MUX_NR_SIDES];
};
/**
* struct omap_board_mux - data for initializing mux registers
* @reg_offset: mux register offset from the mux base
* @mux_value: desired mux value to set
*/
struct omap_board_mux {
u16 reg_offset;
u16 value;
};
#define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad,
needs enable, idle and off
values */
#define OMAP_DEVICE_PAD_WAKEUP BIT(0) /* Pad is wake-up capable */
/**
* struct omap_device_pad - device specific pad configuration
* @name: signal name
* @flags: pad specific runtime flags
* @enable: runtime value for a pad
* @idle: idle value for a pad
* @off: off value for a pad, defaults to safe mode
* @partition: mux partition
* @mux: mux register
*/
struct omap_device_pad {
char *name;
u8 flags;
u16 enable;
u16 idle;
u16 off;
struct omap_mux_partition *partition;
struct omap_mux *mux;
};
struct omap_hwmod_mux_info;
#define OMAP_MUX_STATIC(signal, mode) \
{ \
.name = (signal), \
.enable = (mode), \
}
#if defined(CONFIG_OMAP_MUX)
/**
* omap_mux_init_gpio - initialize a signal based on the GPIO number
* @gpio: GPIO number
* @val: Options for the mux register value
*/
int omap_mux_init_gpio(int gpio, int val);
/**
* omap_mux_init_signal - initialize a signal based on the signal name
* @muxname: Mux name in mode0_name.signal_name format
* @val: Options for the mux register value
*/
int omap_mux_init_signal(const char *muxname, int val);
/**
* omap_hwmod_mux_init - initialize hwmod specific mux data
* @bpads: Board specific device signal names
* @nr_pads: Number of signal names for the device
*/
extern struct omap_hwmod_mux_info *
omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
/**
* omap_hwmod_mux - omap hwmod specific pin muxing
* @hmux: Pads for a hwmod
* @state: Desired _HWMOD_STATE
*
* Called only from omap_hwmod.c, do not use.
*/
void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
int omap_mux_get_by_name(const char *muxname,
struct omap_mux_partition **found_partition,
struct omap_mux **found_mux);
#else
static inline int omap_mux_get_by_name(const char *muxname,
struct omap_mux_partition **found_partition,
struct omap_mux **found_mux)
{
return 0;
}
static inline int omap_mux_init_gpio(int gpio, int val)
{
return 0;
}
static inline int omap_mux_init_signal(char *muxname, int val)
{
return 0;
}
static inline struct omap_hwmod_mux_info *
omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
{
return NULL;
}
static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
{
}
static struct omap_board_mux *board_mux __maybe_unused;
#endif
/**
* omap_mux_get_gpio() - get mux register value based on GPIO number
* @gpio: GPIO number
*
*/
u16 omap_mux_get_gpio(int gpio);
/**
* omap_mux_set_gpio() - set mux register value based on GPIO number
* @val: New mux register value
* @gpio: GPIO number
*
*/
void omap_mux_set_gpio(u16 val, int gpio);
/**
* omap_mux_get() - get a mux partition by name
* @name: Name of the mux partition
*
*/
struct omap_mux_partition *omap_mux_get(const char *name);
/**
* omap_mux_read() - read mux register
* @partition: Mux partition
* @mux_offset: Offset of the mux register
*
*/
u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
/**
* omap_mux_write() - write mux register
* @partition: Mux partition
* @val: New mux register value
* @mux_offset: Offset of the mux register
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
/**
* omap_mux_write_array() - write an array of mux registers
* @partition: Mux partition
* @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
void omap_mux_write_array(struct omap_mux_partition *p,
struct omap_board_mux *board_mux);
/**
* omap2420_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap2430_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap3_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap4_mux_init() - initialize mux system with board specific set
* @board_subset: Board specific mux table
* @board_wkup_subset: Board specific mux table for wakeup instance
* @flags: OMAP package type used for the board
*/
int omap4_mux_init(struct omap_board_mux *board_subset,
struct omap_board_mux *board_wkup_subset, int flags);
/**
* omap_mux_init - private mux init function, do not call
*/
int omap_mux_init(const char *name, u32 flags,
u32 mux_pbase, u32 mux_size,
struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_board_mux *board_mux,
struct omap_ball *package_balls);
arch/arm/mach-omap2/mux34xx.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/init.h>
#include "mux.h"
#ifdef CONFIG_OMAP_MUX
#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
.gpio = (g), \
.muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
}
#else
#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
.gpio = (g), \
}
#endif
#define _OMAP3_BALLENTRY(M0, bb, bt) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
.balls = { bb, bt }, \
}
/*
* Superset of all mux modes for omap3
*/
static struct omap_mux __initdata omap3_muxmodes[] = {
_OMAP3_MUXENTRY(CAM_D0, 99,
"cam_d0", NULL, NULL, NULL,
"gpio_99", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D1, 100,
"cam_d1", NULL, NULL, NULL,
"gpio_100", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", NULL, NULL, NULL,
"gpio_109", "hw_dbg8", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D11, 110,
"cam_d11", NULL, NULL, NULL,
"gpio_110", "hw_dbg9", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", NULL, NULL, NULL,
"gpio_101", "hw_dbg4", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", NULL, NULL, NULL,
"gpio_102", "hw_dbg5", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", NULL, NULL, NULL,
"gpio_103", "hw_dbg6", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", NULL, NULL, NULL,
"gpio_104", "hw_dbg7", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D6, 105,
"cam_d6", NULL, NULL, NULL,
"gpio_105", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D7, 106,
"cam_d7", NULL, NULL, NULL,
"gpio_106", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D8, 107,
"cam_d8", NULL, NULL, NULL,
"gpio_107", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D9, 108,
"cam_d9", NULL, NULL, NULL,
"gpio_108", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_FLD, 98,
"cam_fld", NULL, "cam_global_reset", NULL,
"gpio_98", "hw_dbg3", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", NULL, NULL, NULL,
"gpio_94", "hw_dbg0", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_PCLK, 97,
"cam_pclk", NULL, NULL, NULL,
"gpio_97", "hw_dbg2", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_STROBE, 126,
"cam_strobe", NULL, NULL, NULL,
"gpio_126", "hw_dbg11", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", NULL, NULL, NULL,
"gpio_95", "hw_dbg1", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_WEN, 167,
"cam_wen", NULL, "cam_shutter", NULL,
"gpio_167", "hw_dbg10", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_XCLKA, 96,
"cam_xclka", NULL, NULL, NULL,
"gpio_96", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_XCLKB, 111,
"cam_xclkb", NULL, NULL, NULL,
"gpio_111", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DX0, 112,
"csi2_dx0", NULL, NULL, NULL,
"gpio_112", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DX1, 114,
"csi2_dx1", NULL, NULL, NULL,
"gpio_114", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DY0, 113,
"csi2_dy0", NULL, NULL, NULL,
"gpio_113", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DY1, 115,
"csi2_dy1", NULL, NULL, NULL,
"gpio_115", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_ACBIAS, 69,
"dss_acbias", NULL, NULL, NULL,
"gpio_69", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA0, 70,
"dss_data0", NULL, "uart1_cts", NULL,
"gpio_70", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA1, 71,
"dss_data1", NULL, "uart1_rts", NULL,
"gpio_71", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA10, 80,
"dss_data10", NULL, NULL, NULL,
"gpio_80", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA11, 81,
"dss_data11", NULL, NULL, NULL,
"gpio_81", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA12, 82,
"dss_data12", NULL, NULL, NULL,
"gpio_82", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA13, 83,
"dss_data13", NULL, NULL, NULL,
"gpio_83", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA14, 84,
"dss_data14", NULL, NULL, NULL,
"gpio_84", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA15, 85,
"dss_data15", NULL, NULL, NULL,
"gpio_85", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA16, 86,
"dss_data16", NULL, NULL, NULL,
"gpio_86", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA17, 87,
"dss_data17", NULL, NULL, NULL,
"gpio_87", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA18, 88,
"dss_data18", NULL, "mcspi3_clk", "dss_data0",
"gpio_88", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA19, 89,
"dss_data19", NULL, "mcspi3_simo", "dss_data1",
"gpio_89", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA20, 90,
"dss_data20", NULL, "mcspi3_somi", "dss_data2",
"gpio_90", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA21, 91,
"dss_data21", NULL, "mcspi3_cs0", "dss_data3",
"gpio_91", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA22, 92,
"dss_data22", NULL, "mcspi3_cs1", "dss_data4",
"gpio_92", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA23, 93,
"dss_data23", NULL, NULL, "dss_data5",
"gpio_93", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA2, 72,
"dss_data2", NULL, NULL, NULL,
"gpio_72", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA3, 73,
"dss_data3", NULL, NULL, NULL,
"gpio_73", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA4, 74,
"dss_data4", NULL, "uart3_rx_irrx", NULL,
"gpio_74", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA5, 75,
"dss_data5", NULL, "uart3_tx_irtx", NULL,
"gpio_75", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", NULL,
"gpio_76", "hw_dbg14", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", NULL,
"gpio_77", "hw_dbg15", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, NULL, NULL,
"gpio_78", "hw_dbg16", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, NULL, NULL,
"gpio_79", "hw_dbg17", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_HSYNC, 67,
"dss_hsync", NULL, NULL, NULL,
"gpio_67", "hw_dbg13", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_PCLK, 66,
"dss_pclk", NULL, NULL, NULL,
"gpio_66", "hw_dbg12", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_VSYNC, 68,
"dss_vsync", NULL, NULL, NULL,
"gpio_68", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_CLK, 12,
"etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
"gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"),
_OMAP3_MUXENTRY(ETK_CTL, 13,
"etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
"gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"),
_OMAP3_MUXENTRY(ETK_D0, 14,
"etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
"gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"),
_OMAP3_MUXENTRY(ETK_D1, 15,
"etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
"gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"),
_OMAP3_MUXENTRY(ETK_D10, 24,
"etk_d10", NULL, "uart1_rx", "hsusb2_clk",
"gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"),
_OMAP3_MUXENTRY(ETK_D11, 25,
"etk_d11", NULL, NULL, "hsusb2_stp",
"gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", NULL, NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
_OMAP3_MUXENTRY(ETK_D13, 27,
"etk_d13", NULL, NULL, "hsusb2_nxt",
"gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"),
_OMAP3_MUXENTRY(ETK_D14, 28,
"etk_d14", NULL, NULL, "hsusb2_data0",
"gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"),
_OMAP3_MUXENTRY(ETK_D15, 29,
"etk_d15", NULL, NULL, "hsusb2_data1",
"gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"),
_OMAP3_MUXENTRY(ETK_D2, 16,
"etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
"gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"),
_OMAP3_MUXENTRY(ETK_D3, 17,
"etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
"gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"),
_OMAP3_MUXENTRY(ETK_D4, 18,
"etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
"gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"),
_OMAP3_MUXENTRY(ETK_D5, 19,
"etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
"gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"),
_OMAP3_MUXENTRY(ETK_D6, 20,
"etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
"gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"),
_OMAP3_MUXENTRY(ETK_D7, 21,
"etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
"gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"),
_OMAP3_MUXENTRY(ETK_D8, 22,
"etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
"gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"),
_OMAP3_MUXENTRY(ETK_D9, 23,
"etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
"gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"),
_OMAP3_MUXENTRY(GPMC_A1, 34,
"gpmc_a1", NULL, NULL, NULL,
"gpio_34", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A10, 43,
"gpmc_a10", "sys_ndmareq3", NULL, NULL,
"gpio_43", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A2, 35,
"gpmc_a2", NULL, NULL, NULL,
"gpio_35", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A3, 36,
"gpmc_a3", NULL, NULL, NULL,
"gpio_36", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A4, 37,
"gpmc_a4", NULL, NULL, NULL,
"gpio_37", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A5, 38,
"gpmc_a5", NULL, NULL, NULL,
"gpio_38", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A6, 39,
"gpmc_a6", NULL, NULL, NULL,
"gpio_39", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A7, 40,
"gpmc_a7", NULL, NULL, NULL,
"gpio_40", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A8, 41,
"gpmc_a8", NULL, NULL, NULL,
"gpio_41", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A9, 42,
"gpmc_a9", "sys_ndmareq2", NULL, NULL,
"gpio_42", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_CLK, 59,
"gpmc_clk", NULL, NULL, NULL,
"gpio_59", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D10, 46,
"gpmc_d10", NULL, NULL, NULL,
"gpio_46", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D11, 47,
"gpmc_d11", NULL, NULL, NULL,
"gpio_47", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D12, 48,
"gpmc_d12", NULL, NULL, NULL,
"gpio_48", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D13, 49,
"gpmc_d13", NULL, NULL, NULL,
"gpio_49", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D14, 50,
"gpmc_d14", NULL, NULL, NULL,
"gpio_50", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D15, 51,
"gpmc_d15", NULL, NULL, NULL,
"gpio_51", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D8, 44,
"gpmc_d8", NULL, NULL, NULL,
"gpio_44", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D9, 45,
"gpmc_d9", NULL, NULL, NULL,
"gpio_45", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60,
"gpmc_nbe0_cle", NULL, NULL, NULL,
"gpio_60", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NBE1, 61,
"gpmc_nbe1", NULL, NULL, NULL,
"gpio_61", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS1, 52,
"gpmc_ncs1", NULL, NULL, NULL,
"gpio_52", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS2, 53,
"gpmc_ncs2", NULL, NULL, NULL,
"gpio_53", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS3, 54,
"gpmc_ncs3", "sys_ndmareq0", NULL, NULL,
"gpio_54", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS4, 55,
"gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt",
"gpio_55", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS5, 56,
"gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt",
"gpio_56", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS6, 57,
"gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt",
"gpio_57", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS7, 58,
"gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt",
"gpio_58", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NWP, 62,
"gpmc_nwp", NULL, NULL, NULL,
"gpio_62", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT1, 63,
"gpmc_wait1", NULL, NULL, NULL,
"gpio_63", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT2, 64,
"gpmc_wait2", NULL, NULL, NULL,
"gpio_64", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT3, 65,
"gpmc_wait3", "sys_ndmareq1", NULL, NULL,
"gpio_65", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HDQ_SIO, 170,
"hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe",
"gpio_170", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_CLK, 120,
"hsusb0_clk", NULL, NULL, NULL,
"gpio_120", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
"hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
"gpio_125", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
"hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
"gpio_130", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
"hsusb0_data2", NULL, "uart3_rts_sd", NULL,
"gpio_131", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
"hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
"gpio_169", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA4, 188,
"hsusb0_data4", NULL, NULL, NULL,
"gpio_188", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA5, 189,
"hsusb0_data5", NULL, NULL, NULL,
"gpio_189", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA6, 190,
"hsusb0_data6", NULL, NULL, NULL,
"gpio_190", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA7, 191,
"hsusb0_data7", NULL, NULL, NULL,
"gpio_191", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DIR, 122,
"hsusb0_dir", NULL, NULL, NULL,
"gpio_122", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_NXT, 124,
"hsusb0_nxt", NULL, NULL, NULL,
"gpio_124", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_STP, 121,
"hsusb0_stp", NULL, NULL, NULL,
"gpio_121", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C2_SCL, 168,
"i2c2_scl", NULL, NULL, NULL,
"gpio_168", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C2_SDA, 183,
"i2c2_sda", NULL, NULL, NULL,
"gpio_183", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C3_SCL, 184,
"i2c3_scl", NULL, NULL, NULL,
"gpio_184", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C3_SDA, 185,
"i2c3_sda", NULL, NULL, NULL,
"gpio_185", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C4_SCL, 0,
"i2c4_scl", "sys_nvmode1", NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C4_SDA, 0,
"i2c4_sda", "sys_nvmode2", NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(JTAG_EMU0, 11,
"jtag_emu0", NULL, NULL, NULL,
"gpio_11", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(JTAG_EMU1, 31,
"jtag_emu1", NULL, NULL, NULL,
"gpio_31", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
"mcbsp1_clkr", "mcspi4_clk", NULL, NULL,
"gpio_156", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_CLKX, 162,
"mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL,
"gpio_162", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_DR, 159,
"mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL,
"gpio_159", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_DX, 158,
"mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL,
"gpio_158", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_FSR, 157,
"mcbsp1_fsr", NULL, "cam_global_reset", NULL,
"gpio_157", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_FSX, 161,
"mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL,
"gpio_161", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_CLKX, 117,
"mcbsp2_clkx", NULL, NULL, NULL,
"gpio_117", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_DR, 118,
"mcbsp2_dr", NULL, NULL, NULL,
"gpio_118", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_DX, 119,
"mcbsp2_dx", NULL, NULL, NULL,
"gpio_119", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_FSX, 116,
"mcbsp2_fsx", NULL, NULL, NULL,
"gpio_116", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
"mcbsp3_clkx", "uart2_tx", NULL, NULL,
"gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DR, 141,
"mcbsp3_dr", "uart2_rts", NULL, NULL,
"gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DX, 140,
"mcbsp3_dx", "uart2_cts", NULL, NULL,
"gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_FSX, 143,
"mcbsp3_fsx", "uart2_rx", NULL, NULL,
"gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
"mcbsp4_clkx", NULL, NULL, NULL,
"gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DR, 153,
"mcbsp4_dr", NULL, NULL, NULL,
"gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DX, 154,
"mcbsp4_dx", NULL, NULL, NULL,
"gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_FSX, 155,
"mcbsp4_fsx", NULL, NULL, NULL,
"gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP_CLKS, 160,
"mcbsp_clks", NULL, "cam_shutter", NULL,
"gpio_160", "uart1_cts", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CLK, 171,
"mcspi1_clk", "sdmmc2_dat4", NULL, NULL,
"gpio_171", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS0, 174,
"mcspi1_cs0", "sdmmc2_dat7", NULL, NULL,
"gpio_174", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS1, 175,
"mcspi1_cs1", NULL, NULL, "sdmmc3_cmd",
"gpio_175", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS2, 176,
"mcspi1_cs2", NULL, NULL, "sdmmc3_clk",
"gpio_176", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS3, 177,
"mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2",
"gpio_177", "mm2_txdat", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_SIMO, 172,
"mcspi1_simo", "sdmmc2_dat5", NULL, NULL,
"gpio_172", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_SOMI, 173,
"mcspi1_somi", "sdmmc2_dat6", NULL, NULL,
"gpio_173", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_CLK, 178,
"mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7",
"gpio_178", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_CS0, 181,
"mcspi2_cs0", "gpt11_pwm_evt",
"hsusb2_tll_data6", "hsusb2_data6",
"gpio_181", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_CS1, 182,
"mcspi2_cs1", "gpt8_pwm_evt",
"hsusb2_tll_data3", "hsusb2_data3",
"gpio_182", "mm2_txen_n", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_SIMO, 179,
"mcspi2_simo", "gpt9_pwm_evt",
"hsusb2_tll_data4", "hsusb2_data4",
"gpio_179", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_SOMI, 180,
"mcspi2_somi", "gpt10_pwm_evt",
"hsusb2_tll_data5", "hsusb2_data5",
"gpio_180", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_CLK, 120,
"sdmmc1_clk", NULL, NULL, NULL,
"gpio_120", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_CMD, 121,
"sdmmc1_cmd", NULL, NULL, NULL,
"gpio_121", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
"sdmmc1_dat0", NULL, NULL, NULL,
"gpio_122", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
"sdmmc1_dat1", NULL, NULL, NULL,
"gpio_123", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
"sdmmc1_dat2", NULL, NULL, NULL,
"gpio_124", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
"sdmmc1_dat3", NULL, NULL, NULL,
"gpio_125", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT4, 126,
"sdmmc1_dat4", NULL, "sim_io", NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT5, 127,
"sdmmc1_dat5", NULL, "sim_clk", NULL,
"gpio_127", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT6, 128,
"sdmmc1_dat6", NULL, "sim_pwrctrl", NULL,
"gpio_128", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT7, 129,
"sdmmc1_dat7", NULL, "sim_rst", NULL,
"gpio_129", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_CLK, 130,
"sdmmc2_clk", "mcspi3_clk", NULL, NULL,
"gpio_130", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_CMD, 131,
"sdmmc2_cmd", "mcspi3_simo", NULL, NULL,
"gpio_131", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT0, 132,
"sdmmc2_dat0", "mcspi3_somi", NULL, NULL,
"gpio_132", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT1, 133,
"sdmmc2_dat1", NULL, NULL, NULL,
"gpio_133", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT2, 134,
"sdmmc2_dat2", "mcspi3_cs1", NULL, NULL,
"gpio_134", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT3, 135,
"sdmmc2_dat3", "mcspi3_cs0", NULL, NULL,
"gpio_135", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT4, 136,
"sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0",
"gpio_136", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
"sdmmc2_dat5", "sdmmc2_dir_dat1",
"cam_global_reset", "sdmmc3_dat1",
"gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
"sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
"gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
"sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
"gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"),
_OMAP3_MUXENTRY(SDRC_CKE0, 0,
"sdrc_cke0", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDRC_CKE1, 0,
"sdrc_cke1", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT0, 2,
"sys_boot0", NULL, NULL, NULL,
"gpio_2", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT1, 3,
"sys_boot1", NULL, NULL, NULL,
"gpio_3", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT2, 4,
"sys_boot2", NULL, NULL, NULL,
"gpio_4", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT3, 5,
"sys_boot3", NULL, NULL, NULL,
"gpio_5", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT4, 6,
"sys_boot4", "sdmmc2_dir_dat2", NULL, NULL,
"gpio_6", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT5, 7,
"sys_boot5", "sdmmc2_dir_dat3", NULL, NULL,
"gpio_7", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT6, 8,
"sys_boot6", NULL, NULL, NULL,
"gpio_8", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_CLKOUT1, 10,
"sys_clkout1", NULL, NULL, NULL,
"gpio_10", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_CLKOUT2, 186,
"sys_clkout2", NULL, NULL, NULL,
"gpio_186", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_CLKREQ, 1,
"sys_clkreq", NULL, NULL, NULL,
"gpio_1", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_NIRQ, 0,
"sys_nirq", NULL, NULL, NULL,
"gpio_0", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_NRESWARM, 30,
"sys_nreswarm", NULL, NULL, NULL,
"gpio_30", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_OFF_MODE, 9,
"sys_off_mode", NULL, NULL, NULL,
"gpio_9", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_CTS, 150,
"uart1_cts", "ssi1_rdy_tx", NULL, NULL,
"gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RTS, 149,
"uart1_rts", "ssi1_flag_tx", NULL, NULL,
"gpio_149", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RX, 151,
"uart1_rx", "ssi1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
"gpio_151", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_TX, 148,
"uart1_tx", "ssi1_dat_tx", NULL, NULL,
"gpio_148", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_CTS, 144,
"uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
"gpio_144", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_RTS, 145,
"uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL,
"gpio_145", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_RX, 147,
"uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL,
"gpio_147", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_TX, 146,
"uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL,
"gpio_146", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_CTS_RCTX, 163,
"uart3_cts_rctx", NULL, NULL, NULL,
"gpio_163", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_RTS_SD, 164,
"uart3_rts_sd", NULL, NULL, NULL,
"gpio_164", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_RX_IRRX, 165,
"uart3_rx_irrx", NULL, NULL, NULL,
"gpio_165", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
"uart3_tx_irtx", NULL, NULL, NULL,
"gpio_166", NULL, NULL, "safe_mode"),
/* Only on 3630, see omap36xx_cbp_subset for the signals */
_OMAP3_MUXENTRY(GPMC_A11, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MREAD, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SREAD, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(GPMC_A11, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
/*
* Signals different on CBC package compared to the superset
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC)
static struct omap_mux __initdata omap3_cbc_subset[] = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbc_subset NULL
#endif
/*
* Balls for CBC package
* 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom)
*
* FIXME: What's up with the outdated TI documentation? See:
*
* http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package
* http://community.ti.com/forums/t/10982.aspx
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CBC)
static struct omap_ball __initdata omap3_cbc_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ae16", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ae15", NULL),
_OMAP3_BALLENTRY(CAM_D10, "d25", NULL),
_OMAP3_BALLENTRY(CAM_D11, "e26", NULL),
_OMAP3_BALLENTRY(CAM_D2, "a24", NULL),
_OMAP3_BALLENTRY(CAM_D3, "b24", NULL),
_OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
_OMAP3_BALLENTRY(CAM_D5, "c24", NULL),
_OMAP3_BALLENTRY(CAM_D6, "p25", NULL),
_OMAP3_BALLENTRY(CAM_D7, "p26", NULL),
_OMAP3_BALLENTRY(CAM_D8, "n25", NULL),
_OMAP3_BALLENTRY(CAM_D9, "n26", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "b23", NULL),
_OMAP3_BALLENTRY(CAM_HS, "c23", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL),
_OMAP3_BALLENTRY(CAM_VS, "d23", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "a23", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL),
_OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL),
_OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL),
_OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL),
_OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL),
_OMAP3_BALLENTRY(ETK_D0, "ac3", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ad4", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ae4", NULL),
_OMAP3_BALLENTRY(ETK_D11, "af6", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ae6", NULL),
_OMAP3_BALLENTRY(ETK_D13, "af7", NULL),
_OMAP3_BALLENTRY(ETK_D14, "af9", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ae9", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ad3", NULL),
_OMAP3_BALLENTRY(ETK_D3, "aa3", NULL),
_OMAP3_BALLENTRY(ETK_D4, "y3", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ab1", NULL),
_OMAP3_BALLENTRY(ETK_D6, "ae3", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ad2", NULL),
_OMAP3_BALLENTRY(ETK_D8, "aa4", NULL),
_OMAP3_BALLENTRY(ETK_D9, "v2", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "j2", NULL),
_OMAP3_BALLENTRY(GPMC_A10, "d2", NULL),
_OMAP3_BALLENTRY(GPMC_A2, "h1", NULL),
_OMAP3_BALLENTRY(GPMC_A3, "h2", NULL),
_OMAP3_BALLENTRY(GPMC_A4, "g2", NULL),
_OMAP3_BALLENTRY(GPMC_A5, "f1", NULL),
_OMAP3_BALLENTRY(GPMC_A6, "f2", NULL),
_OMAP3_BALLENTRY(GPMC_A7, "e1", NULL),
_OMAP3_BALLENTRY(GPMC_A8, "e2", NULL),
_OMAP3_BALLENTRY(GPMC_A9, "d1", NULL),
_OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"),
_OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"),
_OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"),
_OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"),
_OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"),
_OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"),
_OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"),
_OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"),
_OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL),
_OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL),
_OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"),
_OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"),
_OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"),
_OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL),
_OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL),
_OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL),
_OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL),
_OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "w2", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "r2", NULL),
_OMAP3_BALLENTRY(UART1_RX, "h3", NULL),
_OMAP3_BALLENTRY(UART1_TX, "l4", NULL),
_OMAP3_BALLENTRY(UART2_CTS, "y24", NULL),
_OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL),
_OMAP3_BALLENTRY(UART2_RX, "ad21", NULL),
_OMAP3_BALLENTRY(UART2_TX, "ad22", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbc_ball NULL
#endif
/*
* Signals different on CUS package compared to superset
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
static struct omap_mux __initdata omap3_cus_subset[] = {
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", NULL, NULL, NULL,
"gpio_109", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D11, 110,
"cam_d11", NULL, NULL, NULL,
"gpio_110", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", NULL, NULL, NULL,
"gpio_101", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", NULL, NULL, NULL,
"gpio_102", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", NULL, NULL, NULL,
"gpio_103", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", NULL, NULL, NULL,
"gpio_104", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_FLD, 98,
"cam_fld", NULL, "cam_global_reset", NULL,
"gpio_98", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", NULL, NULL, NULL,
"gpio_94", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_PCLK, 97,
"cam_pclk", NULL, NULL, NULL,
"gpio_97", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_STROBE, 126,
"cam_strobe", NULL, NULL, NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", NULL, NULL, NULL,
"gpio_95", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_WEN, 167,
"cam_wen", NULL, "cam_shutter", NULL,
"gpio_167", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", NULL,
"gpio_76", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", NULL,
"gpio_77", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, NULL, NULL,
"gpio_78", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, NULL, NULL,
"gpio_79", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_HSYNC, 67,
"dss_hsync", NULL, NULL, NULL,
"gpio_67", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_PCLK, 66,
"dss_pclk", NULL, NULL, NULL,
"gpio_66", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_CLK, 12,
"etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
"gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_CTL, 13,
"etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
"gpio_13", NULL, "hsusb1_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D0, 14,
"etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
"gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D1, 15,
"etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
"gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D10, 24,
"etk_d10", NULL, "uart1_rx", "hsusb2_clk",
"gpio_24", NULL, "hsusb2_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D11, 25,
"etk_d11", NULL, NULL, "hsusb2_stp",
"gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", NULL, NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D13, 27,
"etk_d13", NULL, NULL, "hsusb2_nxt",
"gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
_OMAP3_MUXENTRY(ETK_D14, 28,
"etk_d14", NULL, NULL, "hsusb2_data0",
"gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D15, 29,
"etk_d15", NULL, NULL, "hsusb2_data1",
"gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D2, 16,
"etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
"gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
_OMAP3_MUXENTRY(ETK_D3, 17,
"etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
"gpio_17", NULL, "hsusb1_tll_data7", NULL),
_OMAP3_MUXENTRY(ETK_D4, 18,
"etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
"gpio_18", NULL, "hsusb1_tll_data4", NULL),
_OMAP3_MUXENTRY(ETK_D5, 19,
"etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
"gpio_19", NULL, "hsusb1_tll_data5", NULL),
_OMAP3_MUXENTRY(ETK_D6, 20,
"etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
"gpio_20", NULL, "hsusb1_tll_data6", NULL),
_OMAP3_MUXENTRY(ETK_D7, 21,
"etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
"gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
_OMAP3_MUXENTRY(ETK_D8, 22,
"etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
"gpio_22", NULL, "hsusb1_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D9, 23,
"etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
"gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
_OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
"mcbsp3_clkx", "uart2_tx", NULL, NULL,
"gpio_142", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DR, 141,
"mcbsp3_dr", "uart2_rts", NULL, NULL,
"gpio_141", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DX, 140,
"mcbsp3_dx", "uart2_cts", NULL, NULL,
"gpio_140", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_FSX, 143,
"mcbsp3_fsx", "uart2_rx", NULL, NULL,
"gpio_143", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
"sdmmc2_dat5", "sdmmc2_dir_dat1",
"cam_global_reset", "sdmmc3_dat1",
"gpio_137", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
"sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
"gpio_138", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
"sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
"gpio_139", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_CTS, 150,
"uart1_cts", NULL, NULL, NULL,
"gpio_150", NULL, NULL, "safe_mode"),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cus_subset NULL
#endif
/*
* Balls for CUS package
* 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CUS)
static struct omap_ball __initdata omap3_cus_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
_OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
_OMAP3_BALLENTRY(CAM_D11, "g21", NULL),
_OMAP3_BALLENTRY(CAM_D2, "g19", NULL),
_OMAP3_BALLENTRY(CAM_D3, "f19", NULL),
_OMAP3_BALLENTRY(CAM_D4, "g20", NULL),
_OMAP3_BALLENTRY(CAM_D5, "b21", NULL),
_OMAP3_BALLENTRY(CAM_D6, "l24", NULL),
_OMAP3_BALLENTRY(CAM_D7, "k24", NULL),
_OMAP3_BALLENTRY(CAM_D8, "j23", NULL),
_OMAP3_BALLENTRY(CAM_D9, "k23", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "h24", NULL),
_OMAP3_BALLENTRY(CAM_HS, "a22", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL),
_OMAP3_BALLENTRY(CAM_VS, "e18", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "f18", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL),
_OMAP3_BALLENTRY(ETK_D0, "ad6", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ac6", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ac3", NULL),
_OMAP3_BALLENTRY(ETK_D11, "ac9", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ac10", NULL),
_OMAP3_BALLENTRY(ETK_D13, "ad11", NULL),
_OMAP3_BALLENTRY(ETK_D14, "ac11", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ad12", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ac7", NULL),
_OMAP3_BALLENTRY(ETK_D3, "ad8", NULL),
_OMAP3_BALLENTRY(ETK_D4, "ac5", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ad2", NULL),
_OMAP3_BALLENTRY(ETK_D6, "ac8", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ad9", NULL),
_OMAP3_BALLENTRY(ETK_D8, "ac4", NULL),
_OMAP3_BALLENTRY(ETK_D9, "ad5", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "k4", NULL),
_OMAP3_BALLENTRY(GPMC_A10, "g2", NULL),
_OMAP3_BALLENTRY(GPMC_A2, "k3", NULL),
_OMAP3_BALLENTRY(GPMC_A3, "k2", NULL),
_OMAP3_BALLENTRY(GPMC_A4, "j4", NULL),
_OMAP3_BALLENTRY(GPMC_A5, "j3", NULL),
_OMAP3_BALLENTRY(GPMC_A6, "j2", NULL),
_OMAP3_BALLENTRY(GPMC_A7, "j1", NULL),
_OMAP3_BALLENTRY(GPMC_A8, "h1", NULL),
_OMAP3_BALLENTRY(GPMC_A9, "h2", NULL),
_OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL),
_OMAP3_BALLENTRY(GPMC_D10, "u1", NULL),
_OMAP3_BALLENTRY(GPMC_D11, "r3", NULL),
_OMAP3_BALLENTRY(GPMC_D12, "t3", NULL),
_OMAP3_BALLENTRY(GPMC_D13, "u2", NULL),
_OMAP3_BALLENTRY(GPMC_D14, "v1", NULL),
_OMAP3_BALLENTRY(GPMC_D15, "v2", NULL),
_OMAP3_BALLENTRY(GPMC_D8, "r2", NULL),
_OMAP3_BALLENTRY(GPMC_D9, "t2", NULL),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL),
_OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "w6", NULL),
_OMAP3_BALLENTRY(UART1_RX, "v7", NULL),
_OMAP3_BALLENTRY(UART1_TX, "w7", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cus_ball NULL
#endif
/*
* Signals different on CBB package compared to superset
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
static struct omap_mux __initdata omap3_cbb_subset[] = {
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", NULL, NULL, NULL,
"gpio_109", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D11, 110,
"cam_d11", NULL, NULL, NULL,
"gpio_110", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", NULL, NULL, NULL,
"gpio_101", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", NULL, NULL, NULL,
"gpio_102", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", NULL, NULL, NULL,
"gpio_103", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", NULL, NULL, NULL,
"gpio_104", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_FLD, 98,
"cam_fld", NULL, "cam_global_reset", NULL,
"gpio_98", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", NULL, NULL, NULL,
"gpio_94", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_PCLK, 97,
"cam_pclk", NULL, NULL, NULL,
"gpio_97", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_STROBE, 126,
"cam_strobe", NULL, NULL, NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", NULL, NULL, NULL,
"gpio_95", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_WEN, 167,
"cam_wen", NULL, "cam_shutter", NULL,
"gpio_167", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", NULL,
"gpio_76", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", NULL,
"gpio_77", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, NULL, NULL,
"gpio_78", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, NULL, NULL,
"gpio_79", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_HSYNC, 67,
"dss_hsync", NULL, NULL, NULL,
"gpio_67", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_PCLK, 66,
"dss_pclk", NULL, NULL, NULL,
"gpio_66", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_CLK, 12,
"etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
"gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_CTL, 13,
"etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
"gpio_13", NULL, "hsusb1_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D0, 14,
"etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
"gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D1, 15,
"etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
"gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D10, 24,
"etk_d10", NULL, "uart1_rx", "hsusb2_clk",
"gpio_24", NULL, "hsusb2_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D11, 25,
"etk_d11", NULL, NULL, "hsusb2_stp",
"gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", NULL, NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D13, 27,
"etk_d13", NULL, NULL, "hsusb2_nxt",
"gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
_OMAP3_MUXENTRY(ETK_D14, 28,
"etk_d14", NULL, NULL, "hsusb2_data0",
"gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D15, 29,
"etk_d15", NULL, NULL, "hsusb2_data1",
"gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D2, 16,
"etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
"gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
_OMAP3_MUXENTRY(ETK_D3, 17,
"etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
"gpio_17", NULL, "hsusb1_tll_data7", NULL),
_OMAP3_MUXENTRY(ETK_D4, 18,
"etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
"gpio_18", NULL, "hsusb1_tll_data4", NULL),
_OMAP3_MUXENTRY(ETK_D5, 19,
"etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
"gpio_19", NULL, "hsusb1_tll_data5", NULL),
_OMAP3_MUXENTRY(ETK_D6, 20,
"etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
"gpio_20", NULL, "hsusb1_tll_data6", NULL),
_OMAP3_MUXENTRY(ETK_D7, 21,
"etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
"gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
_OMAP3_MUXENTRY(ETK_D8, 22,
"etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
"gpio_22", NULL, "hsusb1_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D9, 23,
"etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
"gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbb_subset NULL
#endif
/*
* Balls for CBB package
* 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CBB)
static struct omap_ball __initdata omap3_cbb_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
_OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
_OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
_OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
_OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
_OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
_OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
_OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
_OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
_OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
_OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
_OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
_OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
_OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
_OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
_OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
_OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
_OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
_OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
_OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
_OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
_OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
_OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
_OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
_OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
_OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
_OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
_OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
_OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
_OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
_OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
_OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
_OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
_OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
_OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
_OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
_OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
_OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
_OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
_OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
_OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
_OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
_OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
_OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
_OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
_OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
_OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
_OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
_OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
_OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
_OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
_OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
_OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
_OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
_OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
_OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbb_ball NULL
#endif
/*
* Signals different on 36XX CBP package compared to 34XX CBC package
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
static struct omap_mux __initdata omap36xx_cbp_subset[] = {
_OMAP3_MUXENTRY(CAM_D0, 99,
"cam_d0", NULL, "csi2_dx2", NULL,
"gpio_99", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D1, 100,
"cam_d1", NULL, "csi2_dy2", NULL,
"gpio_100", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", "ssi2_wake", NULL, NULL,
"gpio_109", "hw_dbg8", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", "ssi2_rdy_tx", NULL, NULL,
"gpio_101", "hw_dbg4", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", "ssi2_dat_rx", NULL, NULL,
"gpio_102", "hw_dbg5", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", "ssi2_flag_rx", NULL, NULL,
"gpio_103", "hw_dbg6", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", "ssi2_rdy_rx", NULL, NULL,
"gpio_104", "hw_dbg7", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", "ssi2_dat_tx", NULL, NULL,
"gpio_94", "hw_dbg0", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", "ssi2_flag_tx", NULL, NULL,
"gpio_95", "hw_dbg1", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA0, 70,
"dss_data0", "dsi_dx0", "uart1_cts", NULL,
"gpio_70", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA1, 71,
"dss_data1", "dsi_dy0", "uart1_rts", NULL,
"gpio_71", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA2, 72,
"dss_data2", "dsi_dx1", NULL, NULL,
"gpio_72", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA3, 73,
"dss_data3", "dsi_dy1", NULL, NULL,
"gpio_73", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA4, 74,
"dss_data4", "dsi_dx2", "uart3_rx_irrx", NULL,
"gpio_74", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA5, 75,
"dss_data5", "dsi_dy2", "uart3_tx_irtx", NULL,
"gpio_75", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", "dssvenc656_data6",
"gpio_76", "hw_dbg14", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", "dssvenc656_data7",
"gpio_77", "hw_dbg15", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, "uart3_rx_irrx", NULL,
"gpio_78", "hw_dbg16", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, "uart3_tx_irtx", NULL,
"gpio_79", "hw_dbg17", NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", "sys_drm_msecure", NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
_OMAP3_MUXENTRY(GPMC_A11, 0,
"gpmc_a11", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT2, 64,
"gpmc_wait2", NULL, "uart4_tx", NULL,
"gpio_64", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT3, 65,
"gpmc_wait3", "sys_ndmareq1", "uart4_rx", NULL,
"gpio_65", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
"hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
"gpio_125", "uart2_tx", NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
"hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
"gpio_130", "uart2_rx", NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
"hsusb0_data2", NULL, "uart3_rts_sd", NULL,
"gpio_131", "uart2_rts", NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
"hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
"gpio_169", "uart2_cts", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
"mcbsp1_clkr", "mcspi4_clk", "sim_cd", NULL,
"gpio_156", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_FSR, 157,
"mcbsp1_fsr", "adpllv2d_dithering_en1",
"cam_global_reset", NULL,
"gpio_157", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
"mcbsp4_clkx", "ssi1_dat_rx", NULL, NULL,
"gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DR, 153,
"mcbsp4_dr", "ssi1_flag_rx", NULL, NULL,
"gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DX, 154,
"mcbsp4_dx", "ssi1_rdy_rx", NULL, NULL,
"gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_FSX, 155,
"mcbsp4_fsx", "ssi1_wake", NULL, NULL,
"gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS1, 175,
"mcspi1_cs1", "adpllv2d_dithering_en2", NULL, "sdmmc3_cmd",
"gpio_175", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
"sad2d_mbusflag", "mad2d_sbusflag", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
"sad2d_mcad28", "mad2d_mcad28", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
"sad2d_mcad29", "mad2d_mcad29", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
"sad2d_mcad32", "mad2d_mcad32", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
"sad2d_mcad33", "mad2d_mcad33", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
"sad2d_mcad34", "mad2d_mcad34", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
"sad2d_mcad35", "mad2d_mcad35", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
"sad2d_mcad36", "mad2d_mcad36", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MREAD, 0,
"sad2d_mread", "mad2d_sread", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
"sad2d_mwrite", "mad2d_swrite", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
"sad2d_sbusflag", "mad2d_mbusflag", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SREAD, 0,
"sad2d_sread", "mad2d_mread", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
"sad2d_swrite", "mad2d_mwrite", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SDMMC1_CLK, 120,
"sdmmc1_clk", "ms_clk", NULL, NULL,
"gpio_120", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_CMD, 121,
"sdmmc1_cmd", "ms_bs", NULL, NULL,
"gpio_121", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
"sdmmc1_dat0", "ms_dat0", NULL, NULL,
"gpio_122", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
"sdmmc1_dat1", "ms_dat1", NULL, NULL,
"gpio_123", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
"sdmmc1_dat2", "ms_dat2", NULL, NULL,
"gpio_124", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
"sdmmc1_dat3", "ms_dat3", NULL, NULL,
"gpio_125", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDRC_CKE0, 0,
"sdrc_cke0", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode_out1"),
_OMAP3_MUXENTRY(SDRC_CKE1, 0,
"sdrc_cke1", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode_out1"),
_OMAP3_MUXENTRY(SIM_IO, 126,
"sim_io", "sim_io_low_impedance", NULL, NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SIM_CLK, 127,
"sim_clk", NULL, NULL, NULL,
"gpio_127", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SIM_PWRCTRL, 128,
"sim_pwrctrl", NULL, NULL, NULL,
"gpio_128", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SIM_RST, 129,
"sim_rst", NULL, NULL, NULL,
"gpio_129", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT0, 2,
"sys_boot0", NULL, NULL, "dss_data18",
"gpio_2", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT1, 3,
"sys_boot1", NULL, NULL, "dss_data19",
"gpio_3", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT3, 5,
"sys_boot3", NULL, NULL, "dss_data20",
"gpio_5", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT4, 6,
"sys_boot4", "sdmmc2_dir_dat2", NULL, "dss_data21",
"gpio_6", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT5, 7,
"sys_boot5", "sdmmc2_dir_dat3", NULL, "dss_data22",
"gpio_7", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT6, 8,
"sys_boot6", NULL, NULL, "dss_data23",
"gpio_8", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_CTS, 150,
"uart1_cts", "ssi1_rdy_tx", NULL, NULL,
"gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RTS, 149,
"uart1_rts", "ssi1_flag_tx", NULL, NULL,
"gpio_149", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_TX, 148,
"uart1_tx", "ssi1_dat_tx", NULL, NULL,
"gpio_148", NULL, NULL, "safe_mode"),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap36xx_cbp_subset NULL
#endif
/*
* Balls for 36XX CBP package
* 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined (CONFIG_OMAP_PACKAGE_CBP)
static struct omap_ball __initdata omap36xx_cbp_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
_OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
_OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
_OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
_OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
_OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
_OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
_OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
_OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
_OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
_OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
_OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
_OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
_OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
_OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
_OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
_OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
_OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
_OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
_OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
_OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
_OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
_OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
_OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
_OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
_OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
_OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
_OMAP3_BALLENTRY(GPMC_A11, NULL, "ac20"),
_OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
_OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
_OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
_OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
_OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
_OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
_OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
_OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
_OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
_OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
_OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
_OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
_OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
_OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
_OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
_OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
_OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
_OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
_OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
_OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
_OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
_OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
_OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"),
_OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"),
_OMAP3_BALLENTRY(SIM_CLK, "p26", NULL),
_OMAP3_BALLENTRY(SIM_IO, "p27", NULL),
_OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL),
_OMAP3_BALLENTRY(SIM_RST, "r25", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
_OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
_OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
_OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
_OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
_OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
_OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap36xx_cbp_ball NULL
#endif
int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
{
struct omap_mux *package_subset;
struct omap_ball *package_balls;
switch (flags & OMAP_PACKAGE_MASK) {
case OMAP_PACKAGE_CBC:
package_subset = omap3_cbc_subset;
package_balls = omap3_cbc_ball;
break;
case OMAP_PACKAGE_CBB:
package_subset = omap3_cbb_subset;
package_balls = omap3_cbb_ball;
break;
case OMAP_PACKAGE_CUS:
package_subset = omap3_cus_subset;
package_balls = omap3_cus_ball;
break;
case OMAP_PACKAGE_CBP:
package_subset = omap36xx_cbp_subset;
package_balls = omap36xx_cbp_ball;
break;
default:
pr_err("%s Unknown omap package, mux disabled\n", __func__);
return -EINVAL;
}
return omap_mux_init("core", OMAP_MUX_GPIO_IN_MODE4,
OMAP3_CONTROL_PADCONF_MUX_PBASE,
OMAP3_CONTROL_PADCONF_MUX_SIZE,
omap3_muxmodes, package_subset, board_subset,
package_balls);
}
arch/arm/mach-omap2/mux34xx.h deleted 100644 → 0
View file @ a9fa1f7c
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
#define OMAP3_MUX(mode0, mux_value) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
.value = (mux_value), \
}
/*
* OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
*
* Extracted from the TRM. Add 0x48002030 to these values to get the
* absolute addresses. The name in the macro is the mode-0 name of
* the pin. NOTE: These registers are 16-bits wide.
*
* Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
* of CHASSIS for some registers. For the defines, we follow the
* 36XX naming, and use SDMMC and CHASSIS.
*/
#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
/* 36xx only */
#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236
#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570
#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572
#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574
#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576
#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578
#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a
#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c
#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e
#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580
#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582
#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584
#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586
#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588
#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a
#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c
#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e
#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590
#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592
#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594
#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596
#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598
#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a
#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c
#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e
#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0
#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2
#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4
/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120
#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122
#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124
#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126
#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
#define OMAP3_CONTROL_PADCONF_GPIO_127 0xa24
#define OMAP3_CONTROL_PADCONF_GPIO_126 0xa26
#define OMAP3_CONTROL_PADCONF_GPIO_128 0xa28
#define OMAP3_CONTROL_PADCONF_GPIO_129 0xa2a
#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
(OMAP3_CONTROL_PADCONF_GPIO_129 + 0x2)
arch/arm/mach-omap2/omap_hwmod.c
View file @ 6d1e66bb
...@@ -160,7 +160,6 @@ ...@@ -160,7 +160,6 @@
#include "prm44xx.h" #include "prm44xx.h"
#include "prm33xx.h" #include "prm33xx.h"
#include "prminst44xx.h" #include "prminst44xx.h"
#include "mux.h"
#include "pm.h" #include "pm.h"
/* Name of the OMAP hwmod for the MPU */ /* Name of the OMAP hwmod for the MPU */
...@@ -217,9 +216,6 @@ static LIST_HEAD(omap_hwmod_list); ...@@ -217,9 +216,6 @@ static LIST_HEAD(omap_hwmod_list);
/* mpu_oh: used to add/remove MPU initiator from sleepdep list */ /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
static struct omap_hwmod *mpu_oh; static struct omap_hwmod *mpu_oh;
/* io_chain_lock: used to serialize reconfigurations of the I/O chain */
static DEFINE_SPINLOCK(io_chain_lock);
/* /*
* linkspace: ptr to a buffer that struct omap_hwmod_link records are * linkspace: ptr to a buffer that struct omap_hwmod_link records are
* allocated from - used to reduce the number of small memory * allocated from - used to reduce the number of small memory
...@@ -593,51 +589,6 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, ...@@ -593,51 +589,6 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
return 0; return 0;
} }
/**
* _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
* @oh: struct omap_hwmod *
* @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
*
* Set or clear the I/O pad wakeup flag in the mux entries for the
* hwmod @oh. This function changes the @oh->mux->pads_dynamic array
* in memory. If the hwmod is currently idled, and the new idle
* values don't match the previous ones, this function will also
* update the SCM PADCTRL registers. Otherwise, if the hwmod is not
* currently idled, this function won't touch the hardware: the new
* mux settings are written to the SCM PADCTRL registers when the
* hwmod is idled. No return value.
*/
static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
{
struct omap_device_pad *pad;
bool change = false;
u16 prev_idle;
int j;
if (!oh->mux || !oh->mux->enabled)
return;
for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
pad = oh->mux->pads_dynamic[j];
if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
continue;
prev_idle = pad->idle;
if (set_wake)
pad->idle |= OMAP_WAKEUP_EN;
else
pad->idle &= ~OMAP_WAKEUP_EN;
if (prev_idle != pad->idle)
change = true;
}
if (change && oh->_state == _HWMOD_STATE_IDLE)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
}
/** /**
* _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
* @oh: struct omap_hwmod * * @oh: struct omap_hwmod *
...@@ -2017,29 +1968,6 @@ static int _reset(struct omap_hwmod *oh) ...@@ -2017,29 +1968,6 @@ static int _reset(struct omap_hwmod *oh)
return r; return r;
} }
/**
* _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain
*
* Call the appropriate PRM function to clear any logged I/O chain
* wakeups and to reconfigure the chain. This apparently needs to be
* done upon every mux change. Since hwmods can be concurrently
* enabled and idled, hold a spinlock around the I/O chain
* reconfiguration sequence. No return value.
*
* XXX When the PRM code is moved to drivers, this function can be removed,
* as the PRM infrastructure should abstract this.
*/
static void _reconfigure_io_chain(void)
{
unsigned long flags;
spin_lock_irqsave(&io_chain_lock, flags);
omap_prm_reconfigure_io_chain();
spin_unlock_irqrestore(&io_chain_lock, flags);
}
/** /**
* _omap4_update_context_lost - increment hwmod context loss counter if * _omap4_update_context_lost - increment hwmod context loss counter if
* hwmod context was lost, and clear hardware context loss reg * hwmod context was lost, and clear hardware context loss reg
...@@ -2109,18 +2037,9 @@ static int _enable(struct omap_hwmod *oh) ...@@ -2109,18 +2037,9 @@ static int _enable(struct omap_hwmod *oh)
/* /*
* hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
* state at init. Now that someone is really trying to enable * state at init.
* them, just ensure that the hwmod mux is set.
*/ */
if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
/*
* If the caller has mux data populated, do the mux'ing
* which wouldn't have been done as part of the _enable()
* done during setup.
*/
if (oh->mux)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
return 0; return 0;
} }
...@@ -2145,16 +2064,6 @@ static int _enable(struct omap_hwmod *oh) ...@@ -2145,16 +2064,6 @@ static int _enable(struct omap_hwmod *oh)
if (_are_all_hardreset_lines_asserted(oh)) if (_are_all_hardreset_lines_asserted(oh))
return 0; return 0;
/* Mux pins for device runtime if populated */
if (oh->mux && (!oh->mux->enabled ||
((oh->_state == _HWMOD_STATE_IDLE) &&
oh->mux->pads_dynamic))) {
omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
_reconfigure_io_chain();
} else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
_reconfigure_io_chain();
}
_add_initiator_dep(oh, mpu_oh); _add_initiator_dep(oh, mpu_oh);
if (oh->clkdm) { if (oh->clkdm) {
...@@ -2260,14 +2169,6 @@ static int _idle(struct omap_hwmod *oh) ...@@ -2260,14 +2169,6 @@ static int _idle(struct omap_hwmod *oh)
clkdm_hwmod_disable(oh->clkdm, oh); clkdm_hwmod_disable(oh->clkdm, oh);
} }
/* Mux pins for device idle if populated */
if (oh->mux && oh->mux->pads_dynamic) {
omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
_reconfigure_io_chain();
} else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
_reconfigure_io_chain();
}
oh->_state = _HWMOD_STATE_IDLE; oh->_state = _HWMOD_STATE_IDLE;
return 0; return 0;
...@@ -2334,10 +2235,6 @@ static int _shutdown(struct omap_hwmod *oh) ...@@ -2334,10 +2235,6 @@ static int _shutdown(struct omap_hwmod *oh)
for (i = 0; i < oh->rst_lines_cnt; i++) for (i = 0; i < oh->rst_lines_cnt; i++)
_assert_hardreset(oh, oh->rst_lines[i].name); _assert_hardreset(oh, oh->rst_lines[i].name);
/* Mux pins to safe mode or use populated off mode values */
if (oh->mux)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
oh->_state = _HWMOD_STATE_DISABLED; oh->_state = _HWMOD_STATE_DISABLED;
return 0; return 0;
...@@ -3729,7 +3626,6 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) ...@@ -3729,7 +3626,6 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
_write_sysconfig(v, oh); _write_sysconfig(v, oh);
} }
_set_idle_ioring_wakeup(oh, true);
spin_unlock_irqrestore(&oh->_lock, flags); spin_unlock_irqrestore(&oh->_lock, flags);
return 0; return 0;
...@@ -3762,7 +3658,6 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) ...@@ -3762,7 +3658,6 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
_write_sysconfig(v, oh); _write_sysconfig(v, oh);
} }
_set_idle_ioring_wakeup(oh, false);
spin_unlock_irqrestore(&oh->_lock, flags); spin_unlock_irqrestore(&oh->_lock, flags);
return 0; return 0;
......
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
View file @ 6d1e66bb
...@@ -17,156 +17,11 @@ ...@@ -17,156 +17,11 @@
#include "omap_hwmod_common_data.h" #include "omap_hwmod_common_data.h"
struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
{
.pa_start = 0x4809c000,
.pa_end = 0x4809c1ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
{
.pa_start = 0x480b4000,
.pa_end = 0x480b41ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
{
.pa_start = 0x48070000,
.pa_end = 0x48070000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
{
.pa_start = 0x48072000,
.pa_end = 0x48072000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_addrs[] = {
{
.pa_start = 0x48050000,
.pa_end = 0x48050000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
{
.pa_start = 0x48050400,
.pa_end = 0x48050400 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
{
.pa_start = 0x48050800,
.pa_end = 0x48050800 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
{
.pa_start = 0x48050C00,
.pa_end = 0x48050C00 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
{
.pa_start = 0x48086000,
.pa_end = 0x48086000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
{
.pa_start = 0x48088000,
.pa_end = 0x48088000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
{
.pa_start = 0x4808a000,
.pa_end = 0x4808a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x48098000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
{
.pa_start = 0x480b8000,
.pa_end = 0x480b8000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_dma_system_addrs[] = { struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
{ {
.pa_start = 0x48056000, .pa_start = 0x48056000,
.pa_end = 0x48056000 + SZ_4K - 1, .pa_end = 0x48056000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48074000,
.pa_end = 0x480740ff,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_hdq1w_addr_space[] = {
{
.pa_start = 0x480b2000,
.pa_end = 0x480b2fff,
.flags = ADDR_TYPE_RT, .flags = ADDR_TYPE_RT,
}, },
{ } { },
}; };
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
View file @ 6d1e66bb
...@@ -45,204 +45,31 @@ struct omap_hwmod_class omap2_venc_hwmod_class = { ...@@ -45,204 +45,31 @@ struct omap_hwmod_class omap2_venc_hwmod_class = {
.name = "venc", .name = "venc",
}; };
/* Common DMA request line data */
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
{ .name = "rx", .dma_req = 50, },
{ .name = "tx", .dma_req = 49, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
{ .name = "rx", .dma_req = 52, },
{ .name = "tx", .dma_req = 51, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
{ .name = "rx", .dma_req = 54, },
{ .name = "tx", .dma_req = 53, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 27 },
{ .name = "rx", .dma_req = 28 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 29 },
{ .name = "rx", .dma_req = 30 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
{ .name = "rx", .dma_req = 32 },
{ .name = "tx", .dma_req = 31 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
{ .name = "rx", .dma_req = 34 },
{ .name = "tx", .dma_req = 33 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
{ .name = "rx", .dma_req = 18 },
{ .name = "tx", .dma_req = 17 },
{ .dma_req = -1 }
};
/* Other IP block data */
/* /*
* omap_hwmod class data * omap_hwmod class data
*/ */
struct omap_hwmod_class l3_hwmod_class = { struct omap_hwmod_class l3_hwmod_class = {
.name = "l3" .name = "l3",
}; };
struct omap_hwmod_class l4_hwmod_class = { struct omap_hwmod_class l4_hwmod_class = {
.name = "l4" .name = "l4",
}; };
struct omap_hwmod_class mpu_hwmod_class = { struct omap_hwmod_class mpu_hwmod_class = {
.name = "mpu" .name = "mpu",
}; };
struct omap_hwmod_class iva_hwmod_class = { struct omap_hwmod_class iva_hwmod_class = {
.name = "iva" .name = "iva",
}; };
/* Common MPU IRQ line data */ /* Common MPU IRQ line data */
struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
{ .irq = 37 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
{ .irq = 38 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
{ .irq = 39 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
{ .irq = 40 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
{ .irq = 41 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
{ .irq = 42 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
{ .irq = 43 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
{ .irq = 44 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
{ .irq = 45 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
{ .irq = 46 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
{ .irq = 47 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
{ .irq = 72 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
{ .irq = 73 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
{ .irq = 74 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_dispc_irqs[] = { struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
{ .irq = 25 + OMAP_INTC_START, }, { .irq = 25 + OMAP_INTC_START, },
{ .irq = -1 }, { .irq = -1, },
};
struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
{ .irq = 56 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
{ .irq = 57 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
{ .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
{ .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
{ .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
{ .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
{ .irq = -1 },
}; };
struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
...@@ -250,17 +77,7 @@ struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { ...@@ -250,17 +77,7 @@ struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
{ .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */ { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
{ .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */ { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
{ .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */ { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
{ .irq = -1 }, { .irq = -1, },
};
struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
{ .irq = 65 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
{ .irq = 66 + OMAP_INTC_START, },
{ .irq = -1 },
}; };
struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
...@@ -277,9 +94,3 @@ struct omap_hwmod_class omap2_hdq1w_class = { ...@@ -277,9 +94,3 @@ struct omap_hwmod_class omap2_hdq1w_class = {
.sysc = &omap2_hdq1w_sysc, .sysc = &omap2_hdq1w_sysc,
.reset = &omap_hdq1w_reset, .reset = &omap_hdq1w_reset,
}; };
struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
{ .irq = 58 + OMAP_INTC_START, },
{ .irq = -1 },
};
arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
View file @ 6d1e66bb
...@@ -191,7 +191,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = { ...@@ -191,7 +191,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
.master = &omap2xxx_l4_core_hwmod, .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2xxx_dss_core_hwmod, .slave = &omap2xxx_dss_core_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2_dss_addrs,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
...@@ -206,7 +205,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = { ...@@ -206,7 +205,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
.master = &omap2xxx_l4_core_hwmod, .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2xxx_dss_dispc_hwmod, .slave = &omap2xxx_dss_dispc_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2_dss_dispc_addrs,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
...@@ -221,7 +219,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = { ...@@ -221,7 +219,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
.master = &omap2xxx_l4_core_hwmod, .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2xxx_dss_rfbi_hwmod, .slave = &omap2xxx_dss_rfbi_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2_dss_rfbi_addrs,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
...@@ -236,7 +233,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = { ...@@ -236,7 +233,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
.master = &omap2xxx_l4_core_hwmod, .master = &omap2xxx_l4_core_hwmod,
.slave = &omap2xxx_dss_venc_hwmod, .slave = &omap2xxx_dss_venc_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2_dss_venc_addrs,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
......
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
View file @ 6d1e66bb
...@@ -569,7 +569,6 @@ struct omap_hwmod omap2xxx_dss_core_hwmod = { ...@@ -569,7 +569,6 @@ struct omap_hwmod omap2xxx_dss_core_hwmod = {
struct omap_hwmod omap2xxx_dss_dispc_hwmod = { struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
.name = "dss_dispc", .name = "dss_dispc",
.class = &omap2_dispc_hwmod_class, .class = &omap2_dispc_hwmod_class,
.mpu_irqs = omap2_dispc_irqs,
.main_clk = "dss1_fck", .main_clk = "dss1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
......
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View file @ 6d1e66bb
...@@ -53,16 +53,10 @@ ...@@ -53,16 +53,10 @@
*/ */
/* L3 */ /* L3 */
static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
{ .irq = 9 + OMAP_INTC_START, },
{ .irq = 10 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap3xxx_l3_main_hwmod = { static struct omap_hwmod omap3xxx_l3_main_hwmod = {
.name = "l3_main", .name = "l3_main",
.class = &l3_hwmod_class, .class = &l3_hwmod_class,
.mpu_irqs = omap3xxx_l3_main_irqs,
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
...@@ -95,14 +89,9 @@ static struct omap_hwmod omap3xxx_l4_sec_hwmod = { ...@@ -95,14 +89,9 @@ static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
}; };
/* MPU */ /* MPU */
static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
{ .name = "pmu", .irq = 3 + OMAP_INTC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap3xxx_mpu_hwmod = { static struct omap_hwmod omap3xxx_mpu_hwmod = {
.name = "mpu", .name = "mpu",
.mpu_irqs = omap3xxx_mpu_irqs,
.class = &mpu_hwmod_class, .class = &mpu_hwmod_class,
.main_clk = "arm_fck", .main_clk = "arm_fck",
}; };
...@@ -128,7 +117,7 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { ...@@ -128,7 +117,7 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
.module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
.idlest_reg_id = 1, .idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
} },
}, },
}; };
...@@ -197,7 +186,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { ...@@ -197,7 +186,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
/* timer1 */ /* timer1 */
static struct omap_hwmod omap3xxx_timer1_hwmod = { static struct omap_hwmod omap3xxx_timer1_hwmod = {
.name = "timer1", .name = "timer1",
.mpu_irqs = omap2_timer1_mpu_irqs,
.main_clk = "gpt1_fck", .main_clk = "gpt1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -216,7 +204,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = { ...@@ -216,7 +204,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
/* timer2 */ /* timer2 */
static struct omap_hwmod omap3xxx_timer2_hwmod = { static struct omap_hwmod omap3xxx_timer2_hwmod = {
.name = "timer2", .name = "timer2",
.mpu_irqs = omap2_timer2_mpu_irqs,
.main_clk = "gpt2_fck", .main_clk = "gpt2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -234,7 +221,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = { ...@@ -234,7 +221,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
/* timer3 */ /* timer3 */
static struct omap_hwmod omap3xxx_timer3_hwmod = { static struct omap_hwmod omap3xxx_timer3_hwmod = {
.name = "timer3", .name = "timer3",
.mpu_irqs = omap2_timer3_mpu_irqs,
.main_clk = "gpt3_fck", .main_clk = "gpt3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -252,7 +238,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = { ...@@ -252,7 +238,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
/* timer4 */ /* timer4 */
static struct omap_hwmod omap3xxx_timer4_hwmod = { static struct omap_hwmod omap3xxx_timer4_hwmod = {
.name = "timer4", .name = "timer4",
.mpu_irqs = omap2_timer4_mpu_irqs,
.main_clk = "gpt4_fck", .main_clk = "gpt4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -270,7 +255,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = { ...@@ -270,7 +255,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
/* timer5 */ /* timer5 */
static struct omap_hwmod omap3xxx_timer5_hwmod = { static struct omap_hwmod omap3xxx_timer5_hwmod = {
.name = "timer5", .name = "timer5",
.mpu_irqs = omap2_timer5_mpu_irqs,
.main_clk = "gpt5_fck", .main_clk = "gpt5_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -289,7 +273,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { ...@@ -289,7 +273,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
/* timer6 */ /* timer6 */
static struct omap_hwmod omap3xxx_timer6_hwmod = { static struct omap_hwmod omap3xxx_timer6_hwmod = {
.name = "timer6", .name = "timer6",
.mpu_irqs = omap2_timer6_mpu_irqs,
.main_clk = "gpt6_fck", .main_clk = "gpt6_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -308,7 +291,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { ...@@ -308,7 +291,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
/* timer7 */ /* timer7 */
static struct omap_hwmod omap3xxx_timer7_hwmod = { static struct omap_hwmod omap3xxx_timer7_hwmod = {
.name = "timer7", .name = "timer7",
.mpu_irqs = omap2_timer7_mpu_irqs,
.main_clk = "gpt7_fck", .main_clk = "gpt7_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -327,7 +309,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { ...@@ -327,7 +309,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
/* timer8 */ /* timer8 */
static struct omap_hwmod omap3xxx_timer8_hwmod = { static struct omap_hwmod omap3xxx_timer8_hwmod = {
.name = "timer8", .name = "timer8",
.mpu_irqs = omap2_timer8_mpu_irqs,
.main_clk = "gpt8_fck", .main_clk = "gpt8_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -346,7 +327,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = { ...@@ -346,7 +327,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
/* timer9 */ /* timer9 */
static struct omap_hwmod omap3xxx_timer9_hwmod = { static struct omap_hwmod omap3xxx_timer9_hwmod = {
.name = "timer9", .name = "timer9",
.mpu_irqs = omap2_timer9_mpu_irqs,
.main_clk = "gpt9_fck", .main_clk = "gpt9_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -365,7 +345,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = { ...@@ -365,7 +345,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
/* timer10 */ /* timer10 */
static struct omap_hwmod omap3xxx_timer10_hwmod = { static struct omap_hwmod omap3xxx_timer10_hwmod = {
.name = "timer10", .name = "timer10",
.mpu_irqs = omap2_timer10_mpu_irqs,
.main_clk = "gpt10_fck", .main_clk = "gpt10_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -384,7 +363,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = { ...@@ -384,7 +363,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
/* timer11 */ /* timer11 */
static struct omap_hwmod omap3xxx_timer11_hwmod = { static struct omap_hwmod omap3xxx_timer11_hwmod = {
.name = "timer11", .name = "timer11",
.mpu_irqs = omap2_timer11_mpu_irqs,
.main_clk = "gpt11_fck", .main_clk = "gpt11_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -401,14 +379,9 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { ...@@ -401,14 +379,9 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
}; };
/* timer12 */ /* timer12 */
static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
{ .irq = 95 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap3xxx_timer12_hwmod = { static struct omap_hwmod omap3xxx_timer12_hwmod = {
.name = "timer12", .name = "timer12",
.mpu_irqs = omap3xxx_timer12_mpu_irqs,
.main_clk = "gpt12_fck", .main_clk = "gpt12_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -485,8 +458,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { ...@@ -485,8 +458,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
/* UART1 */ /* UART1 */
static struct omap_hwmod omap3xxx_uart1_hwmod = { static struct omap_hwmod omap3xxx_uart1_hwmod = {
.name = "uart1", .name = "uart1",
.mpu_irqs = omap2_uart1_mpu_irqs,
.sdma_reqs = omap2_uart1_sdma_reqs,
.main_clk = "uart1_fck", .main_clk = "uart1_fck",
.flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE, .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
.prcm = { .prcm = {
...@@ -504,8 +475,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = { ...@@ -504,8 +475,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
/* UART2 */ /* UART2 */
static struct omap_hwmod omap3xxx_uart2_hwmod = { static struct omap_hwmod omap3xxx_uart2_hwmod = {
.name = "uart2", .name = "uart2",
.mpu_irqs = omap2_uart2_mpu_irqs,
.sdma_reqs = omap2_uart2_sdma_reqs,
.main_clk = "uart2_fck", .main_clk = "uart2_fck",
.flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE, .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
.prcm = { .prcm = {
...@@ -523,8 +492,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = { ...@@ -523,8 +492,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
/* UART3 */ /* UART3 */
static struct omap_hwmod omap3xxx_uart3_hwmod = { static struct omap_hwmod omap3xxx_uart3_hwmod = {
.name = "uart3", .name = "uart3",
.mpu_irqs = omap2_uart3_mpu_irqs,
.sdma_reqs = omap2_uart3_sdma_reqs,
.main_clk = "uart3_fck", .main_clk = "uart3_fck",
.flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
HWMOD_SWSUP_SIDLE, HWMOD_SWSUP_SIDLE,
...@@ -541,21 +508,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { ...@@ -541,21 +508,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
}; };
/* UART4 */ /* UART4 */
static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
{ .irq = 80 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
{ .name = "rx", .dma_req = 82, },
{ .name = "tx", .dma_req = 81, },
{ .dma_req = -1 }
};
static struct omap_hwmod omap36xx_uart4_hwmod = { static struct omap_hwmod omap36xx_uart4_hwmod = {
.name = "uart4", .name = "uart4",
.mpu_irqs = uart4_mpu_irqs,
.sdma_reqs = uart4_sdma_reqs,
.main_clk = "uart4_fck", .main_clk = "uart4_fck",
.flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE, .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
.prcm = { .prcm = {
...@@ -570,16 +526,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { ...@@ -570,16 +526,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
.class = &omap2_uart_class, .class = &omap2_uart_class,
}; };
static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
{ .irq = 84 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
{ .name = "rx", .dma_req = 55, },
{ .name = "tx", .dma_req = 54, },
{ .dma_req = -1 }
};
/* /*
* XXX AM35xx UART4 cannot complete its softreset without uart1_fck or * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
...@@ -597,8 +544,6 @@ static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { ...@@ -597,8 +544,6 @@ static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
static struct omap_hwmod am35xx_uart4_hwmod = { static struct omap_hwmod am35xx_uart4_hwmod = {
.name = "uart4", .name = "uart4",
.mpu_irqs = am35xx_uart4_mpu_irqs,
.sdma_reqs = am35xx_uart4_sdma_reqs,
.main_clk = "uart4_fck", .main_clk = "uart4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -625,7 +570,7 @@ static struct omap_hwmod_class i2c_class = { ...@@ -625,7 +570,7 @@ static struct omap_hwmod_class i2c_class = {
static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 }, { .name = "dispc", .dma_req = 5 },
{ .name = "dsi1", .dma_req = 74 }, { .name = "dsi1", .dma_req = 74 },
{ .dma_req = -1 } { .dma_req = -1, },
}; };
/* dss */ /* dss */
...@@ -714,7 +659,7 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { ...@@ -714,7 +659,7 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
}, },
}, },
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
.dev_attr = &omap2_3_dss_dispc_dev_attr .dev_attr = &omap2_3_dss_dispc_dev_attr,
}; };
/* /*
...@@ -738,11 +683,6 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { ...@@ -738,11 +683,6 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
.sysc = &omap3xxx_dsi_sysc, .sysc = &omap3xxx_dsi_sysc,
}; };
static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
{ .irq = 25 + OMAP_INTC_START, },
{ .irq = -1 },
};
/* dss_dsi1 */ /* dss_dsi1 */
static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss2_alwon_fck" }, { .role = "sys_clk", .clk = "dss2_alwon_fck" },
...@@ -751,7 +691,6 @@ static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { ...@@ -751,7 +691,6 @@ static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
.name = "dss_dsi1", .name = "dss_dsi1",
.class = &omap3xxx_dsi_hwmod_class, .class = &omap3xxx_dsi_hwmod_class,
.mpu_irqs = omap3xxx_dsi1_irqs,
.main_clk = "dss1_alwon_fck", .main_clk = "dss1_alwon_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -815,8 +754,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = { ...@@ -815,8 +754,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
static struct omap_hwmod omap3xxx_i2c1_hwmod = { static struct omap_hwmod omap3xxx_i2c1_hwmod = {
.name = "i2c1", .name = "i2c1",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap2_i2c1_mpu_irqs,
.sdma_reqs = omap2_i2c1_sdma_reqs,
.main_clk = "i2c1_fck", .main_clk = "i2c1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -840,8 +777,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = { ...@@ -840,8 +777,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
static struct omap_hwmod omap3xxx_i2c2_hwmod = { static struct omap_hwmod omap3xxx_i2c2_hwmod = {
.name = "i2c2", .name = "i2c2",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap2_i2c2_mpu_irqs,
.sdma_reqs = omap2_i2c2_sdma_reqs,
.main_clk = "i2c2_fck", .main_clk = "i2c2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -862,22 +797,11 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = { ...@@ -862,22 +797,11 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
.flags = OMAP_I2C_FLAG_BUS_SHIFT_2, .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
}; };
static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
{ .irq = 61 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 25 },
{ .name = "rx", .dma_req = 26 },
{ .dma_req = -1 }
};
static struct omap_hwmod omap3xxx_i2c3_hwmod = { static struct omap_hwmod omap3xxx_i2c3_hwmod = {
.name = "i2c3", .name = "i2c3",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = i2c3_mpu_irqs,
.sdma_reqs = i2c3_sdma_reqs,
.main_clk = "i2c3_fck", .main_clk = "i2c3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -928,7 +852,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { ...@@ -928,7 +852,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
static struct omap_hwmod omap3xxx_gpio1_hwmod = { static struct omap_hwmod omap3xxx_gpio1_hwmod = {
.name = "gpio1", .name = "gpio1",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2_gpio1_irqs,
.main_clk = "gpio1_ick", .main_clk = "gpio1_ick",
.opt_clks = gpio1_opt_clks, .opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
...@@ -953,7 +876,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { ...@@ -953,7 +876,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
static struct omap_hwmod omap3xxx_gpio2_hwmod = { static struct omap_hwmod omap3xxx_gpio2_hwmod = {
.name = "gpio2", .name = "gpio2",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2_gpio2_irqs,
.main_clk = "gpio2_ick", .main_clk = "gpio2_ick",
.opt_clks = gpio2_opt_clks, .opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
...@@ -978,7 +900,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { ...@@ -978,7 +900,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
static struct omap_hwmod omap3xxx_gpio3_hwmod = { static struct omap_hwmod omap3xxx_gpio3_hwmod = {
.name = "gpio3", .name = "gpio3",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2_gpio3_irqs,
.main_clk = "gpio3_ick", .main_clk = "gpio3_ick",
.opt_clks = gpio3_opt_clks, .opt_clks = gpio3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
...@@ -1003,7 +924,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { ...@@ -1003,7 +924,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
static struct omap_hwmod omap3xxx_gpio4_hwmod = { static struct omap_hwmod omap3xxx_gpio4_hwmod = {
.name = "gpio4", .name = "gpio4",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2_gpio4_irqs,
.main_clk = "gpio4_ick", .main_clk = "gpio4_ick",
.opt_clks = gpio4_opt_clks, .opt_clks = gpio4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
...@@ -1021,10 +941,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = { ...@@ -1021,10 +941,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
}; };
/* gpio5 */ /* gpio5 */
static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
{ .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
{ .irq = -1 },
};
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio5_dbck", }, { .role = "dbclk", .clk = "gpio5_dbck", },
...@@ -1033,7 +949,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { ...@@ -1033,7 +949,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
static struct omap_hwmod omap3xxx_gpio5_hwmod = { static struct omap_hwmod omap3xxx_gpio5_hwmod = {
.name = "gpio5", .name = "gpio5",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio5_irqs,
.main_clk = "gpio5_ick", .main_clk = "gpio5_ick",
.opt_clks = gpio5_opt_clks, .opt_clks = gpio5_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
...@@ -1051,10 +966,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { ...@@ -1051,10 +966,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
}; };
/* gpio6 */ /* gpio6 */
static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
{ .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
{ .irq = -1 },
};
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio6_dbck", }, { .role = "dbclk", .clk = "gpio6_dbck", },
...@@ -1063,7 +974,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { ...@@ -1063,7 +974,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
static struct omap_hwmod omap3xxx_gpio6_hwmod = { static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.name = "gpio6", .name = "gpio6",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio6_irqs,
.main_clk = "gpio6_ick", .main_clk = "gpio6_ick",
.opt_clks = gpio6_opt_clks, .opt_clks = gpio6_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
...@@ -1156,18 +1066,10 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { ...@@ -1156,18 +1066,10 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
}; };
/* mcbsp1 */ /* mcbsp1 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
{ .name = "common", .irq = 16 + OMAP_INTC_START, },
{ .name = "tx", .irq = 59 + OMAP_INTC_START, },
{ .name = "rx", .irq = 60 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
.name = "mcbsp1", .name = "mcbsp1",
.class = &omap3xxx_mcbsp_hwmod_class, .class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp1_irqs,
.sdma_reqs = omap2_mcbsp1_sdma_reqs,
.main_clk = "mcbsp1_fck", .main_clk = "mcbsp1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1183,12 +1085,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { ...@@ -1183,12 +1085,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
}; };
/* mcbsp2 */ /* mcbsp2 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
{ .name = "common", .irq = 17 + OMAP_INTC_START, },
{ .name = "tx", .irq = 62 + OMAP_INTC_START, },
{ .name = "rx", .irq = 63 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
.sidetone = "mcbsp2_sidetone", .sidetone = "mcbsp2_sidetone",
...@@ -1197,8 +1093,6 @@ static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { ...@@ -1197,8 +1093,6 @@ static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
.name = "mcbsp2", .name = "mcbsp2",
.class = &omap3xxx_mcbsp_hwmod_class, .class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp2_irqs,
.sdma_reqs = omap2_mcbsp2_sdma_reqs,
.main_clk = "mcbsp2_fck", .main_clk = "mcbsp2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1215,12 +1109,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { ...@@ -1215,12 +1109,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
}; };
/* mcbsp3 */ /* mcbsp3 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
{ .name = "common", .irq = 22 + OMAP_INTC_START, },
{ .name = "tx", .irq = 89 + OMAP_INTC_START, },
{ .name = "rx", .irq = 90 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
.sidetone = "mcbsp3_sidetone", .sidetone = "mcbsp3_sidetone",
...@@ -1229,8 +1117,6 @@ static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { ...@@ -1229,8 +1117,6 @@ static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
.name = "mcbsp3", .name = "mcbsp3",
.class = &omap3xxx_mcbsp_hwmod_class, .class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp3_irqs,
.sdma_reqs = omap2_mcbsp3_sdma_reqs,
.main_clk = "mcbsp3_fck", .main_clk = "mcbsp3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1247,24 +1133,11 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { ...@@ -1247,24 +1133,11 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
}; };
/* mcbsp4 */ /* mcbsp4 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
{ .name = "common", .irq = 23 + OMAP_INTC_START, },
{ .name = "tx", .irq = 54 + OMAP_INTC_START, },
{ .name = "rx", .irq = 55 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
{ .name = "rx", .dma_req = 20 },
{ .name = "tx", .dma_req = 19 },
{ .dma_req = -1 }
};
static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
.name = "mcbsp4", .name = "mcbsp4",
.class = &omap3xxx_mcbsp_hwmod_class, .class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp4_irqs,
.sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
.main_clk = "mcbsp4_fck", .main_clk = "mcbsp4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1280,24 +1153,11 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { ...@@ -1280,24 +1153,11 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
}; };
/* mcbsp5 */ /* mcbsp5 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
{ .name = "common", .irq = 27 + OMAP_INTC_START, },
{ .name = "tx", .irq = 81 + OMAP_INTC_START, },
{ .name = "rx", .irq = 82 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
{ .name = "rx", .dma_req = 22 },
{ .name = "tx", .dma_req = 21 },
{ .dma_req = -1 }
};
static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
.name = "mcbsp5", .name = "mcbsp5",
.class = &omap3xxx_mcbsp_hwmod_class, .class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp5_irqs,
.sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
.main_clk = "mcbsp5_fck", .main_clk = "mcbsp5_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1325,29 +1185,19 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { ...@@ -1325,29 +1185,19 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
}; };
/* mcbsp2_sidetone */ /* mcbsp2_sidetone */
static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
{ .name = "irq", .irq = 4 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
.name = "mcbsp2_sidetone", .name = "mcbsp2_sidetone",
.class = &omap3xxx_mcbsp_sidetone_hwmod_class, .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
.main_clk = "mcbsp2_ick", .main_clk = "mcbsp2_ick",
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
/* mcbsp3_sidetone */ /* mcbsp3_sidetone */
static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
{ .name = "irq", .irq = 5 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
.name = "mcbsp3_sidetone", .name = "mcbsp3_sidetone",
.class = &omap3xxx_mcbsp_sidetone_hwmod_class, .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
.main_clk = "mcbsp3_ick", .main_clk = "mcbsp3_ick",
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
}; };
...@@ -1394,10 +1244,6 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = { ...@@ -1394,10 +1244,6 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
.sensor_voltdm_name = "mpu_iva", .sensor_voltdm_name = "mpu_iva",
}; };
static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
{ .irq = 18 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap34xx_sr1_hwmod = { static struct omap_hwmod omap34xx_sr1_hwmod = {
.name = "smartreflex_mpu_iva", .name = "smartreflex_mpu_iva",
...@@ -1413,7 +1259,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = { ...@@ -1413,7 +1259,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
}, },
}, },
.dev_attr = &sr1_dev_attr, .dev_attr = &sr1_dev_attr,
.mpu_irqs = omap3_smartreflex_mpu_irqs,
.flags = HWMOD_SET_DEFAULT_CLOCKACT, .flags = HWMOD_SET_DEFAULT_CLOCKACT,
}; };
...@@ -1431,7 +1276,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = { ...@@ -1431,7 +1276,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
}, },
}, },
.dev_attr = &sr1_dev_attr, .dev_attr = &sr1_dev_attr,
.mpu_irqs = omap3_smartreflex_mpu_irqs,
}; };
/* SR2 */ /* SR2 */
...@@ -1439,10 +1283,6 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = { ...@@ -1439,10 +1283,6 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
.sensor_voltdm_name = "core", .sensor_voltdm_name = "core",
}; };
static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
{ .irq = 19 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap34xx_sr2_hwmod = { static struct omap_hwmod omap34xx_sr2_hwmod = {
.name = "smartreflex_core", .name = "smartreflex_core",
...@@ -1458,7 +1298,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = { ...@@ -1458,7 +1298,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
}, },
}, },
.dev_attr = &sr2_dev_attr, .dev_attr = &sr2_dev_attr,
.mpu_irqs = omap3_smartreflex_core_irqs,
.flags = HWMOD_SET_DEFAULT_CLOCKACT, .flags = HWMOD_SET_DEFAULT_CLOCKACT,
}; };
...@@ -1476,7 +1315,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = { ...@@ -1476,7 +1315,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
}, },
}, },
.dev_attr = &sr2_dev_attr, .dev_attr = &sr2_dev_attr,
.mpu_irqs = omap3_smartreflex_core_irqs,
}; };
/* /*
...@@ -1545,8 +1383,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { ...@@ -1545,8 +1383,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
static struct omap_hwmod omap34xx_mcspi1 = { static struct omap_hwmod omap34xx_mcspi1 = {
.name = "mcspi1", .name = "mcspi1",
.mpu_irqs = omap2_mcspi1_mpu_irqs,
.sdma_reqs = omap2_mcspi1_sdma_reqs,
.main_clk = "mcspi1_fck", .main_clk = "mcspi1_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1568,8 +1404,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { ...@@ -1568,8 +1404,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
static struct omap_hwmod omap34xx_mcspi2 = { static struct omap_hwmod omap34xx_mcspi2 = {
.name = "mcspi2", .name = "mcspi2",
.mpu_irqs = omap2_mcspi2_mpu_irqs,
.sdma_reqs = omap2_mcspi2_sdma_reqs,
.main_clk = "mcspi2_fck", .main_clk = "mcspi2_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1585,18 +1419,7 @@ static struct omap_hwmod omap34xx_mcspi2 = { ...@@ -1585,18 +1419,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
}; };
/* mcspi3 */ /* mcspi3 */
static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
{ .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
{ .irq = -1 },
};
static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 15 },
{ .name = "rx0", .dma_req = 16 },
{ .name = "tx1", .dma_req = 23 },
{ .name = "rx1", .dma_req = 24 },
{ .dma_req = -1 }
};
static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
.num_chipselect = 2, .num_chipselect = 2,
...@@ -1604,8 +1427,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { ...@@ -1604,8 +1427,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
static struct omap_hwmod omap34xx_mcspi3 = { static struct omap_hwmod omap34xx_mcspi3 = {
.name = "mcspi3", .name = "mcspi3",
.mpu_irqs = omap34xx_mcspi3_mpu_irqs,
.sdma_reqs = omap34xx_mcspi3_sdma_reqs,
.main_clk = "mcspi3_fck", .main_clk = "mcspi3_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1621,16 +1442,7 @@ static struct omap_hwmod omap34xx_mcspi3 = { ...@@ -1621,16 +1442,7 @@ static struct omap_hwmod omap34xx_mcspi3 = {
}; };
/* mcspi4 */ /* mcspi4 */
static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
{ .name = "irq", .irq = 48 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
{ .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
{ .dma_req = -1 }
};
static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
.num_chipselect = 1, .num_chipselect = 1,
...@@ -1638,8 +1450,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { ...@@ -1638,8 +1450,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
static struct omap_hwmod omap34xx_mcspi4 = { static struct omap_hwmod omap34xx_mcspi4 = {
.name = "mcspi4", .name = "mcspi4",
.mpu_irqs = omap34xx_mcspi4_mpu_irqs,
.sdma_reqs = omap34xx_mcspi4_sdma_reqs,
.main_clk = "mcspi4_fck", .main_clk = "mcspi4_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1673,16 +1483,9 @@ static struct omap_hwmod_class usbotg_class = { ...@@ -1673,16 +1483,9 @@ static struct omap_hwmod_class usbotg_class = {
}; };
/* usb_otg_hs */ /* usb_otg_hs */
static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
{ .name = "mc", .irq = 92 + OMAP_INTC_START, },
{ .name = "dma", .irq = 93 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
.name = "usb_otg_hs", .name = "usb_otg_hs",
.mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
.main_clk = "hsotgusb_ick", .main_clk = "hsotgusb_ick",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -1691,7 +1494,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { ...@@ -1691,7 +1494,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
.module_offs = CORE_MOD, .module_offs = CORE_MOD,
.idlest_reg_id = 1, .idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
.idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT,
}, },
}, },
.class = &usbotg_class, .class = &usbotg_class,
...@@ -1711,10 +1514,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { ...@@ -1711,10 +1514,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
}; };
/* usb_otg_hs */ /* usb_otg_hs */
static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
{ .name = "mc", .irq = 71 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_class am35xx_usbotg_class = { static struct omap_hwmod_class am35xx_usbotg_class = {
.name = "am35xx_usbotg", .name = "am35xx_usbotg",
...@@ -1722,7 +1521,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = { ...@@ -1722,7 +1521,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
static struct omap_hwmod am35xx_usbhsotg_hwmod = { static struct omap_hwmod am35xx_usbhsotg_hwmod = {
.name = "am35x_otg_hs", .name = "am35x_otg_hs",
.mpu_irqs = am35xx_usbhsotg_mpu_irqs,
.main_clk = "hsotgusb_fck", .main_clk = "hsotgusb_fck",
.class = &am35xx_usbotg_class, .class = &am35xx_usbotg_class,
.flags = HWMOD_NO_IDLEST, .flags = HWMOD_NO_IDLEST,
...@@ -1747,16 +1545,7 @@ static struct omap_hwmod_class omap34xx_mmc_class = { ...@@ -1747,16 +1545,7 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
/* MMC/SD/SDIO1 */ /* MMC/SD/SDIO1 */
static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
{ .irq = 83 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 61, },
{ .name = "rx", .dma_req = 62, },
{ .dma_req = -1 }
};
static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
{ .role = "dbck", .clk = "omap_32k_fck", }, { .role = "dbck", .clk = "omap_32k_fck", },
...@@ -1774,8 +1563,6 @@ static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = { ...@@ -1774,8 +1563,6 @@ static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
.name = "mmc1", .name = "mmc1",
.mpu_irqs = omap34xx_mmc1_mpu_irqs,
.sdma_reqs = omap34xx_mmc1_sdma_reqs,
.opt_clks = omap34xx_mmc1_opt_clks, .opt_clks = omap34xx_mmc1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
.main_clk = "mmchs1_fck", .main_clk = "mmchs1_fck",
...@@ -1794,8 +1581,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { ...@@ -1794,8 +1581,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
.name = "mmc1", .name = "mmc1",
.mpu_irqs = omap34xx_mmc1_mpu_irqs,
.sdma_reqs = omap34xx_mmc1_sdma_reqs,
.opt_clks = omap34xx_mmc1_opt_clks, .opt_clks = omap34xx_mmc1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
.main_clk = "mmchs1_fck", .main_clk = "mmchs1_fck",
...@@ -1814,16 +1599,7 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { ...@@ -1814,16 +1599,7 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
/* MMC/SD/SDIO2 */ /* MMC/SD/SDIO2 */
static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
{ .irq = 86 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 47, },
{ .name = "rx", .dma_req = 48, },
{ .dma_req = -1 }
};
static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
{ .role = "dbck", .clk = "omap_32k_fck", }, { .role = "dbck", .clk = "omap_32k_fck", },
...@@ -1836,8 +1612,6 @@ static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = { ...@@ -1836,8 +1612,6 @@ static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
.name = "mmc2", .name = "mmc2",
.mpu_irqs = omap34xx_mmc2_mpu_irqs,
.sdma_reqs = omap34xx_mmc2_sdma_reqs,
.opt_clks = omap34xx_mmc2_opt_clks, .opt_clks = omap34xx_mmc2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
.main_clk = "mmchs2_fck", .main_clk = "mmchs2_fck",
...@@ -1856,8 +1630,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { ...@@ -1856,8 +1630,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
.name = "mmc2", .name = "mmc2",
.mpu_irqs = omap34xx_mmc2_mpu_irqs,
.sdma_reqs = omap34xx_mmc2_sdma_reqs,
.opt_clks = omap34xx_mmc2_opt_clks, .opt_clks = omap34xx_mmc2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
.main_clk = "mmchs2_fck", .main_clk = "mmchs2_fck",
...@@ -1875,16 +1647,7 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { ...@@ -1875,16 +1647,7 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
/* MMC/SD/SDIO3 */ /* MMC/SD/SDIO3 */
static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
{ .irq = 94 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 77, },
{ .name = "rx", .dma_req = 78, },
{ .dma_req = -1 }
};
static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
{ .role = "dbck", .clk = "omap_32k_fck", }, { .role = "dbck", .clk = "omap_32k_fck", },
...@@ -1892,8 +1655,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { ...@@ -1892,8 +1655,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
static struct omap_hwmod omap3xxx_mmc3_hwmod = { static struct omap_hwmod omap3xxx_mmc3_hwmod = {
.name = "mmc3", .name = "mmc3",
.mpu_irqs = omap34xx_mmc3_mpu_irqs,
.sdma_reqs = omap34xx_mmc3_sdma_reqs,
.opt_clks = omap34xx_mmc3_opt_clks, .opt_clks = omap34xx_mmc3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
.main_clk = "mmchs3_fck", .main_clk = "mmchs3_fck",
...@@ -1931,17 +1692,11 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { ...@@ -1931,17 +1692,11 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
.sysc = &omap3xxx_usb_host_hs_sysc, .sysc = &omap3xxx_usb_host_hs_sysc,
}; };
static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
{ .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
{ .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
.name = "usb_host_hs", .name = "usb_host_hs",
.class = &omap3xxx_usb_host_hs_hwmod_class, .class = &omap3xxx_usb_host_hs_hwmod_class,
.clkdm_name = "usbhost_clkdm", .clkdm_name = "usbhost_clkdm",
.mpu_irqs = omap3xxx_usb_host_hs_irqs,
.main_clk = "usbhost_48m_fck", .main_clk = "usbhost_48m_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2015,16 +1770,11 @@ static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { ...@@ -2015,16 +1770,11 @@ static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
.sysc = &omap3xxx_usb_tll_hs_sysc, .sysc = &omap3xxx_usb_tll_hs_sysc,
}; };
static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
{ .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
.name = "usb_tll_hs", .name = "usb_tll_hs",
.class = &omap3xxx_usb_tll_hs_hwmod_class, .class = &omap3xxx_usb_tll_hs_hwmod_class,
.clkdm_name = "core_l4_clkdm", .clkdm_name = "core_l4_clkdm",
.mpu_irqs = omap3xxx_usb_tll_hs_irqs,
.main_clk = "usbtll_fck", .main_clk = "usbtll_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2039,7 +1789,6 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { ...@@ -2039,7 +1789,6 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
static struct omap_hwmod omap3xxx_hdq1w_hwmod = { static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
.name = "hdq1w", .name = "hdq1w",
.mpu_irqs = omap2_hdq1w_mpu_irqs,
.main_clk = "hdq_fck", .main_clk = "hdq_fck",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -2134,16 +1883,10 @@ static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { ...@@ -2134,16 +1883,10 @@ static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
.sysc = &omap3xxx_gpmc_sysc, .sysc = &omap3xxx_gpmc_sysc,
}; };
static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
{ .irq = 20 + OMAP_INTC_START, },
{ .irq = -1 }
};
static struct omap_hwmod omap3xxx_gpmc_hwmod = { static struct omap_hwmod omap3xxx_gpmc_hwmod = {
.name = "gpmc", .name = "gpmc",
.class = &omap3xxx_gpmc_hwmod_class, .class = &omap3xxx_gpmc_hwmod_class,
.clkdm_name = "core_l3_clkdm", .clkdm_name = "core_l3_clkdm",
.mpu_irqs = omap3xxx_gpmc_irqs,
.main_clk = "gpmc_fck", .main_clk = "gpmc_fck",
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
.flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
...@@ -2167,37 +1910,19 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { ...@@ -2167,37 +1910,19 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
{
.pa_start = 0x68000000,
.pa_end = 0x6800ffff,
.flags = ADDR_TYPE_RT,
},
{ }
};
/* MPU -> L3 interface */ /* MPU -> L3 interface */
static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
.master = &omap3xxx_mpu_hwmod, .master = &omap3xxx_mpu_hwmod,
.slave = &omap3xxx_l3_main_hwmod, .slave = &omap3xxx_l3_main_hwmod,
.addr = omap3xxx_l3_main_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
{
.pa_start = 0x54000000,
.pa_end = 0x547fffff,
.flags = ADDR_TYPE_RT,
},
{ }
};
/* l3 -> debugss */ /* l3 -> debugss */
static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
.master = &omap3xxx_l3_main_hwmod, .master = &omap3xxx_l3_main_hwmod,
.slave = &omap3xxx_debugss_hwmod, .slave = &omap3xxx_debugss_hwmod,
.addr = omap3xxx_l4_emu_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2215,7 +1940,7 @@ static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { ...@@ -2215,7 +1940,7 @@ static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
.omap2 = { .omap2 = {
.l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
.flags = OMAP_FIREWALL_L3, .flags = OMAP_FIREWALL_L3,
} },
}, },
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2256,18 +1981,16 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { ...@@ -2256,18 +1981,16 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_pre_es3_mmc1_hwmod, .slave = &omap3xxx_pre_es3_mmc1_hwmod,
.clk = "mmchs1_ick", .clk = "mmchs1_ick",
.addr = omap2430_mmc1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4 .flags = OMAP_FIREWALL_L4,
}; };
static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_es3plus_mmc1_hwmod, .slave = &omap3xxx_es3plus_mmc1_hwmod,
.clk = "mmchs1_ick", .clk = "mmchs1_ick",
.addr = omap2430_mmc1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4 .flags = OMAP_FIREWALL_L4,
}; };
/* L4 CORE -> MMC2 interface */ /* L4 CORE -> MMC2 interface */
...@@ -2275,126 +1998,70 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { ...@@ -2275,126 +1998,70 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_pre_es3_mmc2_hwmod, .slave = &omap3xxx_pre_es3_mmc2_hwmod,
.clk = "mmchs2_ick", .clk = "mmchs2_ick",
.addr = omap2430_mmc2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4 .flags = OMAP_FIREWALL_L4,
}; };
static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_es3plus_mmc2_hwmod, .slave = &omap3xxx_es3plus_mmc2_hwmod,
.clk = "mmchs2_ick", .clk = "mmchs2_ick",
.addr = omap2430_mmc2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4 .flags = OMAP_FIREWALL_L4,
}; };
/* L4 CORE -> MMC3 interface */ /* L4 CORE -> MMC3 interface */
static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
{
.pa_start = 0x480ad000,
.pa_end = 0x480ad1ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mmc3_hwmod, .slave = &omap3xxx_mmc3_hwmod,
.clk = "mmchs3_ick", .clk = "mmchs3_ick",
.addr = omap3xxx_mmc3_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4 .flags = OMAP_FIREWALL_L4,
}; };
/* L4 CORE -> UART1 interface */ /* L4 CORE -> UART1 interface */
static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
{
.pa_start = OMAP3_UART1_BASE,
.pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_uart1_hwmod, .slave = &omap3xxx_uart1_hwmod,
.clk = "uart1_ick", .clk = "uart1_ick",
.addr = omap3xxx_uart1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 CORE -> UART2 interface */ /* L4 CORE -> UART2 interface */
static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
{
.pa_start = OMAP3_UART2_BASE,
.pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_uart2_hwmod, .slave = &omap3xxx_uart2_hwmod,
.clk = "uart2_ick", .clk = "uart2_ick",
.addr = omap3xxx_uart2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 PER -> UART3 interface */ /* L4 PER -> UART3 interface */
static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
{
.pa_start = OMAP3_UART3_BASE,
.pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_uart3_hwmod, .slave = &omap3xxx_uart3_hwmod,
.clk = "uart3_ick", .clk = "uart3_ick",
.addr = omap3xxx_uart3_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 PER -> UART4 interface */ /* L4 PER -> UART4 interface */
static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
{
.pa_start = OMAP3_UART4_BASE,
.pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap36xx_uart4_hwmod, .slave = &omap36xx_uart4_hwmod,
.clk = "uart4_ick", .clk = "uart4_ick",
.addr = omap36xx_uart4_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* AM35xx: L4 CORE -> UART4 interface */ /* AM35xx: L4 CORE -> UART4 interface */
static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
{
.pa_start = OMAP3_UART4_AM35XX_BASE,
.pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &am35xx_uart4_hwmod, .slave = &am35xx_uart4_hwmod,
.clk = "uart4_ick", .clk = "uart4_ick",
.addr = am35xx_uart4_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2403,13 +2070,12 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { ...@@ -2403,13 +2070,12 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_i2c1_hwmod, .slave = &omap3xxx_i2c1_hwmod,
.clk = "i2c1_ick", .clk = "i2c1_ick",
.addr = omap2_i2c1_addr_space,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
.l4_prot_group = 7, .l4_prot_group = 7,
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
} },
}, },
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2419,57 +2085,38 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { ...@@ -2419,57 +2085,38 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_i2c2_hwmod, .slave = &omap3xxx_i2c2_hwmod,
.clk = "i2c2_ick", .clk = "i2c2_ick",
.addr = omap2_i2c2_addr_space,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
.l4_prot_group = 7, .l4_prot_group = 7,
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
} },
}, },
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 CORE -> I2C3 interface */ /* L4 CORE -> I2C3 interface */
static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
{
.pa_start = 0x48060000,
.pa_end = 0x48060000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_i2c3_hwmod, .slave = &omap3xxx_i2c3_hwmod,
.clk = "i2c3_ick", .clk = "i2c3_ick",
.addr = omap3xxx_i2c3_addr_space,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
.l4_prot_group = 7, .l4_prot_group = 7,
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
} },
}, },
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* L4 CORE -> SR1 interface */ /* L4 CORE -> SR1 interface */
static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
{
.pa_start = OMAP34XX_SR1_BASE,
.pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_sr1_hwmod, .slave = &omap34xx_sr1_hwmod,
.clk = "sr_l4_ick", .clk = "sr_l4_ick",
.addr = omap3_sr1_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2477,25 +2124,15 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { ...@@ -2477,25 +2124,15 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap36xx_sr1_hwmod, .slave = &omap36xx_sr1_hwmod,
.clk = "sr_l4_ick", .clk = "sr_l4_ick",
.addr = omap3_sr1_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* L4 CORE -> SR1 interface */ /* L4 CORE -> SR1 interface */
static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
{
.pa_start = OMAP34XX_SR2_BASE,
.pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_sr2_hwmod, .slave = &omap34xx_sr2_hwmod,
.clk = "sr_l4_ick", .clk = "sr_l4_ick",
.addr = omap3_sr2_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2503,43 +2140,24 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { ...@@ -2503,43 +2140,24 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap36xx_sr2_hwmod, .slave = &omap36xx_sr2_hwmod,
.clk = "sr_l4_ick", .clk = "sr_l4_ick",
.addr = omap3_sr2_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
{
.pa_start = OMAP34XX_HSUSB_OTG_BASE,
.pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_core -> usbhsotg */ /* l4_core -> usbhsotg */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_usbhsotg_hwmod, .slave = &omap3xxx_usbhsotg_hwmod,
.clk = "l4_ick", .clk = "l4_ick",
.addr = omap3xxx_usbhsotg_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
{
.pa_start = AM35XX_IPSS_USBOTGSS_BASE,
.pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_core -> usbhsotg */ /* l4_core -> usbhsotg */
static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &am35xx_usbhsotg_hwmod, .slave = &am35xx_usbhsotg_hwmod,
.clk = "hsotgusb_ick", .clk = "hsotgusb_ick",
.addr = am35xx_usbhsotg_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -2558,165 +2176,84 @@ static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { ...@@ -2558,165 +2176,84 @@ static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
{
.pa_start = 0x48318000,
.pa_end = 0x48318000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_wkup -> timer1 */ /* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
.master = &omap3xxx_l4_wkup_hwmod, .master = &omap3xxx_l4_wkup_hwmod,
.slave = &omap3xxx_timer1_hwmod, .slave = &omap3xxx_timer1_hwmod,
.clk = "gpt1_ick", .clk = "gpt1_ick",
.addr = omap3xxx_timer1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
{
.pa_start = 0x49032000,
.pa_end = 0x49032000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer2 */ /* l4_per -> timer2 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_timer2_hwmod, .slave = &omap3xxx_timer2_hwmod,
.clk = "gpt2_ick", .clk = "gpt2_ick",
.addr = omap3xxx_timer2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
{
.pa_start = 0x49034000,
.pa_end = 0x49034000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer3 */ /* l4_per -> timer3 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_timer3_hwmod, .slave = &omap3xxx_timer3_hwmod,
.clk = "gpt3_ick", .clk = "gpt3_ick",
.addr = omap3xxx_timer3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
{
.pa_start = 0x49036000,
.pa_end = 0x49036000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer4 */ /* l4_per -> timer4 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_timer4_hwmod, .slave = &omap3xxx_timer4_hwmod,
.clk = "gpt4_ick", .clk = "gpt4_ick",
.addr = omap3xxx_timer4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
{
.pa_start = 0x49038000,
.pa_end = 0x49038000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer5 */ /* l4_per -> timer5 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_timer5_hwmod, .slave = &omap3xxx_timer5_hwmod,
.clk = "gpt5_ick", .clk = "gpt5_ick",
.addr = omap3xxx_timer5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
{
.pa_start = 0x4903A000,
.pa_end = 0x4903A000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer6 */ /* l4_per -> timer6 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_timer6_hwmod, .slave = &omap3xxx_timer6_hwmod,
.clk = "gpt6_ick", .clk = "gpt6_ick",
.addr = omap3xxx_timer6_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
{
.pa_start = 0x4903C000,
.pa_end = 0x4903C000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer7 */ /* l4_per -> timer7 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_timer7_hwmod, .slave = &omap3xxx_timer7_hwmod,
.clk = "gpt7_ick", .clk = "gpt7_ick",
.addr = omap3xxx_timer7_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
{
.pa_start = 0x4903E000,
.pa_end = 0x4903E000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer8 */ /* l4_per -> timer8 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_timer8_hwmod, .slave = &omap3xxx_timer8_hwmod,
.clk = "gpt8_ick", .clk = "gpt8_ick",
.addr = omap3xxx_timer8_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
{
.pa_start = 0x49040000,
.pa_end = 0x49040000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer9 */ /* l4_per -> timer9 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_timer9_hwmod, .slave = &omap3xxx_timer9_hwmod,
.clk = "gpt9_ick", .clk = "gpt9_ick",
.addr = omap3xxx_timer9_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2725,7 +2262,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { ...@@ -2725,7 +2262,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_timer10_hwmod, .slave = &omap3xxx_timer10_hwmod,
.clk = "gpt10_ick", .clk = "gpt10_ick",
.addr = omap2_timer10_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2734,43 +2270,24 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { ...@@ -2734,43 +2270,24 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_timer11_hwmod, .slave = &omap3xxx_timer11_hwmod,
.clk = "gpt11_ick", .clk = "gpt11_ick",
.addr = omap2_timer11_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
{
.pa_start = 0x48304000,
.pa_end = 0x48304000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_core -> timer12 */ /* l4_core -> timer12 */
static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
.master = &omap3xxx_l4_sec_hwmod, .master = &omap3xxx_l4_sec_hwmod,
.slave = &omap3xxx_timer12_hwmod, .slave = &omap3xxx_timer12_hwmod,
.clk = "gpt12_ick", .clk = "gpt12_ick",
.addr = omap3xxx_timer12_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4_wkup -> wd_timer2 */ /* l4_wkup -> wd_timer2 */
static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
{
.pa_start = 0x48314000,
.pa_end = 0x4831407f,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
.master = &omap3xxx_l4_wkup_hwmod, .master = &omap3xxx_l4_wkup_hwmod,
.slave = &omap3xxx_wd_timer2_hwmod, .slave = &omap3xxx_wd_timer2_hwmod,
.clk = "wdt2_ick", .clk = "wdt2_ick",
.addr = omap3xxx_wd_timer2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2779,13 +2296,12 @@ static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { ...@@ -2779,13 +2296,12 @@ static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3430es1_dss_core_hwmod, .slave = &omap3430es1_dss_core_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2_dss_addrs,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
} },
}, },
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2794,13 +2310,12 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { ...@@ -2794,13 +2310,12 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_core_hwmod, .slave = &omap3xxx_dss_core_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2_dss_addrs,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
} },
}, },
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2810,24 +2325,14 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { ...@@ -2810,24 +2325,14 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_dispc_hwmod, .slave = &omap3xxx_dss_dispc_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2_dss_dispc_addrs,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
}
}, },
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
{
.pa_start = 0x4804FC00,
.pa_end = 0x4804FFFF,
.flags = ADDR_TYPE_RT
}, },
{ } .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4_core -> dss_dsi1 */ /* l4_core -> dss_dsi1 */
...@@ -2835,13 +2340,12 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { ...@@ -2835,13 +2340,12 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_dsi1_hwmod, .slave = &omap3xxx_dss_dsi1_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap3xxx_dss_dsi1_addrs,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
} },
}, },
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2851,13 +2355,12 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { ...@@ -2851,13 +2355,12 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_rfbi_hwmod, .slave = &omap3xxx_dss_rfbi_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2_dss_rfbi_addrs,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
} },
}, },
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -2867,66 +2370,38 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { ...@@ -2867,66 +2370,38 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_venc_hwmod, .slave = &omap3xxx_dss_venc_hwmod,
.clk = "dss_ick", .clk = "dss_ick",
.addr = omap2_dss_venc_addrs,
.fw = { .fw = {
.omap2 = { .omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
.flags = OMAP_FIREWALL_L4, .flags = OMAP_FIREWALL_L4,
} },
}, },
.flags = OCPIF_SWSUP_IDLE, .flags = OCPIF_SWSUP_IDLE,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4_wkup -> gpio1 */ /* l4_wkup -> gpio1 */
static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
{
.pa_start = 0x48310000,
.pa_end = 0x483101ff,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
.master = &omap3xxx_l4_wkup_hwmod, .master = &omap3xxx_l4_wkup_hwmod,
.slave = &omap3xxx_gpio1_hwmod, .slave = &omap3xxx_gpio1_hwmod,
.addr = omap3xxx_gpio1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4_per -> gpio2 */ /* l4_per -> gpio2 */
static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
{
.pa_start = 0x49050000,
.pa_end = 0x490501ff,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio2_hwmod, .slave = &omap3xxx_gpio2_hwmod,
.addr = omap3xxx_gpio2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4_per -> gpio3 */ /* l4_per -> gpio3 */
static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
{
.pa_start = 0x49052000,
.pa_end = 0x490521ff,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio3_hwmod, .slave = &omap3xxx_gpio3_hwmod,
.addr = omap3xxx_gpio3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3002,53 +2477,26 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { ...@@ -3002,53 +2477,26 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
}; };
/* l4_per -> gpio4 */ /* l4_per -> gpio4 */
static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
{
.pa_start = 0x49054000,
.pa_end = 0x490541ff,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio4_hwmod, .slave = &omap3xxx_gpio4_hwmod,
.addr = omap3xxx_gpio4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4_per -> gpio5 */ /* l4_per -> gpio5 */
static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
{
.pa_start = 0x49056000,
.pa_end = 0x490561ff,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio5_hwmod, .slave = &omap3xxx_gpio5_hwmod,
.addr = omap3xxx_gpio5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4_per -> gpio6 */ /* l4_per -> gpio6 */
static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
{
.pa_start = 0x49058000,
.pa_end = 0x490581ff,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio6_hwmod, .slave = &omap3xxx_gpio6_hwmod,
.addr = omap3xxx_gpio6_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3064,9 +2512,9 @@ static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { ...@@ -3064,9 +2512,9 @@ static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
{ {
.pa_start = 0x48056000, .pa_start = 0x48056000,
.pa_end = 0x48056fff, .pa_end = 0x48056fff,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT,
}, },
{ } { },
}; };
/* l4_cfg -> dma_system */ /* l4_cfg -> dma_system */
...@@ -3078,136 +2526,66 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { ...@@ -3078,136 +2526,66 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48074000,
.pa_end = 0x480740ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_core -> mcbsp1 */ /* l4_core -> mcbsp1 */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mcbsp1_hwmod, .slave = &omap3xxx_mcbsp1_hwmod,
.clk = "mcbsp1_ick", .clk = "mcbsp1_ick",
.addr = omap3xxx_mcbsp1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
{
.name = "mpu",
.pa_start = 0x49022000,
.pa_end = 0x490220ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mcbsp2 */ /* l4_per -> mcbsp2 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_mcbsp2_hwmod, .slave = &omap3xxx_mcbsp2_hwmod,
.clk = "mcbsp2_ick", .clk = "mcbsp2_ick",
.addr = omap3xxx_mcbsp2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
{
.name = "mpu",
.pa_start = 0x49024000,
.pa_end = 0x490240ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mcbsp3 */ /* l4_per -> mcbsp3 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_mcbsp3_hwmod, .slave = &omap3xxx_mcbsp3_hwmod,
.clk = "mcbsp3_ick", .clk = "mcbsp3_ick",
.addr = omap3xxx_mcbsp3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
{
.name = "mpu",
.pa_start = 0x49026000,
.pa_end = 0x490260ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mcbsp4 */ /* l4_per -> mcbsp4 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_mcbsp4_hwmod, .slave = &omap3xxx_mcbsp4_hwmod,
.clk = "mcbsp4_ick", .clk = "mcbsp4_ick",
.addr = omap3xxx_mcbsp4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48096000,
.pa_end = 0x480960ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_core -> mcbsp5 */ /* l4_core -> mcbsp5 */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mcbsp5_hwmod, .slave = &omap3xxx_mcbsp5_hwmod,
.clk = "mcbsp5_ick", .clk = "mcbsp5_ick",
.addr = omap3xxx_mcbsp5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
{
.name = "sidetone",
.pa_start = 0x49028000,
.pa_end = 0x490280ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mcbsp2_sidetone */ /* l4_per -> mcbsp2_sidetone */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_mcbsp2_sidetone_hwmod, .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
.clk = "mcbsp2_ick", .clk = "mcbsp2_ick",
.addr = omap3xxx_mcbsp2_sidetone_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
{
.name = "sidetone",
.pa_start = 0x4902A000,
.pa_end = 0x4902A0ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mcbsp3_sidetone */ /* l4_per -> mcbsp3_sidetone */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
.master = &omap3xxx_l4_per_hwmod, .master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_mcbsp3_sidetone_hwmod, .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
.clk = "mcbsp3_ick", .clk = "mcbsp3_ick",
.addr = omap3xxx_mcbsp3_sidetone_addrs,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -3223,7 +2601,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { ...@@ -3223,7 +2601,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi1, .slave = &omap34xx_mcspi1,
.clk = "mcspi1_ick", .clk = "mcspi1_ick",
.addr = omap2_mcspi1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3232,7 +2609,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { ...@@ -3232,7 +2609,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi2, .slave = &omap34xx_mcspi2,
.clk = "mcspi2_ick", .clk = "mcspi2_ick",
.addr = omap2_mcspi2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3241,25 +2617,15 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { ...@@ -3241,25 +2617,15 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi3, .slave = &omap34xx_mcspi3,
.clk = "mcspi3_ick", .clk = "mcspi3_ick",
.addr = omap2430_mcspi3_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
/* l4 core -> mcspi4 interface */ /* l4 core -> mcspi4 interface */
static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
{
.pa_start = 0x480ba000,
.pa_end = 0x480ba0ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi4, .slave = &omap34xx_mcspi4,
.clk = "mcspi4_ick", .clk = "mcspi4_ick",
.addr = omap34xx_mcspi4_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3270,49 +2636,19 @@ static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { ...@@ -3270,49 +2636,19 @@ static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
{
.name = "uhh",
.pa_start = 0x48064000,
.pa_end = 0x480643ff,
.flags = ADDR_TYPE_RT
},
{
.name = "ohci",
.pa_start = 0x48064400,
.pa_end = 0x480647ff,
},
{
.name = "ehci",
.pa_start = 0x48064800,
.pa_end = 0x48064cff,
},
{}
};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_usb_host_hs_hwmod, .slave = &omap3xxx_usb_host_hs_hwmod,
.clk = "usbhost_ick", .clk = "usbhost_ick",
.addr = omap3xxx_usb_host_hs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
{
.name = "tll",
.pa_start = 0x48062000,
.pa_end = 0x48062fff,
.flags = ADDR_TYPE_RT
},
{}
};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_usb_tll_hs_hwmod, .slave = &omap3xxx_usb_tll_hs_hwmod,
.clk = "usbtll_ick", .clk = "usbtll_ick",
.addr = omap3xxx_usb_tll_hs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3321,35 +2657,17 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { ...@@ -3321,35 +2657,17 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_hdq1w_hwmod, .slave = &omap3xxx_hdq1w_hwmod,
.clk = "hdq_ick", .clk = "hdq_ick",
.addr = omap2_hdq1w_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
}; };
/* l4_wkup -> 32ksync_counter */ /* l4_wkup -> 32ksync_counter */
static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
{
.pa_start = 0x48320000,
.pa_end = 0x4832001f,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
{
.pa_start = 0x6e000000,
.pa_end = 0x6e000fff,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
.master = &omap3xxx_l4_wkup_hwmod, .master = &omap3xxx_l4_wkup_hwmod,
.slave = &omap3xxx_counter_32k_hwmod, .slave = &omap3xxx_counter_32k_hwmod,
.clk = "omap_32ksync_ick", .clk = "omap_32ksync_ick",
.addr = omap3xxx_counter_32k_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3434,7 +2752,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { ...@@ -3434,7 +2752,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
.master = &omap3xxx_l3_main_hwmod, .master = &omap3xxx_l3_main_hwmod,
.slave = &omap3xxx_gpmc_hwmod, .slave = &omap3xxx_gpmc_hwmod,
.clk = "core_l3_ick", .clk = "core_l3_ick",
.addr = omap3xxx_gpmc_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3459,20 +2776,10 @@ static struct omap_hwmod_class omap3xxx_sham_class = { ...@@ -3459,20 +2776,10 @@ static struct omap_hwmod_class omap3xxx_sham_class = {
.sysc = &omap3_sham_sysc, .sysc = &omap3_sham_sysc,
}; };
static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
{ .irq = 49 + OMAP_INTC_START, },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
{ .name = "rx", .dma_req = 69, },
{ .dma_req = -1 }
};
static struct omap_hwmod omap3xxx_sham_hwmod = { static struct omap_hwmod omap3xxx_sham_hwmod = {
.name = "sham", .name = "sham",
.mpu_irqs = omap3_sham_mpu_irqs,
.sdma_reqs = omap3_sham_sdma_reqs,
.main_clk = "sha12_ick", .main_clk = "sha12_ick",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -3486,20 +2793,11 @@ static struct omap_hwmod omap3xxx_sham_hwmod = { ...@@ -3486,20 +2793,11 @@ static struct omap_hwmod omap3xxx_sham_hwmod = {
.class = &omap3xxx_sham_class, .class = &omap3xxx_sham_class,
}; };
static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
{
.pa_start = 0x480c3000,
.pa_end = 0x480c3000 + 0x64 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_sham_hwmod, .slave = &omap3xxx_sham_hwmod,
.clk = "sha12_ick", .clk = "sha12_ick",
.addr = omap3xxx_sham_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3525,15 +2823,9 @@ static struct omap_hwmod_class omap3xxx_aes_class = { ...@@ -3525,15 +2823,9 @@ static struct omap_hwmod_class omap3xxx_aes_class = {
.sysc = &omap3_aes_sysc, .sysc = &omap3_aes_sysc,
}; };
static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
{ .name = "tx", .dma_req = 65, },
{ .name = "rx", .dma_req = 66, },
{ .dma_req = -1 }
};
static struct omap_hwmod omap3xxx_aes_hwmod = { static struct omap_hwmod omap3xxx_aes_hwmod = {
.name = "aes", .name = "aes",
.sdma_reqs = omap3_aes_sdma_reqs,
.main_clk = "aes2_ick", .main_clk = "aes2_ick",
.prcm = { .prcm = {
.omap2 = { .omap2 = {
...@@ -3547,20 +2839,11 @@ static struct omap_hwmod omap3xxx_aes_hwmod = { ...@@ -3547,20 +2839,11 @@ static struct omap_hwmod omap3xxx_aes_hwmod = {
.class = &omap3xxx_aes_class, .class = &omap3xxx_aes_class,
}; };
static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
{
.pa_start = 0x480c5000,
.pa_end = 0x480c5000 + 0x50 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_aes_hwmod, .slave = &omap3xxx_aes_hwmod,
.clk = "aes2_ick", .clk = "aes2_ick",
.addr = omap3xxx_aes_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3661,28 +2944,28 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { ...@@ -3661,28 +2944,28 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
/* GP-only hwmod links */ /* GP-only hwmod links */
static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12, &omap3xxx_l4_sec__timer12,
NULL NULL,
}; };
static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12, &omap3xxx_l4_sec__timer12,
NULL NULL,
}; };
static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12, &omap3xxx_l4_sec__timer12,
NULL NULL,
}; };
/* crypto hwmod links */ /* crypto hwmod links */
static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__sham, &omap3xxx_l4_core__sham,
NULL NULL,
}; };
static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__aes, &omap3xxx_l4_core__aes,
NULL NULL,
}; };
static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
...@@ -3710,14 +2993,14 @@ static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = { ...@@ -3710,14 +2993,14 @@ static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
/* &omap3xxx_l4_core__aes, */ /* &omap3xxx_l4_core__aes, */
NULL NULL,
}; };
/* 3430ES1-only hwmod links */ /* 3430ES1-only hwmod links */
static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
&omap3430es1_dss__l3, &omap3430es1_dss__l3,
&omap3430es1_l4_core__dss, &omap3430es1_l4_core__dss,
NULL NULL,
}; };
/* 3430ES2+-only hwmod links */ /* 3430ES2+-only hwmod links */
...@@ -3729,21 +3012,21 @@ static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { ...@@ -3729,21 +3012,21 @@ static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_usb_host_hs__l3_main_2, &omap3xxx_usb_host_hs__l3_main_2,
&omap3xxx_l4_core__usb_host_hs, &omap3xxx_l4_core__usb_host_hs,
&omap3xxx_l4_core__usb_tll_hs, &omap3xxx_l4_core__usb_tll_hs,
NULL NULL,
}; };
/* <= 3430ES3-only hwmod links */ /* <= 3430ES3-only hwmod links */
static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__pre_es3_mmc1, &omap3xxx_l4_core__pre_es3_mmc1,
&omap3xxx_l4_core__pre_es3_mmc2, &omap3xxx_l4_core__pre_es3_mmc2,
NULL NULL,
}; };
/* 3430ES3+-only hwmod links */ /* 3430ES3+-only hwmod links */
static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__es3plus_mmc1, &omap3xxx_l4_core__es3plus_mmc1,
&omap3xxx_l4_core__es3plus_mmc2, &omap3xxx_l4_core__es3plus_mmc2,
NULL NULL,
}; };
/* 34xx-only hwmod links (all ES revisions) */ /* 34xx-only hwmod links (all ES revisions) */
...@@ -3757,7 +3040,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3757,7 +3040,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__mmu_isp, &omap3xxx_l4_core__mmu_isp,
&omap3xxx_l3_main__mmu_iva, &omap3xxx_l3_main__mmu_iva,
&omap3xxx_l4_core__ssi, &omap3xxx_l4_core__ssi,
NULL NULL,
}; };
/* 36xx-only hwmod links (all ES revisions) */ /* 36xx-only hwmod links (all ES revisions) */
...@@ -3781,7 +3064,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3781,7 +3064,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__mmu_isp, &omap3xxx_l4_core__mmu_isp,
&omap3xxx_l3_main__mmu_iva, &omap3xxx_l3_main__mmu_iva,
&omap3xxx_l4_core__ssi, &omap3xxx_l4_core__ssi,
NULL NULL,
}; };
static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
...@@ -3800,7 +3083,7 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3800,7 +3083,7 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
&am35xx_l4_core__mdio, &am35xx_l4_core__mdio,
&am35xx_emac__l3, &am35xx_emac__l3,
&am35xx_l4_core__emac, &am35xx_l4_core__emac,
NULL NULL,
}; };
static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
...@@ -3808,7 +3091,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { ...@@ -3808,7 +3091,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__dss_dsi1, &omap3xxx_l4_core__dss_dsi1,
&omap3xxx_l4_core__dss_rfbi, &omap3xxx_l4_core__dss_rfbi,
&omap3xxx_l4_core__dss_venc, &omap3xxx_l4_core__dss_venc,
NULL NULL,
}; };
/** /**
......
arch/arm/mach-omap2/omap_hwmod_common_data.h
View file @ 6d1e66bb
...@@ -19,22 +19,7 @@ ...@@ -19,22 +19,7 @@
#include "display.h" #include "display.h"
/* Common address space across OMAP2xxx/3xxx */ /* Common address space across OMAP2xxx/3xxx */
extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
extern struct omap_hwmod_addr_space omap2_dss_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
/* Common IP block data across OMAP2xxx */ /* Common IP block data across OMAP2xxx */
extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
......
arch/arm/mach-omap2/pdata-quirks.c
View file @ 6d1e66bb
...@@ -31,7 +31,6 @@ ...@@ -31,7 +31,6 @@
#include "common.h" #include "common.h"
#include "common-board-devices.h" #include "common-board-devices.h"
#include "dss-common.h"
#include "control.h" #include "control.h"
#include "omap_device.h" #include "omap_device.h"
#include "omap-pm.h" #include "omap-pm.h"
......
arch/arm/mach-omap2/pm.c
View file @ 6d1e66bb
...@@ -30,7 +30,6 @@ ...@@ -30,7 +30,6 @@
#include "powerdomain.h" #include "powerdomain.h"
#include "clockdomain.h" #include "clockdomain.h"
#include "pm.h" #include "pm.h"
#include "twl-common.h"
#ifdef CONFIG_SUSPEND #ifdef CONFIG_SUSPEND
/* /*
...@@ -72,42 +71,6 @@ void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) ...@@ -72,42 +71,6 @@ void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
} }
#endif #endif
static int __init _init_omap_device(char *name)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
oh = omap_hwmod_lookup(name);
if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
__func__, name))
return -ENODEV;
pdev = omap_device_build(oh->name, 0, oh, NULL, 0);
if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
__func__, name))
return -ENODEV;
return 0;
}
/*
* Build omap_devices for processors and bus.
*/
static void __init omap2_init_processor_devices(void)
{
_init_omap_device("mpu");
if (omap3_has_iva())
_init_omap_device("iva");
if (cpu_is_omap44xx()) {
_init_omap_device("l3_main_1");
_init_omap_device("dsp");
_init_omap_device("iva");
} else {
_init_omap_device("l3_main");
}
}
int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
{ {
clkdm_allow_idle(clkdm); clkdm_allow_idle(clkdm);
...@@ -215,7 +178,7 @@ static int omap_pm_enter(suspend_state_t suspend_state) ...@@ -215,7 +178,7 @@ static int omap_pm_enter(suspend_state_t suspend_state)
static int omap_pm_begin(suspend_state_t state) static int omap_pm_begin(suspend_state_t state)
{ {
cpu_idle_poll_ctrl(true); cpu_idle_poll_ctrl(true);
if (cpu_is_omap34xx()) if (soc_is_omap34xx())
omap_prcm_irq_prepare(); omap_prcm_irq_prepare();
return 0; return 0;
} }
...@@ -227,7 +190,7 @@ static void omap_pm_end(void) ...@@ -227,7 +190,7 @@ static void omap_pm_end(void)
static void omap_pm_finish(void) static void omap_pm_finish(void)
{ {
if (cpu_is_omap34xx()) if (soc_is_omap34xx())
omap_prcm_irq_complete(); omap_prcm_irq_complete();
} }
...@@ -252,7 +215,7 @@ void omap_common_suspend_init(void *pm_suspend) ...@@ -252,7 +215,7 @@ void omap_common_suspend_init(void *pm_suspend)
static void __init omap3_init_voltages(void) static void __init omap3_init_voltages(void)
{ {
if (!cpu_is_omap34xx()) if (!soc_is_omap34xx())
return; return;
omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu"); omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
...@@ -261,7 +224,7 @@ static void __init omap3_init_voltages(void) ...@@ -261,7 +224,7 @@ static void __init omap3_init_voltages(void)
static void __init omap4_init_voltages(void) static void __init omap4_init_voltages(void)
{ {
if (!cpu_is_omap44xx()) if (!soc_is_omap44xx())
return; return;
omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu"); omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
...@@ -269,18 +232,8 @@ static void __init omap4_init_voltages(void) ...@@ -269,18 +232,8 @@ static void __init omap4_init_voltages(void)
omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
} }
static inline void omap_init_cpufreq(void)
{
struct platform_device_info devinfo = { .name = "omap-cpufreq" };
if (!of_have_populated_dt())
platform_device_register_full(&devinfo);
}
static int __init omap2_common_pm_init(void) static int __init omap2_common_pm_init(void)
{ {
if (!of_have_populated_dt())
omap2_init_processor_devices();
omap_pm_if_init(); omap_pm_if_init();
return 0; return 0;
...@@ -289,13 +242,9 @@ omap_postcore_initcall(omap2_common_pm_init); ...@@ -289,13 +242,9 @@ omap_postcore_initcall(omap2_common_pm_init);
int __init omap2_common_pm_late_init(void) int __init omap2_common_pm_late_init(void)
{ {
if (of_have_populated_dt()) { /* Init the voltage layer */
omap3_twl_init(); omap3_twl_init();
omap4_twl_init(); omap4_twl_init();
}
/* Init the voltage layer */
omap_pmic_late_init();
omap_voltage_late_init(); omap_voltage_late_init();
/* Initialize the voltages */ /* Initialize the voltages */
...@@ -305,8 +254,5 @@ int __init omap2_common_pm_late_init(void) ...@@ -305,8 +254,5 @@ int __init omap2_common_pm_late_init(void)
/* Smartreflex device init */ /* Smartreflex device init */
omap_devinit_smartreflex(); omap_devinit_smartreflex();
/* cpufreq dummy device instantiation */
omap_init_cpufreq();
return 0; return 0;
} }
arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h deleted 100644 → 0
View file @ a9fa1f7c
/*
* SDRC register values for the Hynix H8MBX00U0MER-0EM
*
* Copyright (C) 2009 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
#define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
#include "sdrc.h"
/* Hynix H8MBX00U0MER-0EM */
static struct omap_sdrc_params h8mbx00u0mer0em_sdrc_params[] = {
[0] = {
.rate = 200000000,
.actim_ctrla = 0xa2e1b4c6,
.actim_ctrlb = 0x0002131c,
.rfr_ctrl = 0x0005e601,
.mr = 0x00000032,
},
[1] = {
.rate = 166000000,
.actim_ctrla = 0x629db4c6,
.actim_ctrlb = 0x00012214,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[2] = {
.rate = 100000000,
.actim_ctrla = 0x51912284,
.actim_ctrlb = 0x0002120e,
.rfr_ctrl = 0x0002d101,
.mr = 0x00000022,
},
[3] = {
.rate = 83000000,
.actim_ctrla = 0x31512283,
.actim_ctrlb = 0x0001220a,
.rfr_ctrl = 0x00025501,
.mr = 0x00000022,
},
[4] = {
.rate = 0
},
};
#endif
arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h deleted 100644 → 0
View file @ a9fa1f7c
/*
* SDRC register values for the Micron MT46H32M32LF-6
*
* Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008-2009 Nokia Corporation
*
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
#include "sdrc.h"
/* Micron MT46H32M32LF-6 */
/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
[0] = {
.rate = 166000000,
.actim_ctrla = 0x9a9db4c6,
.actim_ctrlb = 0x00011217,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[1] = {
.rate = 165941176,
.actim_ctrla = 0x9a9db4c6,
.actim_ctrlb = 0x00011217,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[2] = {
.rate = 83000000,
.actim_ctrla = 0x51512283,
.actim_ctrlb = 0x0001120c,
.rfr_ctrl = 0x00025501,
.mr = 0x00000032,
},
[3] = {
.rate = 82970588,
.actim_ctrla = 0x51512283,
.actim_ctrlb = 0x0001120c,
.rfr_ctrl = 0x00025501,
.mr = 0x00000032,
},
[4] = {
.rate = 0
},
};
#endif
arch/arm/mach-omap2/sdram-nokia.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* SDRC register values for Nokia boards
*
* Copyright (C) 2008, 2010-2011 Nokia Corporation
*
* Lauri Leukkunen <lauri.leukkunen@nokia.com>
*
* Original code by Juha Yrjola <juha.yrjola@solidboot.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include "common.h"
#include "sdram-nokia.h"
#include "sdrc.h"
/* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
struct sdram_timings {
u32 casl;
u32 tDAL;
u32 tDPL;
u32 tRRD;
u32 tRCD;
u32 tRP;
u32 tRAS;
u32 tRC;
u32 tRFC;
u32 tXSR;
u32 tREF; /* in ns */
u32 tXP;
u32 tCKE;
u32 tWTR;
};
static const struct sdram_timings nokia_97dot6mhz_timings[] = {
{
.casl = 3,
.tDAL = 30725,
.tDPL = 15362,
.tRRD = 10241,
.tRCD = 20483,
.tRP = 15362,
.tRAS = 40967,
.tRC = 56330,
.tRFC = 138266,
.tXSR = 204839,
.tREF = 7798,
.tXP = 2,
.tCKE = 4,
.tWTR = 2,
},
};
static const struct sdram_timings nokia_166mhz_timings[] = {
{
.casl = 3,
.tDAL = 33000,
.tDPL = 15000,
.tRRD = 12000,
.tRCD = 22500,
.tRP = 18000,
.tRAS = 42000,
.tRC = 66000,
.tRFC = 138000,
.tXSR = 200000,
.tREF = 7800,
.tXP = 2,
.tCKE = 2,
.tWTR = 2
},
};
static const struct sdram_timings nokia_195dot2mhz_timings[] = {
{
.casl = 3,
.tDAL = 30725,
.tDPL = 15362,
.tRRD = 10241,
.tRCD = 20483,
.tRP = 15362,
.tRAS = 40967,
.tRC = 56330,
.tRFC = 138266,
.tXSR = 204839,
.tREF = 7752,
.tXP = 2,
.tCKE = 4,
.tWTR = 2,
},
};
static const struct sdram_timings nokia_200mhz_timings[] = {
{
.casl = 3,
.tDAL = 30000,
.tDPL = 15000,
.tRRD = 10000,
.tRCD = 20000,
.tRP = 15000,
.tRAS = 40000,
.tRC = 55000,
.tRFC = 140000,
.tXSR = 200000,
.tREF = 7800,
.tXP = 2,
.tCKE = 4,
.tWTR = 2
},
};
static const struct {
long rate;
struct sdram_timings const *data;
} nokia_timings[] = {
{ 83000000, nokia_166mhz_timings },
{ 97600000, nokia_97dot6mhz_timings },
{ 100000000, nokia_200mhz_timings },
{ 166000000, nokia_166mhz_timings },
{ 195200000, nokia_195dot2mhz_timings },
{ 200000000, nokia_200mhz_timings },
};
static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
static unsigned long sdrc_get_fclk_period(long rate)
{
/* In picoseconds */
return 1000000000 / rate;
}
static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate)
{
unsigned long tick_ps;
/* Calculate in picosecs to yield more exact results */
tick_ps = sdrc_get_fclk_period(rate);
return (time_ps + tick_ps - 1) / tick_ps;
}
#undef DEBUG
#ifdef DEBUG
static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
int ticks, long rate, const char *name)
#else
static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
int ticks)
#endif
{
int mask, nr_bits;
nr_bits = end_bit - st_bit + 1;
if (ticks >= 1 << nr_bits)
return -1;
mask = (1 << nr_bits) - 1;
*regval &= ~(mask << st_bit);
*regval |= ticks << st_bit;
#ifdef DEBUG
printk(KERN_INFO "SDRC %s: %i ticks %i ns\n", name, ticks,
(unsigned int)sdrc_get_fclk_period(rate) * ticks /
1000);
#endif
return 0;
}
#ifdef DEBUG
#define SDRC_SET_ONE(reg, st, end, field, rate) \
if (set_sdrc_timing_regval((reg), (st), (end), \
memory_timings->field, (rate), #field) < 0) \
err = -1;
#else
#define SDRC_SET_ONE(reg, st, end, field, rate) \
if (set_sdrc_timing_regval((reg), (st), (end), \
memory_timings->field) < 0) \
err = -1;
#endif
#ifdef DEBUG
static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
int time, long rate, const char *name)
#else
static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
int time, long rate)
#endif
{
int ticks, ret;
ret = 0;
if (time == 0)
ticks = 0;
else
ticks = sdrc_ps_to_ticks(time, rate);
#ifdef DEBUG
ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks,
rate, name);
#else
ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks);
#endif
return ret;
}
#ifdef DEBUG
#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
if (set_sdrc_timing_regval_ps((reg), (st), (end), \
memory_timings->field, \
(rate), #field) < 0) \
err = -1;
#else
#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
if (set_sdrc_timing_regval_ps((reg), (st), (end), \
memory_timings->field, (rate)) < 0) \
err = -1;
#endif
static int sdrc_timings(int id, long rate,
const struct sdram_timings *memory_timings)
{
u32 ticks_per_ms;
u32 rfr, l;
u32 actim_ctrla = 0, actim_ctrlb = 0;
u32 rfr_ctrl;
int err = 0;
long l3_rate = rate / 1000;
SDRC_SET_ONE_PS(&actim_ctrla, 0, 4, tDAL, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 6, 8, tDPL, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 9, 11, tRRD, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 12, 14, tRCD, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 15, 17, tRP, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 18, 21, tRAS, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 22, 26, tRC, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 27, 31, tRFC, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrlb, 0, 7, tXSR, l3_rate);
SDRC_SET_ONE(&actim_ctrlb, 8, 10, tXP, l3_rate);
SDRC_SET_ONE(&actim_ctrlb, 12, 14, tCKE, l3_rate);
SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate);
ticks_per_ms = l3_rate;
rfr = memory_timings[0].tREF * ticks_per_ms / 1000000;
if (rfr > 65535 + 50)
rfr = 65535;
else
rfr -= 50;
#ifdef DEBUG
printk(KERN_INFO "SDRC tREF: %i ticks\n", rfr);
#endif
l = rfr << 8;
rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */
nokia_sdrc_params[id].rate = rate;
nokia_sdrc_params[id].actim_ctrla = actim_ctrla;
nokia_sdrc_params[id].actim_ctrlb = actim_ctrlb;
nokia_sdrc_params[id].rfr_ctrl = rfr_ctrl;
nokia_sdrc_params[id].mr = 0x32;
nokia_sdrc_params[id + 1].rate = 0;
return err;
}
struct omap_sdrc_params *nokia_get_sdram_timings(void)
{
int err = 0;
int i;
for (i = 0; i < ARRAY_SIZE(nokia_timings); i++) {
err |= sdrc_timings(i, nokia_timings[i].rate,
nokia_timings[i].data);
if (err)
pr_err("%s: error with rate %ld: %d\n", __func__,
nokia_timings[i].rate, err);
}
return err ? NULL : nokia_sdrc_params;
}
arch/arm/mach-omap2/sdram-nokia.h deleted 100644 → 0
View file @ a9fa1f7c
/*
* SDRC register values for Nokia boards
*
* Copyright (C) 2010 Nokia
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
struct omap_sdrc_params *nokia_get_sdram_timings(void);
arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h deleted 100644 → 0
View file @ a9fa1f7c
/*
* SDRC register values for the Numonyx M65KXXXXAM
*
* Copyright (C) 2009 Integration Software and Electronic Engineering.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
#define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
#include "sdrc.h"
/* Numonyx M65KXXXXAM */
static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = {
[0] = {
.rate = 200000000,
.actim_ctrla = 0xe321d4c6,
.actim_ctrlb = 0x00022328,
.rfr_ctrl = 0x0005e601,
.mr = 0x00000032,
},
[1] = {
.rate = 166000000,
.actim_ctrla = 0xba9dc485,
.actim_ctrlb = 0x00022321,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[2] = {
.rate = 133000000,
.actim_ctrla = 0x9a19b485,
.actim_ctrlb = 0x0002231b,
.rfr_ctrl = 0x0003de01,
.mr = 0x00000032,
},
[3] = {
.rate = 83000000,
.actim_ctrla = 0x594ca242,
.actim_ctrlb = 0x00022310,
.rfr_ctrl = 0x00025501,
.mr = 0x00000032,
},
[4] = {
.rate = 0
},
};
#endif
arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h deleted 100644 → 0
View file @ a9fa1f7c
/*
* SDRC register values for the Qimonda HYB18M512160AF-6
*
* Copyright (C) 2008-2009 Texas Instruments, Inc.
* Copyright (C) 2008-2009 Nokia Corporation
*
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
#include "sdrc.h"
/* Qimonda HYB18M512160AF-6 */
static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
[0] = {
.rate = 166000000,
.actim_ctrla = 0x629db4c6,
.actim_ctrlb = 0x00012214,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[1] = {
.rate = 165941176,
.actim_ctrla = 0x629db4c6,
.actim_ctrlb = 0x00012214,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[2] = {
.rate = 83000000,
.actim_ctrla = 0x31512283,
.actim_ctrlb = 0x0001220a,
.rfr_ctrl = 0x00025501,
.mr = 0x00000022,
},
[3] = {
.rate = 82970588,
.actim_ctrla = 0x31512283,
.actim_ctrlb = 0x0001220a,
.rfr_ctrl = 0x00025501,
.mr = 0x00000022,
},
[4] = {
.rate = 0
},
};
#endif
arch/arm/mach-omap2/serial.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* arch/arm/mach-omap2/serial.c
*
* OMAP2 serial support.
*
* Copyright (C) 2005-2008 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
*
* Major rework for PM support by Kevin Hilman
*
* Based off of arch/arm/mach-omap/omap1/serial.c
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/console.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/serial-omap.h>
#include "common.h"
#include "omap_hwmod.h"
#include "omap_device.h"
#include "omap-pm.h"
#include "soc.h"
#include "prm2xxx_3xxx.h"
#include "pm.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "control.h"
#include "mux.h"
#include "serial.h"
/*
* NOTE: By default the serial auto_suspend timeout is disabled as it causes
* lost characters over the serial ports. This means that the UART clocks will
* stay on until power/autosuspend_delay is set for the uart from sysfs.
* This also causes that any deeper omap sleep states are blocked.
*/
#define DEFAULT_AUTOSUSPEND_DELAY -1
#define MAX_UART_HWMOD_NAME_LEN 16
struct omap_uart_state {
int num;
struct list_head node;
struct omap_hwmod *oh;
struct omap_device_pad default_omap_uart_pads[2];
};
static LIST_HEAD(uart_list);
static u8 num_uarts;
static u8 console_uart_id = -1;
static u8 uart_debug;
#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */
#define DEFAULT_RXDMA_BUFSIZE 4096 /* RX DMA buffer size */
#define DEFAULT_RXDMA_TIMEOUT (3 * HZ)/* RX DMA timeout (jiffies) */
static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
{
.dma_enabled = false,
.dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
.dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
.dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
.autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
},
};
#ifdef CONFIG_PM
static void omap_uart_enable_wakeup(struct device *dev, bool enable)
{
struct platform_device *pdev = to_platform_device(dev);
struct omap_device *od = to_omap_device(pdev);
if (!od)
return;
if (enable)
omap_hwmod_enable_wakeup(od->hwmods[0]);
else
omap_hwmod_disable_wakeup(od->hwmods[0]);
}
#else
static void omap_uart_enable_wakeup(struct device *dev, bool enable)
{}
#endif /* CONFIG_PM */
#ifdef CONFIG_OMAP_MUX
#define OMAP_UART_DEFAULT_PAD_NAME_LEN 28
static char rx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN],
tx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN] __initdata;
static void __init
omap_serial_fill_uart_tx_rx_pads(struct omap_board_data *bdata,
struct omap_uart_state *uart)
{
uart->default_omap_uart_pads[0].name = rx_pad_name;
uart->default_omap_uart_pads[0].flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP;
uart->default_omap_uart_pads[0].enable = OMAP_PIN_INPUT |
OMAP_MUX_MODE0;
uart->default_omap_uart_pads[0].idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0;
uart->default_omap_uart_pads[1].name = tx_pad_name;
uart->default_omap_uart_pads[1].enable = OMAP_PIN_OUTPUT |
OMAP_MUX_MODE0;
bdata->pads = uart->default_omap_uart_pads;
bdata->pads_cnt = ARRAY_SIZE(uart->default_omap_uart_pads);
}
static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
struct omap_uart_state *uart)
{
struct omap_mux_partition *tx_partition = NULL, *rx_partition = NULL;
struct omap_mux *rx_mux = NULL, *tx_mux = NULL;
char *rx_fmt, *tx_fmt;
int uart_nr = bdata->id + 1;
if (bdata->id != 2) {
rx_fmt = "uart%d_rx.uart%d_rx";
tx_fmt = "uart%d_tx.uart%d_tx";
} else {
rx_fmt = "uart%d_rx_irrx.uart%d_rx_irrx";
tx_fmt = "uart%d_tx_irtx.uart%d_tx_irtx";
}
snprintf(rx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, rx_fmt,
uart_nr, uart_nr);
snprintf(tx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, tx_fmt,
uart_nr, uart_nr);
if (omap_mux_get_by_name(rx_pad_name, &rx_partition, &rx_mux) >= 0 &&
omap_mux_get_by_name
(tx_pad_name, &tx_partition, &tx_mux) >= 0) {
u16 tx_mode, rx_mode;
tx_mode = omap_mux_read(tx_partition, tx_mux->reg_offset);
rx_mode = omap_mux_read(rx_partition, rx_mux->reg_offset);
/*
* Check if uart is used in default tx/rx mode i.e. in mux mode0
* if yes then configure rx pin for wake up capability
*/
if (OMAP_MODE_UART(rx_mode) && OMAP_MODE_UART(tx_mode))
omap_serial_fill_uart_tx_rx_pads(bdata, uart);
}
}
#else
static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
struct omap_uart_state *uart)
{
}
#endif
static char *cmdline_find_option(char *str)
{
extern char *saved_command_line;
return strstr(saved_command_line, str);
}
static int __init omap_serial_early_init(void)
{
if (of_have_populated_dt())
return -ENODEV;
do {
char oh_name[MAX_UART_HWMOD_NAME_LEN];
struct omap_hwmod *oh;
struct omap_uart_state *uart;
char uart_name[MAX_UART_HWMOD_NAME_LEN];
snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
"uart%d", num_uarts + 1);
oh = omap_hwmod_lookup(oh_name);
if (!oh)
break;
uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
if (WARN_ON(!uart))
return -ENODEV;
uart->oh = oh;
uart->num = num_uarts++;
list_add_tail(&uart->node, &uart_list);
snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
"%s%d", OMAP_SERIAL_NAME, uart->num);
if (cmdline_find_option(uart_name)) {
console_uart_id = uart->num;
if (console_loglevel >= CONSOLE_LOGLEVEL_DEBUG) {
uart_debug = true;
pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
uart_name, uart->num);
}
}
} while (1);
return 0;
}
omap_postcore_initcall(omap_serial_early_init);
/**
* omap_serial_init_port() - initialize single serial port
* @bdata: port specific board data pointer
* @info: platform specific data pointer
*
* This function initialies serial driver for given port only.
* Platforms can call this function instead of omap_serial_init()
* if they don't plan to use all available UARTs as serial ports.
*
* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
* use only one of the two.
*/
void __init omap_serial_init_port(struct omap_board_data *bdata,
struct omap_uart_port_info *info)
{
struct omap_uart_state *uart;
struct omap_hwmod *oh;
struct platform_device *pdev;
void *pdata = NULL;
u32 pdata_size = 0;
char *name;
struct omap_uart_port_info omap_up;
if (WARN_ON(!bdata))
return;
if (WARN_ON(bdata->id < 0))
return;
if (WARN_ON(bdata->id >= num_uarts))
return;
list_for_each_entry(uart, &uart_list, node)
if (bdata->id == uart->num)
break;
if (!info)
info = omap_serial_default_info;
oh = uart->oh;
name = OMAP_SERIAL_DRIVER_NAME;
omap_up.dma_enabled = info->dma_enabled;
omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
omap_up.flags = UPF_BOOT_AUTOCONF;
omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
omap_up.enable_wakeup = omap_uart_enable_wakeup;
omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
omap_up.dma_rx_timeout = info->dma_rx_timeout;
omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
omap_up.autosuspend_timeout = info->autosuspend_timeout;
pdata = &omap_up;
pdata_size = sizeof(struct omap_uart_port_info);
if (WARN_ON(!oh))
return;
pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size);
if (IS_ERR(pdev)) {
WARN(1, "Could not build omap_device for %s: %s.\n", name,
oh->name);
return;
}
oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
if (console_uart_id == bdata->id) {
omap_device_enable(pdev);
pm_runtime_set_active(&pdev->dev);
}
oh->dev_attr = uart;
if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
&& !uart_debug)
device_init_wakeup(&pdev->dev, true);
}
/**
* omap_serial_board_init() - initialize all supported serial ports
* @info: platform specific data pointer
*
* Initializes all available UARTs as serial ports. Platforms
* can call this function when they want to have default behaviour
* for serial ports (e.g initialize them all as serial ports).
*/
void __init omap_serial_board_init(struct omap_uart_port_info *info)
{
struct omap_uart_state *uart;
struct omap_board_data bdata;
list_for_each_entry(uart, &uart_list, node) {
bdata.id = uart->num;
bdata.flags = 0;
bdata.pads = NULL;
bdata.pads_cnt = 0;
omap_serial_check_wakeup(&bdata, uart);
if (!info)
omap_serial_init_port(&bdata, NULL);
else
omap_serial_init_port(&bdata, &info[uart->num]);
}
}
/**
* omap_serial_init() - initialize all supported serial ports
*
* Initializes all available UARTs.
* Platforms can call this function when they want to have default behaviour
* for serial ports (e.g initialize them all as serial ports).
*/
void __init omap_serial_init(void)
{
omap_serial_board_init(NULL);
}
arch/arm/mach-omap2/twl-common.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* twl-common.c
*
* Copyright (C) 2011 Texas Instruments, Inc..
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/i2c.h>
#include <linux/i2c/twl.h>
#include <linux/gpio.h>
#include <linux/string.h>
#include <linux/phy/phy.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include "soc.h"
#include "twl-common.h"
#include "pm.h"
#include "voltage.h"
#include "mux.h"
static struct i2c_board_info __initdata pmic_i2c_board_info = {
.addr = 0x48,
.flags = I2C_CLIENT_WAKE,
};
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
static int twl_set_voltage(void *data, int target_uV)
{
struct voltagedomain *voltdm = (struct voltagedomain *)data;
return voltdm_scale(voltdm, target_uV);
}
static int twl_get_voltage(void *data)
{
struct voltagedomain *voltdm = (struct voltagedomain *)data;
return voltdm_get_voltage(voltdm);
}
#endif
void __init omap_pmic_init(int bus, u32 clkrate,
const char *pmic_type, int pmic_irq,
struct twl4030_platform_data *pmic_data)
{
omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
strlcpy(pmic_i2c_board_info.type, pmic_type,
sizeof(pmic_i2c_board_info.type));
pmic_i2c_board_info.irq = pmic_irq;
pmic_i2c_board_info.platform_data = pmic_data;
omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
}
#ifdef CONFIG_ARCH_OMAP4
void __init omap4_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data,
struct i2c_board_info *devices, int nr_devices)
{
/* PMIC part*/
unsigned int irq;
omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
irq = omap4_xlate_irq(7 + OMAP44XX_IRQ_GIC_START);
omap_pmic_init(1, 400, pmic_type, irq, pmic_data);
/* Register additional devices on i2c1 bus if needed */
if (devices)
i2c_register_board_info(1, devices, nr_devices);
}
#endif
void __init omap_pmic_late_init(void)
{
/* Init the OMAP TWL parameters (if PMIC has been registerd) */
if (!pmic_i2c_board_info.irq)
return;
omap3_twl_init();
omap4_twl_init();
}
#if defined(CONFIG_ARCH_OMAP3)
static struct twl4030_usb_data omap3_usb_pdata = {
.usb_mode = T2_USB_MODE_ULPI,
};
static int omap3_batt_table[] = {
/* 0 C */
30800, 29500, 28300, 27100,
26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
4040, 3910, 3790, 3670, 3550
};
static struct twl4030_bci_platform_data omap3_bci_pdata = {
.battery_tmp_tbl = omap3_batt_table,
.tblsize = ARRAY_SIZE(omap3_batt_table),
};
static struct twl4030_madc_platform_data omap3_madc_pdata = {
.irq_line = 1,
};
static struct twl4030_codec_data omap3_codec;
static struct twl4030_audio_data omap3_audio_pdata = {
.audio_mclk = 26000000,
.codec = &omap3_codec,
};
static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = {
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
};
static struct regulator_init_data omap3_vdac_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap3_vdda_dac_supplies),
.consumer_supplies = omap3_vdda_dac_supplies,
};
static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
};
static struct regulator_init_data omap3_vpll2_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap3_vpll2_supplies),
.consumer_supplies = omap3_vpll2_supplies,
};
static struct regulator_consumer_supply omap3_vdd1_supply[] = {
REGULATOR_SUPPLY("vcc", "cpu0"),
};
static struct regulator_consumer_supply omap3_vdd2_supply[] = {
REGULATOR_SUPPLY("vcc", "l3_main.0"),
};
static struct regulator_init_data omap3_vdd1 = {
.constraints = {
.name = "vdd_mpu_iva",
.min_uV = 600000,
.max_uV = 1450000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(omap3_vdd1_supply),
.consumer_supplies = omap3_vdd1_supply,
};
static struct regulator_init_data omap3_vdd2 = {
.constraints = {
.name = "vdd_core",
.min_uV = 600000,
.max_uV = 1450000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(omap3_vdd2_supply),
.consumer_supplies = omap3_vdd2_supply,
};
static struct twl_regulator_driver_data omap3_vdd1_drvdata = {
.get_voltage = twl_get_voltage,
.set_voltage = twl_set_voltage,
};
static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
.get_voltage = twl_get_voltage,
.set_voltage = twl_set_voltage,
};
void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
u32 pdata_flags, u32 regulators_flags)
{
if (!pmic_data->vdd1) {
omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
pmic_data->vdd1 = &omap3_vdd1;
}
if (!pmic_data->vdd2) {
omap3_vdd2.driver_data = &omap3_vdd2_drvdata;
omap3_vdd2_drvdata.data = voltdm_lookup("core");
pmic_data->vdd2 = &omap3_vdd2;
}
/* Common platform data configurations */
if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
pmic_data->usb = &omap3_usb_pdata;
if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
pmic_data->bci = &omap3_bci_pdata;
if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
pmic_data->madc = &omap3_madc_pdata;
if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->audio)
pmic_data->audio = &omap3_audio_pdata;
/* Common regulator configurations */
if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
pmic_data->vdac = &omap3_vdac_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
pmic_data->vpll2 = &omap3_vpll2_idata;
}
#endif /* CONFIG_ARCH_OMAP3 */
#if defined(CONFIG_ARCH_OMAP4)
static struct twl4030_usb_data omap4_usb_pdata = {
};
static struct regulator_consumer_supply omap4_vdda_hdmi_dac_supplies[] = {
REGULATOR_SUPPLY("vdda_hdmi_dac", "omapdss_hdmi"),
};
static struct regulator_init_data omap4_vdac_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vdda_hdmi_dac_supplies),
.consumer_supplies = omap4_vdda_hdmi_dac_supplies,
.supply_regulator = "V2V1",
};
static struct regulator_init_data omap4_vaux2_idata = {
.constraints = {
.min_uV = 1200000,
.max_uV = 2800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_vaux3_idata = {
.constraints = {
.min_uV = 1000000,
.max_uV = 3000000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_consumer_supply omap4_vmmc_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 card */
static struct regulator_init_data omap4_vmmc_idata = {
.constraints = {
.min_uV = 1200000,
.max_uV = 3000000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vmmc_supply),
.consumer_supplies = omap4_vmmc_supply,
};
static struct regulator_init_data omap4_vpp_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 2500000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_vana_idata = {
.constraints = {
.min_uV = 2100000,
.max_uV = 2100000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_consumer_supply omap4_vcxio_supply[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.1"),
};
static struct regulator_init_data omap4_vcxio_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
.always_on = true,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vcxio_supply),
.consumer_supplies = omap4_vcxio_supply,
.supply_regulator = "V2V1",
};
static struct regulator_init_data omap4_vusb_idata = {
.constraints = {
.min_uV = 3300000,
.max_uV = 3300000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_clk32kg_idata = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_consumer_supply omap4_vdd1_supply[] = {
REGULATOR_SUPPLY("vcc", "cpu0"),
};
static struct regulator_consumer_supply omap4_vdd2_supply[] = {
REGULATOR_SUPPLY("vcc", "iva.0"),
};
static struct regulator_consumer_supply omap4_vdd3_supply[] = {
REGULATOR_SUPPLY("vcc", "l3_main.0"),
};
static struct regulator_init_data omap4_vdd1 = {
.constraints = {
.name = "vdd_mpu",
.min_uV = 500000,
.max_uV = 1500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vdd1_supply),
.consumer_supplies = omap4_vdd1_supply,
};
static struct regulator_init_data omap4_vdd2 = {
.constraints = {
.name = "vdd_iva",
.min_uV = 500000,
.max_uV = 1500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vdd2_supply),
.consumer_supplies = omap4_vdd2_supply,
};
static struct regulator_init_data omap4_vdd3 = {
.constraints = {
.name = "vdd_core",
.min_uV = 500000,
.max_uV = 1500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vdd3_supply),
.consumer_supplies = omap4_vdd3_supply,
};
static struct twl_regulator_driver_data omap4_vdd1_drvdata = {
.get_voltage = twl_get_voltage,
.set_voltage = twl_set_voltage,
};
static struct twl_regulator_driver_data omap4_vdd2_drvdata = {
.get_voltage = twl_get_voltage,
.set_voltage = twl_set_voltage,
};
static struct twl_regulator_driver_data omap4_vdd3_drvdata = {
.get_voltage = twl_get_voltage,
.set_voltage = twl_set_voltage,
};
static struct regulator_consumer_supply omap4_v1v8_supply[] = {
REGULATOR_SUPPLY("vio", "1-004b"),
};
static struct regulator_init_data omap4_v1v8_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
.always_on = true,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_v1v8_supply),
.consumer_supplies = omap4_v1v8_supply,
};
static struct regulator_consumer_supply omap4_v2v1_supply[] = {
REGULATOR_SUPPLY("v2v1", "1-004b"),
};
static struct regulator_init_data omap4_v2v1_idata = {
.constraints = {
.min_uV = 2100000,
.max_uV = 2100000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_v2v1_supply),
.consumer_supplies = omap4_v2v1_supply,
};
void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
u32 pdata_flags, u32 regulators_flags)
{
if (!pmic_data->vdd1) {
omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
pmic_data->vdd1 = &omap4_vdd1;
}
if (!pmic_data->vdd2) {
omap4_vdd2.driver_data = &omap4_vdd2_drvdata;
omap4_vdd2_drvdata.data = voltdm_lookup("iva");
pmic_data->vdd2 = &omap4_vdd2;
}
if (!pmic_data->vdd3) {
omap4_vdd3.driver_data = &omap4_vdd3_drvdata;
omap4_vdd3_drvdata.data = voltdm_lookup("core");
pmic_data->vdd3 = &omap4_vdd3;
}
/* Common platform data configurations */
if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
pmic_data->usb = &omap4_usb_pdata;
/* Common regulator configurations */
if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
pmic_data->vdac = &omap4_vdac_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VAUX2 && !pmic_data->vaux2)
pmic_data->vaux2 = &omap4_vaux2_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VAUX3 && !pmic_data->vaux3)
pmic_data->vaux3 = &omap4_vaux3_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VMMC && !pmic_data->vmmc)
pmic_data->vmmc = &omap4_vmmc_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VPP && !pmic_data->vpp)
pmic_data->vpp = &omap4_vpp_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VANA && !pmic_data->vana)
pmic_data->vana = &omap4_vana_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VCXIO && !pmic_data->vcxio)
pmic_data->vcxio = &omap4_vcxio_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VUSB && !pmic_data->vusb)
pmic_data->vusb = &omap4_vusb_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
!pmic_data->clk32kg)
pmic_data->clk32kg = &omap4_clk32kg_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_V1V8 && !pmic_data->v1v8)
pmic_data->v1v8 = &omap4_v1v8_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_V2V1 && !pmic_data->v2v1)
pmic_data->v2v1 = &omap4_v2v1_idata;
}
#endif /* CONFIG_ARCH_OMAP4 */
#if IS_ENABLED(CONFIG_SND_OMAP_SOC_OMAP_TWL4030)
#include <linux/platform_data/omap-twl4030.h>
/* Commonly used configuration */
static struct omap_tw4030_pdata omap_twl4030_audio_data;
static struct platform_device audio_device = {
.name = "omap-twl4030",
.id = -1,
};
void omap_twl4030_audio_init(char *card_name,
struct omap_tw4030_pdata *pdata)
{
if (!pdata)
pdata = &omap_twl4030_audio_data;
pdata->card_name = card_name;
audio_device.dev.platform_data = pdata;
platform_device_register(&audio_device);
}
#else /* SOC_OMAP_TWL4030 */
void omap_twl4030_audio_init(char *card_name,
struct omap_tw4030_pdata *pdata)
{
return;
}
#endif /* SOC_OMAP_TWL4030 */
arch/arm/mach-omap2/twl-common.h deleted 100644 → 0
View file @ a9fa1f7c
#ifndef __OMAP_PMIC_COMMON__
#define __OMAP_PMIC_COMMON__
#include "common.h"
#define TWL_COMMON_PDATA_USB (1 << 0)
#define TWL_COMMON_PDATA_BCI (1 << 1)
#define TWL_COMMON_PDATA_MADC (1 << 2)
#define TWL_COMMON_PDATA_AUDIO (1 << 3)
/* Common LDO regulators for TWL4030/TWL6030 */
#define TWL_COMMON_REGULATOR_VDAC (1 << 0)
#define TWL_COMMON_REGULATOR_VAUX1 (1 << 1)
#define TWL_COMMON_REGULATOR_VAUX2 (1 << 2)
#define TWL_COMMON_REGULATOR_VAUX3 (1 << 3)
/* TWL6030 LDO regulators */
#define TWL_COMMON_REGULATOR_VMMC (1 << 4)
#define TWL_COMMON_REGULATOR_VPP (1 << 5)
#define TWL_COMMON_REGULATOR_VUSIM (1 << 6)
#define TWL_COMMON_REGULATOR_VANA (1 << 7)
#define TWL_COMMON_REGULATOR_VCXIO (1 << 8)
#define TWL_COMMON_REGULATOR_VUSB (1 << 9)
#define TWL_COMMON_REGULATOR_CLK32KG (1 << 10)
#define TWL_COMMON_REGULATOR_V1V8 (1 << 11)
#define TWL_COMMON_REGULATOR_V2V1 (1 << 12)
/* TWL4030 LDO regulators */
#define TWL_COMMON_REGULATOR_VPLL1 (1 << 4)
#define TWL_COMMON_REGULATOR_VPLL2 (1 << 5)
struct twl4030_platform_data;
struct twl6040_platform_data;
struct omap_tw4030_pdata;
struct i2c_board_info;
void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
struct twl4030_platform_data *pmic_data);
void omap_pmic_late_init(void);
static inline void omap2_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data)
{
omap_pmic_init(2, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
}
static inline void omap3_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data)
{
omap_pmic_init(1, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
}
void omap4_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data,
struct i2c_board_info *devices, int nr_devices);
void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
u32 pdata_flags, u32 regulators_flags);
void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
u32 pdata_flags, u32 regulators_flags);
void omap_twl4030_audio_init(char *card_name, struct omap_tw4030_pdata *pdata);
#endif /* __OMAP_PMIC_COMMON__ */
arch/arm/mach-omap2/usb-host.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* usb-host.c - OMAP USB Host
*
* This file will contain the board specific details for the
* Synopsys EHCI/OHCI host controller on OMAP3430 and onwards
*
* Copyright (C) 2007-2011 Texas Instruments
* Author: Vikram Pandita <vikram.pandita@ti.com>
* Author: Keshava Munegowda <keshava_mgowda@ti.com>
*
* Generalization by:
* Felipe Balbi <balbi@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/string.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/usb/phy.h>
#include <linux/usb/usb_phy_generic.h>
#include "soc.h"
#include "omap_device.h"
#include "mux.h"
#include "usb.h"
#ifdef CONFIG_MFD_OMAP_USB_HOST
#define OMAP_USBHS_DEVICE "usbhs_omap"
#define OMAP_USBTLL_DEVICE "usbhs_tll"
#define USBHS_UHH_HWMODNAME "usb_host_hs"
#define USBHS_TLL_HWMODNAME "usb_tll_hs"
/* MUX settings for EHCI pins */
/*
* setup_ehci_io_mux - initialize IO pad mux for USBHOST
*/
static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
{
switch (port_mode[0]) {
case OMAP_EHCI_PORT_MODE_PHY:
omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_EHCI_PORT_MODE_TLL:
omap_mux_init_signal("hsusb1_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb1_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
switch (port_mode[1]) {
case OMAP_EHCI_PORT_MODE_PHY:
omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_EHCI_PORT_MODE_TLL:
omap_mux_init_signal("hsusb2_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb2_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
switch (port_mode[2]) {
case OMAP_EHCI_PORT_MODE_PHY:
printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
break;
case OMAP_EHCI_PORT_MODE_TLL:
omap_mux_init_signal("hsusb3_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb3_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
return;
}
static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
{
switch (port_mode[0]) {
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
omap_mux_init_signal("mm1_rxdp",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm1_rxdm",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
omap_mux_init_signal("mm1_rxrcv",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
omap_mux_init_signal("mm1_txen_n", OMAP_PIN_OUTPUT);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
omap_mux_init_signal("mm1_txse0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm1_txdat",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
switch (port_mode[1]) {
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
omap_mux_init_signal("mm2_rxdp",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm2_rxdm",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
omap_mux_init_signal("mm2_rxrcv",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
omap_mux_init_signal("mm2_txen_n", OMAP_PIN_OUTPUT);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
omap_mux_init_signal("mm2_txse0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm2_txdat",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
switch (port_mode[2]) {
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
omap_mux_init_signal("mm3_rxdp",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm3_rxdm",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
omap_mux_init_signal("mm3_rxrcv",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
omap_mux_init_signal("mm3_txen_n", OMAP_PIN_OUTPUT);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
omap_mux_init_signal("mm3_txse0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm3_txdat",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
}
void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
{
struct omap_hwmod *uhh_hwm, *tll_hwm;
struct platform_device *pdev;
int bus_id = -1;
if (cpu_is_omap34xx()) {
setup_ehci_io_mux(pdata->port_mode);
setup_ohci_io_mux(pdata->port_mode);
if (omap_rev() <= OMAP3430_REV_ES2_1)
pdata->single_ulpi_bypass = true;
}
uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
if (!uhh_hwm) {
pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
return;
}
tll_hwm = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
if (!tll_hwm) {
pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
return;
}
pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
pdata, sizeof(*pdata));
if (IS_ERR(pdev)) {
pr_err("Could not build hwmod device %s\n",
USBHS_TLL_HWMODNAME);
return;
}
pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
pdata, sizeof(*pdata));
if (IS_ERR(pdev)) {
pr_err("Could not build hwmod devices %s\n",
USBHS_UHH_HWMODNAME);
return;
}
}
#else
void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
{
}
#endif
/* Template for PHY regulators */
static struct fixed_voltage_config hsusb_reg_config = {
/* .supply_name filled later */
.microvolts = 3300000,
.gpio = -1, /* updated later */
.startup_delay = 70000, /* 70msec */
.enable_high = 1, /* updated later */
.enabled_at_boot = 0, /* keep in RESET */
/* .init_data filled later */
};
static const char *nop_name = "usb_phy_generic"; /* NOP PHY driver */
static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */
/**
* usbhs_add_regulator - Add a gpio based fixed voltage regulator device
* @name: name for the regulator
* @dev_id: device id of the device this regulator supplies power to
* @dev_supply: supply name that the device expects
* @gpio: GPIO number
* @polarity: 1 - Active high, 0 - Active low
*/
static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
int gpio, int polarity)
{
struct regulator_consumer_supply *supplies;
struct regulator_init_data *reg_data;
struct fixed_voltage_config *config;
struct platform_device *pdev;
struct platform_device_info pdevinfo;
int ret = -ENOMEM;
supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
if (!supplies)
return -ENOMEM;
supplies->supply = dev_supply;
supplies->dev_name = dev_id;
reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
if (!reg_data)
goto err_data;
reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
reg_data->consumer_supplies = supplies;
reg_data->num_consumer_supplies = 1;
config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
GFP_KERNEL);
if (!config)
goto err_config;
config->supply_name = kstrdup(name, GFP_KERNEL);
if (!config->supply_name)
goto err_supplyname;
config->gpio = gpio;
config->enable_high = polarity;
config->init_data = reg_data;
/* create a regulator device */
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo.name = reg_name;
pdevinfo.id = PLATFORM_DEVID_AUTO;
pdevinfo.data = config;
pdevinfo.size_data = sizeof(*config);
pdev = platform_device_register_full(&pdevinfo);
if (IS_ERR(pdev)) {
ret = PTR_ERR(pdev);
pr_err("%s: Failed registering regulator %s for %s : %d\n",
__func__, name, dev_id, ret);
goto err_register;
}
return 0;
err_register:
kfree(config->supply_name);
err_supplyname:
kfree(config);
err_config:
kfree(reg_data);
err_data:
kfree(supplies);
return ret;
}
#define MAX_STR 20
int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
{
char rail_name[MAX_STR];
int i;
struct platform_device *pdev;
char *phy_id;
struct platform_device_info pdevinfo;
struct usb_phy_generic_platform_data nop_pdata;
for (i = 0; i < num_phys; i++) {
if (!phy->port) {
pr_err("%s: Invalid port 0. Must start from 1\n",
__func__);
continue;
}
/* do we need a NOP PHY device ? */
if (!gpio_is_valid(phy->reset_gpio) &&
!gpio_is_valid(phy->vcc_gpio))
continue;
phy_id = kmalloc(MAX_STR, GFP_KERNEL);
if (!phy_id) {
pr_err("%s: kmalloc() failed\n", __func__);
return -ENOMEM;
}
/* set platform data */
memset(&nop_pdata, 0, sizeof(nop_pdata));
if (gpio_is_valid(phy->vcc_gpio))
nop_pdata.needs_vcc = true;
nop_pdata.gpio_reset = phy->reset_gpio;
nop_pdata.type = USB_PHY_TYPE_USB2;
/* create a NOP PHY device */
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo.name = nop_name;
pdevinfo.id = phy->port;
pdevinfo.data = &nop_pdata;
pdevinfo.size_data =
sizeof(struct usb_phy_generic_platform_data);
scnprintf(phy_id, MAX_STR, "usb_phy_generic.%d",
phy->port);
pdev = platform_device_register_full(&pdevinfo);
if (IS_ERR(pdev)) {
pr_err("%s: Failed to register device %s : %ld\n",
__func__, phy_id, PTR_ERR(pdev));
kfree(phy_id);
continue;
}
usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id);
/* Do we need VCC regulator ? */
if (gpio_is_valid(phy->vcc_gpio)) {
scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
usbhs_add_regulator(rail_name, phy_id, "vcc",
phy->vcc_gpio, phy->vcc_polarity);
}
phy++;
}
return 0;
}
arch/arm/mach-omap2/usb-musb.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* linux/arch/arm/mach-omap2/usb-musb.c
*
* This file will contain the board specific details for the
* MENTOR USB OTG controller on OMAP3430
*
* Copyright (C) 2007-2008 Texas Instruments
* Copyright (C) 2008 Nokia Corporation
* Author: Vikram Pandita
*
* Generalization by:
* Felipe Balbi <felipe.balbi@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/usb/musb.h>
#include "omap_device.h"
#include "soc.h"
#include "mux.h"
#include "usb.h"
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
.num_eps = 16,
.ram_bits = 12,
};
static struct musb_hdrc_platform_data musb_plat = {
.mode = MUSB_OTG,
/* .clock is set dynamically */
.config = &musb_config,
/* REVISIT charge pump on TWL4030 can supply up to
* 100 mA ... but this value is board-specific, like
* "mode", and should be passed to usb_musb_init().
*/
.power = 50, /* up to 100 mA */
};
static u64 musb_dmamask = DMA_BIT_MASK(32);
static struct omap_musb_board_data musb_default_board_data = {
.interface_type = MUSB_INTERFACE_ULPI,
.mode = MUSB_OTG,
.power = 100,
};
void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
struct device *dev;
int bus_id = -1;
const char *oh_name, *name;
struct omap_musb_board_data *board_data;
if (musb_board_data)
board_data = musb_board_data;
else
board_data = &musb_default_board_data;
/*
* REVISIT: This line can be removed once all the platforms using
* musb_core.c have been converted to use use clkdev.
*/
musb_plat.clock = "ick";
musb_plat.board_data = board_data;
musb_plat.power = board_data->power >> 1;
musb_plat.mode = board_data->mode;
musb_plat.extvbus = board_data->extvbus;
oh_name = "usb_otg_hs";
name = "musb-omap2430";
oh = omap_hwmod_lookup(oh_name);
if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
__func__, oh_name))
return;
pdev = omap_device_build(name, bus_id, oh, &musb_plat,
sizeof(musb_plat));
if (IS_ERR(pdev)) {
pr_err("Could not build omap_device for %s %s\n",
name, oh_name);
return;
}
dev = &pdev->dev;
get_device(dev);
dev->dma_mask = &musb_dmamask;
dev->coherent_dma_mask = musb_dmamask;
put_device(dev);
}
arch/arm/mach-omap2/usb-tusb6010.c
View file @ 6d1e66bb
...@@ -22,8 +22,6 @@ ...@@ -22,8 +22,6 @@
#include "gpmc.h" #include "gpmc.h"
#include "mux.h"
static u8 async_cs, sync_cs; static u8 async_cs, sync_cs;
static unsigned refclk_psec; static unsigned refclk_psec;
...@@ -226,25 +224,6 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data, ...@@ -226,25 +224,6 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
} }
tusb_device.dev.platform_data = data; tusb_device.dev.platform_data = data;
/* REVISIT let the driver know what DMA channels work */
if (!dmachan)
tusb_device.dev.dma_mask = NULL;
else {
/* assume OMAP 2420 ES2.0 and later */
if (dmachan & (1 << 0))
omap_mux_init_signal("sys_ndmareq0", 0);
if (dmachan & (1 << 1))
omap_mux_init_signal("sys_ndmareq1", 0);
if (dmachan & (1 << 2))
omap_mux_init_signal("sys_ndmareq2", 0);
if (dmachan & (1 << 3))
omap_mux_init_signal("sys_ndmareq3", 0);
if (dmachan & (1 << 4))
omap_mux_init_signal("sys_ndmareq4", 0);
if (dmachan & (1 << 5))
omap_mux_init_signal("sys_ndmareq5", 0);
}
/* so far so good ... register the device */ /* so far so good ... register the device */
status = platform_device_register(&tusb_device); status = platform_device_register(&tusb_device);
if (status < 0) { if (status < 0) {
......
arch/arm/plat-omap/Kconfig
View file @ 6d1e66bb
...@@ -63,32 +63,6 @@ config OMAP_RESET_CLOCKS ...@@ -63,32 +63,6 @@ config OMAP_RESET_CLOCKS
probably do not want this option enabled until your probably do not want this option enabled until your
device drivers work properly. device drivers work properly.
config OMAP_MUX
bool "OMAP multiplexing support"
depends on ARCH_OMAP
default y
help
Pin multiplexing support for OMAP boards. If your bootloader
sets the multiplexing correctly, say N. Otherwise, or if unsure,
say Y.
config OMAP_MUX_DEBUG
bool "Multiplexing debug output"
depends on OMAP_MUX
help
Makes the multiplexing functions print out a lot of debug info.
This is useful if you want to find out the correct values of the
multiplexing registers.
config OMAP_MUX_WARNINGS
bool "Warn about pins the bootloader didn't set up"
depends on OMAP_MUX
default y
help
Choose Y here to warn whenever driver initialization logic needs
to change the pin multiplexing setup. When there are no warnings
printed, it's safe to deselect OMAP_MUX for your product.
config OMAP_MPU_TIMER config OMAP_MPU_TIMER
bool "Use mpu timer" bool "Use mpu timer"
depends on ARCH_OMAP1 depends on ARCH_OMAP1
......
arch/arm/plat-omap/Makefile
View file @ 6d1e66bb
...@@ -11,6 +11,3 @@ obj-y := sram.o dma.o counter_32k.o ...@@ -11,6 +11,3 @@ obj-y := sram.o dma.o counter_32k.o
obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
obj-y += $(i2c-omap-m) $(i2c-omap-y)
arch/arm/plat-omap/i2c.c deleted 100644 → 0
View file @ a9fa1f7c
/*
* linux/arch/arm/plat-omap/i2c.c
*
* Helper module for board specific I2C bus registration
*
* Copyright (C) 2007 Nokia Corporation.
*
* Contact: Jarkko Nikula <jhnikula@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c-omap.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <plat/i2c.h>
#define OMAP_I2C_MAX_CONTROLLERS 4
static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
/**
* omap_i2c_bus_setup - Process command line options for the I2C bus speed
* @str: String of options
*
* This function allow to override the default I2C bus speed for given I2C
* bus with a command line option.
*
* Format: i2c_bus=bus_id,clkrate (in kHz)
*
* Returns 1 on success, 0 otherwise.
*/
static int __init omap_i2c_bus_setup(char *str)
{
int ints[3];
get_options(str, 3, ints);
if (ints[0] < 2 || ints[1] < 1 ||
ints[1] > OMAP_I2C_MAX_CONTROLLERS)
return 0;
i2c_pdata[ints[1] - 1].clkrate = ints[2];
i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
return 1;
}
__setup("i2c_bus=", omap_i2c_bus_setup);
/*
* Register busses defined in command line but that are not registered with
* omap_register_i2c_bus from board initialization code.
*/
int __init omap_register_i2c_bus_cmdline(void)
{
int i, err = 0;
for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
err = omap_i2c_add_bus(&i2c_pdata[i], i + 1);
if (err)
goto out;
}
out:
return err;
}
/**
* omap_register_i2c_bus - register I2C bus with device descriptors
* @bus_id: bus id counting from number 1
* @clkrate: clock rate of the bus in kHz
* @info: pointer into I2C device descriptor table or NULL
* @len: number of descriptors in the table
*
* Returns 0 on success or an error code.
*/
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
int err;
BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
if (info) {
err = i2c_register_board_info(bus_id, info, len);
if (err)
return err;
}
if (!i2c_pdata[bus_id - 1].clkrate)
i2c_pdata[bus_id - 1].clkrate = clkrate;
i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id);
}
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