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Commit 6df383cf authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

- fix display regression on DCE6/8
- Powergating fixes for GFX8
- amdgpu SI fixes (golden settings, proper rev id setup, etc.)

* 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (21 commits)
  drm/amdgpu: update tile table for oland/hainan
  drm/amdgpu: update tile table for verde
  drm/amdgpu: update rev id for verde
  drm/amdgpu: update golden setting for verde
  drm/amdgpu: update rev id for oland
  drm/amdgpu: update golden setting for oland
  drm/amdgpu: update rev id for hainan
  drm/amdgpu: update golden setting for hainan
  drm/amdgpu: update rev id for pitcairn
  drm/amdgpu: update golden setting for pitcairn
  drm/amdgpu: update golden setting/tiling table of tahiti
  drm/amdgpu: fix cursor setting of dce6/dce8
  drm/amdgpu: refine set clock gating for tonga/polaris
  drm/amdgpu: initialize cg flags for tonga/polaris10/polaris11.
  drm/amdgpu: add new gfx cg flags.
  drm/amdgpu: fix pg can't be disabled by PG mask.
  drm/amdgpu: always initialize gfx pg for gfx_v8.0.
  drm/amdgpu: enable AMD_PG_SUPPORT_CP in Carrizo/Stoney.
  drm/amdgpu: fix init save/restore list in gfx_v8.0
  drm/amdgpu: fix enable_cp_power_gating in gfx_v8.0.
  ...
parents 50f6584e f8d9422e
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Showing with 1218 additions and 631 deletions
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
View file @ 6df383cf
...@@ -1944,9 +1944,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, ...@@ -1944,9 +1944,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
dce_v6_0_lock_cursor(crtc, true); dce_v6_0_lock_cursor(crtc, true);
if (width != amdgpu_crtc->cursor_width || if (hot_x != amdgpu_crtc->cursor_hot_x ||
height != amdgpu_crtc->cursor_height ||
hot_x != amdgpu_crtc->cursor_hot_x ||
hot_y != amdgpu_crtc->cursor_hot_y) { hot_y != amdgpu_crtc->cursor_hot_y) {
int x, y; int x, y;
...@@ -1955,8 +1953,6 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, ...@@ -1955,8 +1953,6 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
dce_v6_0_cursor_move_locked(crtc, x, y); dce_v6_0_cursor_move_locked(crtc, x, y);
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
amdgpu_crtc->cursor_hot_x = hot_x; amdgpu_crtc->cursor_hot_x = hot_x;
amdgpu_crtc->cursor_hot_y = hot_y; amdgpu_crtc->cursor_hot_y = hot_y;
} }
......
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
View file @ 6df383cf
...@@ -2438,8 +2438,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, ...@@ -2438,8 +2438,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
dce_v8_0_cursor_move_locked(crtc, x, y); dce_v8_0_cursor_move_locked(crtc, x, y);
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
amdgpu_crtc->cursor_hot_x = hot_x; amdgpu_crtc->cursor_hot_x = hot_x;
amdgpu_crtc->cursor_hot_y = hot_y; amdgpu_crtc->cursor_hot_y = hot_y;
} }
......
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
View file @ 6df383cf
...@@ -411,244 +411,587 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) ...@@ -411,244 +411,587 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
break; break;
} }
if (adev->asic_type == CHIP_VERDE || if (adev->asic_type == CHIP_VERDE) {
adev->asic_type == CHIP_OLAND ||
adev->asic_type == CHIP_HAINAN) {
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
switch (reg_offset) { switch (reg_offset) {
case 0: case 0:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 1: case 1:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 2: case 2:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 3: case 3:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break; break;
case 4: case 4:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; break;
case 5: case 5:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(split_equal_to_row_size) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break; break;
case 6: case 6:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(split_equal_to_row_size) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break; break;
case 7: case 7:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(split_equal_to_row_size) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break; break;
case 8: case 8:
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; break;
case 9: case 9:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; break;
case 10: case 10:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 11: case 11:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 12: case 12:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 13: case 13:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; break;
case 14: case 14:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 15: case 15:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 16: case 16:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 17: case 17:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 18:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_1D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P4_8x16));
break;
case 19:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(split_equal_to_row_size) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 20:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break; break;
case 21: case 21:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break; break;
case 22: case 22:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 23:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 24:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 25:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 26:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 27:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 28:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 29:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 30:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
default:
continue;
}
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
}
} else if (adev->asic_type == CHIP_OLAND ||
adev->asic_type == CHIP_HAINAN) {
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 1:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 2:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 3:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 4:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2));
break;
case 5:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 6:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 7:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 8:
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
break;
case 9:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2));
break;
case 10:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 11:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 12:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 13:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2));
break;
case 14:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 15:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 16:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 17:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 18:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_1D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P2));
break;
case 19:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
PIPE_CONFIG(ADDR_SURF_P2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 20:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 21:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 22:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break; break;
case 23: case 23:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break; break;
case 24: case 24:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break; break;
case 25: case 25:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
NUM_BANKS(ADDR_SURF_8_BANK) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 26:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 27:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 28:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 29:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 30:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break; break;
default: default:
gb_tile_moden = 0; continue;
break;
} }
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
...@@ -656,239 +999,291 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) ...@@ -656,239 +999,291 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
} else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
switch (reg_offset) { switch (reg_offset) {
case 0: /* non-AA compressed depth or any compressed stencil */ case 0:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 1: /* 2xAA/4xAA compressed depth only */ case 1:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 2: /* 8xAA compressed depth only */ case 2:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ case 3:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break; break;
case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ case 4:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; break;
case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ case 5:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(split_equal_to_row_size) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break; break;
case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ case 6:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(split_equal_to_row_size) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break; break;
case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ case 7:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(split_equal_to_row_size) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break; break;
case 8: /* 1D and 1D Array Surfaces */ case 8:
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; break;
case 9: /* Displayable maps. */ case 9:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; break;
case 10: /* Display 8bpp. */ case 10:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 11: /* Display 16bpp. */ case 11:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 12: /* Display 32bpp. */ case 12:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 13: /* Thin. */ case 13:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; break;
case 14: /* Thin 8 bpp. */ case 14:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 15: /* Thin 16 bpp. */ case 15:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 16: /* Thin 32 bpp. */ case 16:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK));
break; break;
case 17: /* Thin 64 bpp. */ case 17:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(split_equal_to_row_size) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 18:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_1D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
break;
case 19:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break; break;
case 21: /* 8 bpp PRT. */ case 20:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | TILE_SPLIT(split_equal_to_row_size));
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
break; break;
case 22: /* 16 bpp PRT */ case 21:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 22:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break; break;
case 23: /* 32 bpp PRT */ case 23:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break; break;
case 24: /* 64 bpp PRT */ case 24:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break; break;
case 25: /* 128 bpp PRT */ case 25:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
NUM_BANKS(ADDR_SURF_8_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break; break;
default: case 26:
gb_tile_moden = 0; gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 27:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 28:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break; break;
case 29:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 30:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
default:
continue;
} }
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
......
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View file @ 6df383cf
...@@ -3949,8 +3949,12 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) ...@@ -3949,8 +3949,12 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
temp = mmRLC_SRM_INDEX_CNTL_ADDR_0; temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
data = mmRLC_SRM_INDEX_CNTL_DATA_0; data = mmRLC_SRM_INDEX_CNTL_DATA_0;
for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) { for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false); if (unique_indices[i] != 0) {
amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false); amdgpu_mm_wreg(adev, temp + i,
unique_indices[i] & 0x3FFFF, false);
amdgpu_mm_wreg(adev, data + i,
unique_indices[i] >> 20, false);
}
} }
kfree(register_list_format); kfree(register_list_format);
...@@ -3966,20 +3970,17 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev) ...@@ -3966,20 +3970,17 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
{ {
uint32_t data; uint32_t data;
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
AMD_PG_SUPPORT_GFX_SMG |
AMD_PG_SUPPORT_GFX_DMG)) {
WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10); data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10); data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10); data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10); data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
WREG32(mmRLC_PG_DELAY, data); WREG32(mmRLC_PG_DELAY, data);
WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
}
} }
static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
...@@ -3996,41 +3997,37 @@ static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, ...@@ -3996,41 +3997,37 @@ static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable) static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
{ {
WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0); WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
} }
static void gfx_v8_0_init_pg(struct amdgpu_device *adev) static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
{ {
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | if ((adev->asic_type == CHIP_CARRIZO) ||
AMD_PG_SUPPORT_GFX_SMG | (adev->asic_type == CHIP_STONEY)) {
AMD_PG_SUPPORT_GFX_DMG |
AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_GDS |
AMD_PG_SUPPORT_RLC_SMU_HS)) {
gfx_v8_0_init_csb(adev); gfx_v8_0_init_csb(adev);
gfx_v8_0_init_save_restore_list(adev); gfx_v8_0_init_save_restore_list(adev);
gfx_v8_0_enable_save_restore_machine(adev); gfx_v8_0_enable_save_restore_machine(adev);
WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
if ((adev->asic_type == CHIP_CARRIZO) || gfx_v8_0_init_power_gating(adev);
(adev->asic_type == CHIP_STONEY)) { WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
gfx_v8_0_init_power_gating(adev); cz_enable_sck_slow_down_on_power_up(adev, true);
WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); cz_enable_sck_slow_down_on_power_down(adev, true);
if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { } else {
cz_enable_sck_slow_down_on_power_up(adev, true); cz_enable_sck_slow_down_on_power_up(adev, false);
cz_enable_sck_slow_down_on_power_down(adev, true); cz_enable_sck_slow_down_on_power_down(adev, false);
} else {
cz_enable_sck_slow_down_on_power_up(adev, false);
cz_enable_sck_slow_down_on_power_down(adev, false);
}
if (adev->pg_flags & AMD_PG_SUPPORT_CP)
cz_enable_cp_power_gating(adev, true);
else
cz_enable_cp_power_gating(adev, false);
} else if (adev->asic_type == CHIP_POLARIS11) {
gfx_v8_0_init_power_gating(adev);
} }
if (adev->pg_flags & AMD_PG_SUPPORT_CP)
cz_enable_cp_power_gating(adev, true);
else
cz_enable_cp_power_gating(adev, false);
} else if (adev->asic_type == CHIP_POLARIS11) {
gfx_v8_0_init_csb(adev);
gfx_v8_0_init_save_restore_list(adev);
gfx_v8_0_enable_save_restore_machine(adev);
gfx_v8_0_init_power_gating(adev);
} }
} }
static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
...@@ -5339,14 +5336,11 @@ static int gfx_v8_0_set_powergating_state(void *handle, ...@@ -5339,14 +5336,11 @@ static int gfx_v8_0_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = (state == AMD_PG_STATE_GATE) ? true : false; bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
return 0;
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_CARRIZO: case CHIP_CARRIZO:
case CHIP_STONEY: case CHIP_STONEY:
if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
cz_update_gfx_cg_power_gating(adev, enable); cz_update_gfx_cg_power_gating(adev, enable);
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true); gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
...@@ -5791,25 +5785,49 @@ static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev, ...@@ -5791,25 +5785,49 @@ static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
enum amd_clockgating_state state) enum amd_clockgating_state state)
{ {
uint32_t msg_id, pp_state; uint32_t msg_id, pp_state = 0;
uint32_t pp_support_state = 0;
void *pp_handle = adev->powerplay.pp_handle; void *pp_handle = adev->powerplay.pp_handle;
if (state == AMD_CG_STATE_UNGATE) if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
pp_state = 0; if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
else pp_support_state = PP_STATE_SUPPORT_LS;
pp_state = PP_STATE_CG | PP_STATE_LS; pp_state = PP_STATE_LS;
}
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
pp_support_state |= PP_STATE_SUPPORT_CG;
pp_state |= PP_STATE_CG;
}
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
PP_BLOCK_GFX_CG,
pp_support_state,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
PP_BLOCK_GFX_CG, if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, pp_support_state = PP_STATE_SUPPORT_LS;
pp_state); pp_state = PP_STATE_LS;
amd_set_clockgating_by_smu(pp_handle, msg_id); }
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
PP_BLOCK_GFX_MG, pp_support_state |= PP_STATE_SUPPORT_CG;
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, pp_state |= PP_STATE_CG;
pp_state); }
amd_set_clockgating_by_smu(pp_handle, msg_id);
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
PP_BLOCK_GFX_MG,
pp_support_state,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
return 0; return 0;
} }
...@@ -5817,43 +5835,98 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, ...@@ -5817,43 +5835,98 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
enum amd_clockgating_state state) enum amd_clockgating_state state)
{ {
uint32_t msg_id, pp_state;
uint32_t msg_id, pp_state = 0;
uint32_t pp_support_state = 0;
void *pp_handle = adev->powerplay.pp_handle; void *pp_handle = adev->powerplay.pp_handle;
if (state == AMD_CG_STATE_UNGATE) if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
pp_state = 0; if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
else pp_support_state = PP_STATE_SUPPORT_LS;
pp_state = PP_STATE_CG | PP_STATE_LS; pp_state = PP_STATE_LS;
}
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
pp_support_state |= PP_STATE_SUPPORT_CG;
pp_state |= PP_STATE_CG;
}
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
PP_BLOCK_GFX_CG,
pp_support_state,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
PP_BLOCK_GFX_CG, if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, pp_support_state = PP_STATE_SUPPORT_LS;
pp_state); pp_state = PP_STATE_LS;
amd_set_clockgating_by_smu(pp_handle, msg_id); }
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
pp_support_state |= PP_STATE_SUPPORT_CG;
pp_state |= PP_STATE_CG;
}
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
PP_BLOCK_GFX_3D,
pp_support_state,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
PP_BLOCK_GFX_3D, if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, pp_support_state = PP_STATE_SUPPORT_LS;
pp_state); pp_state = PP_STATE_LS;
amd_set_clockgating_by_smu(pp_handle, msg_id); }
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
PP_BLOCK_GFX_MG, pp_support_state |= PP_STATE_SUPPORT_CG;
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, pp_state |= PP_STATE_CG;
pp_state); }
amd_set_clockgating_by_smu(pp_handle, msg_id);
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, if (state == AMD_CG_STATE_UNGATE)
PP_BLOCK_GFX_RLC, pp_state = 0;
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
pp_state); msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
amd_set_clockgating_by_smu(pp_handle, msg_id); PP_BLOCK_GFX_MG,
pp_support_state,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
pp_support_state = PP_STATE_SUPPORT_LS;
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
else
pp_state = PP_STATE_LS;
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
PP_BLOCK_GFX_RLC,
pp_support_state,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
pp_support_state = PP_STATE_SUPPORT_LS;
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
else
pp_state = PP_STATE_LS;
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
PP_BLOCK_GFX_CP, PP_BLOCK_GFX_CP,
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, pp_support_state,
pp_state); pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id); amd_set_clockgating_by_smu(pp_handle, msg_id);
}
return 0; return 0;
} }
......
drivers/gpu/drm/amd/amdgpu/si.c
View file @ 6df383cf
...@@ -43,13 +43,14 @@ ...@@ -43,13 +43,14 @@
static const u32 tahiti_golden_registers[] = static const u32 tahiti_golden_registers[] =
{ {
0x17bc, 0x00000030, 0x00000011,
0x2684, 0x00010000, 0x00018208, 0x2684, 0x00010000, 0x00018208,
0x260c, 0xffffffff, 0x00000000, 0x260c, 0xffffffff, 0x00000000,
0x260d, 0xf00fffff, 0x00000400, 0x260d, 0xf00fffff, 0x00000400,
0x260e, 0x0002021c, 0x00020200, 0x260e, 0x0002021c, 0x00020200,
0x031e, 0x00000080, 0x00000000, 0x031e, 0x00000080, 0x00000000,
0x340c, 0x000300c0, 0x00800040, 0x340c, 0x000000c0, 0x00800040,
0x360c, 0x000300c0, 0x00800040, 0x360c, 0x000000c0, 0x00800040,
0x16ec, 0x000000f0, 0x00000070, 0x16ec, 0x000000f0, 0x00000070,
0x16f0, 0x00200000, 0x50100000, 0x16f0, 0x00200000, 0x50100000,
0x1c0c, 0x31000311, 0x00000011, 0x1c0c, 0x31000311, 0x00000011,
...@@ -60,7 +61,7 @@ static const u32 tahiti_golden_registers[] = ...@@ -60,7 +61,7 @@ static const u32 tahiti_golden_registers[] =
0x22c4, 0x0000ff0f, 0x00000000, 0x22c4, 0x0000ff0f, 0x00000000,
0xa293, 0x07ffffff, 0x4e000000, 0xa293, 0x07ffffff, 0x4e000000,
0xa0d4, 0x3f3f3fff, 0x2a00126a, 0xa0d4, 0x3f3f3fff, 0x2a00126a,
0x000c, 0x000000ff, 0x0040, 0x000c, 0xffffffff, 0x0040,
0x000d, 0x00000040, 0x00004040, 0x000d, 0x00000040, 0x00004040,
0x2440, 0x07ffffff, 0x03000000, 0x2440, 0x07ffffff, 0x03000000,
0x23a2, 0x01ff1f3f, 0x00000000, 0x23a2, 0x01ff1f3f, 0x00000000,
...@@ -73,7 +74,11 @@ static const u32 tahiti_golden_registers[] = ...@@ -73,7 +74,11 @@ static const u32 tahiti_golden_registers[] =
0x2234, 0xffffffff, 0x000fff40, 0x2234, 0xffffffff, 0x000fff40,
0x2235, 0x0000001f, 0x00000010, 0x2235, 0x0000001f, 0x00000010,
0x0504, 0x20000000, 0x20fffed8, 0x0504, 0x20000000, 0x20fffed8,
0x0570, 0x000c0fc0, 0x000c0400 0x0570, 0x000c0fc0, 0x000c0400,
0x052c, 0x0fffffff, 0xffffffff,
0x052d, 0x0fffffff, 0x0fffffff,
0x052e, 0x0fffffff, 0x0fffffff,
0x052f, 0x0fffffff, 0x0fffffff
}; };
static const u32 tahiti_golden_registers2[] = static const u32 tahiti_golden_registers2[] =
...@@ -83,16 +88,18 @@ static const u32 tahiti_golden_registers2[] = ...@@ -83,16 +88,18 @@ static const u32 tahiti_golden_registers2[] =
static const u32 tahiti_golden_rlc_registers[] = static const u32 tahiti_golden_rlc_registers[] =
{ {
0x263e, 0xffffffff, 0x12011003,
0x3109, 0xffffffff, 0x00601005, 0x3109, 0xffffffff, 0x00601005,
0x311f, 0xffffffff, 0x10104040, 0x311f, 0xffffffff, 0x10104040,
0x3122, 0xffffffff, 0x0100000a, 0x3122, 0xffffffff, 0x0100000a,
0x30c5, 0xffffffff, 0x00000800, 0x30c5, 0xffffffff, 0x00000800,
0x30c3, 0xffffffff, 0x800000f4, 0x30c3, 0xffffffff, 0x800000f4,
0x3d2a, 0xffffffff, 0x00000000 0x3d2a, 0x00000008, 0x00000000
}; };
static const u32 pitcairn_golden_registers[] = static const u32 pitcairn_golden_registers[] =
{ {
0x17bc, 0x00000030, 0x00000011,
0x2684, 0x00010000, 0x00018208, 0x2684, 0x00010000, 0x00018208,
0x260c, 0xffffffff, 0x00000000, 0x260c, 0xffffffff, 0x00000000,
0x260d, 0xf00fffff, 0x00000400, 0x260d, 0xf00fffff, 0x00000400,
...@@ -110,7 +117,7 @@ static const u32 pitcairn_golden_registers[] = ...@@ -110,7 +117,7 @@ static const u32 pitcairn_golden_registers[] =
0x22c4, 0x0000ff0f, 0x00000000, 0x22c4, 0x0000ff0f, 0x00000000,
0xa293, 0x07ffffff, 0x4e000000, 0xa293, 0x07ffffff, 0x4e000000,
0xa0d4, 0x3f3f3fff, 0x2a00126a, 0xa0d4, 0x3f3f3fff, 0x2a00126a,
0x000c, 0x000000ff, 0x0040, 0x000c, 0xffffffff, 0x0040,
0x000d, 0x00000040, 0x00004040, 0x000d, 0x00000040, 0x00004040,
0x2440, 0x07ffffff, 0x03000000, 0x2440, 0x07ffffff, 0x03000000,
0x2418, 0x0000007f, 0x00000020, 0x2418, 0x0000007f, 0x00000020,
...@@ -119,11 +126,16 @@ static const u32 pitcairn_golden_registers[] = ...@@ -119,11 +126,16 @@ static const u32 pitcairn_golden_registers[] =
0x2b04, 0xffffffff, 0x00000000, 0x2b04, 0xffffffff, 0x00000000,
0x2b03, 0xffffffff, 0x32761054, 0x2b03, 0xffffffff, 0x32761054,
0x2235, 0x0000001f, 0x00000010, 0x2235, 0x0000001f, 0x00000010,
0x0570, 0x000c0fc0, 0x000c0400 0x0570, 0x000c0fc0, 0x000c0400,
0x052c, 0x0fffffff, 0xffffffff,
0x052d, 0x0fffffff, 0x0fffffff,
0x052e, 0x0fffffff, 0x0fffffff,
0x052f, 0x0fffffff, 0x0fffffff
}; };
static const u32 pitcairn_golden_rlc_registers[] = static const u32 pitcairn_golden_rlc_registers[] =
{ {
0x263e, 0xffffffff, 0x12011003,
0x3109, 0xffffffff, 0x00601004, 0x3109, 0xffffffff, 0x00601004,
0x311f, 0xffffffff, 0x10102020, 0x311f, 0xffffffff, 0x10102020,
0x3122, 0xffffffff, 0x01000020, 0x3122, 0xffffffff, 0x01000020,
...@@ -133,133 +145,134 @@ static const u32 pitcairn_golden_rlc_registers[] = ...@@ -133,133 +145,134 @@ static const u32 pitcairn_golden_rlc_registers[] =
static const u32 verde_pg_init[] = static const u32 verde_pg_init[] =
{ {
0xd4f, 0xffffffff, 0x40000, 0x0d4f, 0xffffffff, 0x40000,
0xd4e, 0xffffffff, 0x200010ff, 0x0d4e, 0xffffffff, 0x200010ff,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x7007, 0x0d4f, 0xffffffff, 0x7007,
0xd4e, 0xffffffff, 0x300010ff, 0x0d4e, 0xffffffff, 0x300010ff,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x400000, 0x0d4f, 0xffffffff, 0x400000,
0xd4e, 0xffffffff, 0x100010ff, 0x0d4e, 0xffffffff, 0x100010ff,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x120200, 0x0d4f, 0xffffffff, 0x120200,
0xd4e, 0xffffffff, 0x500010ff, 0x0d4e, 0xffffffff, 0x500010ff,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x1e1e16, 0x0d4f, 0xffffffff, 0x1e1e16,
0xd4e, 0xffffffff, 0x600010ff, 0x0d4e, 0xffffffff, 0x600010ff,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x171f1e, 0x0d4f, 0xffffffff, 0x171f1e,
0xd4e, 0xffffffff, 0x700010ff, 0x0d4e, 0xffffffff, 0x700010ff,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4f, 0xffffffff, 0x0, 0x0d4f, 0xffffffff, 0x0,
0xd4e, 0xffffffff, 0x9ff, 0x0d4e, 0xffffffff, 0x9ff,
0xd40, 0xffffffff, 0x0, 0x0d40, 0xffffffff, 0x0,
0xd41, 0xffffffff, 0x10000800, 0x0d41, 0xffffffff, 0x10000800,
0xd41, 0xffffffff, 0xf, 0x0d41, 0xffffffff, 0xf,
0xd41, 0xffffffff, 0xf, 0x0d41, 0xffffffff, 0xf,
0xd40, 0xffffffff, 0x4, 0x0d40, 0xffffffff, 0x4,
0xd41, 0xffffffff, 0x1000051e, 0x0d41, 0xffffffff, 0x1000051e,
0xd41, 0xffffffff, 0xffff, 0x0d41, 0xffffffff, 0xffff,
0xd41, 0xffffffff, 0xffff, 0x0d41, 0xffffffff, 0xffff,
0xd40, 0xffffffff, 0x8, 0x0d40, 0xffffffff, 0x8,
0xd41, 0xffffffff, 0x80500, 0x0d41, 0xffffffff, 0x80500,
0xd40, 0xffffffff, 0x12, 0x0d40, 0xffffffff, 0x12,
0xd41, 0xffffffff, 0x9050c, 0x0d41, 0xffffffff, 0x9050c,
0xd40, 0xffffffff, 0x1d, 0x0d40, 0xffffffff, 0x1d,
0xd41, 0xffffffff, 0xb052c, 0x0d41, 0xffffffff, 0xb052c,
0xd40, 0xffffffff, 0x2a, 0x0d40, 0xffffffff, 0x2a,
0xd41, 0xffffffff, 0x1053e, 0x0d41, 0xffffffff, 0x1053e,
0xd40, 0xffffffff, 0x2d, 0x0d40, 0xffffffff, 0x2d,
0xd41, 0xffffffff, 0x10546, 0x0d41, 0xffffffff, 0x10546,
0xd40, 0xffffffff, 0x30, 0x0d40, 0xffffffff, 0x30,
0xd41, 0xffffffff, 0xa054e, 0x0d41, 0xffffffff, 0xa054e,
0xd40, 0xffffffff, 0x3c, 0x0d40, 0xffffffff, 0x3c,
0xd41, 0xffffffff, 0x1055f, 0x0d41, 0xffffffff, 0x1055f,
0xd40, 0xffffffff, 0x3f, 0x0d40, 0xffffffff, 0x3f,
0xd41, 0xffffffff, 0x10567, 0x0d41, 0xffffffff, 0x10567,
0xd40, 0xffffffff, 0x42, 0x0d40, 0xffffffff, 0x42,
0xd41, 0xffffffff, 0x1056f, 0x0d41, 0xffffffff, 0x1056f,
0xd40, 0xffffffff, 0x45, 0x0d40, 0xffffffff, 0x45,
0xd41, 0xffffffff, 0x10572, 0x0d41, 0xffffffff, 0x10572,
0xd40, 0xffffffff, 0x48, 0x0d40, 0xffffffff, 0x48,
0xd41, 0xffffffff, 0x20575, 0x0d41, 0xffffffff, 0x20575,
0xd40, 0xffffffff, 0x4c, 0x0d40, 0xffffffff, 0x4c,
0xd41, 0xffffffff, 0x190801, 0x0d41, 0xffffffff, 0x190801,
0xd40, 0xffffffff, 0x67, 0x0d40, 0xffffffff, 0x67,
0xd41, 0xffffffff, 0x1082a, 0x0d41, 0xffffffff, 0x1082a,
0xd40, 0xffffffff, 0x6a, 0x0d40, 0xffffffff, 0x6a,
0xd41, 0xffffffff, 0x1b082d, 0x0d41, 0xffffffff, 0x1b082d,
0xd40, 0xffffffff, 0x87, 0x0d40, 0xffffffff, 0x87,
0xd41, 0xffffffff, 0x310851, 0x0d41, 0xffffffff, 0x310851,
0xd40, 0xffffffff, 0xba, 0x0d40, 0xffffffff, 0xba,
0xd41, 0xffffffff, 0x891, 0x0d41, 0xffffffff, 0x891,
0xd40, 0xffffffff, 0xbc, 0x0d40, 0xffffffff, 0xbc,
0xd41, 0xffffffff, 0x893, 0x0d41, 0xffffffff, 0x893,
0xd40, 0xffffffff, 0xbe, 0x0d40, 0xffffffff, 0xbe,
0xd41, 0xffffffff, 0x20895, 0x0d41, 0xffffffff, 0x20895,
0xd40, 0xffffffff, 0xc2, 0x0d40, 0xffffffff, 0xc2,
0xd41, 0xffffffff, 0x20899, 0x0d41, 0xffffffff, 0x20899,
0xd40, 0xffffffff, 0xc6, 0x0d40, 0xffffffff, 0xc6,
0xd41, 0xffffffff, 0x2089d, 0x0d41, 0xffffffff, 0x2089d,
0xd40, 0xffffffff, 0xca, 0x0d40, 0xffffffff, 0xca,
0xd41, 0xffffffff, 0x8a1, 0x0d41, 0xffffffff, 0x8a1,
0xd40, 0xffffffff, 0xcc, 0x0d40, 0xffffffff, 0xcc,
0xd41, 0xffffffff, 0x8a3, 0x0d41, 0xffffffff, 0x8a3,
0xd40, 0xffffffff, 0xce, 0x0d40, 0xffffffff, 0xce,
0xd41, 0xffffffff, 0x308a5, 0x0d41, 0xffffffff, 0x308a5,
0xd40, 0xffffffff, 0xd3, 0x0d40, 0xffffffff, 0xd3,
0xd41, 0xffffffff, 0x6d08cd, 0x0d41, 0xffffffff, 0x6d08cd,
0xd40, 0xffffffff, 0x142, 0x0d40, 0xffffffff, 0x142,
0xd41, 0xffffffff, 0x2000095a, 0x0d41, 0xffffffff, 0x2000095a,
0xd41, 0xffffffff, 0x1, 0x0d41, 0xffffffff, 0x1,
0xd40, 0xffffffff, 0x144, 0x0d40, 0xffffffff, 0x144,
0xd41, 0xffffffff, 0x301f095b, 0x0d41, 0xffffffff, 0x301f095b,
0xd40, 0xffffffff, 0x165, 0x0d40, 0xffffffff, 0x165,
0xd41, 0xffffffff, 0xc094d, 0x0d41, 0xffffffff, 0xc094d,
0xd40, 0xffffffff, 0x173, 0x0d40, 0xffffffff, 0x173,
0xd41, 0xffffffff, 0xf096d, 0x0d41, 0xffffffff, 0xf096d,
0xd40, 0xffffffff, 0x184, 0x0d40, 0xffffffff, 0x184,
0xd41, 0xffffffff, 0x15097f, 0x0d41, 0xffffffff, 0x15097f,
0xd40, 0xffffffff, 0x19b, 0x0d40, 0xffffffff, 0x19b,
0xd41, 0xffffffff, 0xc0998, 0x0d41, 0xffffffff, 0xc0998,
0xd40, 0xffffffff, 0x1a9, 0x0d40, 0xffffffff, 0x1a9,
0xd41, 0xffffffff, 0x409a7, 0x0d41, 0xffffffff, 0x409a7,
0xd40, 0xffffffff, 0x1af, 0x0d40, 0xffffffff, 0x1af,
0xd41, 0xffffffff, 0xcdc, 0x0d41, 0xffffffff, 0xcdc,
0xd40, 0xffffffff, 0x1b1, 0x0d40, 0xffffffff, 0x1b1,
0xd41, 0xffffffff, 0x800, 0x0d41, 0xffffffff, 0x800,
0xd42, 0xffffffff, 0x6c9b2000, 0x0d42, 0xffffffff, 0x6c9b2000,
0xd44, 0xfc00, 0x2000, 0x0d44, 0xfc00, 0x2000,
0xd51, 0xffffffff, 0xfc0, 0x0d51, 0xffffffff, 0xfc0,
0xa35, 0x00000100, 0x100 0x0a35, 0x00000100, 0x100
}; };
static const u32 verde_golden_rlc_registers[] = static const u32 verde_golden_rlc_registers[] =
{ {
0x263e, 0xffffffff, 0x02010002,
0x3109, 0xffffffff, 0x033f1005, 0x3109, 0xffffffff, 0x033f1005,
0x311f, 0xffffffff, 0x10808020, 0x311f, 0xffffffff, 0x10808020,
0x3122, 0xffffffff, 0x00800008, 0x3122, 0xffffffff, 0x00800008,
...@@ -269,65 +282,45 @@ static const u32 verde_golden_rlc_registers[] = ...@@ -269,65 +282,45 @@ static const u32 verde_golden_rlc_registers[] =
static const u32 verde_golden_registers[] = static const u32 verde_golden_registers[] =
{ {
0x17bc, 0x00000030, 0x00000011,
0x2684, 0x00010000, 0x00018208, 0x2684, 0x00010000, 0x00018208,
0x260c, 0xffffffff, 0x00000000, 0x260c, 0xffffffff, 0x00000000,
0x260d, 0xf00fffff, 0x00000400, 0x260d, 0xf00fffff, 0x00000400,
0x260e, 0x0002021c, 0x00020200, 0x260e, 0x0002021c, 0x00020200,
0x031e, 0x00000080, 0x00000000, 0x031e, 0x00000080, 0x00000000,
0x340c, 0x000300c0, 0x00800040, 0x340c, 0x000300c0, 0x00800040,
0x340c, 0x000300c0, 0x00800040,
0x360c, 0x000300c0, 0x00800040,
0x360c, 0x000300c0, 0x00800040, 0x360c, 0x000300c0, 0x00800040,
0x16ec, 0x000000f0, 0x00000070, 0x16ec, 0x000000f0, 0x00000070,
0x16f0, 0x00200000, 0x50100000, 0x16f0, 0x00200000, 0x50100000,
0x1c0c, 0x31000311, 0x00000011, 0x1c0c, 0x31000311, 0x00000011,
0x0ab9, 0x00073ffe, 0x000022a2, 0x0ab9, 0x00073ffe, 0x000022a2,
0x0ab9, 0x00073ffe, 0x000022a2,
0x0ab9, 0x00073ffe, 0x000022a2,
0x0903, 0x000007ff, 0x00000000,
0x0903, 0x000007ff, 0x00000000,
0x0903, 0x000007ff, 0x00000000, 0x0903, 0x000007ff, 0x00000000,
0x2285, 0xf000001f, 0x00000007, 0x2285, 0xf000001f, 0x00000007,
0x2285, 0xf000001f, 0x00000007, 0x22c9, 0xffffffff, 0x00ffffff,
0x2285, 0xf000001f, 0x00000007,
0x2285, 0xffffffff, 0x00ffffff,
0x22c4, 0x0000ff0f, 0x00000000, 0x22c4, 0x0000ff0f, 0x00000000,
0xa293, 0x07ffffff, 0x4e000000, 0xa293, 0x07ffffff, 0x4e000000,
0xa0d4, 0x3f3f3fff, 0x0000124a, 0xa0d4, 0x3f3f3fff, 0x0000124a,
0xa0d4, 0x3f3f3fff, 0x0000124a, 0x000c, 0xffffffff, 0x0040,
0xa0d4, 0x3f3f3fff, 0x0000124a,
0x000c, 0x000000ff, 0x0040,
0x000d, 0x00000040, 0x00004040, 0x000d, 0x00000040, 0x00004040,
0x2440, 0x07ffffff, 0x03000000, 0x2440, 0x07ffffff, 0x03000000,
0x2440, 0x07ffffff, 0x03000000,
0x23a2, 0x01ff1f3f, 0x00000000,
0x23a3, 0x01ff1f3f, 0x00000000,
0x23a2, 0x01ff1f3f, 0x00000000, 0x23a2, 0x01ff1f3f, 0x00000000,
0x23a1, 0x01ff1f3f, 0x00000000,
0x23a1, 0x01ff1f3f, 0x00000000,
0x23a1, 0x01ff1f3f, 0x00000000, 0x23a1, 0x01ff1f3f, 0x00000000,
0x2418, 0x0000007f, 0x00000020, 0x2418, 0x0000007f, 0x00000020,
0x2542, 0x00010000, 0x00010000, 0x2542, 0x00010000, 0x00010000,
0x2b01, 0x000003ff, 0x00000003,
0x2b05, 0x000003ff, 0x00000003,
0x2b05, 0x000003ff, 0x00000003, 0x2b05, 0x000003ff, 0x00000003,
0x2b04, 0xffffffff, 0x00000000, 0x2b04, 0xffffffff, 0x00000000,
0x2b04, 0xffffffff, 0x00000000,
0x2b04, 0xffffffff, 0x00000000,
0x2b03, 0xffffffff, 0x00001032,
0x2b03, 0xffffffff, 0x00001032,
0x2b03, 0xffffffff, 0x00001032, 0x2b03, 0xffffffff, 0x00001032,
0x2235, 0x0000001f, 0x00000010, 0x2235, 0x0000001f, 0x00000010,
0x2235, 0x0000001f, 0x00000010, 0x0570, 0x000c0fc0, 0x000c0400,
0x2235, 0x0000001f, 0x00000010, 0x052c, 0x0fffffff, 0xffffffff,
0x0570, 0x000c0fc0, 0x000c0400 0x052d, 0x0fffffff, 0x0fffffff,
0x052e, 0x0fffffff, 0x0fffffff,
0x052f, 0x0fffffff, 0x0fffffff
}; };
static const u32 oland_golden_registers[] = static const u32 oland_golden_registers[] =
{ {
0x17bc, 0x00000030, 0x00000011,
0x2684, 0x00010000, 0x00018208, 0x2684, 0x00010000, 0x00018208,
0x260c, 0xffffffff, 0x00000000, 0x260c, 0xffffffff, 0x00000000,
0x260d, 0xf00fffff, 0x00000400, 0x260d, 0xf00fffff, 0x00000400,
...@@ -336,7 +329,7 @@ static const u32 oland_golden_registers[] = ...@@ -336,7 +329,7 @@ static const u32 oland_golden_registers[] =
0x340c, 0x000300c0, 0x00800040, 0x340c, 0x000300c0, 0x00800040,
0x360c, 0x000300c0, 0x00800040, 0x360c, 0x000300c0, 0x00800040,
0x16ec, 0x000000f0, 0x00000070, 0x16ec, 0x000000f0, 0x00000070,
0x16f9, 0x00200000, 0x50100000, 0x16f0, 0x00200000, 0x50100000,
0x1c0c, 0x31000311, 0x00000011, 0x1c0c, 0x31000311, 0x00000011,
0x0ab9, 0x00073ffe, 0x000022a2, 0x0ab9, 0x00073ffe, 0x000022a2,
0x0903, 0x000007ff, 0x00000000, 0x0903, 0x000007ff, 0x00000000,
...@@ -345,7 +338,7 @@ static const u32 oland_golden_registers[] = ...@@ -345,7 +338,7 @@ static const u32 oland_golden_registers[] =
0x22c4, 0x0000ff0f, 0x00000000, 0x22c4, 0x0000ff0f, 0x00000000,
0xa293, 0x07ffffff, 0x4e000000, 0xa293, 0x07ffffff, 0x4e000000,
0xa0d4, 0x3f3f3fff, 0x00000082, 0xa0d4, 0x3f3f3fff, 0x00000082,
0x000c, 0x000000ff, 0x0040, 0x000c, 0xffffffff, 0x0040,
0x000d, 0x00000040, 0x00004040, 0x000d, 0x00000040, 0x00004040,
0x2440, 0x07ffffff, 0x03000000, 0x2440, 0x07ffffff, 0x03000000,
0x2418, 0x0000007f, 0x00000020, 0x2418, 0x0000007f, 0x00000020,
...@@ -354,11 +347,16 @@ static const u32 oland_golden_registers[] = ...@@ -354,11 +347,16 @@ static const u32 oland_golden_registers[] =
0x2b04, 0xffffffff, 0x00000000, 0x2b04, 0xffffffff, 0x00000000,
0x2b03, 0xffffffff, 0x00003210, 0x2b03, 0xffffffff, 0x00003210,
0x2235, 0x0000001f, 0x00000010, 0x2235, 0x0000001f, 0x00000010,
0x0570, 0x000c0fc0, 0x000c0400 0x0570, 0x000c0fc0, 0x000c0400,
0x052c, 0x0fffffff, 0xffffffff,
0x052d, 0x0fffffff, 0x0fffffff,
0x052e, 0x0fffffff, 0x0fffffff,
0x052f, 0x0fffffff, 0x0fffffff
}; };
static const u32 oland_golden_rlc_registers[] = static const u32 oland_golden_rlc_registers[] =
{ {
0x263e, 0xffffffff, 0x02010002,
0x3109, 0xffffffff, 0x00601005, 0x3109, 0xffffffff, 0x00601005,
0x311f, 0xffffffff, 0x10104040, 0x311f, 0xffffffff, 0x10104040,
0x3122, 0xffffffff, 0x0100000a, 0x3122, 0xffffffff, 0x0100000a,
...@@ -368,22 +366,27 @@ static const u32 oland_golden_rlc_registers[] = ...@@ -368,22 +366,27 @@ static const u32 oland_golden_rlc_registers[] =
static const u32 hainan_golden_registers[] = static const u32 hainan_golden_registers[] =
{ {
0x17bc, 0x00000030, 0x00000011,
0x2684, 0x00010000, 0x00018208, 0x2684, 0x00010000, 0x00018208,
0x260c, 0xffffffff, 0x00000000, 0x260c, 0xffffffff, 0x00000000,
0x260d, 0xf00fffff, 0x00000400, 0x260d, 0xf00fffff, 0x00000400,
0x260e, 0x0002021c, 0x00020200, 0x260e, 0x0002021c, 0x00020200,
0x4595, 0xff000fff, 0x00000100, 0x031e, 0x00000080, 0x00000000,
0x3430, 0xff000fff, 0x00000100,
0x340c, 0x000300c0, 0x00800040, 0x340c, 0x000300c0, 0x00800040,
0x3630, 0xff000fff, 0x00000100, 0x3630, 0xff000fff, 0x00000100,
0x360c, 0x000300c0, 0x00800040, 0x360c, 0x000300c0, 0x00800040,
0x16ec, 0x000000f0, 0x00000070,
0x16f0, 0x00200000, 0x50100000,
0x1c0c, 0x31000311, 0x00000011,
0x0ab9, 0x00073ffe, 0x000022a2, 0x0ab9, 0x00073ffe, 0x000022a2,
0x0903, 0x000007ff, 0x00000000, 0x0903, 0x000007ff, 0x00000000,
0x2285, 0xf000001f, 0x00000007, 0x2285, 0xf000001f, 0x00000007,
0x22c9, 0xffffffff, 0x00ffffff, 0x22c9, 0xffffffff, 0x00ffffff,
0x22c4, 0x0000ff0f, 0x00000000, 0x22c4, 0x0000ff0f, 0x00000000,
0xa393, 0x07ffffff, 0x4e000000, 0xa293, 0x07ffffff, 0x4e000000,
0xa0d4, 0x3f3f3fff, 0x00000000, 0xa0d4, 0x3f3f3fff, 0x00000000,
0x000c, 0x000000ff, 0x0040, 0x000c, 0xffffffff, 0x0040,
0x000d, 0x00000040, 0x00004040, 0x000d, 0x00000040, 0x00004040,
0x2440, 0x03e00000, 0x03600000, 0x2440, 0x03e00000, 0x03600000,
0x2418, 0x0000007f, 0x00000020, 0x2418, 0x0000007f, 0x00000020,
...@@ -392,12 +395,16 @@ static const u32 hainan_golden_registers[] = ...@@ -392,12 +395,16 @@ static const u32 hainan_golden_registers[] =
0x2b04, 0xffffffff, 0x00000000, 0x2b04, 0xffffffff, 0x00000000,
0x2b03, 0xffffffff, 0x00003210, 0x2b03, 0xffffffff, 0x00003210,
0x2235, 0x0000001f, 0x00000010, 0x2235, 0x0000001f, 0x00000010,
0x0570, 0x000c0fc0, 0x000c0400 0x0570, 0x000c0fc0, 0x000c0400,
0x052c, 0x0fffffff, 0xffffffff,
0x052d, 0x0fffffff, 0x0fffffff,
0x052e, 0x0fffffff, 0x0fffffff,
0x052f, 0x0fffffff, 0x0fffffff
}; };
static const u32 hainan_golden_registers2[] = static const u32 hainan_golden_registers2[] =
{ {
0x263e, 0xffffffff, 0x02010001 0x263e, 0xffffffff, 0x2011003
}; };
static const u32 tahiti_mgcg_cgcg_init[] = static const u32 tahiti_mgcg_cgcg_init[] =
...@@ -513,18 +520,18 @@ static const u32 tahiti_mgcg_cgcg_init[] = ...@@ -513,18 +520,18 @@ static const u32 tahiti_mgcg_cgcg_init[] =
0x21c2, 0xffffffff, 0x00900100, 0x21c2, 0xffffffff, 0x00900100,
0x311e, 0xffffffff, 0x00000080, 0x311e, 0xffffffff, 0x00000080,
0x3101, 0xffffffff, 0x0020003f, 0x3101, 0xffffffff, 0x0020003f,
0xc, 0xffffffff, 0x0000001c, 0x000c, 0xffffffff, 0x0000001c,
0xd, 0x000f0000, 0x000f0000, 0x000d, 0x000f0000, 0x000f0000,
0x583, 0xffffffff, 0x00000100, 0x0583, 0xffffffff, 0x00000100,
0x409, 0xffffffff, 0x00000100, 0x0409, 0xffffffff, 0x00000100,
0x40b, 0x00000101, 0x00000000, 0x040b, 0x00000101, 0x00000000,
0x82a, 0xffffffff, 0x00000104, 0x082a, 0xffffffff, 0x00000104,
0x993, 0x000c0000, 0x000c0000, 0x0993, 0x000c0000, 0x000c0000,
0x992, 0x000c0000, 0x000c0000, 0x0992, 0x000c0000, 0x000c0000,
0x1579, 0xff000fff, 0x00000100, 0x1579, 0xff000fff, 0x00000100,
0x157a, 0x00000001, 0x00000001, 0x157a, 0x00000001, 0x00000001,
0xbd4, 0x00000001, 0x00000001, 0x0bd4, 0x00000001, 0x00000001,
0xc33, 0xc0000fff, 0x00000104, 0x0c33, 0xc0000fff, 0x00000104,
0x3079, 0x00000001, 0x00000001, 0x3079, 0x00000001, 0x00000001,
0x3430, 0xfffffff0, 0x00000100, 0x3430, 0xfffffff0, 0x00000100,
0x3630, 0xfffffff0, 0x00000100 0x3630, 0xfffffff0, 0x00000100
...@@ -612,16 +619,16 @@ static const u32 pitcairn_mgcg_cgcg_init[] = ...@@ -612,16 +619,16 @@ static const u32 pitcairn_mgcg_cgcg_init[] =
0x21c2, 0xffffffff, 0x00900100, 0x21c2, 0xffffffff, 0x00900100,
0x311e, 0xffffffff, 0x00000080, 0x311e, 0xffffffff, 0x00000080,
0x3101, 0xffffffff, 0x0020003f, 0x3101, 0xffffffff, 0x0020003f,
0xc, 0xffffffff, 0x0000001c, 0x000c, 0xffffffff, 0x0000001c,
0xd, 0x000f0000, 0x000f0000, 0x000d, 0x000f0000, 0x000f0000,
0x583, 0xffffffff, 0x00000100, 0x0583, 0xffffffff, 0x00000100,
0x409, 0xffffffff, 0x00000100, 0x0409, 0xffffffff, 0x00000100,
0x40b, 0x00000101, 0x00000000, 0x040b, 0x00000101, 0x00000000,
0x82a, 0xffffffff, 0x00000104, 0x082a, 0xffffffff, 0x00000104,
0x1579, 0xff000fff, 0x00000100, 0x1579, 0xff000fff, 0x00000100,
0x157a, 0x00000001, 0x00000001, 0x157a, 0x00000001, 0x00000001,
0xbd4, 0x00000001, 0x00000001, 0x0bd4, 0x00000001, 0x00000001,
0xc33, 0xc0000fff, 0x00000104, 0x0c33, 0xc0000fff, 0x00000104,
0x3079, 0x00000001, 0x00000001, 0x3079, 0x00000001, 0x00000001,
0x3430, 0xfffffff0, 0x00000100, 0x3430, 0xfffffff0, 0x00000100,
0x3630, 0xfffffff0, 0x00000100 0x3630, 0xfffffff0, 0x00000100
...@@ -709,18 +716,18 @@ static const u32 verde_mgcg_cgcg_init[] = ...@@ -709,18 +716,18 @@ static const u32 verde_mgcg_cgcg_init[] =
0x21c2, 0xffffffff, 0x00900100, 0x21c2, 0xffffffff, 0x00900100,
0x311e, 0xffffffff, 0x00000080, 0x311e, 0xffffffff, 0x00000080,
0x3101, 0xffffffff, 0x0020003f, 0x3101, 0xffffffff, 0x0020003f,
0xc, 0xffffffff, 0x0000001c, 0x000c, 0xffffffff, 0x0000001c,
0xd, 0x000f0000, 0x000f0000, 0x000d, 0x000f0000, 0x000f0000,
0x583, 0xffffffff, 0x00000100, 0x0583, 0xffffffff, 0x00000100,
0x409, 0xffffffff, 0x00000100, 0x0409, 0xffffffff, 0x00000100,
0x40b, 0x00000101, 0x00000000, 0x040b, 0x00000101, 0x00000000,
0x82a, 0xffffffff, 0x00000104, 0x082a, 0xffffffff, 0x00000104,
0x993, 0x000c0000, 0x000c0000, 0x0993, 0x000c0000, 0x000c0000,
0x992, 0x000c0000, 0x000c0000, 0x0992, 0x000c0000, 0x000c0000,
0x1579, 0xff000fff, 0x00000100, 0x1579, 0xff000fff, 0x00000100,
0x157a, 0x00000001, 0x00000001, 0x157a, 0x00000001, 0x00000001,
0xbd4, 0x00000001, 0x00000001, 0x0bd4, 0x00000001, 0x00000001,
0xc33, 0xc0000fff, 0x00000104, 0x0c33, 0xc0000fff, 0x00000104,
0x3079, 0x00000001, 0x00000001, 0x3079, 0x00000001, 0x00000001,
0x3430, 0xfffffff0, 0x00000100, 0x3430, 0xfffffff0, 0x00000100,
0x3630, 0xfffffff0, 0x00000100 0x3630, 0xfffffff0, 0x00000100
...@@ -788,18 +795,18 @@ static const u32 oland_mgcg_cgcg_init[] = ...@@ -788,18 +795,18 @@ static const u32 oland_mgcg_cgcg_init[] =
0x21c2, 0xffffffff, 0x00900100, 0x21c2, 0xffffffff, 0x00900100,
0x311e, 0xffffffff, 0x00000080, 0x311e, 0xffffffff, 0x00000080,
0x3101, 0xffffffff, 0x0020003f, 0x3101, 0xffffffff, 0x0020003f,
0xc, 0xffffffff, 0x0000001c, 0x000c, 0xffffffff, 0x0000001c,
0xd, 0x000f0000, 0x000f0000, 0x000d, 0x000f0000, 0x000f0000,
0x583, 0xffffffff, 0x00000100, 0x0583, 0xffffffff, 0x00000100,
0x409, 0xffffffff, 0x00000100, 0x0409, 0xffffffff, 0x00000100,
0x40b, 0x00000101, 0x00000000, 0x040b, 0x00000101, 0x00000000,
0x82a, 0xffffffff, 0x00000104, 0x082a, 0xffffffff, 0x00000104,
0x993, 0x000c0000, 0x000c0000, 0x0993, 0x000c0000, 0x000c0000,
0x992, 0x000c0000, 0x000c0000, 0x0992, 0x000c0000, 0x000c0000,
0x1579, 0xff000fff, 0x00000100, 0x1579, 0xff000fff, 0x00000100,
0x157a, 0x00000001, 0x00000001, 0x157a, 0x00000001, 0x00000001,
0xbd4, 0x00000001, 0x00000001, 0x0bd4, 0x00000001, 0x00000001,
0xc33, 0xc0000fff, 0x00000104, 0x0c33, 0xc0000fff, 0x00000104,
0x3079, 0x00000001, 0x00000001, 0x3079, 0x00000001, 0x00000001,
0x3430, 0xfffffff0, 0x00000100, 0x3430, 0xfffffff0, 0x00000100,
0x3630, 0xfffffff0, 0x00000100 0x3630, 0xfffffff0, 0x00000100
...@@ -867,15 +874,15 @@ static const u32 hainan_mgcg_cgcg_init[] = ...@@ -867,15 +874,15 @@ static const u32 hainan_mgcg_cgcg_init[] =
0x21c2, 0xffffffff, 0x00900100, 0x21c2, 0xffffffff, 0x00900100,
0x311e, 0xffffffff, 0x00000080, 0x311e, 0xffffffff, 0x00000080,
0x3101, 0xffffffff, 0x0020003f, 0x3101, 0xffffffff, 0x0020003f,
0xc, 0xffffffff, 0x0000001c, 0x000c, 0xffffffff, 0x0000001c,
0xd, 0x000f0000, 0x000f0000, 0x000d, 0x000f0000, 0x000f0000,
0x583, 0xffffffff, 0x00000100, 0x0583, 0xffffffff, 0x00000100,
0x409, 0xffffffff, 0x00000100, 0x0409, 0xffffffff, 0x00000100,
0x82a, 0xffffffff, 0x00000104, 0x082a, 0xffffffff, 0x00000104,
0x993, 0x000c0000, 0x000c0000, 0x0993, 0x000c0000, 0x000c0000,
0x992, 0x000c0000, 0x000c0000, 0x0992, 0x000c0000, 0x000c0000,
0xbd4, 0x00000001, 0x00000001, 0x0bd4, 0x00000001, 0x00000001,
0xc33, 0xc0000fff, 0x00000104, 0x0c33, 0xc0000fff, 0x00000104,
0x3079, 0x00000001, 0x00000001, 0x3079, 0x00000001, 0x00000001,
0x3430, 0xfffffff0, 0x00000100, 0x3430, 0xfffffff0, 0x00000100,
0x3630, 0xfffffff0, 0x00000100 0x3630, 0xfffffff0, 0x00000100
...@@ -1179,6 +1186,8 @@ static int si_common_early_init(void *handle) ...@@ -1179,6 +1186,8 @@ static int si_common_early_init(void *handle)
AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_HDP_MGCG; AMD_CG_SUPPORT_HDP_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = (adev->rev_id == 0) ? 1 :
(adev->rev_id == 1) ? 5 : 6;
break; break;
case CHIP_PITCAIRN: case CHIP_PITCAIRN:
adev->cg_flags = adev->cg_flags =
...@@ -1198,6 +1207,7 @@ static int si_common_early_init(void *handle) ...@@ -1198,6 +1207,7 @@ static int si_common_early_init(void *handle)
AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_HDP_MGCG; AMD_CG_SUPPORT_HDP_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 20;
break; break;
case CHIP_VERDE: case CHIP_VERDE:
...@@ -1219,7 +1229,7 @@ static int si_common_early_init(void *handle) ...@@ -1219,7 +1229,7 @@ static int si_common_early_init(void *handle)
AMD_CG_SUPPORT_HDP_MGCG; AMD_CG_SUPPORT_HDP_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
//??? //???
adev->external_rev_id = adev->rev_id + 0x14; adev->external_rev_id = adev->rev_id + 40;
break; break;
case CHIP_OLAND: case CHIP_OLAND:
adev->cg_flags = adev->cg_flags =
...@@ -1238,6 +1248,7 @@ static int si_common_early_init(void *handle) ...@@ -1238,6 +1248,7 @@ static int si_common_early_init(void *handle)
AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_HDP_MGCG; AMD_CG_SUPPORT_HDP_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = 60;
break; break;
case CHIP_HAINAN: case CHIP_HAINAN:
adev->cg_flags = adev->cg_flags =
...@@ -1255,6 +1266,7 @@ static int si_common_early_init(void *handle) ...@@ -1255,6 +1266,7 @@ static int si_common_early_init(void *handle)
AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_HDP_MGCG; AMD_CG_SUPPORT_HDP_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = 70;
break; break;
default: default:
......
drivers/gpu/drm/amd/amdgpu/vi.c
View file @ 6df383cf
...@@ -932,18 +932,64 @@ static int vi_common_early_init(void *handle) ...@@ -932,18 +932,64 @@ static int vi_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x3c; adev->external_rev_id = adev->rev_id + 0x3c;
break; break;
case CHIP_TONGA: case CHIP_TONGA:
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
adev->pg_flags = AMD_PG_SUPPORT_UVD; AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_HDP_MGCG |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_ROM_MGCG |
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_DRM_LS |
AMD_CG_SUPPORT_UVD_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x14; adev->external_rev_id = adev->rev_id + 0x14;
break; break;
case CHIP_POLARIS11: case CHIP_POLARIS11:
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_RLC_LS |
AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_BIF_MGCG |
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_HDP_MGCG |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_ROM_MGCG |
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_DRM_LS |
AMD_CG_SUPPORT_UVD_MGCG |
AMD_CG_SUPPORT_VCE_MGCG; AMD_CG_SUPPORT_VCE_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x5A; adev->external_rev_id = adev->rev_id + 0x5A;
break; break;
case CHIP_POLARIS10: case CHIP_POLARIS10:
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_RLC_LS |
AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_BIF_MGCG |
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_HDP_MGCG |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_ROM_MGCG |
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_DRM_LS |
AMD_CG_SUPPORT_UVD_MGCG |
AMD_CG_SUPPORT_VCE_MGCG; AMD_CG_SUPPORT_VCE_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x50; adev->external_rev_id = adev->rev_id + 0x50;
...@@ -971,6 +1017,7 @@ static int vi_common_early_init(void *handle) ...@@ -971,6 +1017,7 @@ static int vi_common_early_init(void *handle)
adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_GFX_SMG | AMD_PG_SUPPORT_GFX_SMG |
AMD_PG_SUPPORT_GFX_PIPELINE | AMD_PG_SUPPORT_GFX_PIPELINE |
AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_UVD | AMD_PG_SUPPORT_UVD |
AMD_PG_SUPPORT_VCE; AMD_PG_SUPPORT_VCE;
} }
...@@ -996,6 +1043,7 @@ static int vi_common_early_init(void *handle) ...@@ -996,6 +1043,7 @@ static int vi_common_early_init(void *handle)
adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_GFX_SMG | AMD_PG_SUPPORT_GFX_SMG |
AMD_PG_SUPPORT_GFX_PIPELINE | AMD_PG_SUPPORT_GFX_PIPELINE |
AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_UVD | AMD_PG_SUPPORT_UVD |
AMD_PG_SUPPORT_VCE; AMD_PG_SUPPORT_VCE;
adev->external_rev_id = adev->rev_id + 0x61; adev->external_rev_id = adev->rev_id + 0x61;
...@@ -1155,57 +1203,118 @@ static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, ...@@ -1155,57 +1203,118 @@ static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
static int vi_common_set_clockgating_state_by_smu(void *handle, static int vi_common_set_clockgating_state_by_smu(void *handle,
enum amd_clockgating_state state) enum amd_clockgating_state state)
{ {
uint32_t msg_id, pp_state; uint32_t msg_id, pp_state = 0;
uint32_t pp_support_state = 0;
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
void *pp_handle = adev->powerplay.pp_handle; void *pp_handle = adev->powerplay.pp_handle;
if (state == AMD_CG_STATE_UNGATE) if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
pp_state = 0; if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
else pp_support_state = AMD_CG_SUPPORT_MC_LS;
pp_state = PP_STATE_CG | PP_STATE_LS; pp_state = PP_STATE_LS;
}
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
PP_BLOCK_SYS_MC, pp_support_state |= AMD_CG_SUPPORT_MC_MGCG;
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, pp_state |= PP_STATE_CG;
pp_state); }
amd_set_clockgating_by_smu(pp_handle, msg_id); if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
PP_BLOCK_SYS_SDMA, PP_BLOCK_SYS_MC,
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, pp_support_state,
pp_state); pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id); amd_set_clockgating_by_smu(pp_handle, msg_id);
}
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
PP_BLOCK_SYS_HDP, if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
pp_state); pp_support_state = AMD_CG_SUPPORT_SDMA_LS;
amd_set_clockgating_by_smu(pp_handle, msg_id); pp_state = PP_STATE_LS;
}
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
PP_BLOCK_SYS_BIF, pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG;
PP_STATE_SUPPORT_LS, pp_state |= PP_STATE_CG;
pp_state); }
amd_set_clockgating_by_smu(pp_handle, msg_id); if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
PP_BLOCK_SYS_BIF, PP_BLOCK_SYS_SDMA,
PP_STATE_SUPPORT_CG, pp_support_state,
pp_state); pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id); amd_set_clockgating_by_smu(pp_handle, msg_id);
}
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
PP_BLOCK_SYS_DRM, if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
PP_STATE_SUPPORT_LS, if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
pp_state); pp_support_state = AMD_CG_SUPPORT_HDP_LS;
amd_set_clockgating_by_smu(pp_handle, msg_id); pp_state = PP_STATE_LS;
}
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
PP_BLOCK_SYS_ROM, pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG;
PP_STATE_SUPPORT_CG, pp_state |= PP_STATE_CG;
pp_state); }
amd_set_clockgating_by_smu(pp_handle, msg_id); if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
PP_BLOCK_SYS_HDP,
pp_support_state,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
else
pp_state = PP_STATE_LS;
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
PP_BLOCK_SYS_BIF,
PP_STATE_SUPPORT_LS,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
else
pp_state = PP_STATE_CG;
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
PP_BLOCK_SYS_BIF,
PP_STATE_SUPPORT_CG,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
else
pp_state = PP_STATE_LS;
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
PP_BLOCK_SYS_DRM,
PP_STATE_SUPPORT_LS,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
else
pp_state = PP_STATE_CG;
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
PP_BLOCK_SYS_ROM,
PP_STATE_SUPPORT_CG,
pp_state);
amd_set_clockgating_by_smu(pp_handle, msg_id);
}
return 0; return 0;
} }
......
drivers/gpu/drm/amd/include/amd_shared.h
View file @ 6df383cf
...@@ -126,6 +126,10 @@ enum amd_vce_level { ...@@ -126,6 +126,10 @@ enum amd_vce_level {
#define AMD_CG_SUPPORT_HDP_LS (1 << 15) #define AMD_CG_SUPPORT_HDP_LS (1 << 15)
#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
#define AMD_CG_SUPPORT_DRM_LS (1 << 18)
#define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
#define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
#define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
/* PG flags */ /* PG flags */
#define AMD_PG_SUPPORT_GFX_PG (1 << 0) #define AMD_PG_SUPPORT_GFX_PG (1 << 0)
......
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