Commit 6e409668 authored by Anton Blanchard's avatar Anton Blanchard

Merge samba.org:/scratch/anton/linux-2.5

into samba.org:/scratch/anton/sfr
parents 611f4c04 a9500b1c
......@@ -46,6 +46,7 @@ CONFIG_NR_CPUS=32
# CONFIG_HMT is not set
# CONFIG_DISCONTIGMEM is not set
# CONFIG_RTAS_FLASH is not set
CONFIG_SCANLOG=y
CONFIG_PPC_RTAS=y
#
......@@ -54,7 +55,6 @@ CONFIG_PPC_RTAS=y
CONFIG_PCI=y
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_ELF32=y
# CONFIG_BINFMT_MISC is not set
CONFIG_PCI_LEGACY_PROC=y
CONFIG_PCI_NAMES=y
......
......@@ -46,6 +46,7 @@
#include <asm/io.h>
#include <asm/eeh.h>
#include <asm/tlb.h>
#include <asm/cacheflush.h>
/*
* Note: pte --> Linux PTE
......@@ -348,6 +349,9 @@ int __hash_page(unsigned long ea, unsigned long access, unsigned long vsid,
}
}
if (unlikely(slot == -2))
panic("hash_page: pte_insert failed\n");
pte_val(new_pte) |= (slot<<12) & _PAGE_GROUP_IX;
/*
......
......@@ -555,14 +555,15 @@ void openpic_request_IPIs(void)
if (OpenPIC == NULL)
return;
request_irq(openpic_vec_ipi,
openpic_ipi_action, 0, "IPI0 (call function)", 0);
request_irq(openpic_vec_ipi+1,
openpic_ipi_action, 0, "IPI1 (reschedule)", 0);
request_irq(openpic_vec_ipi+2,
openpic_ipi_action, 0, "IPI2 (invalidate tlb)", 0);
request_irq(openpic_vec_ipi+3,
openpic_ipi_action, 0, "IPI3 (xmon break)", 0);
/* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
request_irq(openpic_vec_ipi, openpic_ipi_action, SA_INTERRUPT,
"IPI0 (call function)", 0);
request_irq(openpic_vec_ipi+1, openpic_ipi_action, SA_INTERRUPT,
"IPI1 (reschedule)", 0);
request_irq(openpic_vec_ipi+2, openpic_ipi_action, SA_INTERRUPT,
"IPI2 (invalidate tlb)", 0);
request_irq(openpic_vec_ipi+3, openpic_ipi_action, SA_INTERRUPT,
"IPI3 (xmon break)", 0);
for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
openpic_enable_ipi(openpic_vec_ipi+i);
......@@ -754,17 +755,12 @@ static void openpic_set_affinity(unsigned int irq_nr, unsigned long cpumask)
#ifdef CONFIG_SMP
static void openpic_end_ipi(unsigned int irq_nr)
{
/* IPIs are marked IRQ_PER_CPU. This has the side effect of
/*
* IPIs are marked IRQ_PER_CPU. This has the side effect of
* preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
* applying to them. We EOI them late to avoid re-entering.
* however, I'm wondering if we could simply let them have the
* SA_INTERRUPT flag and let them execute with all interrupts OFF.
* This would have the side effect of either running cross-CPU
* functions with interrupts off, or we can re-enable them explicitely
* with a local_irq_enable() in smp_call_function_interrupt(), since
* smp_call_function() is protected by a spinlock.
* Or maybe we shouldn't set the IRQ_PER_CPU flag on cross-CPU
* function calls IPI at all but that would make a special case.
* We mark IPI's with SA_INTERRUPT as they must run with
* irqs disabled.
*/
openpic_eoi();
}
......
......@@ -460,8 +460,13 @@ long pSeries_lpar_hpte_insert(unsigned long hpte_group,
if (lpar_rc == H_PTEG_Full)
return -1;
/*
* Since we try and ioremap PHBs we dont own, the pte insert
* will fail. However we must catch the failure in hash_page
* or we will loop forever, so return -2 in this case.
*/
if (lpar_rc != H_Success)
panic("Bad return code from pte enter rc = %lx\n", lpar_rc);
return -2;
return slot;
}
......
......@@ -29,6 +29,8 @@
#include <asm/unistd.h>
#include <asm/cacheflush.h>
#define DEBUG_SIG 0
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
/*
* These are the flags in the MSR that the user is allowed to change
......
......@@ -15,6 +15,7 @@
#include <linux/irq.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/signal.h>
#include <asm/prom.h>
#include <asm/io.h>
#include <asm/pgtable.h>
......@@ -423,8 +424,11 @@ xics_init_IRQ( void )
}
#ifdef CONFIG_SMP
real_irq_to_virt_map[XICS_IPI] = virt_irq_to_real_map[XICS_IPI] = XICS_IPI;
request_irq(XICS_IPI + XICS_IRQ_OFFSET, xics_ipi_action, 0, "IPI", 0);
real_irq_to_virt_map[XICS_IPI] = virt_irq_to_real_map[XICS_IPI] =
XICS_IPI;
/* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
request_irq(XICS_IPI + XICS_IRQ_OFFSET, xics_ipi_action, SA_INTERRUPT,
"IPI", 0);
irq_desc[XICS_IPI+XICS_IRQ_OFFSET].status |= IRQ_PER_CPU;
#endif
ppc64_boot_msg(0x21, "XICS Done");
......
......@@ -233,6 +233,7 @@ static void map_io_page(unsigned long ea, unsigned long pa, int flags)
hpteg = ((hash & htab_data.htab_hash_mask)*HPTES_PER_GROUP);
/* Panic if a pte grpup is full */
if (ppc_md.hpte_insert(hpteg, va, pa >> PAGE_SHIFT, 0,
_PAGE_NO_CACHE|_PAGE_GUARDED|PP_RWXX,
1, 0) == -1) {
......
......@@ -82,7 +82,7 @@ typedef struct {
#define irq_enter() (preempt_count() += HARDIRQ_OFFSET)
#if CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT
# define in_atomic() ((preempt_count() & ~PREEMPT_ACTIVE) != kernel_locked())
# define IRQ_EXIT_OFFSET (HARDIRQ_OFFSET-1)
#else
......
......@@ -23,12 +23,12 @@ struct semaphore {
*/
atomic_t count;
wait_queue_head_t wait;
#if WAITQUEUE_DEBUG
#ifdef WAITQUEUE_DEBUG
long __magic;
#endif
};
#if WAITQUEUE_DEBUG
#ifdef WAITQUEUE_DEBUG
# define __SEM_DEBUG_INIT(name) \
, (long)&(name).__magic
#else
......@@ -53,7 +53,7 @@ static inline void sema_init (struct semaphore *sem, int val)
{
atomic_set(&sem->count, val);
init_waitqueue_head(&sem->wait);
#if WAITQUEUE_DEBUG
#ifdef WAITQUEUE_DEBUG
sem->__magic = (long)&sem->__magic;
#endif
}
......@@ -74,7 +74,7 @@ extern void __up(struct semaphore * sem);
static inline void down(struct semaphore * sem)
{
#if WAITQUEUE_DEBUG
#ifdef WAITQUEUE_DEBUG
CHECK_MAGIC(sem->__magic);
#endif
might_sleep();
......@@ -91,7 +91,7 @@ static inline int down_interruptible(struct semaphore * sem)
{
int ret = 0;
#if WAITQUEUE_DEBUG
#ifdef WAITQUEUE_DEBUG
CHECK_MAGIC(sem->__magic);
#endif
might_sleep();
......@@ -106,7 +106,7 @@ static inline int down_trylock(struct semaphore * sem)
{
int ret;
#if WAITQUEUE_DEBUG
#ifdef WAITQUEUE_DEBUG
CHECK_MAGIC(sem->__magic);
#endif
......@@ -117,7 +117,7 @@ static inline int down_trylock(struct semaphore * sem)
static inline void up(struct semaphore * sem)
{
#if WAITQUEUE_DEBUG
#ifdef WAITQUEUE_DEBUG
CHECK_MAGIC(sem->__magic);
#endif
......
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