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Commit 709d015b authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel 

* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (41 commits)
  drm/i915: add HAS_BSD check to i915_getparam
  drm/i915: Honor sync polarity from VBT panel timing descriptors
  drm/i915: Unmask interrupt for render engine on Sandybridge
  drm/i915: Fix PIPE_CONTROL command on Sandybridge
  drm/i915: Fix up address spaces in slow_kernel_write()
  drm/i915: Use non-atomic kmap for slow copy paths
  drm/i915: Avoid moving from CPU domain during pwrite
  drm/i915: Cleanup after failed initialization of ringbuffers
  drm/i915: Reject bind_to_gtt() early if object > aperture
  drm/i915: Check error code whilst moving buffer to GTT domain.
  drm/i915: Remove spurious warning "Failure to install fence"
  drm/i915: Rebind bo if currently bound with incorrect alignment.
  drm/i915: Include pitch in set_base debug statement.
  drm/i915: Only print "nothing to do" debug message as required.
  drm/i915: Propagate error from unbinding an unfenceable object.
  drm/i915: Avoid nesting of domain changes when setting display plane
  drm/i915: Hold the spinlock whilst resetting unpin_work along error path
  drm/i915: Only print an message if there was an error
  drm/i915: Clean up leftover bits from hws move to ring structure.
  drm/i915: Add CxSR support on Pineview DDR3
  ...
parents 08a66859 e3a815fc
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drivers/char/agp/intel-gtt.c
View file @ 709d015b
......@@ -1059,7 +1059,7 @@ static void intel_i9xx_setup_flush(void)
}
}
static int intel_i915_configure(void)
static int intel_i9xx_configure(void)
{
struct aper_size_info_fixed *current_size;
u32 temp;
......@@ -1207,6 +1207,38 @@ static int intel_i9xx_fetch_size(void)
return 0;
}
static int intel_i915_get_gtt_size(void)
{
int size;
if (IS_G33) {
u16 gmch_ctrl;
/* G33's GTT size defined in gmch_ctrl */
pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
case G33_PGETBL_SIZE_1M:
size = 1024;
break;
case G33_PGETBL_SIZE_2M:
size = 2048;
break;
default:
dev_info(&agp_bridge->dev->dev,
"unknown page table size 0x%x, assuming 512KB\n",
(gmch_ctrl & G33_PGETBL_SIZE_MASK));
size = 512;
}
} else {
/* On previous hardware, the GTT size was just what was
* required to map the aperture.
*/
size = agp_bridge->driver->fetch_size();
}
return KB(size);
}
/* The intel i915 automatically initializes the agp aperture during POST.
* Use the memory already set aside for in the GTT.
*/
......@@ -1216,7 +1248,7 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
struct aper_size_info_fixed *size;
int num_entries;
u32 temp, temp2;
int gtt_map_size = 256 * 1024;
int gtt_map_size;
size = agp_bridge->current_size;
page_order = size->page_order;
......@@ -1226,8 +1258,8 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
if (IS_G33)
gtt_map_size = 1024 * 1024; /* 1M on G33 */
gtt_map_size = intel_i915_get_gtt_size();
intel_private.gtt = ioremap(temp2, gtt_map_size);
if (!intel_private.gtt)
return -ENOMEM;
......@@ -1422,7 +1454,7 @@ static const struct agp_bridge_driver intel_915_driver = {
.size_type = FIXED_APER_SIZE,
.num_aperture_sizes = 4,
.needs_scratch_page = true,
.configure = intel_i915_configure,
.configure = intel_i9xx_configure,
.fetch_size = intel_i9xx_fetch_size,
.cleanup = intel_i915_cleanup,
.mask_memory = intel_i810_mask_memory,
......@@ -1455,7 +1487,7 @@ static const struct agp_bridge_driver intel_i965_driver = {
.size_type = FIXED_APER_SIZE,
.num_aperture_sizes = 4,
.needs_scratch_page = true,
.configure = intel_i915_configure,
.configure = intel_i9xx_configure,
.fetch_size = intel_i9xx_fetch_size,
.cleanup = intel_i915_cleanup,
.mask_memory = intel_i965_mask_memory,
......@@ -1488,7 +1520,7 @@ static const struct agp_bridge_driver intel_g33_driver = {
.size_type = FIXED_APER_SIZE,
.num_aperture_sizes = 4,
.needs_scratch_page = true,
.configure = intel_i915_configure,
.configure = intel_i9xx_configure,
.fetch_size = intel_i9xx_fetch_size,
.cleanup = intel_i915_cleanup,
.mask_memory = intel_i965_mask_memory,
......
drivers/gpu/drm/i915/Makefile
View file @ 709d015b
......@@ -22,6 +22,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
intel_fb.o \
intel_tv.o \
intel_dvo.o \
intel_ringbuffer.o \
intel_overlay.o \
dvo_ch7xxx.o \
dvo_ch7017.o \
......
drivers/gpu/drm/i915/i915_debugfs.c
View file @ 709d015b
......@@ -77,7 +77,7 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data)
case ACTIVE_LIST:
seq_printf(m, "Active:\n");
lock = &dev_priv->mm.active_list_lock;
head = &dev_priv->mm.active_list;
head = &dev_priv->render_ring.active_list;
break;
case INACTIVE_LIST:
seq_printf(m, "Inactive:\n");
......@@ -129,7 +129,8 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
struct drm_i915_gem_request *gem_request;
seq_printf(m, "Request:\n");
list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) {
list_for_each_entry(gem_request, &dev_priv->render_ring.request_list,
list) {
seq_printf(m, " %d @ %d\n",
gem_request->seqno,
(int) (jiffies - gem_request->emitted_jiffies));
......@@ -143,9 +144,9 @@ static int i915_gem_seqno_info(struct seq_file *m, void *data)
struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
if (dev_priv->hw_status_page != NULL) {
if (dev_priv->render_ring.status_page.page_addr != NULL) {
seq_printf(m, "Current sequence: %d\n",
i915_get_gem_seqno(dev));
i915_get_gem_seqno(dev, &dev_priv->render_ring));
} else {
seq_printf(m, "Current sequence: hws uninitialized\n");
}
......@@ -195,9 +196,9 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
}
seq_printf(m, "Interrupts received: %d\n",
atomic_read(&dev_priv->irq_received));
if (dev_priv->hw_status_page != NULL) {
if (dev_priv->render_ring.status_page.page_addr != NULL) {
seq_printf(m, "Current sequence: %d\n",
i915_get_gem_seqno(dev));
i915_get_gem_seqno(dev, &dev_priv->render_ring));
} else {
seq_printf(m, "Current sequence: hws uninitialized\n");
}
......@@ -251,7 +252,7 @@ static int i915_hws_info(struct seq_file *m, void *data)
int i;
volatile u32 *hws;
hws = (volatile u32 *)dev_priv->hw_status_page;
hws = (volatile u32 *)dev_priv->render_ring.status_page.page_addr;
if (hws == NULL)
return 0;
......@@ -287,7 +288,8 @@ static int i915_batchbuffer_info(struct seq_file *m, void *data)
spin_lock(&dev_priv->mm.active_list_lock);
list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
list_for_each_entry(obj_priv, &dev_priv->render_ring.active_list,
list) {
obj = &obj_priv->base;
if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
ret = i915_gem_object_get_pages(obj, 0);
......@@ -317,14 +319,14 @@ static int i915_ringbuffer_data(struct seq_file *m, void *data)
u8 *virt;
uint32_t *ptr, off;
if (!dev_priv->ring.ring_obj) {
if (!dev_priv->render_ring.gem_object) {
seq_printf(m, "No ringbuffer setup\n");
return 0;
}
virt = dev_priv->ring.virtual_start;
virt = dev_priv->render_ring.virtual_start;
for (off = 0; off < dev_priv->ring.Size; off += 4) {
for (off = 0; off < dev_priv->render_ring.size; off += 4) {
ptr = (uint32_t *)(virt + off);
seq_printf(m, "%08x : %08x\n", off, *ptr);
}
......@@ -344,7 +346,7 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
seq_printf(m, "RingHead : %08x\n", head);
seq_printf(m, "RingTail : %08x\n", tail);
seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size);
seq_printf(m, "RingSize : %08lx\n", dev_priv->render_ring.size);
seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
return 0;
......@@ -489,11 +491,14 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
u16 rgvswctl = I915_READ16(MEMSWCTL);
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
seq_printf(m, "Last command: 0x%01x\n", (rgvswctl >> 13) & 0x3);
seq_printf(m, "Command status: %d\n", (rgvswctl >> 12) & 1);
seq_printf(m, "P%d DELAY 0x%02x\n", (rgvswctl >> 8) & 0xf,
rgvswctl & 0x3f);
seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
MEMSTAT_VID_SHIFT);
seq_printf(m, "Current P-state: %d\n",
(rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
return 0;
}
......@@ -508,7 +513,8 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused)
for (i = 0; i < 16; i++) {
delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
seq_printf(m, "P%02dVIDFREQ: 0x%08x\n", i, delayfreq);
seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
(delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
}
return 0;
......@@ -541,6 +547,8 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
u32 rgvmodectl = I915_READ(MEMMODECTL);
u32 rstdbyctl = I915_READ(MCHBAR_RENDER_STANDBY);
u16 crstandvid = I915_READ16(CRSTANDVID);
seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
"yes" : "no");
......@@ -555,9 +563,13 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
seq_printf(m, "Starting frequency: P%d\n",
(rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
seq_printf(m, "Max frequency: P%d\n",
seq_printf(m, "Max P-state: P%d\n",
(rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
seq_printf(m, "Min frequency: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
seq_printf(m, "Render standby enabled: %s\n",
(rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
return 0;
}
......@@ -621,6 +633,36 @@ static int i915_sr_status(struct seq_file *m, void *unused)
return 0;
}
static int i915_emon_status(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
unsigned long temp, chipset, gfx;
temp = i915_mch_val(dev_priv);
chipset = i915_chipset_val(dev_priv);
gfx = i915_gfx_val(dev_priv);
seq_printf(m, "GMCH temp: %ld\n", temp);
seq_printf(m, "Chipset power: %ld\n", chipset);
seq_printf(m, "GFX power: %ld\n", gfx);
seq_printf(m, "Total power: %ld\n", chipset + gfx);
return 0;
}
static int i915_gfxec(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
return 0;
}
static int
i915_wedged_open(struct inode *inode,
struct file *filp)
......@@ -743,6 +785,8 @@ static struct drm_info_list i915_debugfs_list[] = {
{"i915_delayfreq_table", i915_delayfreq_table, 0},
{"i915_inttoext_table", i915_inttoext_table, 0},
{"i915_drpc_info", i915_drpc_info, 0},
{"i915_emon_status", i915_emon_status, 0},
{"i915_gfxec", i915_gfxec, 0},
{"i915_fbc_status", i915_fbc_status, 0},
{"i915_sr_status", i915_sr_status, 0},
};
......
drivers/gpu/drm/i915/i915_dma.c
View file @ 709d015b
This diff is collapsed.
drivers/gpu/drm/i915/i915_drv.c
View file @ 709d015b
......@@ -60,95 +60,95 @@ extern int intel_agp_enabled;
.subdevice = PCI_ANY_ID, \
.driver_data = (unsigned long) info }
const static struct intel_device_info intel_i830_info = {
static const struct intel_device_info intel_i830_info = {
.is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
};
const static struct intel_device_info intel_845g_info = {
static const struct intel_device_info intel_845g_info = {
.is_i8xx = 1,
};
const static struct intel_device_info intel_i85x_info = {
static const struct intel_device_info intel_i85x_info = {
.is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,
.cursor_needs_physical = 1,
};
const static struct intel_device_info intel_i865g_info = {
static const struct intel_device_info intel_i865g_info = {
.is_i8xx = 1,
};
const static struct intel_device_info intel_i915g_info = {
static const struct intel_device_info intel_i915g_info = {
.is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
};
const static struct intel_device_info intel_i915gm_info = {
static const struct intel_device_info intel_i915gm_info = {
.is_i9xx = 1, .is_mobile = 1,
.cursor_needs_physical = 1,
};
const static struct intel_device_info intel_i945g_info = {
static const struct intel_device_info intel_i945g_info = {
.is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
};
const static struct intel_device_info intel_i945gm_info = {
static const struct intel_device_info intel_i945gm_info = {
.is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
.has_hotplug = 1, .cursor_needs_physical = 1,
};
const static struct intel_device_info intel_i965g_info = {
static const struct intel_device_info intel_i965g_info = {
.is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
};
const static struct intel_device_info intel_i965gm_info = {
static const struct intel_device_info intel_i965gm_info = {
.is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
.is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_g33_info = {
static const struct intel_device_info intel_g33_info = {
.is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_g45_info = {
static const struct intel_device_info intel_g45_info = {
.is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
.has_pipe_cxsr = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_gm45_info = {
static const struct intel_device_info intel_gm45_info = {
.is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
.has_pipe_cxsr = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_pineview_info = {
static const struct intel_device_info intel_pineview_info = {
.is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
.need_gfx_hws = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_ironlake_d_info = {
static const struct intel_device_info intel_ironlake_d_info = {
.is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
.has_pipe_cxsr = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_ironlake_m_info = {
static const struct intel_device_info intel_ironlake_m_info = {
.is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
.need_gfx_hws = 1, .has_rc6 = 1,
.has_hotplug = 1,
};
const static struct intel_device_info intel_sandybridge_d_info = {
static const struct intel_device_info intel_sandybridge_d_info = {
.is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
.has_hotplug = 1, .is_gen6 = 1,
};
const static struct intel_device_info intel_sandybridge_m_info = {
static const struct intel_device_info intel_sandybridge_m_info = {
.is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1,
.has_hotplug = 1, .is_gen6 = 1,
};
const static struct pci_device_id pciidlist[] = {
static const struct pci_device_id pciidlist[] = {
INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
......@@ -340,7 +340,7 @@ int i965_reset(struct drm_device *dev, u8 flags)
/*
* Clear request list
*/
i915_gem_retire_requests(dev);
i915_gem_retire_requests(dev, &dev_priv->render_ring);
if (need_display)
i915_save_display(dev);
......@@ -370,6 +370,7 @@ int i965_reset(struct drm_device *dev, u8 flags)
}
} else {
DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
mutex_unlock(&dev->struct_mutex);
return -ENODEV;
}
......@@ -389,32 +390,9 @@ int i965_reset(struct drm_device *dev, u8 flags)
*/
if (drm_core_check_feature(dev, DRIVER_MODESET) ||
!dev_priv->mm.suspended) {
drm_i915_ring_buffer_t *ring = &dev_priv->ring;
struct drm_gem_object *obj = ring->ring_obj;
struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
struct intel_ring_buffer *ring = &dev_priv->render_ring;
dev_priv->mm.suspended = 0;
/* Stop the ring if it's running. */
I915_WRITE(PRB0_CTL, 0);
I915_WRITE(PRB0_TAIL, 0);
I915_WRITE(PRB0_HEAD, 0);
/* Initialize the ring. */
I915_WRITE(PRB0_START, obj_priv->gtt_offset);
I915_WRITE(PRB0_CTL,
((obj->size - 4096) & RING_NR_PAGES) |
RING_NO_REPORT |
RING_VALID);
if (!drm_core_check_feature(dev, DRIVER_MODESET))
i915_kernel_lost_context(dev);
else {
ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
ring->space = ring->head - (ring->tail + 8);
if (ring->space < 0)
ring->space += ring->Size;
}
ring->init(dev, ring);
mutex_unlock(&dev->struct_mutex);
drm_irq_uninstall(dev);
drm_irq_install(dev);
......
drivers/gpu/drm/i915/i915_drv.h
View file @ 709d015b
This diff is collapsed.
drivers/gpu/drm/i915/i915_gem.c
View file @ 709d015b
This diff is collapsed.
drivers/gpu/drm/i915/i915_irq.c
View file @ 709d015b
This diff is collapsed.
drivers/gpu/drm/i915/i915_reg.h
View file @ 709d015b
......@@ -334,6 +334,7 @@
#define I915_DEBUG_INTERRUPT (1<<2)
#define I915_USER_INTERRUPT (1<<1)
#define I915_ASLE_INTERRUPT (1<<0)
#define I915_BSD_USER_INTERRUPT (1<<25)
#define EIR 0x020b0
#define EMR 0x020b4
#define ESR 0x020b8
......@@ -368,6 +369,36 @@
#define BB_ADDR 0x02140 /* 8 bytes */
#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
/* GEN6 interrupt control */
#define GEN6_RENDER_HWSTAM 0x2098
#define GEN6_RENDER_IMR 0x20a8
#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
#define GEN6_RENDER TIMEOUT_COUNTER_EXPIRED (1 << 6)
#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
#define GEN6_RENDER_SYNC_STATUS (1 << 2)
#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
#define GEN6_BLITTER_HWSTAM 0x22098
#define GEN6_BLITTER_IMR 0x220a8
#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
/*
* BSD (bit stream decoder instruction and interrupt control register defines
* (G4X and Ironlake only)
*/
#define BSD_RING_TAIL 0x04030
#define BSD_RING_HEAD 0x04034
#define BSD_RING_START 0x04038
#define BSD_RING_CTL 0x0403c
#define BSD_RING_ACTHD 0x04074
#define BSD_HWS_PGA 0x04080
/*
* Framebuffer compression (915+ only)
......@@ -805,6 +836,10 @@
#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
/** Pineview MCH register contains DDR3 setting */
#define CSHRDDR3CTL 0x101a8
#define CSHRDDR3CTL_DDR3 (1 << 2)
/** 965 MCH register controlling DRAM channel configuration */
#define C0DRB3 0x10206
#define C1DRB3 0x10606
......@@ -826,6 +861,12 @@
#define CLKCFG_MEM_800 (3 << 4)
#define CLKCFG_MEM_MASK (7 << 4)
#define TR1 0x11006
#define TSFS 0x11020
#define TSFS_SLOPE_MASK 0x0000ff00
#define TSFS_SLOPE_SHIFT 8
#define TSFS_INTR_MASK 0x000000ff
#define CRSTANDVID 0x11100
#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
#define PXVFREQ_PX_MASK 0x7f000000
......@@ -964,6 +1005,41 @@
#define MEMSTAT_SRC_CTL_STDBY 3
#define RCPREVBSYTUPAVG 0x113b8
#define RCPREVBSYTDNAVG 0x113bc
#define SDEW 0x1124c
#define CSIEW0 0x11250
#define CSIEW1 0x11254
#define CSIEW2 0x11258
#define PEW 0x1125c
#define DEW 0x11270
#define MCHAFE 0x112c0
#define CSIEC 0x112e0
#define DMIEC 0x112e4
#define DDREC 0x112e8
#define PEG0EC 0x112ec
#define PEG1EC 0x112f0
#define GFXEC 0x112f4
#define RPPREVBSYTUPAVG 0x113b8
#define RPPREVBSYTDNAVG 0x113bc
#define ECR 0x11600
#define ECR_GPFE (1<<31)
#define ECR_IMONE (1<<30)
#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
#define OGW0 0x11608
#define OGW1 0x1160c
#define EG0 0x11610
#define EG1 0x11614
#define EG2 0x11618
#define EG3 0x1161c
#define EG4 0x11620
#define EG5 0x11624
#define EG6 0x11628
#define EG7 0x1162c
#define PXW 0x11664
#define PXWL 0x11680
#define LCFUSE02 0x116c0
#define LCFUSE_HIV_MASK 0x000000ff
#define CSIPLL0 0x12c10
#define DDRMPLL1 0X12c20
#define PEG_BAND_GAP_DATA 0x14d68
/*
......@@ -1055,7 +1131,6 @@
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
#define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
#define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f
#define PORT_HOTPLUG_STAT 0x61114
#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
......@@ -2355,6 +2430,8 @@
#define GT_PIPE_NOTIFY (1 << 4)
#define GT_SYNC_STATUS (1 << 2)
#define GT_USER_INTERRUPT (1 << 0)
#define GT_BSD_USER_INTERRUPT (1 << 5)
#define GTISR 0x44010
#define GTIMR 0x44014
......@@ -2690,6 +2767,9 @@
#define SDVO_ENCODING (0)
#define TMDS_ENCODING (2 << 10)
#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
/* CPT */
#define HDMI_MODE_SELECT (1 << 9)
#define DVI_MODE_SELECT (0)
#define SDVOB_BORDER_ENABLE (1 << 7)
#define AUDIO_ENABLE (1 << 6)
#define VSYNC_ACTIVE_HIGH (1 << 4)
......
drivers/gpu/drm/i915/i915_trace.h
View file @ 709d015b
......@@ -53,23 +53,6 @@ TRACE_EVENT(i915_gem_object_bind,
__entry->obj, __entry->gtt_offset)
);
TRACE_EVENT(i915_gem_object_clflush,
TP_PROTO(struct drm_gem_object *obj),
TP_ARGS(obj),
TP_STRUCT__entry(
__field(struct drm_gem_object *, obj)
),
TP_fast_assign(
__entry->obj = obj;
),
TP_printk("obj=%p", __entry->obj)
);
TRACE_EVENT(i915_gem_object_change_domain,
TP_PROTO(struct drm_gem_object *obj, uint32_t old_read_domains, uint32_t old_write_domain),
......@@ -132,6 +115,13 @@ DECLARE_EVENT_CLASS(i915_gem_object,
TP_printk("obj=%p", __entry->obj)
);
DEFINE_EVENT(i915_gem_object, i915_gem_object_clflush,
TP_PROTO(struct drm_gem_object *obj),
TP_ARGS(obj)
);
DEFINE_EVENT(i915_gem_object, i915_gem_object_unbind,
TP_PROTO(struct drm_gem_object *obj),
......
drivers/gpu/drm/i915/intel_bios.c
View file @ 709d015b
......@@ -95,6 +95,16 @@ fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
panel_fixed_mode->clock = dvo_timing->clock * 10;
panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
if (dvo_timing->hsync_positive)
panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
else
panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
if (dvo_timing->vsync_positive)
panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
else
panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
/* Some VBTs have bogus h/vtotal values */
if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
......
drivers/gpu/drm/i915/intel_crt.c
View file @ 709d015b
......@@ -217,7 +217,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
u32 hotplug_en;
u32 hotplug_en, orig, stat;
bool ret = false;
int i, tries = 0;
if (HAS_PCH_SPLIT(dev))
......@@ -232,8 +233,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
tries = 2;
else
tries = 1;
hotplug_en = I915_READ(PORT_HOTPLUG_EN);
hotplug_en &= CRT_FORCE_HOTPLUG_MASK;
hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
hotplug_en &= CRT_HOTPLUG_MASK;
hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
if (IS_G4X(dev))
......@@ -255,11 +256,17 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
} while (time_after(timeout, jiffies));
}
if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
CRT_HOTPLUG_MONITOR_NONE)
return true;
stat = I915_READ(PORT_HOTPLUG_STAT);
if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
ret = true;
return false;
/* clear the interrupt we just generated, if any */
I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
/* and put the bits back */
I915_WRITE(PORT_HOTPLUG_EN, orig);
return ret;
}
static bool intel_crt_detect_ddc(struct drm_encoder *encoder)
......@@ -569,7 +576,7 @@ void intel_crt_init(struct drm_device *dev)
(1 << INTEL_ANALOG_CLONE_BIT) |
(1 << INTEL_SDVO_LVDS_CLONE_BIT);
intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
connector->interlace_allowed = 0;
connector->interlace_allowed = 1;
connector->doublescan_allowed = 0;
drm_encoder_helper_add(&intel_encoder->enc, &intel_crt_helper_funcs);
......
drivers/gpu/drm/i915/intel_display.c
View file @ 709d015b
This diff is collapsed.
drivers/gpu/drm/i915/intel_dp.c
View file @ 709d015b
......@@ -576,7 +576,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
struct intel_encoder *intel_encoder;
struct intel_dp_priv *dp_priv;
if (!encoder || encoder->crtc != crtc)
if (encoder->crtc != crtc)
continue;
intel_encoder = enc_to_intel_encoder(encoder);
......@@ -675,10 +675,9 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
dp_priv->link_configuration[1] = dp_priv->lane_count;
/*
* Check for DPCD version > 1.1,
* enable enahanced frame stuff in that case
* Check for DPCD version > 1.1 and enhanced framing support
*/
if (dp_priv->dpcd[0] >= 0x11) {
if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
dp_priv->DP |= DP_ENHANCED_FRAMING;
}
......@@ -1208,6 +1207,8 @@ ironlake_dp_detect(struct drm_connector *connector)
if (dp_priv->dpcd[0] != 0)
status = connector_status_connected;
}
DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0],
dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]);
return status;
}
......@@ -1352,7 +1353,7 @@ intel_trans_dp_port_sel (struct drm_crtc *crtc)
struct intel_encoder *intel_encoder = NULL;
list_for_each_entry(encoder, &mode_config->encoder_list, head) {
if (!encoder || encoder->crtc != crtc)
if (encoder->crtc != crtc)
continue;
intel_encoder = enc_to_intel_encoder(encoder);
......
drivers/gpu/drm/i915/intel_fb.c
View file @ 709d015b
......@@ -105,7 +105,11 @@ static int intelfb_create(struct intel_fbdev *ifbdev,
}
/* Flush everything out, we'll be doing GTT only from now on */
i915_gem_object_set_to_gtt_domain(fbo, 1);
ret = i915_gem_object_set_to_gtt_domain(fbo, 1);
if (ret) {
DRM_ERROR("failed to bind fb: %d.\n", ret);
goto out_unpin;
}
info = framebuffer_alloc(0, device);
if (!info) {
......
drivers/gpu/drm/i915/intel_hdmi.c
View file @ 709d015b
......@@ -59,8 +59,11 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
SDVO_VSYNC_ACTIVE_HIGH |
SDVO_HSYNC_ACTIVE_HIGH;
if (hdmi_priv->has_hdmi_sink)
if (hdmi_priv->has_hdmi_sink) {
sdvox |= SDVO_AUDIO_ENABLE;
if (HAS_PCH_CPT(dev))
sdvox |= HDMI_MODE_SELECT;
}
if (intel_crtc->pipe == 1) {
if (HAS_PCH_CPT(dev))
......
drivers/gpu/drm/i915/intel_overlay.c
View file @ 709d015b
......@@ -211,9 +211,8 @@ static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
static int intel_overlay_on(struct intel_overlay *overlay)
{
struct drm_device *dev = overlay->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
int ret;
RING_LOCALS;
drm_i915_private_t *dev_priv = dev->dev_private;
BUG_ON(overlay->active);
......@@ -227,11 +226,13 @@ static int intel_overlay_on(struct intel_overlay *overlay)
OUT_RING(MI_NOOP);
ADVANCE_LP_RING();
overlay->last_flip_req = i915_add_request(dev, NULL, 0);
overlay->last_flip_req =
i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
if (overlay->last_flip_req == 0)
return -ENOMEM;
ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
ret = i915_do_wait_request(dev,
overlay->last_flip_req, 1, &dev_priv->render_ring);
if (ret != 0)
return ret;
......@@ -248,7 +249,6 @@ static void intel_overlay_continue(struct intel_overlay *overlay,
drm_i915_private_t *dev_priv = dev->dev_private;
u32 flip_addr = overlay->flip_addr;
u32 tmp;
RING_LOCALS;
BUG_ON(!overlay->active);
......@@ -265,7 +265,8 @@ static void intel_overlay_continue(struct intel_overlay *overlay,
OUT_RING(flip_addr);
ADVANCE_LP_RING();
overlay->last_flip_req = i915_add_request(dev, NULL, 0);
overlay->last_flip_req =
i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
}
static int intel_overlay_wait_flip(struct intel_overlay *overlay)
......@@ -274,10 +275,10 @@ static int intel_overlay_wait_flip(struct intel_overlay *overlay)
drm_i915_private_t *dev_priv = dev->dev_private;
int ret;
u32 tmp;
RING_LOCALS;
if (overlay->last_flip_req != 0) {
ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
ret = i915_do_wait_request(dev, overlay->last_flip_req,
1, &dev_priv->render_ring);
if (ret == 0) {
overlay->last_flip_req = 0;
......@@ -296,11 +297,13 @@ static int intel_overlay_wait_flip(struct intel_overlay *overlay)
OUT_RING(MI_NOOP);
ADVANCE_LP_RING();
overlay->last_flip_req = i915_add_request(dev, NULL, 0);
overlay->last_flip_req =
i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
if (overlay->last_flip_req == 0)
return -ENOMEM;
ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
ret = i915_do_wait_request(dev, overlay->last_flip_req,
1, &dev_priv->render_ring);
if (ret != 0)
return ret;
......@@ -316,7 +319,6 @@ static int intel_overlay_off(struct intel_overlay *overlay)
struct drm_device *dev = overlay->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
int ret;
RING_LOCALS;
BUG_ON(!overlay->active);
......@@ -336,11 +338,13 @@ static int intel_overlay_off(struct intel_overlay *overlay)
OUT_RING(MI_NOOP);
ADVANCE_LP_RING();
overlay->last_flip_req = i915_add_request(dev, NULL, 0);
overlay->last_flip_req =
i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
if (overlay->last_flip_req == 0)
return -ENOMEM;
ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
ret = i915_do_wait_request(dev, overlay->last_flip_req,
1, &dev_priv->render_ring);
if (ret != 0)
return ret;
......@@ -354,11 +358,13 @@ static int intel_overlay_off(struct intel_overlay *overlay)
OUT_RING(MI_NOOP);
ADVANCE_LP_RING();
overlay->last_flip_req = i915_add_request(dev, NULL, 0);
overlay->last_flip_req =
i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
if (overlay->last_flip_req == 0)
return -ENOMEM;
ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
ret = i915_do_wait_request(dev, overlay->last_flip_req,
1, &dev_priv->render_ring);
if (ret != 0)
return ret;
......@@ -390,22 +396,23 @@ int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
int interruptible)
{
struct drm_device *dev = overlay->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
struct drm_gem_object *obj;
drm_i915_private_t *dev_priv = dev->dev_private;
u32 flip_addr;
int ret;
RING_LOCALS;
if (overlay->hw_wedged == HW_WEDGED)
return -EIO;
if (overlay->last_flip_req == 0) {
overlay->last_flip_req = i915_add_request(dev, NULL, 0);
overlay->last_flip_req =
i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
if (overlay->last_flip_req == 0)
return -ENOMEM;
}
ret = i915_do_wait_request(dev, overlay->last_flip_req, interruptible);
ret = i915_do_wait_request(dev, overlay->last_flip_req,
interruptible, &dev_priv->render_ring);
if (ret != 0)
return ret;
......@@ -429,12 +436,13 @@ int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
OUT_RING(MI_NOOP);
ADVANCE_LP_RING();
overlay->last_flip_req = i915_add_request(dev, NULL, 0);
overlay->last_flip_req = i915_add_request(dev, NULL,
0, &dev_priv->render_ring);
if (overlay->last_flip_req == 0)
return -ENOMEM;
ret = i915_do_wait_request(dev, overlay->last_flip_req,
interruptible);
interruptible, &dev_priv->render_ring);
if (ret != 0)
return ret;
......
drivers/gpu/drm/i915/intel_ringbuffer.c 0 → 100644
View file @ 709d015b
This diff is collapsed.
drivers/gpu/drm/i915/intel_ringbuffer.h 0 → 100644
View file @ 709d015b
#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_
struct intel_hw_status_page {
void *page_addr;
unsigned int gfx_addr;
struct drm_gem_object *obj;
};
struct drm_i915_gem_execbuffer2;
struct intel_ring_buffer {
const char *name;
struct ring_regs {
u32 ctl;
u32 head;
u32 tail;
u32 start;
} regs;
unsigned int ring_flag;
unsigned long size;
unsigned int alignment;
void *virtual_start;
struct drm_device *dev;
struct drm_gem_object *gem_object;
unsigned int head;
unsigned int tail;
unsigned int space;
u32 next_seqno;
struct intel_hw_status_page status_page;
u32 irq_gem_seqno; /* last seq seem at irq time */
u32 waiting_gem_seqno;
int user_irq_refcount;
void (*user_irq_get)(struct drm_device *dev,
struct intel_ring_buffer *ring);
void (*user_irq_put)(struct drm_device *dev,
struct intel_ring_buffer *ring);
void (*setup_status_page)(struct drm_device *dev,
struct intel_ring_buffer *ring);
int (*init)(struct drm_device *dev,
struct intel_ring_buffer *ring);
unsigned int (*get_head)(struct drm_device *dev,
struct intel_ring_buffer *ring);
unsigned int (*get_tail)(struct drm_device *dev,
struct intel_ring_buffer *ring);
unsigned int (*get_active_head)(struct drm_device *dev,
struct intel_ring_buffer *ring);
void (*advance_ring)(struct drm_device *dev,
struct intel_ring_buffer *ring);
void (*flush)(struct drm_device *dev,
struct intel_ring_buffer *ring,
u32 invalidate_domains,
u32 flush_domains);
u32 (*add_request)(struct drm_device *dev,
struct intel_ring_buffer *ring,
struct drm_file *file_priv,
u32 flush_domains);
u32 (*get_gem_seqno)(struct drm_device *dev,
struct intel_ring_buffer *ring);
int (*dispatch_gem_execbuffer)(struct drm_device *dev,
struct intel_ring_buffer *ring,
struct drm_i915_gem_execbuffer2 *exec,
struct drm_clip_rect *cliprects,
uint64_t exec_offset);
/**
* List of objects currently involved in rendering from the
* ringbuffer.
*
* Includes buffers having the contents of their GPU caches
* flushed, not necessarily primitives. last_rendering_seqno
* represents when the rendering involved will be completed.
*
* A reference is held on the buffer while on this list.
*/
struct list_head active_list;
/**
* List of breadcrumbs associated with GPU requests currently
* outstanding.
*/
struct list_head request_list;
wait_queue_head_t irq_queue;
drm_local_map_t map;
};
static inline u32
intel_read_status_page(struct intel_ring_buffer *ring,
int reg)
{
u32 *regs = ring->status_page.page_addr;
return regs[reg];
}
int intel_init_ring_buffer(struct drm_device *dev,
struct intel_ring_buffer *ring);
void intel_cleanup_ring_buffer(struct drm_device *dev,
struct intel_ring_buffer *ring);
int intel_wait_ring_buffer(struct drm_device *dev,
struct intel_ring_buffer *ring, int n);
int intel_wrap_ring_buffer(struct drm_device *dev,
struct intel_ring_buffer *ring);
void intel_ring_begin(struct drm_device *dev,
struct intel_ring_buffer *ring, int n);
void intel_ring_emit(struct drm_device *dev,
struct intel_ring_buffer *ring, u32 data);
void intel_fill_struct(struct drm_device *dev,
struct intel_ring_buffer *ring,
void *data,
unsigned int len);
void intel_ring_advance(struct drm_device *dev,
struct intel_ring_buffer *ring);
u32 intel_ring_get_seqno(struct drm_device *dev,
struct intel_ring_buffer *ring);
extern struct intel_ring_buffer render_ring;
extern struct intel_ring_buffer bsd_ring;
#endif /* _INTEL_RINGBUFFER_H_ */
drivers/gpu/drm/i915/intel_sdvo.c
View file @ 709d015b
......@@ -1479,7 +1479,7 @@ intel_find_analog_connector(struct drm_device *dev)
intel_encoder = enc_to_intel_encoder(encoder);
if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
if (connector && encoder == intel_attached_encoder(connector))
if (encoder == intel_attached_encoder(connector))
return connector;
}
}
......
include/drm/i915_drm.h
View file @ 709d015b
......@@ -275,6 +275,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_OVERLAY 7
#define I915_PARAM_HAS_PAGEFLIPPING 8
#define I915_PARAM_HAS_EXECBUF2 9
#define I915_PARAM_HAS_BSD 10
typedef struct drm_i915_getparam {
int param;
......@@ -616,7 +617,9 @@ struct drm_i915_gem_execbuffer2 {
__u32 num_cliprects;
/** This is a struct drm_clip_rect *cliprects */
__u64 cliprects_ptr;
__u64 flags; /* currently unused */
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD (1<<1)
__u64 flags;
__u64 rsvd1;
__u64 rsvd2;
};
......
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