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nexedi
linux
Commits
728dd198
Commit
728dd198
authored
May 28, 2014
by
Rob Herring
Browse files
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Plain Diff
Merge branch 'earlycon-dt' into for-next
parents
e723e442
45e0f0f5
Changes
51
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Showing
51 changed files
with
3598 additions
and
1100 deletions
+3598
-1100
Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt
Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt
+33
-0
Documentation/kernel-parameters.txt
Documentation/kernel-parameters.txt
+9
-0
arch/arm/kernel/devtree.c
arch/arm/kernel/devtree.c
+7
-4
arch/arm/mach-imx/clk-imx35.c
arch/arm/mach-imx/clk-imx35.c
+1
-3
arch/arm64/Kconfig
arch/arm64/Kconfig
+3
-0
arch/arm64/Kconfig.debug
arch/arm64/Kconfig.debug
+0
-9
arch/arm64/kernel/Makefile
arch/arm64/kernel/Makefile
+0
-1
arch/arm64/kernel/early_printk.c
arch/arm64/kernel/early_printk.c
+0
-156
arch/x86/Kconfig
arch/x86/Kconfig
+3
-0
drivers/bluetooth/hci_ldisc.c
drivers/bluetooth/hci_ldisc.c
+19
-5
drivers/bluetooth/hci_uart.h
drivers/bluetooth/hci_uart.h
+1
-0
drivers/clk/rockchip/clk-rockchip.c
drivers/clk/rockchip/clk-rockchip.c
+1
-2
drivers/clk/sunxi/clk-sunxi.c
drivers/clk/sunxi/clk-sunxi.c
+2
-3
drivers/clk/ti/gate.c
drivers/clk/ti/gate.c
+1
-1
drivers/clocksource/clksrc-of.c
drivers/clocksource/clksrc-of.c
+1
-1
drivers/irqchip/irq-mxs.c
drivers/irqchip/irq-mxs.c
+2
-2
drivers/irqchip/irq-s3c24xx.c
drivers/irqchip/irq-s3c24xx.c
+2
-4
drivers/irqchip/irqchip.c
drivers/irqchip/irqchip.c
+3
-3
drivers/irqchip/irqchip.h
drivers/irqchip/irqchip.h
+3
-4
drivers/of/Makefile
drivers/of/Makefile
+2
-0
drivers/of/fdt.c
drivers/of/fdt.c
+56
-0
drivers/of/fdt_address.c
drivers/of/fdt_address.c
+241
-0
drivers/of/of_reserved_mem.c
drivers/of/of_reserved_mem.c
+1
-1
drivers/tty/serial/8250/8250_core.c
drivers/tty/serial/8250/8250_core.c
+0
-5
drivers/tty/serial/8250/8250_dw.c
drivers/tty/serial/8250/8250_dw.c
+77
-4
drivers/tty/serial/8250/8250_early.c
drivers/tty/serial/8250/8250_early.c
+20
-118
drivers/tty/serial/8250/Kconfig
drivers/tty/serial/8250/Kconfig
+1
-5
drivers/tty/serial/Kconfig
drivers/tty/serial/Kconfig
+43
-4
drivers/tty/serial/Makefile
drivers/tty/serial/Makefile
+5
-0
drivers/tty/serial/amba-pl011.c
drivers/tty/serial/amba-pl011.c
+30
-1
drivers/tty/serial/earlycon-arm-semihost.c
drivers/tty/serial/earlycon-arm-semihost.c
+61
-0
drivers/tty/serial/earlycon.c
drivers/tty/serial/earlycon.c
+172
-0
drivers/tty/serial/men_z135_uart.c
drivers/tty/serial/men_z135_uart.c
+866
-0
drivers/tty/serial/mux.c
drivers/tty/serial/mux.c
+2
-2
drivers/tty/serial/omap-serial.c
drivers/tty/serial/omap-serial.c
+19
-75
drivers/tty/serial/pch_uart.c
drivers/tty/serial/pch_uart.c
+7
-6
drivers/tty/serial/pxa.c
drivers/tty/serial/pxa.c
+0
-5
drivers/tty/serial/sc16is7xx.c
drivers/tty/serial/sc16is7xx.c
+1280
-0
drivers/tty/serial/serial_core.c
drivers/tty/serial/serial_core.c
+3
-0
drivers/tty/serial/serial_txx9.c
drivers/tty/serial/serial_txx9.c
+0
-5
drivers/tty/serial/xilinx_uartps.c
drivers/tty/serial/xilinx_uartps.c
+540
-589
include/asm-generic/vmlinux.lds.h
include/asm-generic/vmlinux.lds.h
+16
-44
include/linux/clk-provider.h
include/linux/clk-provider.h
+1
-4
include/linux/clocksource.h
include/linux/clocksource.h
+3
-13
include/linux/of.h
include/linux/of.h
+22
-0
include/linux/of_fdt.h
include/linux/of_fdt.h
+1
-0
include/linux/of_reserved_mem.h
include/linux/of_reserved_mem.h
+4
-18
include/linux/serial_core.h
include/linux/serial_core.h
+22
-0
include/linux/tty_ldisc.h
include/linux/tty_ldisc.h
+4
-1
include/uapi/linux/serial_core.h
include/uapi/linux/serial_core.h
+7
-1
include/uapi/linux/serial_reg.h
include/uapi/linux/serial_reg.h
+1
-1
No files found.
Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt
0 → 100644
View file @
728dd198
* NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
Required properties:
- compatible: Should be one of the following:
- "nxp,sc16is740" for NXP SC16IS740,
- "nxp,sc16is741" for NXP SC16IS741,
- "nxp,sc16is750" for NXP SC16IS750,
- "nxp,sc16is752" for NXP SC16IS752,
- "nxp,sc16is760" for NXP SC16IS760,
- "nxp,sc16is762" for NXP SC16IS762.
- reg: I2C address of the SC16IS7xx device.
- interrupt-parent: The phandle for the interrupt controller that
services interrupts for this IC.
- interrupts: Should contain the UART interrupt
- clocks: Reference to the IC source clock.
Optional properties:
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be two. The first cell is the GPIO number and
the second cell is used to specify the GPIO polarity:
0 = active high,
1 = active low.
Example:
sc16is750: sc16is750@51 {
compatible = "nxp,sc16is750";
reg = <0x51>;
clocks = <&clk20m>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
};
Documentation/kernel-parameters.txt
View file @
728dd198
...
@@ -883,6 +883,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
...
@@ -883,6 +883,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
which are not unmapped.
which are not unmapped.
earlycon= [KNL] Output early console device and options.
earlycon= [KNL] Output early console device and options.
uart[8250],io,<addr>[,options]
uart[8250],io,<addr>[,options]
uart[8250],mmio,<addr>[,options]
uart[8250],mmio,<addr>[,options]
uart[8250],mmio32,<addr>[,options]
uart[8250],mmio32,<addr>[,options]
...
@@ -892,6 +893,14 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
...
@@ -892,6 +893,14 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
(mmio) or 32-bit (mmio32).
(mmio) or 32-bit (mmio32).
The options are the same as for ttyS, above.
The options are the same as for ttyS, above.
pl011,<addr>
Start an early, polled-mode console on a pl011 serial
port at the specified address. The pl011 serial port
must already be setup and configured. Options are not
yet supported.
smh Use ARM semihosting calls for early console.
earlyprintk= [X86,SH,BLACKFIN,ARM]
earlyprintk= [X86,SH,BLACKFIN,ARM]
earlyprintk=vga
earlyprintk=vga
earlyprintk=efi
earlyprintk=efi
...
...
arch/arm/kernel/devtree.c
View file @
728dd198
...
@@ -33,18 +33,21 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
...
@@ -33,18 +33,21 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
}
}
#ifdef CONFIG_SMP
#ifdef CONFIG_SMP
extern
struct
of_cpu_method
__cpu_method_of_table_begin
[];
extern
struct
of_cpu_method
__cpu_method_of_table
[];
extern
struct
of_cpu_method
__cpu_method_of_table_end
[];
static
const
struct
of_cpu_method
__cpu_method_of_table_sentinel
__used
__section
(
__cpu_method_of_table_end
);
static
int
__init
set_smp_ops_by_method
(
struct
device_node
*
node
)
static
int
__init
set_smp_ops_by_method
(
struct
device_node
*
node
)
{
{
const
char
*
method
;
const
char
*
method
;
struct
of_cpu_method
*
m
=
__cpu_method_of_table
_begin
;
struct
of_cpu_method
*
m
=
__cpu_method_of_table
;
if
(
of_property_read_string
(
node
,
"enable-method"
,
&
method
))
if
(
of_property_read_string
(
node
,
"enable-method"
,
&
method
))
return
0
;
return
0
;
for
(;
m
<
__cpu_method_of_table_en
d
;
m
++
)
for
(;
m
->
metho
d
;
m
++
)
if
(
!
strcmp
(
m
->
method
,
method
))
{
if
(
!
strcmp
(
m
->
method
,
method
))
{
smp_set_ops
(
m
->
ops
);
smp_set_ops
(
m
->
ops
);
return
1
;
return
1
;
...
...
arch/arm/mach-imx/clk-imx35.c
View file @
728dd198
...
@@ -289,14 +289,12 @@ int __init mx35_clocks_init(void)
...
@@ -289,14 +289,12 @@ int __init mx35_clocks_init(void)
return
0
;
return
0
;
}
}
static
int
__init
mx35_clocks_init_dt
(
struct
device_node
*
ccm_node
)
static
void
__init
mx35_clocks_init_dt
(
struct
device_node
*
ccm_node
)
{
{
clk_data
.
clks
=
clk
;
clk_data
.
clks
=
clk
;
clk_data
.
clk_num
=
ARRAY_SIZE
(
clk
);
clk_data
.
clk_num
=
ARRAY_SIZE
(
clk
);
of_clk_add_provider
(
ccm_node
,
of_clk_src_onecell_get
,
&
clk_data
);
of_clk_add_provider
(
ccm_node
,
of_clk_src_onecell_get
,
&
clk_data
);
mx35_clocks_init
();
mx35_clocks_init
();
return
0
;
}
}
CLK_OF_DECLARE
(
imx35
,
"fsl,imx35-ccm"
,
mx35_clocks_init_dt
);
CLK_OF_DECLARE
(
imx35
,
"fsl,imx35-ccm"
,
mx35_clocks_init_dt
);
arch/arm64/Kconfig
View file @
728dd198
...
@@ -112,6 +112,9 @@ config IOMMU_HELPER
...
@@ -112,6 +112,9 @@ config IOMMU_HELPER
config KERNEL_MODE_NEON
config KERNEL_MODE_NEON
def_bool y
def_bool y
config FIX_EARLYCON_MEM
def_bool y
source "init/Kconfig"
source "init/Kconfig"
source "kernel/Kconfig.freezer"
source "kernel/Kconfig.freezer"
...
...
arch/arm64/Kconfig.debug
View file @
728dd198
...
@@ -20,15 +20,6 @@ config STRICT_DEVMEM
...
@@ -20,15 +20,6 @@ config STRICT_DEVMEM
If in doubt, say Y.
If in doubt, say Y.
config EARLY_PRINTK
bool "Early printk support"
default y
help
Say Y here if you want to have an early console using the
earlyprintk=<name>[,<addr>][,<options>] kernel parameter. It
is assumed that the early console device has been initialised
by the boot loader prior to starting the Linux kernel.
config PID_IN_CONTEXTIDR
config PID_IN_CONTEXTIDR
bool "Write the current PID to the CONTEXTIDR register"
bool "Write the current PID to the CONTEXTIDR register"
help
help
...
...
arch/arm64/kernel/Makefile
View file @
728dd198
...
@@ -18,7 +18,6 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o topology.o
...
@@ -18,7 +18,6 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o topology.o
arm64-obj-$(CONFIG_PERF_EVENTS)
+=
perf_regs.o
arm64-obj-$(CONFIG_PERF_EVENTS)
+=
perf_regs.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS)
+=
perf_event.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS)
+=
perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)
+=
hw_breakpoint.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)
+=
hw_breakpoint.o
arm64-obj-$(CONFIG_EARLY_PRINTK)
+=
early_printk.o
arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND)
+=
sleep.o suspend.o
arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND)
+=
sleep.o suspend.o
arm64-obj-$(CONFIG_JUMP_LABEL)
+=
jump_label.o
arm64-obj-$(CONFIG_JUMP_LABEL)
+=
jump_label.o
arm64-obj-$(CONFIG_KGDB)
+=
kgdb.o
arm64-obj-$(CONFIG_KGDB)
+=
kgdb.o
...
...
arch/arm64/kernel/early_printk.c
deleted
100644 → 0
View file @
e723e442
/*
* Earlyprintk support.
*
* Copyright (C) 2012 ARM Ltd.
* Author: Catalin Marinas <catalin.marinas@arm.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/kernel.h>
#include <linux/console.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <linux/amba/serial.h>
#include <linux/serial_reg.h>
#include <asm/fixmap.h>
static
void
__iomem
*
early_base
;
static
void
(
*
printch
)(
char
ch
);
/*
* PL011 single character TX.
*/
static
void
pl011_printch
(
char
ch
)
{
while
(
readl_relaxed
(
early_base
+
UART01x_FR
)
&
UART01x_FR_TXFF
)
;
writeb_relaxed
(
ch
,
early_base
+
UART01x_DR
);
while
(
readl_relaxed
(
early_base
+
UART01x_FR
)
&
UART01x_FR_BUSY
)
;
}
/*
* Semihosting-based debug console
*/
static
void
smh_printch
(
char
ch
)
{
asm
volatile
(
"mov x1, %0
\n
"
"mov x0, #3
\n
"
"hlt 0xf000
\n
"
:
:
"r"
(
&
ch
)
:
"x0"
,
"x1"
,
"memory"
);
}
/*
* 8250/16550 (8-bit aligned registers) single character TX.
*/
static
void
uart8250_8bit_printch
(
char
ch
)
{
while
(
!
(
readb_relaxed
(
early_base
+
UART_LSR
)
&
UART_LSR_THRE
))
;
writeb_relaxed
(
ch
,
early_base
+
UART_TX
);
}
/*
* 8250/16550 (32-bit aligned registers) single character TX.
*/
static
void
uart8250_32bit_printch
(
char
ch
)
{
while
(
!
(
readl_relaxed
(
early_base
+
(
UART_LSR
<<
2
))
&
UART_LSR_THRE
))
;
writel_relaxed
(
ch
,
early_base
+
(
UART_TX
<<
2
));
}
struct
earlycon_match
{
const
char
*
name
;
void
(
*
printch
)(
char
ch
);
};
static
const
struct
earlycon_match
earlycon_match
[]
__initconst
=
{
{
.
name
=
"pl011"
,
.
printch
=
pl011_printch
,
},
{
.
name
=
"smh"
,
.
printch
=
smh_printch
,
},
{
.
name
=
"uart8250-8bit"
,
.
printch
=
uart8250_8bit_printch
,
},
{
.
name
=
"uart8250-32bit"
,
.
printch
=
uart8250_32bit_printch
,
},
{}
};
static
void
early_write
(
struct
console
*
con
,
const
char
*
s
,
unsigned
n
)
{
while
(
n
--
>
0
)
{
if
(
*
s
==
'\n'
)
printch
(
'\r'
);
printch
(
*
s
);
s
++
;
}
}
static
struct
console
early_console_dev
=
{
.
name
=
"earlycon"
,
.
write
=
early_write
,
.
flags
=
CON_PRINTBUFFER
|
CON_BOOT
,
.
index
=
-
1
,
};
/*
* Parse earlyprintk=... parameter in the format:
*
* <name>[,<addr>][,<options>]
*
* and register the early console. It is assumed that the UART has been
* initialised by the bootloader already.
*/
static
int
__init
setup_early_printk
(
char
*
buf
)
{
const
struct
earlycon_match
*
match
=
earlycon_match
;
phys_addr_t
paddr
=
0
;
if
(
!
buf
)
{
pr_warning
(
"No earlyprintk arguments passed.
\n
"
);
return
0
;
}
while
(
match
->
name
)
{
size_t
len
=
strlen
(
match
->
name
);
if
(
!
strncmp
(
buf
,
match
->
name
,
len
))
{
buf
+=
len
;
break
;
}
match
++
;
}
if
(
!
match
->
name
)
{
pr_warning
(
"Unknown earlyprintk arguments: %s
\n
"
,
buf
);
return
0
;
}
/* I/O address */
if
(
!
strncmp
(
buf
,
",0x"
,
3
))
{
char
*
e
;
paddr
=
simple_strtoul
(
buf
+
1
,
&
e
,
16
);
buf
=
e
;
}
/* no options parsing yet */
if
(
paddr
)
early_base
=
(
void
__iomem
*
)
set_fixmap_offset_io
(
FIX_EARLYCON_MEM_BASE
,
paddr
);
printch
=
match
->
printch
;
early_console
=
&
early_console_dev
;
register_console
(
&
early_console_dev
);
return
0
;
}
early_param
(
"earlyprintk"
,
setup_early_printk
);
arch/x86/Kconfig
View file @
728dd198
...
@@ -261,6 +261,9 @@ config ARCH_HWEIGHT_CFLAGS
...
@@ -261,6 +261,9 @@ config ARCH_HWEIGHT_CFLAGS
config ARCH_SUPPORTS_UPROBES
config ARCH_SUPPORTS_UPROBES
def_bool y
def_bool y
config FIX_EARLYCON_MEM
def_bool y
source "init/Kconfig"
source "init/Kconfig"
source "kernel/Kconfig.freezer"
source "kernel/Kconfig.freezer"
...
...
drivers/bluetooth/hci_ldisc.c
View file @
728dd198
...
@@ -118,10 +118,6 @@ static inline struct sk_buff *hci_uart_dequeue(struct hci_uart *hu)
...
@@ -118,10 +118,6 @@ static inline struct sk_buff *hci_uart_dequeue(struct hci_uart *hu)
int
hci_uart_tx_wakeup
(
struct
hci_uart
*
hu
)
int
hci_uart_tx_wakeup
(
struct
hci_uart
*
hu
)
{
{
struct
tty_struct
*
tty
=
hu
->
tty
;
struct
hci_dev
*
hdev
=
hu
->
hdev
;
struct
sk_buff
*
skb
;
if
(
test_and_set_bit
(
HCI_UART_SENDING
,
&
hu
->
tx_state
))
{
if
(
test_and_set_bit
(
HCI_UART_SENDING
,
&
hu
->
tx_state
))
{
set_bit
(
HCI_UART_TX_WAKEUP
,
&
hu
->
tx_state
);
set_bit
(
HCI_UART_TX_WAKEUP
,
&
hu
->
tx_state
);
return
0
;
return
0
;
...
@@ -129,6 +125,22 @@ int hci_uart_tx_wakeup(struct hci_uart *hu)
...
@@ -129,6 +125,22 @@ int hci_uart_tx_wakeup(struct hci_uart *hu)
BT_DBG
(
""
);
BT_DBG
(
""
);
schedule_work
(
&
hu
->
write_work
);
return
0
;
}
static
void
hci_uart_write_work
(
struct
work_struct
*
work
)
{
struct
hci_uart
*
hu
=
container_of
(
work
,
struct
hci_uart
,
write_work
);
struct
tty_struct
*
tty
=
hu
->
tty
;
struct
hci_dev
*
hdev
=
hu
->
hdev
;
struct
sk_buff
*
skb
;
/* REVISIT: should we cope with bad skbs or ->write() returning
* and error value ?
*/
restart:
restart:
clear_bit
(
HCI_UART_TX_WAKEUP
,
&
hu
->
tx_state
);
clear_bit
(
HCI_UART_TX_WAKEUP
,
&
hu
->
tx_state
);
...
@@ -153,7 +165,6 @@ int hci_uart_tx_wakeup(struct hci_uart *hu)
...
@@ -153,7 +165,6 @@ int hci_uart_tx_wakeup(struct hci_uart *hu)
goto
restart
;
goto
restart
;
clear_bit
(
HCI_UART_SENDING
,
&
hu
->
tx_state
);
clear_bit
(
HCI_UART_SENDING
,
&
hu
->
tx_state
);
return
0
;
}
}
static
void
hci_uart_init_work
(
struct
work_struct
*
work
)
static
void
hci_uart_init_work
(
struct
work_struct
*
work
)
...
@@ -282,6 +293,7 @@ static int hci_uart_tty_open(struct tty_struct *tty)
...
@@ -282,6 +293,7 @@ static int hci_uart_tty_open(struct tty_struct *tty)
tty
->
receive_room
=
65536
;
tty
->
receive_room
=
65536
;
INIT_WORK
(
&
hu
->
init_ready
,
hci_uart_init_work
);
INIT_WORK
(
&
hu
->
init_ready
,
hci_uart_init_work
);
INIT_WORK
(
&
hu
->
write_work
,
hci_uart_write_work
);
spin_lock_init
(
&
hu
->
rx_lock
);
spin_lock_init
(
&
hu
->
rx_lock
);
...
@@ -319,6 +331,8 @@ static void hci_uart_tty_close(struct tty_struct *tty)
...
@@ -319,6 +331,8 @@ static void hci_uart_tty_close(struct tty_struct *tty)
if
(
hdev
)
if
(
hdev
)
hci_uart_close
(
hdev
);
hci_uart_close
(
hdev
);
cancel_work_sync
(
&
hu
->
write_work
);
if
(
test_and_clear_bit
(
HCI_UART_PROTO_SET
,
&
hu
->
flags
))
{
if
(
test_and_clear_bit
(
HCI_UART_PROTO_SET
,
&
hu
->
flags
))
{
if
(
hdev
)
{
if
(
hdev
)
{
if
(
test_bit
(
HCI_UART_REGISTERED
,
&
hu
->
flags
))
if
(
test_bit
(
HCI_UART_REGISTERED
,
&
hu
->
flags
))
...
...
drivers/bluetooth/hci_uart.h
View file @
728dd198
...
@@ -68,6 +68,7 @@ struct hci_uart {
...
@@ -68,6 +68,7 @@ struct hci_uart {
unsigned
long
hdev_flags
;
unsigned
long
hdev_flags
;
struct
work_struct
init_ready
;
struct
work_struct
init_ready
;
struct
work_struct
write_work
;
struct
hci_uart_proto
*
proto
;
struct
hci_uart_proto
*
proto
;
void
*
priv
;
void
*
priv
;
...
...
drivers/clk/rockchip/clk-rockchip.c
View file @
728dd198
...
@@ -24,8 +24,7 @@ static DEFINE_SPINLOCK(clk_lock);
...
@@ -24,8 +24,7 @@ static DEFINE_SPINLOCK(clk_lock);
* Gate clocks
* Gate clocks
*/
*/
static
void
__init
rk2928_gate_clk_init
(
struct
device_node
*
node
,
static
void
__init
rk2928_gate_clk_init
(
struct
device_node
*
node
)
void
*
data
)
{
{
struct
clk_onecell_data
*
clk_data
;
struct
clk_onecell_data
*
clk_data
;
const
char
*
clk_parent
;
const
char
*
clk_parent
;
...
...
drivers/clk/sunxi/clk-sunxi.c
View file @
728dd198
...
@@ -1278,8 +1278,7 @@ static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_mat
...
@@ -1278,8 +1278,7 @@ static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_mat
const
struct
of_device_id
*
match
;
const
struct
of_device_id
*
match
;
void
(
*
setup_function
)(
struct
device_node
*
,
const
void
*
)
=
function
;
void
(
*
setup_function
)(
struct
device_node
*
,
const
void
*
)
=
function
;
for_each_matching_node
(
np
,
clk_match
)
{
for_each_matching_node_and_match
(
np
,
clk_match
,
&
match
)
{
match
=
of_match_node
(
clk_match
,
np
);
data
=
match
->
data
;
data
=
match
->
data
;
setup_function
(
np
,
data
);
setup_function
(
np
,
data
);
}
}
...
@@ -1310,7 +1309,7 @@ static void __init sunxi_clock_protect(void)
...
@@ -1310,7 +1309,7 @@ static void __init sunxi_clock_protect(void)
}
}
}
}
static
void
__init
sunxi_init_clocks
(
void
)
static
void
__init
sunxi_init_clocks
(
struct
device_node
*
np
)
{
{
/* Register factor clocks */
/* Register factor clocks */
of_sunxi_table_clock_setup
(
clk_factors_match
,
sunxi_factors_clk_setup
);
of_sunxi_table_clock_setup
(
clk_factors_match
,
sunxi_factors_clk_setup
);
...
...
drivers/clk/ti/gate.c
View file @
728dd198
...
@@ -221,7 +221,7 @@ static void __init of_ti_gate_clk_setup(struct device_node *node)
...
@@ -221,7 +221,7 @@ static void __init of_ti_gate_clk_setup(struct device_node *node)
{
{
_of_ti_gate_clk_setup
(
node
,
&
omap_gate_clk_ops
,
NULL
);
_of_ti_gate_clk_setup
(
node
,
&
omap_gate_clk_ops
,
NULL
);
}
}
CLK_OF_DECLARE
(
ti_gate_clk
,
"ti,gate-clock"
,
of_ti_gate_clk_setup
)
CLK_OF_DECLARE
(
ti_gate_clk
,
"ti,gate-clock"
,
of_ti_gate_clk_setup
)
;
static
void
__init
of_ti_wait_gate_clk_setup
(
struct
device_node
*
node
)
static
void
__init
of_ti_wait_gate_clk_setup
(
struct
device_node
*
node
)
{
{
...
...
drivers/clocksource/clksrc-of.c
View file @
728dd198
...
@@ -27,7 +27,7 @@ void __init clocksource_of_init(void)
...
@@ -27,7 +27,7 @@ void __init clocksource_of_init(void)
{
{
struct
device_node
*
np
;
struct
device_node
*
np
;
const
struct
of_device_id
*
match
;
const
struct
of_device_id
*
match
;
clocksource_of_init_fn
init_func
;
of_init_fn_1
init_func
;
unsigned
clocksources
=
0
;
unsigned
clocksources
=
0
;
for_each_matching_node_and_match
(
np
,
__clksrc_of_table
,
&
match
)
{
for_each_matching_node_and_match
(
np
,
__clksrc_of_table
,
&
match
)
{
...
...
drivers/irqchip/irq-mxs.c
View file @
728dd198
...
@@ -96,7 +96,7 @@ static struct irq_domain_ops icoll_irq_domain_ops = {
...
@@ -96,7 +96,7 @@ static struct irq_domain_ops icoll_irq_domain_ops = {
.
xlate
=
irq_domain_xlate_onecell
,
.
xlate
=
irq_domain_xlate_onecell
,
};
};
static
void
__init
icoll_of_init
(
struct
device_node
*
np
,
static
int
__init
icoll_of_init
(
struct
device_node
*
np
,
struct
device_node
*
interrupt_parent
)
struct
device_node
*
interrupt_parent
)
{
{
icoll_base
=
of_iomap
(
np
,
0
);
icoll_base
=
of_iomap
(
np
,
0
);
...
@@ -110,6 +110,6 @@ static void __init icoll_of_init(struct device_node *np,
...
@@ -110,6 +110,6 @@ static void __init icoll_of_init(struct device_node *np,
icoll_domain
=
irq_domain_add_linear
(
np
,
ICOLL_NUM_IRQS
,
icoll_domain
=
irq_domain_add_linear
(
np
,
ICOLL_NUM_IRQS
,
&
icoll_irq_domain_ops
,
NULL
);
&
icoll_irq_domain_ops
,
NULL
);
WARN_ON
(
!
icoll_domain
)
;
return
icoll_domain
?
0
:
-
ENODEV
;
}
}
IRQCHIP_DECLARE
(
mxs
,
"fsl,icoll"
,
icoll_of_init
);
IRQCHIP_DECLARE
(
mxs
,
"fsl,icoll"
,
icoll_of_init
);
drivers/irqchip/irq-s3c24xx.c
View file @
728dd198
...
@@ -1323,8 +1323,7 @@ static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
...
@@ -1323,8 +1323,7 @@ static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
};
};
int
__init
s3c2410_init_intc_of
(
struct
device_node
*
np
,
int
__init
s3c2410_init_intc_of
(
struct
device_node
*
np
,
struct
device_node
*
interrupt_parent
,
struct
device_node
*
interrupt_parent
)
struct
s3c24xx_irq_of_ctrl
*
ctrl
,
int
num_ctrl
)
{
{
return
s3c_init_intc_of
(
np
,
interrupt_parent
,
return
s3c_init_intc_of
(
np
,
interrupt_parent
,
s3c2410_ctrl
,
ARRAY_SIZE
(
s3c2410_ctrl
));
s3c2410_ctrl
,
ARRAY_SIZE
(
s3c2410_ctrl
));
...
@@ -1346,8 +1345,7 @@ static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
...
@@ -1346,8 +1345,7 @@ static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
};
};
int
__init
s3c2416_init_intc_of
(
struct
device_node
*
np
,
int
__init
s3c2416_init_intc_of
(
struct
device_node
*
np
,
struct
device_node
*
interrupt_parent
,
struct
device_node
*
interrupt_parent
)
struct
s3c24xx_irq_of_ctrl
*
ctrl
,
int
num_ctrl
)
{
{
return
s3c_init_intc_of
(
np
,
interrupt_parent
,
return
s3c_init_intc_of
(
np
,
interrupt_parent
,
s3c2416_ctrl
,
ARRAY_SIZE
(
s3c2416_ctrl
));
s3c2416_ctrl
,
ARRAY_SIZE
(
s3c2416_ctrl
));
...
...
drivers/irqchip/irqchip.c
View file @
728dd198
...
@@ -19,11 +19,11 @@
...
@@ -19,11 +19,11 @@
* special section.
* special section.
*/
*/
static
const
struct
of_device_id
static
const
struct
of_device_id
irqchip_of_match_end
__used
__section
(
__irqchip_of_end
);
irqchip_of_match_end
__used
__section
(
__irqchip_of_
table_
end
);
extern
struct
of_device_id
__irqchip_
begin
[];
extern
struct
of_device_id
__irqchip_
of_table
[];
void
__init
irqchip_init
(
void
)
void
__init
irqchip_init
(
void
)
{
{
of_irq_init
(
__irqchip_
begin
);
of_irq_init
(
__irqchip_
of_table
);
}
}
drivers/irqchip/irqchip.h
View file @
728dd198
...
@@ -11,6 +11,8 @@
...
@@ -11,6 +11,8 @@
#ifndef _IRQCHIP_H
#ifndef _IRQCHIP_H
#define _IRQCHIP_H
#define _IRQCHIP_H
#include <linux/of.h>
/*
/*
* This macro must be used by the different irqchip drivers to declare
* This macro must be used by the different irqchip drivers to declare
* the association between their DT compatible string and their
* the association between their DT compatible string and their
...
@@ -21,9 +23,6 @@
...
@@ -21,9 +23,6 @@
* @compstr: compatible string of the irqchip driver
* @compstr: compatible string of the irqchip driver
* @fn: initialization function
* @fn: initialization function
*/
*/
#define IRQCHIP_DECLARE(name,compstr,fn) \
#define IRQCHIP_DECLARE(name, compat, fn) OF_DECLARE_2(irqchip, name, compat, fn)
static const struct of_device_id irqchip_of_match_##name \
__used __section(__irqchip_of_table) \
= { .compatible = compstr, .data = fn }
#endif
#endif
drivers/of/Makefile
View file @
728dd198
obj-y
=
base.o device.o platform.o
obj-y
=
base.o device.o platform.o
obj-$(CONFIG_OF_FLATTREE)
+=
fdt.o
obj-$(CONFIG_OF_FLATTREE)
+=
fdt.o
obj-$(CONFIG_OF_EARLY_FLATTREE)
+=
fdt_address.o
obj-$(CONFIG_OF_PROMTREE)
+=
pdt.o
obj-$(CONFIG_OF_PROMTREE)
+=
pdt.o
obj-$(CONFIG_OF_ADDRESS)
+=
address.o
obj-$(CONFIG_OF_ADDRESS)
+=
address.o
obj-$(CONFIG_OF_IRQ)
+=
irq.o
obj-$(CONFIG_OF_IRQ)
+=
irq.o
...
@@ -12,3 +13,4 @@ obj-$(CONFIG_OF_MTD) += of_mtd.o
...
@@ -12,3 +13,4 @@ obj-$(CONFIG_OF_MTD) += of_mtd.o
obj-$(CONFIG_OF_RESERVED_MEM)
+=
of_reserved_mem.o
obj-$(CONFIG_OF_RESERVED_MEM)
+=
of_reserved_mem.o
CFLAGS_fdt.o
=
-I
$(src)
/../../scripts/dtc/libfdt
CFLAGS_fdt.o
=
-I
$(src)
/../../scripts/dtc/libfdt
CFLAGS_fdt_address.o
=
-I
$(src)
/../../scripts/dtc/libfdt
drivers/of/fdt.c
View file @
728dd198
...
@@ -21,6 +21,7 @@
...
@@ -21,6 +21,7 @@
#include <linux/slab.h>
#include <linux/slab.h>
#include <linux/libfdt.h>
#include <linux/libfdt.h>
#include <linux/debugfs.h>
#include <linux/debugfs.h>
#include <linux/serial_core.h>
#include <asm/setup.h>
/* for COMMAND_LINE_SIZE */
#include <asm/setup.h>
/* for COMMAND_LINE_SIZE */
#include <asm/page.h>
#include <asm/page.h>
...
@@ -696,6 +697,61 @@ static inline void early_init_dt_check_for_initrd(unsigned long node)
...
@@ -696,6 +697,61 @@ static inline void early_init_dt_check_for_initrd(unsigned long node)
}
}
#endif
/* CONFIG_BLK_DEV_INITRD */
#endif
/* CONFIG_BLK_DEV_INITRD */
#ifdef CONFIG_SERIAL_EARLYCON
extern
struct
of_device_id
__earlycon_of_table
[];
int
__init
early_init_dt_scan_chosen_serial
(
void
)
{
int
offset
;
const
char
*
p
;
int
l
;
const
struct
of_device_id
*
match
=
__earlycon_of_table
;
const
void
*
fdt
=
initial_boot_params
;
offset
=
fdt_path_offset
(
fdt
,
"/chosen"
);
if
(
offset
<
0
)
offset
=
fdt_path_offset
(
fdt
,
"/chosen@0"
);
if
(
offset
<
0
)
return
-
ENOENT
;
p
=
fdt_getprop
(
fdt
,
offset
,
"stdout-path"
,
&
l
);
if
(
!
p
)
p
=
fdt_getprop
(
fdt
,
offset
,
"linux,stdout-path"
,
&
l
);
if
(
!
p
||
!
l
)
return
-
ENOENT
;
/* Get the node specified by stdout-path */
offset
=
fdt_path_offset
(
fdt
,
p
);
if
(
offset
<
0
)
return
-
ENODEV
;
while
(
match
->
compatible
)
{
unsigned
long
addr
;
if
(
fdt_node_check_compatible
(
fdt
,
offset
,
match
->
compatible
))
{
match
++
;
continue
;
}
addr
=
fdt_translate_address
(
fdt
,
offset
);
if
(
!
addr
)
return
-
ENXIO
;
of_setup_earlycon
(
addr
,
match
->
data
);
return
0
;
}
return
-
ENODEV
;
}
static
int
__init
setup_of_earlycon
(
char
*
buf
)
{
if
(
buf
)
return
0
;
return
early_init_dt_scan_chosen_serial
();
}
early_param
(
"earlycon"
,
setup_of_earlycon
);
#endif
/**
/**
* early_init_dt_scan_root - fetch the top level address and size cells
* early_init_dt_scan_root - fetch the top level address and size cells
*/
*/
...
...
drivers/of/fdt_address.c
0 → 100644
View file @
728dd198
/*
* FDT Address translation based on u-boot fdt_support.c which in turn was
* based on the kernel unflattened DT address translation code.
*
* (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*/
#include <linux/kernel.h>
#include <linux/libfdt.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/sizes.h>
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
(ns) > 0)
/* Debug utility */
#ifdef DEBUG
static
void
__init
of_dump_addr
(
const
char
*
s
,
const
__be32
*
addr
,
int
na
)
{
pr_debug
(
"%s"
,
s
);
while
(
na
--
)
pr_cont
(
" %08x"
,
*
(
addr
++
));
pr_debug
(
"
\n
"
);
}
#else
static
void
__init
of_dump_addr
(
const
char
*
s
,
const
__be32
*
addr
,
int
na
)
{
}
#endif
/* Callbacks for bus specific translators */
struct
of_bus
{
void
(
*
count_cells
)(
const
void
*
blob
,
int
parentoffset
,
int
*
addrc
,
int
*
sizec
);
u64
(
*
map
)(
__be32
*
addr
,
const
__be32
*
range
,
int
na
,
int
ns
,
int
pna
);
int
(
*
translate
)(
__be32
*
addr
,
u64
offset
,
int
na
);
};
/* Default translator (generic bus) */
static
void
__init
fdt_bus_default_count_cells
(
const
void
*
blob
,
int
parentoffset
,
int
*
addrc
,
int
*
sizec
)
{
const
__be32
*
prop
;
if
(
addrc
)
{
prop
=
fdt_getprop
(
blob
,
parentoffset
,
"#address-cells"
,
NULL
);
if
(
prop
)
*
addrc
=
be32_to_cpup
(
prop
);
else
*
addrc
=
dt_root_addr_cells
;
}
if
(
sizec
)
{
prop
=
fdt_getprop
(
blob
,
parentoffset
,
"#size-cells"
,
NULL
);
if
(
prop
)
*
sizec
=
be32_to_cpup
(
prop
);
else
*
sizec
=
dt_root_size_cells
;
}
}
static
u64
__init
fdt_bus_default_map
(
__be32
*
addr
,
const
__be32
*
range
,
int
na
,
int
ns
,
int
pna
)
{
u64
cp
,
s
,
da
;
cp
=
of_read_number
(
range
,
na
);
s
=
of_read_number
(
range
+
na
+
pna
,
ns
);
da
=
of_read_number
(
addr
,
na
);
pr_debug
(
"FDT: default map, cp=%llx, s=%llx, da=%llx
\n
"
,
cp
,
s
,
da
);
if
(
da
<
cp
||
da
>=
(
cp
+
s
))
return
OF_BAD_ADDR
;
return
da
-
cp
;
}
static
int
__init
fdt_bus_default_translate
(
__be32
*
addr
,
u64
offset
,
int
na
)
{
u64
a
=
of_read_number
(
addr
,
na
);
memset
(
addr
,
0
,
na
*
4
);
a
+=
offset
;
if
(
na
>
1
)
addr
[
na
-
2
]
=
cpu_to_fdt32
(
a
>>
32
);
addr
[
na
-
1
]
=
cpu_to_fdt32
(
a
&
0xffffffffu
);
return
0
;
}
/* Array of bus specific translators */
static
const
struct
of_bus
of_busses
[]
__initconst
=
{
/* Default */
{
.
count_cells
=
fdt_bus_default_count_cells
,
.
map
=
fdt_bus_default_map
,
.
translate
=
fdt_bus_default_translate
,
},
};
static
int
__init
fdt_translate_one
(
const
void
*
blob
,
int
parent
,
const
struct
of_bus
*
bus
,
const
struct
of_bus
*
pbus
,
__be32
*
addr
,
int
na
,
int
ns
,
int
pna
,
const
char
*
rprop
)
{
const
__be32
*
ranges
;
int
rlen
;
int
rone
;
u64
offset
=
OF_BAD_ADDR
;
ranges
=
fdt_getprop
(
blob
,
parent
,
rprop
,
&
rlen
);
if
(
!
ranges
)
return
1
;
if
(
rlen
==
0
)
{
offset
=
of_read_number
(
addr
,
na
);
memset
(
addr
,
0
,
pna
*
4
);
pr_debug
(
"FDT: empty ranges, 1:1 translation
\n
"
);
goto
finish
;
}
pr_debug
(
"FDT: walking ranges...
\n
"
);
/* Now walk through the ranges */
rlen
/=
4
;
rone
=
na
+
pna
+
ns
;
for
(;
rlen
>=
rone
;
rlen
-=
rone
,
ranges
+=
rone
)
{
offset
=
bus
->
map
(
addr
,
ranges
,
na
,
ns
,
pna
);
if
(
offset
!=
OF_BAD_ADDR
)
break
;
}
if
(
offset
==
OF_BAD_ADDR
)
{
pr_debug
(
"FDT: not found !
\n
"
);
return
1
;
}
memcpy
(
addr
,
ranges
+
na
,
4
*
pna
);
finish:
of_dump_addr
(
"FDT: parent translation for:"
,
addr
,
pna
);
pr_debug
(
"FDT: with offset: %llx
\n
"
,
offset
);
/* Translate it into parent bus space */
return
pbus
->
translate
(
addr
,
offset
,
pna
);
}
/*
* Translate an address from the device-tree into a CPU physical address,
* this walks up the tree and applies the various bus mappings on the
* way.
*
* Note: We consider that crossing any level with #size-cells == 0 to mean
* that translation is impossible (that is we are not dealing with a value
* that can be mapped to a cpu physical address). This is not really specified
* that way, but this is traditionally the way IBM at least do things
*/
u64
__init
fdt_translate_address
(
const
void
*
blob
,
int
node_offset
)
{
int
parent
,
len
;
const
struct
of_bus
*
bus
,
*
pbus
;
const
__be32
*
reg
;
__be32
addr
[
OF_MAX_ADDR_CELLS
];
int
na
,
ns
,
pna
,
pns
;
u64
result
=
OF_BAD_ADDR
;
pr_debug
(
"FDT: ** translation for device %s **
\n
"
,
fdt_get_name
(
blob
,
node_offset
,
NULL
));
reg
=
fdt_getprop
(
blob
,
node_offset
,
"reg"
,
&
len
);
if
(
!
reg
)
{
pr_err
(
"FDT: warning: device tree node '%s' has no address.
\n
"
,
fdt_get_name
(
blob
,
node_offset
,
NULL
));
goto
bail
;
}
/* Get parent & match bus type */
parent
=
fdt_parent_offset
(
blob
,
node_offset
);
if
(
parent
<
0
)
goto
bail
;
bus
=
&
of_busses
[
0
];
/* Cound address cells & copy address locally */
bus
->
count_cells
(
blob
,
parent
,
&
na
,
&
ns
);
if
(
!
OF_CHECK_COUNTS
(
na
,
ns
))
{
pr_err
(
"FDT: Bad cell count for %s
\n
"
,
fdt_get_name
(
blob
,
node_offset
,
NULL
));
goto
bail
;
}
memcpy
(
addr
,
reg
,
na
*
4
);
pr_debug
(
"FDT: bus (na=%d, ns=%d) on %s
\n
"
,
na
,
ns
,
fdt_get_name
(
blob
,
parent
,
NULL
));
of_dump_addr
(
"OF: translating address:"
,
addr
,
na
);
/* Translate */
for
(;;)
{
/* Switch to parent bus */
node_offset
=
parent
;
parent
=
fdt_parent_offset
(
blob
,
node_offset
);
/* If root, we have finished */
if
(
parent
<
0
)
{
pr_debug
(
"FDT: reached root node
\n
"
);
result
=
of_read_number
(
addr
,
na
);
break
;
}
/* Get new parent bus and counts */
pbus
=
&
of_busses
[
0
];
pbus
->
count_cells
(
blob
,
parent
,
&
pna
,
&
pns
);
if
(
!
OF_CHECK_COUNTS
(
pna
,
pns
))
{
pr_err
(
"FDT: Bad cell count for %s
\n
"
,
fdt_get_name
(
blob
,
node_offset
,
NULL
));
break
;
}
pr_debug
(
"FDT: parent bus (na=%d, ns=%d) on %s
\n
"
,
pna
,
pns
,
fdt_get_name
(
blob
,
parent
,
NULL
));
/* Apply bus translation */
if
(
fdt_translate_one
(
blob
,
node_offset
,
bus
,
pbus
,
addr
,
na
,
ns
,
pna
,
"ranges"
))
break
;
/* Complete the move up one level */
na
=
pna
;
ns
=
pns
;
bus
=
pbus
;
of_dump_addr
(
"FDT: one level translation:"
,
addr
,
na
);
}
bail:
return
result
;
}
drivers/of/of_reserved_mem.c
View file @
728dd198
...
@@ -188,7 +188,7 @@ static int __init __reserved_mem_init_node(struct reserved_mem *rmem)
...
@@ -188,7 +188,7 @@ static int __init __reserved_mem_init_node(struct reserved_mem *rmem)
if
(
!
of_flat_dt_is_compatible
(
rmem
->
fdt_node
,
compat
))
if
(
!
of_flat_dt_is_compatible
(
rmem
->
fdt_node
,
compat
))
continue
;
continue
;
if
(
initfn
(
rmem
,
rmem
->
fdt_node
,
rmem
->
name
)
==
0
)
{
if
(
initfn
(
rmem
)
==
0
)
{
pr_info
(
"Reserved memory: initialized node %s, compatible id %s
\n
"
,
pr_info
(
"Reserved memory: initialized node %s, compatible id %s
\n
"
,
rmem
->
name
,
compat
);
rmem
->
name
,
compat
);
return
0
;
return
0
;
...
...
drivers/tty/serial/8250/8250_core.c
View file @
728dd198
...
@@ -1926,13 +1926,8 @@ static void serial8250_put_poll_char(struct uart_port *port,
...
@@ -1926,13 +1926,8 @@ static void serial8250_put_poll_char(struct uart_port *port,
wait_for_xmitr
(
up
,
BOTH_EMPTY
);
wait_for_xmitr
(
up
,
BOTH_EMPTY
);
/*
/*
* Send the character out.
* Send the character out.
* If a LF, also do CR...
*/
*/
serial_port_out
(
port
,
UART_TX
,
c
);
serial_port_out
(
port
,
UART_TX
,
c
);
if
(
c
==
10
)
{
wait_for_xmitr
(
up
,
BOTH_EMPTY
);
serial_port_out
(
port
,
UART_TX
,
13
);
}
/*
/*
* Finally, wait for transmitter to become empty
* Finally, wait for transmitter to become empty
...
...
drivers/tty/serial/8250/8250_dw.c
View file @
728dd198
...
@@ -62,6 +62,70 @@ struct dw8250_data {
...
@@ -62,6 +62,70 @@ struct dw8250_data {
struct
uart_8250_dma
dma
;
struct
uart_8250_dma
dma
;
};
};
struct
dw8250_acpi_desc
{
void
(
*
set_termios
)(
struct
uart_port
*
p
,
struct
ktermios
*
termios
,
struct
ktermios
*
old
);
};
#define BYT_PRV_CLK 0x800
#define BYT_PRV_CLK_EN (1 << 0)
#define BYT_PRV_CLK_M_VAL_SHIFT 1
#define BYT_PRV_CLK_N_VAL_SHIFT 16
#define BYT_PRV_CLK_UPDATE (1 << 31)
static
void
byt_set_termios
(
struct
uart_port
*
p
,
struct
ktermios
*
termios
,
struct
ktermios
*
old
)
{
unsigned
int
baud
=
tty_termios_baud_rate
(
termios
);
unsigned
int
m
,
n
;
u32
reg
;
/*
* For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
* dividers must be adjusted.
*
* uartclk = (m / n) * 100 MHz, where m <= n
*/
switch
(
baud
)
{
case
500000
:
case
1000000
:
case
2000000
:
case
4000000
:
m
=
64
;
n
=
100
;
p
->
uartclk
=
64000000
;
break
;
case
3500000
:
m
=
56
;
n
=
100
;
p
->
uartclk
=
56000000
;
break
;
case
1500000
:
case
3000000
:
m
=
48
;
n
=
100
;
p
->
uartclk
=
48000000
;
break
;
case
2500000
:
m
=
40
;
n
=
100
;
p
->
uartclk
=
40000000
;
break
;
default:
m
=
2304
;
n
=
3125
;
p
->
uartclk
=
73728000
;
}
/* Reset the clock */
reg
=
(
m
<<
BYT_PRV_CLK_M_VAL_SHIFT
)
|
(
n
<<
BYT_PRV_CLK_N_VAL_SHIFT
);
writel
(
reg
,
p
->
membase
+
BYT_PRV_CLK
);
reg
|=
BYT_PRV_CLK_EN
|
BYT_PRV_CLK_UPDATE
;
writel
(
reg
,
p
->
membase
+
BYT_PRV_CLK
);
serial8250_do_set_termios
(
p
,
termios
,
old
);
}
static
inline
int
dw8250_modify_msr
(
struct
uart_port
*
p
,
int
offset
,
int
value
)
static
inline
int
dw8250_modify_msr
(
struct
uart_port
*
p
,
int
offset
,
int
value
)
{
{
struct
dw8250_data
*
d
=
p
->
private_data
;
struct
dw8250_data
*
d
=
p
->
private_data
;
...
@@ -278,6 +342,7 @@ static int dw8250_probe_acpi(struct uart_8250_port *up,
...
@@ -278,6 +342,7 @@ static int dw8250_probe_acpi(struct uart_8250_port *up,
{
{
const
struct
acpi_device_id
*
id
;
const
struct
acpi_device_id
*
id
;
struct
uart_port
*
p
=
&
up
->
port
;
struct
uart_port
*
p
=
&
up
->
port
;
struct
dw8250_acpi_desc
*
acpi_desc
;
dw8250_setup_port
(
up
);
dw8250_setup_port
(
up
);
...
@@ -290,14 +355,18 @@ static int dw8250_probe_acpi(struct uart_8250_port *up,
...
@@ -290,14 +355,18 @@ static int dw8250_probe_acpi(struct uart_8250_port *up,
p
->
serial_out
=
dw8250_serial_out32
;
p
->
serial_out
=
dw8250_serial_out32
;
p
->
regshift
=
2
;
p
->
regshift
=
2
;
if
(
!
p
->
uartclk
)
p
->
uartclk
=
(
unsigned
int
)
id
->
driver_data
;
up
->
dma
=
&
data
->
dma
;
up
->
dma
=
&
data
->
dma
;
up
->
dma
->
rxconf
.
src_maxburst
=
p
->
fifosize
/
4
;
up
->
dma
->
rxconf
.
src_maxburst
=
p
->
fifosize
/
4
;
up
->
dma
->
txconf
.
dst_maxburst
=
p
->
fifosize
/
4
;
up
->
dma
->
txconf
.
dst_maxburst
=
p
->
fifosize
/
4
;
acpi_desc
=
(
struct
dw8250_acpi_desc
*
)
id
->
driver_data
;
if
(
!
acpi_desc
)
return
0
;
if
(
acpi_desc
->
set_termios
)
p
->
set_termios
=
acpi_desc
->
set_termios
;
return
0
;
return
0
;
}
}
...
@@ -445,12 +514,16 @@ static const struct of_device_id dw8250_of_match[] = {
...
@@ -445,12 +514,16 @@ static const struct of_device_id dw8250_of_match[] = {
};
};
MODULE_DEVICE_TABLE
(
of
,
dw8250_of_match
);
MODULE_DEVICE_TABLE
(
of
,
dw8250_of_match
);
static
struct
dw8250_acpi_desc
byt_8250_desc
=
{
.
set_termios
=
byt_set_termios
,
};
static
const
struct
acpi_device_id
dw8250_acpi_match
[]
=
{
static
const
struct
acpi_device_id
dw8250_acpi_match
[]
=
{
{
"INT33C4"
,
0
},
{
"INT33C4"
,
0
},
{
"INT33C5"
,
0
},
{
"INT33C5"
,
0
},
{
"INT3434"
,
0
},
{
"INT3434"
,
0
},
{
"INT3435"
,
0
},
{
"INT3435"
,
0
},
{
"80860F0A"
,
0
},
{
"80860F0A"
,
(
kernel_ulong_t
)
&
byt_8250_desc
},
{
},
{
},
};
};
MODULE_DEVICE_TABLE
(
acpi
,
dw8250_acpi_match
);
MODULE_DEVICE_TABLE
(
acpi
,
dw8250_acpi_match
);
...
...
drivers/tty/serial/8250/8250_early.c
View file @
728dd198
...
@@ -35,18 +35,8 @@
...
@@ -35,18 +35,8 @@
#include <linux/serial_8250.h>
#include <linux/serial_8250.h>
#include <asm/io.h>
#include <asm/io.h>
#include <asm/serial.h>
#include <asm/serial.h>
#ifdef CONFIG_FIX_EARLYCON_MEM
#include <asm/pgtable.h>
#include <asm/fixmap.h>
#endif
struct
early_serial8250_device
{
static
struct
earlycon_device
*
early_device
;
struct
uart_port
port
;
char
options
[
16
];
/* e.g., 115200n8 */
unsigned
int
baud
;
};
static
struct
early_serial8250_device
early_device
;
unsigned
int
__weak
__init
serial8250_early_in
(
struct
uart_port
*
port
,
int
offset
)
unsigned
int
__weak
__init
serial8250_early_in
(
struct
uart_port
*
port
,
int
offset
)
{
{
...
@@ -100,7 +90,7 @@ static void __init serial_putc(struct uart_port *port, int c)
...
@@ -100,7 +90,7 @@ static void __init serial_putc(struct uart_port *port, int c)
static
void
__init
early_serial8250_write
(
struct
console
*
console
,
static
void
__init
early_serial8250_write
(
struct
console
*
console
,
const
char
*
s
,
unsigned
int
count
)
const
char
*
s
,
unsigned
int
count
)
{
{
struct
uart_port
*
port
=
&
early_device
.
port
;
struct
uart_port
*
port
=
&
early_device
->
port
;
unsigned
int
ier
;
unsigned
int
ier
;
/* Save the IER and disable interrupts */
/* Save the IER and disable interrupts */
...
@@ -129,7 +119,7 @@ static unsigned int __init probe_baud(struct uart_port *port)
...
@@ -129,7 +119,7 @@ static unsigned int __init probe_baud(struct uart_port *port)
return
(
port
->
uartclk
/
16
)
/
quot
;
return
(
port
->
uartclk
/
16
)
/
quot
;
}
}
static
void
__init
init_port
(
struct
early
_serial8250
_device
*
device
)
static
void
__init
init_port
(
struct
early
con
_device
*
device
)
{
{
struct
uart_port
*
port
=
&
device
->
port
;
struct
uart_port
*
port
=
&
device
->
port
;
unsigned
int
divisor
;
unsigned
int
divisor
;
...
@@ -148,128 +138,42 @@ static void __init init_port(struct early_serial8250_device *device)
...
@@ -148,128 +138,42 @@ static void __init init_port(struct early_serial8250_device *device)
serial8250_early_out
(
port
,
UART_LCR
,
c
&
~
UART_LCR_DLAB
);
serial8250_early_out
(
port
,
UART_LCR
,
c
&
~
UART_LCR_DLAB
);
}
}
static
int
__init
parse_options
(
struct
early_serial8250
_device
*
device
,
static
int
__init
early_serial8250_setup
(
struct
earlycon
_device
*
device
,
char
*
options
)
const
char
*
options
)
{
{
struct
uart_port
*
port
=
&
device
->
port
;
if
(
!
(
device
->
port
.
membase
||
device
->
port
.
iobase
))
int
mmio
,
mmio32
,
length
;
if
(
!
options
)
return
-
ENODEV
;
port
->
uartclk
=
BASE_BAUD
*
16
;
mmio
=
!
strncmp
(
options
,
"mmio,"
,
5
);
mmio32
=
!
strncmp
(
options
,
"mmio32,"
,
7
);
if
(
mmio
||
mmio32
)
{
port
->
iotype
=
(
mmio
?
UPIO_MEM
:
UPIO_MEM32
);
port
->
mapbase
=
simple_strtoul
(
options
+
(
mmio
?
5
:
7
),
&
options
,
0
);
if
(
mmio32
)
port
->
regshift
=
2
;
#ifdef CONFIG_FIX_EARLYCON_MEM
set_fixmap_nocache
(
FIX_EARLYCON_MEM_BASE
,
port
->
mapbase
&
PAGE_MASK
);
port
->
membase
=
(
void
__iomem
*
)
__fix_to_virt
(
FIX_EARLYCON_MEM_BASE
);
port
->
membase
+=
port
->
mapbase
&
~
PAGE_MASK
;
#else
port
->
membase
=
ioremap_nocache
(
port
->
mapbase
,
64
);
if
(
!
port
->
membase
)
{
printk
(
KERN_ERR
"%s: Couldn't ioremap 0x%llx
\n
"
,
__func__
,
(
unsigned
long
long
)
port
->
mapbase
);
return
-
ENOMEM
;
}
#endif
}
else
if
(
!
strncmp
(
options
,
"io,"
,
3
))
{
port
->
iotype
=
UPIO_PORT
;
port
->
iobase
=
simple_strtoul
(
options
+
3
,
&
options
,
0
);
mmio
=
0
;
}
else
return
-
EINVAL
;
options
=
strchr
(
options
,
','
);
if
(
options
)
{
options
++
;
device
->
baud
=
simple_strtoul
(
options
,
NULL
,
0
);
length
=
min
(
strcspn
(
options
,
" "
)
+
1
,
(
size_t
)(
sizeof
(
device
->
options
)));
strlcpy
(
device
->
options
,
options
,
length
);
}
else
{
device
->
baud
=
probe_baud
(
port
);
snprintf
(
device
->
options
,
sizeof
(
device
->
options
),
"%u"
,
device
->
baud
);
}
if
(
mmio
||
mmio32
)
printk
(
KERN_INFO
"Early serial console at MMIO%s 0x%llx (options '%s')
\n
"
,
mmio32
?
"32"
:
""
,
(
unsigned
long
long
)
port
->
mapbase
,
device
->
options
);
else
printk
(
KERN_INFO
"Early serial console at I/O port 0x%lx (options '%s')
\n
"
,
port
->
iobase
,
device
->
options
);
return
0
;
return
0
;
}
static
struct
console
early_serial8250_console
__initdata
=
{
if
(
!
device
->
baud
)
.
name
=
"uart"
,
device
->
baud
=
probe_baud
(
&
device
->
port
);
.
write
=
early_serial8250_write
,
.
flags
=
CON_PRINTBUFFER
|
CON_BOOT
,
.
index
=
-
1
,
};
static
int
__init
early_serial8250_setup
(
char
*
options
)
{
struct
early_serial8250_device
*
device
=
&
early_device
;
int
err
;
if
(
device
->
port
.
membase
||
device
->
port
.
iobase
)
return
0
;
err
=
parse_options
(
device
,
options
);
if
(
err
<
0
)
return
err
;
init_port
(
device
);
init_port
(
device
);
early_device
=
device
;
device
->
con
->
write
=
early_serial8250_write
;
return
0
;
return
0
;
}
}
EARLYCON_DECLARE
(
uart8250
,
early_serial8250_setup
);
EARLYCON_DECLARE
(
uart
,
early_serial8250_setup
);
int
__init
setup_early_serial8250_console
(
char
*
cmdline
)
int
__init
setup_early_serial8250_console
(
char
*
cmdline
)
{
{
char
*
options
;
char
match
[]
=
"uart8250"
;
int
err
;
options
=
strstr
(
cmdline
,
"uart8250,"
);
if
(
!
options
)
{
options
=
strstr
(
cmdline
,
"uart,"
);
if
(
!
options
)
return
0
;
}
options
=
strchr
(
cmdline
,
','
)
+
1
;
err
=
early_serial8250_setup
(
options
);
if
(
err
<
0
)
return
err
;
register_console
(
&
early_serial8250_console
);
if
(
cmdline
&&
cmdline
[
4
]
==
','
)
match
[
4
]
=
'\0'
;
return
0
;
return
setup_earlycon
(
cmdline
,
match
,
early_serial8250_setup
)
;
}
}
int
serial8250_find_port_for_earlycon
(
void
)
int
serial8250_find_port_for_earlycon
(
void
)
{
{
struct
early
_serial8250_device
*
device
=
&
early_device
;
struct
early
con_device
*
device
=
early_device
;
struct
uart_port
*
port
=
&
device
->
port
;
struct
uart_port
*
port
=
device
?
&
device
->
port
:
NULL
;
int
line
;
int
line
;
int
ret
;
int
ret
;
if
(
!
device
->
port
.
membase
&&
!
device
->
port
.
iobase
)
if
(
!
port
||
(
!
port
->
membase
&&
!
port
->
iobase
)
)
return
-
ENODEV
;
return
-
ENODEV
;
line
=
serial8250_find_port
(
port
);
line
=
serial8250_find_port
(
port
);
...
@@ -284,5 +188,3 @@ int serial8250_find_port_for_earlycon(void)
...
@@ -284,5 +188,3 @@ int serial8250_find_port_for_earlycon(void)
return
ret
;
return
ret
;
}
}
early_param
(
"earlycon"
,
setup_early_serial8250_console
);
drivers/tty/serial/8250/Kconfig
View file @
728dd198
...
@@ -61,6 +61,7 @@ config SERIAL_8250_CONSOLE
...
@@ -61,6 +61,7 @@ config SERIAL_8250_CONSOLE
bool "Console on 8250/16550 and compatible serial port"
bool "Console on 8250/16550 and compatible serial port"
depends on SERIAL_8250=y
depends on SERIAL_8250=y
select SERIAL_CORE_CONSOLE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
---help---
---help---
If you say Y here, it will be possible to use a serial port as the
If you say Y here, it will be possible to use a serial port as the
system console (the system console is the device which receives all
system console (the system console is the device which receives all
...
@@ -90,11 +91,6 @@ config SERIAL_8250_CONSOLE
...
@@ -90,11 +91,6 @@ config SERIAL_8250_CONSOLE
If unsure, say N.
If unsure, say N.
config FIX_EARLYCON_MEM
bool
depends on X86
default y
config SERIAL_8250_GSC
config SERIAL_8250_GSC
tristate
tristate
depends on SERIAL_8250 && GSC
depends on SERIAL_8250 && GSC
...
...
drivers/tty/serial/Kconfig
View file @
728dd198
...
@@ -7,6 +7,13 @@ if TTY
...
@@ -7,6 +7,13 @@ if TTY
menu "Serial drivers"
menu "Serial drivers"
depends on HAS_IOMEM
depends on HAS_IOMEM
config SERIAL_EARLYCON
bool
help
Support for early consoles with the earlycon parameter. This enables
the console before standard serial driver is probed. The console is
enabled when early_param is processed.
source "drivers/tty/serial/8250/Kconfig"
source "drivers/tty/serial/8250/Kconfig"
comment "Non-8250 serial port support"
comment "Non-8250 serial port support"
...
@@ -53,6 +60,7 @@ config SERIAL_AMBA_PL011_CONSOLE
...
@@ -53,6 +60,7 @@ config SERIAL_AMBA_PL011_CONSOLE
bool "Support for console on AMBA serial port"
bool "Support for console on AMBA serial port"
depends on SERIAL_AMBA_PL011=y
depends on SERIAL_AMBA_PL011=y
select SERIAL_CORE_CONSOLE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
---help---
---help---
Say Y here if you wish to use an AMBA PrimeCell UART as the system
Say Y here if you wish to use an AMBA PrimeCell UART as the system
console (the system console is the device which receives all kernel
console (the system console is the device which receives all kernel
...
@@ -65,6 +73,16 @@ config SERIAL_AMBA_PL011_CONSOLE
...
@@ -65,6 +73,16 @@ config SERIAL_AMBA_PL011_CONSOLE
your boot loader (lilo or loadlin) about how to pass options to the
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
kernel at boot time.)
config SERIAL_EARLYCON_ARM_SEMIHOST
bool "Early console using ARM semihosting"
depends on ARM64 || ARM
select SERIAL_EARLYCON
help
Support for early debug console using ARM semihosting. This enables
the console before standard serial driver is probed. This is enabled
with "earlycon=smh" on the kernel command line. The console is
enabled when early_param is processed.
config SERIAL_SB1250_DUART
config SERIAL_SB1250_DUART
tristate "BCM1xxx on-chip DUART serial support"
tristate "BCM1xxx on-chip DUART serial support"
depends on SIBYTE_SB1xxx_SOC=y
depends on SIBYTE_SB1xxx_SOC=y
...
@@ -1160,6 +1178,16 @@ config SERIAL_SCCNXP_CONSOLE
...
@@ -1160,6 +1178,16 @@ config SERIAL_SCCNXP_CONSOLE
help
help
Support for console on SCCNXP serial ports.
Support for console on SCCNXP serial ports.
config SERIAL_SC16IS7XX
tristate "SC16IS7xx serial support"
depends on I2C
select SERIAL_CORE
select REGMAP_I2C if I2C
help
This selects support for SC16IS7xx serial ports.
Supported ICs are SC16IS740, SC16IS741, SC16IS750, SC16IS752,
SC16IS760 and SC16IS762.
config SERIAL_BFIN_SPORT
config SERIAL_BFIN_SPORT
tristate "Blackfin SPORT emulate UART"
tristate "Blackfin SPORT emulate UART"
depends on BLACKFIN
depends on BLACKFIN
...
@@ -1369,18 +1397,19 @@ config SERIAL_MXS_AUART_CONSOLE
...
@@ -1369,18 +1397,19 @@ config SERIAL_MXS_AUART_CONSOLE
Enable a MXS AUART port to be the system console.
Enable a MXS AUART port to be the system console.
config SERIAL_XILINX_PS_UART
config SERIAL_XILINX_PS_UART
tristate "
Xilinx PS
UART support"
tristate "
Cadence (Xilinx Zynq)
UART support"
depends on OF
depends on OF
select SERIAL_CORE
select SERIAL_CORE
help
help
This driver supports the Xilinx PS UART port.
This driver supports the Cadence UART. It is found e.g. in Xilinx
Zynq.
config SERIAL_XILINX_PS_UART_CONSOLE
config SERIAL_XILINX_PS_UART_CONSOLE
bool "
Xilinx PS
UART console support"
bool "
Cadence
UART console support"
depends on SERIAL_XILINX_PS_UART=y
depends on SERIAL_XILINX_PS_UART=y
select SERIAL_CORE_CONSOLE
select SERIAL_CORE_CONSOLE
help
help
Enable a
Xilinx PS
UART port to be the system console.
Enable a
Cadence
UART port to be the system console.
config SERIAL_AR933X
config SERIAL_AR933X
tristate "AR933X serial port support"
tristate "AR933X serial port support"
...
@@ -1508,6 +1537,16 @@ config SERIAL_ST_ASC_CONSOLE
...
@@ -1508,6 +1537,16 @@ config SERIAL_ST_ASC_CONSOLE
depends on SERIAL_ST_ASC=y
depends on SERIAL_ST_ASC=y
select SERIAL_CORE_CONSOLE
select SERIAL_CORE_CONSOLE
config SERIAL_MEN_Z135
tristate "MEN 16z135 Support"
depends on MCB
help
Say yes here to enable support for the MEN 16z135 High Speed UART IP-Core
on a MCB carrier.
This driver can also be build as a module. If so, the module will be called
men_z135_uart.ko
endmenu
endmenu
endif # TTY
endif # TTY
drivers/tty/serial/Makefile
View file @
728dd198
...
@@ -5,6 +5,9 @@
...
@@ -5,6 +5,9 @@
obj-$(CONFIG_SERIAL_CORE)
+=
serial_core.o
obj-$(CONFIG_SERIAL_CORE)
+=
serial_core.o
obj-$(CONFIG_SERIAL_21285)
+=
21285.o
obj-$(CONFIG_SERIAL_21285)
+=
21285.o
obj-$(CONFIG_SERIAL_EARLYCON)
+=
earlycon.o
obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST)
+=
earlycon-arm-semihost.o
# These Sparc drivers have to appear before others such as 8250
# These Sparc drivers have to appear before others such as 8250
# which share ttySx minor node space. Otherwise console device
# which share ttySx minor node space. Otherwise console device
# names change and other unplesantries.
# names change and other unplesantries.
...
@@ -48,6 +51,7 @@ obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
...
@@ -48,6 +51,7 @@ obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
obj-$(CONFIG_SERIAL_SB1250_DUART)
+=
sb1250-duart.o
obj-$(CONFIG_SERIAL_SB1250_DUART)
+=
sb1250-duart.o
obj-$(CONFIG_ETRAX_SERIAL)
+=
crisv10.o
obj-$(CONFIG_ETRAX_SERIAL)
+=
crisv10.o
obj-$(CONFIG_SERIAL_SCCNXP)
+=
sccnxp.o
obj-$(CONFIG_SERIAL_SCCNXP)
+=
sccnxp.o
obj-$(CONFIG_SERIAL_SC16IS7XX)
+=
sc16is7xx.o
obj-$(CONFIG_SERIAL_JSM)
+=
jsm/
obj-$(CONFIG_SERIAL_JSM)
+=
jsm/
obj-$(CONFIG_SERIAL_TXX9)
+=
serial_txx9.o
obj-$(CONFIG_SERIAL_TXX9)
+=
serial_txx9.o
obj-$(CONFIG_SERIAL_VR41XX)
+=
vr41xx_siu.o
obj-$(CONFIG_SERIAL_VR41XX)
+=
vr41xx_siu.o
...
@@ -87,3 +91,4 @@ obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
...
@@ -87,3 +91,4 @@ obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
obj-$(CONFIG_SERIAL_ARC)
+=
arc_uart.o
obj-$(CONFIG_SERIAL_ARC)
+=
arc_uart.o
obj-$(CONFIG_SERIAL_RP2)
+=
rp2.o
obj-$(CONFIG_SERIAL_RP2)
+=
rp2.o
obj-$(CONFIG_SERIAL_FSL_LPUART)
+=
fsl_lpuart.o
obj-$(CONFIG_SERIAL_FSL_LPUART)
+=
fsl_lpuart.o
obj-$(CONFIG_SERIAL_MEN_Z135)
+=
men_z135_uart.o
drivers/tty/serial/amba-pl011.c
View file @
728dd198
...
@@ -2045,6 +2045,35 @@ static struct console amba_console = {
...
@@ -2045,6 +2045,35 @@ static struct console amba_console = {
};
};
#define AMBA_CONSOLE (&amba_console)
#define AMBA_CONSOLE (&amba_console)
static
void
pl011_putc
(
struct
uart_port
*
port
,
int
c
)
{
while
(
readl
(
port
->
membase
+
UART01x_FR
)
&
UART01x_FR_TXFF
)
;
writeb
(
c
,
port
->
membase
+
UART01x_DR
);
while
(
readl
(
port
->
membase
+
UART01x_FR
)
&
UART01x_FR_BUSY
)
;
}
static
void
pl011_early_write
(
struct
console
*
con
,
const
char
*
s
,
unsigned
n
)
{
struct
earlycon_device
*
dev
=
con
->
data
;
uart_console_write
(
&
dev
->
port
,
s
,
n
,
pl011_putc
);
}
static
int
__init
pl011_early_console_setup
(
struct
earlycon_device
*
device
,
const
char
*
opt
)
{
if
(
!
device
->
port
.
membase
)
return
-
ENODEV
;
device
->
con
->
write
=
pl011_early_write
;
return
0
;
}
EARLYCON_DECLARE
(
pl011
,
pl011_early_console_setup
);
OF_EARLYCON_DECLARE
(
pl011
,
"arm,pl011"
,
pl011_early_console_setup
);
#else
#else
#define AMBA_CONSOLE NULL
#define AMBA_CONSOLE NULL
#endif
#endif
...
...
drivers/tty/serial/earlycon-arm-semihost.c
0 → 100644
View file @
728dd198
/*
* Copyright (C) 2012 ARM Ltd.
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* Adapted for ARM and earlycon:
* Copyright (C) 2014 Linaro Ltd.
* Author: Rob Herring <robh@kernel.org>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/kernel.h>
#include <linux/console.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#ifdef CONFIG_THUMB2_KERNEL
#define SEMIHOST_SWI "0xab"
#else
#define SEMIHOST_SWI "0x123456"
#endif
/*
* Semihosting-based debug console
*/
static
void
smh_putc
(
struct
uart_port
*
port
,
int
c
)
{
#ifdef CONFIG_ARM64
asm
volatile
(
"mov x1, %0
\n
"
"mov x0, #3
\n
"
"hlt 0xf000
\n
"
:
:
"r"
(
&
c
)
:
"x0"
,
"x1"
,
"memory"
);
#else
asm
volatile
(
"mov r1, %0
\n
"
"mov r0, #3
\n
"
"svc "
SEMIHOST_SWI
"
\n
"
:
:
"r"
(
&
c
)
:
"r0"
,
"r1"
,
"memory"
);
#endif
}
static
void
smh_write
(
struct
console
*
con
,
const
char
*
s
,
unsigned
n
)
{
struct
earlycon_device
*
dev
=
con
->
data
;
uart_console_write
(
&
dev
->
port
,
s
,
n
,
smh_putc
);
}
int
__init
early_smh_setup
(
struct
earlycon_device
*
device
,
const
char
*
opt
)
{
device
->
con
->
write
=
smh_write
;
return
0
;
}
EARLYCON_DECLARE
(
smh
,
early_smh_setup
);
drivers/tty/serial/earlycon.c
0 → 100644
View file @
728dd198
/*
* Copyright (C) 2014 Linaro Ltd.
* Author: Rob Herring <robh@kernel.org>
*
* Based on 8250 earlycon:
* (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
* Bjorn Helgaas <bjorn.helgaas@hp.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/console.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/serial_core.h>
#include <linux/sizes.h>
#include <linux/mod_devicetable.h>
#ifdef CONFIG_FIX_EARLYCON_MEM
#include <asm/fixmap.h>
#endif
#include <asm/serial.h>
static
struct
console
early_con
=
{
.
name
=
"earlycon"
,
.
flags
=
CON_PRINTBUFFER
|
CON_BOOT
,
.
index
=
-
1
,
};
static
struct
earlycon_device
early_console_dev
=
{
.
con
=
&
early_con
,
};
static
const
struct
of_device_id
__earlycon_of_table_sentinel
__used
__section
(
__earlycon_of_table_end
);
static
void
__iomem
*
__init
earlycon_map
(
unsigned
long
paddr
,
size_t
size
)
{
void
__iomem
*
base
;
#ifdef CONFIG_FIX_EARLYCON_MEM
set_fixmap_io
(
FIX_EARLYCON_MEM_BASE
,
paddr
&
PAGE_MASK
);
base
=
(
void
__iomem
*
)
__fix_to_virt
(
FIX_EARLYCON_MEM_BASE
);
base
+=
paddr
&
~
PAGE_MASK
;
#else
base
=
ioremap
(
paddr
,
size
);
#endif
if
(
!
base
)
pr_err
(
"%s: Couldn't map 0x%llx
\n
"
,
__func__
,
(
unsigned
long
long
)
paddr
);
return
base
;
}
static
int
__init
parse_options
(
struct
earlycon_device
*
device
,
char
*
options
)
{
struct
uart_port
*
port
=
&
device
->
port
;
int
mmio
,
mmio32
,
length
;
unsigned
long
addr
;
if
(
!
options
)
return
-
ENODEV
;
mmio
=
!
strncmp
(
options
,
"mmio,"
,
5
);
mmio32
=
!
strncmp
(
options
,
"mmio32,"
,
7
);
if
(
mmio
||
mmio32
)
{
port
->
iotype
=
(
mmio
?
UPIO_MEM
:
UPIO_MEM32
);
options
+=
mmio
?
5
:
7
;
addr
=
simple_strtoul
(
options
,
NULL
,
0
);
port
->
mapbase
=
addr
;
if
(
mmio32
)
port
->
regshift
=
2
;
}
else
if
(
!
strncmp
(
options
,
"io,"
,
3
))
{
port
->
iotype
=
UPIO_PORT
;
options
+=
3
;
addr
=
simple_strtoul
(
options
,
NULL
,
0
);
port
->
iobase
=
addr
;
mmio
=
0
;
}
else
if
(
!
strncmp
(
options
,
"0x"
,
2
))
{
port
->
iotype
=
UPIO_MEM
;
addr
=
simple_strtoul
(
options
,
NULL
,
0
);
port
->
mapbase
=
addr
;
}
else
{
return
-
EINVAL
;
}
port
->
uartclk
=
BASE_BAUD
*
16
;
options
=
strchr
(
options
,
','
);
if
(
options
)
{
options
++
;
device
->
baud
=
simple_strtoul
(
options
,
NULL
,
0
);
length
=
min
(
strcspn
(
options
,
" "
)
+
1
,
(
size_t
)(
sizeof
(
device
->
options
)));
strlcpy
(
device
->
options
,
options
,
length
);
}
if
(
mmio
||
mmio32
)
pr_info
(
"Early serial console at MMIO%s 0x%llx (options '%s')
\n
"
,
mmio32
?
"32"
:
""
,
(
unsigned
long
long
)
port
->
mapbase
,
device
->
options
);
else
pr_info
(
"Early serial console at I/O port 0x%lx (options '%s')
\n
"
,
port
->
iobase
,
device
->
options
);
return
0
;
}
int
__init
setup_earlycon
(
char
*
buf
,
const
char
*
match
,
int
(
*
setup
)(
struct
earlycon_device
*
,
const
char
*
))
{
int
err
;
size_t
len
;
struct
uart_port
*
port
=
&
early_console_dev
.
port
;
if
(
!
buf
||
!
match
||
!
setup
)
return
0
;
len
=
strlen
(
match
);
if
(
strncmp
(
buf
,
match
,
len
))
return
0
;
if
(
buf
[
len
]
&&
(
buf
[
len
]
!=
','
))
return
0
;
buf
+=
len
+
1
;
err
=
parse_options
(
&
early_console_dev
,
buf
);
/* On parsing error, pass the options buf to the setup function */
if
(
!
err
)
buf
=
NULL
;
if
(
port
->
mapbase
)
port
->
membase
=
earlycon_map
(
port
->
mapbase
,
64
);
early_console_dev
.
con
->
data
=
&
early_console_dev
;
err
=
setup
(
&
early_console_dev
,
buf
);
if
(
err
<
0
)
return
err
;
if
(
!
early_console_dev
.
con
->
write
)
return
-
ENODEV
;
register_console
(
early_console_dev
.
con
);
return
0
;
}
int
__init
of_setup_earlycon
(
unsigned
long
addr
,
int
(
*
setup
)(
struct
earlycon_device
*
,
const
char
*
))
{
int
err
;
struct
uart_port
*
port
=
&
early_console_dev
.
port
;
port
->
iotype
=
UPIO_MEM
;
port
->
mapbase
=
addr
;
port
->
uartclk
=
BASE_BAUD
*
16
;
port
->
membase
=
earlycon_map
(
addr
,
SZ_4K
);
early_console_dev
.
con
->
data
=
&
early_console_dev
;
err
=
setup
(
&
early_console_dev
,
NULL
);
if
(
err
<
0
)
return
err
;
if
(
!
early_console_dev
.
con
->
write
)
return
-
ENODEV
;
register_console
(
early_console_dev
.
con
);
return
0
;
}
drivers/tty/serial/men_z135_uart.c
0 → 100644
View file @
728dd198
/*
* MEN 16z135 High Speed UART
*
* Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de)
* Author: Johannes Thumshirn <johannes.thumshirn@men.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; version 2 of the License.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/serial_core.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/tty_flip.h>
#include <linux/bitops.h>
#include <linux/mcb.h>
#define MEN_Z135_MAX_PORTS 12
#define MEN_Z135_BASECLK 29491200
#define MEN_Z135_FIFO_SIZE 1024
#define MEN_Z135_NUM_MSI_VECTORS 2
#define MEN_Z135_FIFO_WATERMARK 1020
#define MEN_Z135_STAT_REG 0x0
#define MEN_Z135_RX_RAM 0x4
#define MEN_Z135_TX_RAM 0x400
#define MEN_Z135_RX_CTRL 0x800
#define MEN_Z135_TX_CTRL 0x804
#define MEN_Z135_CONF_REG 0x808
#define MEN_Z135_UART_FREQ 0x80c
#define MEN_Z135_BAUD_REG 0x810
#define MENZ135_TIMEOUT 0x814
#define MEN_Z135_MEM_SIZE 0x818
#define IS_IRQ(x) ((x) & 1)
#define IRQ_ID(x) (((x) >> 1) & 7)
#define MEN_Z135_IER_RXCIEN BIT(0)
/* TX Space IRQ */
#define MEN_Z135_IER_TXCIEN BIT(1)
/* RX Space IRQ */
#define MEN_Z135_IER_RLSIEN BIT(2)
/* Receiver Line Status IRQ */
#define MEN_Z135_IER_MSIEN BIT(3)
/* Modem Status IRQ */
#define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN \
| MEN_Z135_IER_RLSIEN \
| MEN_Z135_IER_MSIEN \
| MEN_Z135_IER_TXCIEN)
#define MEN_Z135_MCR_DTR BIT(24)
#define MEN_Z135_MCR_RTS BIT(25)
#define MEN_Z135_MCR_OUT1 BIT(26)
#define MEN_Z135_MCR_OUT2 BIT(27)
#define MEN_Z135_MCR_LOOP BIT(28)
#define MEN_Z135_MCR_RCFC BIT(29)
#define MEN_Z135_MSR_DCTS BIT(0)
#define MEN_Z135_MSR_DDSR BIT(1)
#define MEN_Z135_MSR_DRI BIT(2)
#define MEN_Z135_MSR_DDCD BIT(3)
#define MEN_Z135_MSR_CTS BIT(4)
#define MEN_Z135_MSR_DSR BIT(5)
#define MEN_Z135_MSR_RI BIT(6)
#define MEN_Z135_MSR_DCD BIT(7)
#define MEN_Z135_LCR_SHIFT 8
/* LCR shift mask */
#define MEN_Z135_WL5 0
/* CS5 */
#define MEN_Z135_WL6 1
/* CS6 */
#define MEN_Z135_WL7 2
/* CS7 */
#define MEN_Z135_WL8 3
/* CS8 */
#define MEN_Z135_STB_SHIFT 2
/* Stopbits */
#define MEN_Z135_NSTB1 0
#define MEN_Z135_NSTB2 1
#define MEN_Z135_PEN_SHIFT 3
/* Parity enable */
#define MEN_Z135_PAR_DIS 0
#define MEN_Z135_PAR_ENA 1
#define MEN_Z135_PTY_SHIFT 4
/* Parity type */
#define MEN_Z135_PTY_ODD 0
#define MEN_Z135_PTY_EVN 1
#define MEN_Z135_LSR_DR BIT(0)
#define MEN_Z135_LSR_OE BIT(1)
#define MEN_Z135_LSR_PE BIT(2)
#define MEN_Z135_LSR_FE BIT(3)
#define MEN_Z135_LSR_BI BIT(4)
#define MEN_Z135_LSR_THEP BIT(5)
#define MEN_Z135_LSR_TEXP BIT(6)
#define MEN_Z135_LSR_RXFIFOERR BIT(7)
#define MEN_Z135_IRQ_ID_MST 0
#define MEN_Z135_IRQ_ID_TSA 1
#define MEN_Z135_IRQ_ID_RDA 2
#define MEN_Z135_IRQ_ID_RLS 3
#define MEN_Z135_IRQ_ID_CTI 6
#define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff)
#define BYTES_TO_ALIGN(x) ((x) & 0x3)
static
int
line
;
static
int
txlvl
=
5
;
module_param
(
txlvl
,
int
,
S_IRUGO
);
MODULE_PARM_DESC
(
txlvl
,
"TX IRQ trigger level 0-7, default 5 (128 byte)"
);
static
int
rxlvl
=
6
;
module_param
(
rxlvl
,
int
,
S_IRUGO
);
MODULE_PARM_DESC
(
rxlvl
,
"RX IRQ trigger level 0-7, default 6 (256 byte)"
);
static
int
align
;
module_param
(
align
,
int
,
S_IRUGO
);
MODULE_PARM_DESC
(
align
,
"Keep hardware FIFO write pointer aligned, default 0"
);
struct
men_z135_port
{
struct
uart_port
port
;
struct
mcb_device
*
mdev
;
unsigned
char
*
rxbuf
;
u32
stat_reg
;
spinlock_t
lock
;
};
#define to_men_z135(port) container_of((port), struct men_z135_port, port)
/**
* men_z135_reg_set() - Set value in register
* @uart: The UART port
* @addr: Register address
* @val: value to set
*/
static
inline
void
men_z135_reg_set
(
struct
men_z135_port
*
uart
,
u32
addr
,
u32
val
)
{
struct
uart_port
*
port
=
&
uart
->
port
;
unsigned
long
flags
;
u32
reg
;
spin_lock_irqsave
(
&
uart
->
lock
,
flags
);
reg
=
ioread32
(
port
->
membase
+
addr
);
reg
|=
val
;
iowrite32
(
reg
,
port
->
membase
+
addr
);
spin_unlock_irqrestore
(
&
uart
->
lock
,
flags
);
}
/**
* men_z135_reg_clr() - Unset value in register
* @uart: The UART port
* @addr: Register address
* @val: value to clear
*/
static
inline
void
men_z135_reg_clr
(
struct
men_z135_port
*
uart
,
u32
addr
,
u32
val
)
{
struct
uart_port
*
port
=
&
uart
->
port
;
unsigned
long
flags
;
u32
reg
;
spin_lock_irqsave
(
&
uart
->
lock
,
flags
);
reg
=
ioread32
(
port
->
membase
+
addr
);
reg
&=
~
val
;
iowrite32
(
reg
,
port
->
membase
+
addr
);
spin_unlock_irqrestore
(
&
uart
->
lock
,
flags
);
}
/**
* men_z135_handle_modem_status() - Handle change of modem status
* @port: The UART port
*
* Handle change of modem status register. This is done by reading the "delta"
* versions of DCD (Data Carrier Detect) and CTS (Clear To Send).
*/
static
void
men_z135_handle_modem_status
(
struct
men_z135_port
*
uart
)
{
if
(
uart
->
stat_reg
&
MEN_Z135_MSR_DDCD
)
uart_handle_dcd_change
(
&
uart
->
port
,
uart
->
stat_reg
&
~
MEN_Z135_MSR_DCD
);
if
(
uart
->
stat_reg
&
MEN_Z135_MSR_DCTS
)
uart_handle_cts_change
(
&
uart
->
port
,
uart
->
stat_reg
&
~
MEN_Z135_MSR_CTS
);
}
static
void
men_z135_handle_lsr
(
struct
men_z135_port
*
uart
)
{
struct
uart_port
*
port
=
&
uart
->
port
;
u8
lsr
;
lsr
=
(
uart
->
stat_reg
>>
16
)
&
0xff
;
if
(
lsr
&
MEN_Z135_LSR_OE
)
port
->
icount
.
overrun
++
;
if
(
lsr
&
MEN_Z135_LSR_PE
)
port
->
icount
.
parity
++
;
if
(
lsr
&
MEN_Z135_LSR_FE
)
port
->
icount
.
frame
++
;
if
(
lsr
&
MEN_Z135_LSR_BI
)
{
port
->
icount
.
brk
++
;
uart_handle_break
(
port
);
}
}
/**
* get_rx_fifo_content() - Get the number of bytes in RX FIFO
* @uart: The UART port
*
* Read RXC register from hardware and return current FIFO fill size.
*/
static
u16
get_rx_fifo_content
(
struct
men_z135_port
*
uart
)
{
struct
uart_port
*
port
=
&
uart
->
port
;
u32
stat_reg
;
u16
rxc
;
u8
rxc_lo
;
u8
rxc_hi
;
stat_reg
=
ioread32
(
port
->
membase
+
MEN_Z135_STAT_REG
);
rxc_lo
=
stat_reg
>>
24
;
rxc_hi
=
(
stat_reg
&
0xC0
)
>>
6
;
rxc
=
rxc_lo
|
(
rxc_hi
<<
8
);
return
rxc
;
}
/**
* men_z135_handle_rx() - RX tasklet routine
* @arg: Pointer to struct men_z135_port
*
* Copy from RX FIFO and acknowledge number of bytes copied.
*/
static
void
men_z135_handle_rx
(
struct
men_z135_port
*
uart
)
{
struct
uart_port
*
port
=
&
uart
->
port
;
struct
tty_port
*
tport
=
&
port
->
state
->
port
;
int
copied
;
u16
size
;
int
room
;
size
=
get_rx_fifo_content
(
uart
);
if
(
size
==
0
)
return
;
/* Avoid accidently accessing TX FIFO instead of RX FIFO. Last
* longword in RX FIFO cannot be read.(0x004-0x3FF)
*/
if
(
size
>
MEN_Z135_FIFO_WATERMARK
)
size
=
MEN_Z135_FIFO_WATERMARK
;
room
=
tty_buffer_request_room
(
tport
,
size
);
if
(
room
!=
size
)
dev_warn
(
&
uart
->
mdev
->
dev
,
"Not enough room in flip buffer, truncating to %d
\n
"
,
room
);
if
(
room
==
0
)
return
;
memcpy_fromio
(
uart
->
rxbuf
,
port
->
membase
+
MEN_Z135_RX_RAM
,
room
);
/* Be sure to first copy all data and then acknowledge it */
mb
();
iowrite32
(
room
,
port
->
membase
+
MEN_Z135_RX_CTRL
);
copied
=
tty_insert_flip_string
(
tport
,
uart
->
rxbuf
,
room
);
if
(
copied
!=
room
)
dev_warn
(
&
uart
->
mdev
->
dev
,
"Only copied %d instead of %d bytes
\n
"
,
copied
,
room
);
port
->
icount
.
rx
+=
copied
;
tty_flip_buffer_push
(
tport
);
}
/**
* men_z135_handle_tx() - TX tasklet routine
* @arg: Pointer to struct men_z135_port
*
*/
static
void
men_z135_handle_tx
(
struct
men_z135_port
*
uart
)
{
struct
uart_port
*
port
=
&
uart
->
port
;
struct
circ_buf
*
xmit
=
&
port
->
state
->
xmit
;
u32
txc
;
u32
wptr
;
int
qlen
;
int
n
;
int
txfree
;
int
head
;
int
tail
;
int
s
;
if
(
uart_circ_empty
(
xmit
))
goto
out
;
if
(
uart_tx_stopped
(
port
))
goto
out
;
if
(
port
->
x_char
)
goto
out
;
if
(
uart_circ_chars_pending
(
xmit
)
<
WAKEUP_CHARS
)
uart_write_wakeup
(
port
);
/* calculate bytes to copy */
qlen
=
uart_circ_chars_pending
(
xmit
);
if
(
qlen
<=
0
)
goto
out
;
wptr
=
ioread32
(
port
->
membase
+
MEN_Z135_TX_CTRL
);
txc
=
(
wptr
>>
16
)
&
0x3ff
;
wptr
&=
0x3ff
;
if
(
txc
>
MEN_Z135_FIFO_WATERMARK
)
txc
=
MEN_Z135_FIFO_WATERMARK
;
txfree
=
MEN_Z135_FIFO_WATERMARK
-
txc
;
if
(
txfree
<=
0
)
{
pr_err
(
"Not enough room in TX FIFO have %d, need %d
\n
"
,
txfree
,
qlen
);
goto
irq_en
;
}
/* if we're not aligned, it's better to copy only 1 or 2 bytes and
* then the rest.
*/
if
(
align
&&
qlen
>=
3
&&
BYTES_TO_ALIGN
(
wptr
))
n
=
4
-
BYTES_TO_ALIGN
(
wptr
);
else
if
(
qlen
>
txfree
)
n
=
txfree
;
else
n
=
qlen
;
if
(
n
<=
0
)
goto
irq_en
;
head
=
xmit
->
head
&
(
UART_XMIT_SIZE
-
1
);
tail
=
xmit
->
tail
&
(
UART_XMIT_SIZE
-
1
);
s
=
((
head
>=
tail
)
?
head
:
UART_XMIT_SIZE
)
-
tail
;
n
=
min
(
n
,
s
);
memcpy_toio
(
port
->
membase
+
MEN_Z135_TX_RAM
,
&
xmit
->
buf
[
xmit
->
tail
],
n
);
xmit
->
tail
=
(
xmit
->
tail
+
n
)
&
(
UART_XMIT_SIZE
-
1
);
mmiowb
();
iowrite32
(
n
&
0x3ff
,
port
->
membase
+
MEN_Z135_TX_CTRL
);
port
->
icount
.
tx
+=
n
;
irq_en:
if
(
!
uart_circ_empty
(
xmit
))
men_z135_reg_set
(
uart
,
MEN_Z135_CONF_REG
,
MEN_Z135_IER_TXCIEN
);
else
men_z135_reg_clr
(
uart
,
MEN_Z135_CONF_REG
,
MEN_Z135_IER_TXCIEN
);
out:
return
;
}
/**
* men_z135_intr() - Handle legacy IRQs
* @irq: The IRQ number
* @data: Pointer to UART port
*
* Check IIR register to see which tasklet to start.
*/
static
irqreturn_t
men_z135_intr
(
int
irq
,
void
*
data
)
{
struct
men_z135_port
*
uart
=
(
struct
men_z135_port
*
)
data
;
struct
uart_port
*
port
=
&
uart
->
port
;
int
irq_id
;
uart
->
stat_reg
=
ioread32
(
port
->
membase
+
MEN_Z135_STAT_REG
);
/* IRQ pending is low active */
if
(
IS_IRQ
(
uart
->
stat_reg
))
return
IRQ_NONE
;
irq_id
=
IRQ_ID
(
uart
->
stat_reg
);
switch
(
irq_id
)
{
case
MEN_Z135_IRQ_ID_MST
:
men_z135_handle_modem_status
(
uart
);
break
;
case
MEN_Z135_IRQ_ID_TSA
:
men_z135_handle_tx
(
uart
);
break
;
case
MEN_Z135_IRQ_ID_CTI
:
dev_dbg
(
&
uart
->
mdev
->
dev
,
"Character Timeout Indication
\n
"
);
/* Fallthrough */
case
MEN_Z135_IRQ_ID_RDA
:
/* Reading data clears RX IRQ */
men_z135_handle_rx
(
uart
);
break
;
case
MEN_Z135_IRQ_ID_RLS
:
men_z135_handle_lsr
(
uart
);
break
;
default:
dev_warn
(
&
uart
->
mdev
->
dev
,
"Unknown IRQ id %d
\n
"
,
irq_id
);
return
IRQ_NONE
;
}
return
IRQ_HANDLED
;
}
/**
* men_z135_request_irq() - Request IRQ for 16z135 core
* @uart: z135 private uart port structure
*
* Request an IRQ for 16z135 to use. First try using MSI, if it fails
* fall back to using legacy interrupts.
*/
static
int
men_z135_request_irq
(
struct
men_z135_port
*
uart
)
{
struct
device
*
dev
=
&
uart
->
mdev
->
dev
;
struct
uart_port
*
port
=
&
uart
->
port
;
int
err
=
0
;
err
=
request_irq
(
port
->
irq
,
men_z135_intr
,
IRQF_SHARED
,
"men_z135_intr"
,
uart
);
if
(
err
)
dev_err
(
dev
,
"Error %d getting interrupt
\n
"
,
err
);
return
err
;
}
/**
* men_z135_tx_empty() - Handle tx_empty call
* @port: The UART port
*
* This function tests whether the TX FIFO and shifter for the port
* described by @port is empty.
*/
static
unsigned
int
men_z135_tx_empty
(
struct
uart_port
*
port
)
{
u32
wptr
;
u16
txc
;
wptr
=
ioread32
(
port
->
membase
+
MEN_Z135_TX_CTRL
);
txc
=
(
wptr
>>
16
)
&
0x3ff
;
if
(
txc
==
0
)
return
TIOCSER_TEMT
;
else
return
0
;
}
/**
* men_z135_set_mctrl() - Set modem control lines
* @port: The UART port
* @mctrl: The modem control lines
*
* This function sets the modem control lines for a port described by @port
* to the state described by @mctrl
*/
static
void
men_z135_set_mctrl
(
struct
uart_port
*
port
,
unsigned
int
mctrl
)
{
struct
men_z135_port
*
uart
=
to_men_z135
(
port
);
u32
conf_reg
=
0
;
if
(
mctrl
&
TIOCM_RTS
)
conf_reg
|=
MEN_Z135_MCR_RTS
;
if
(
mctrl
&
TIOCM_DTR
)
conf_reg
|=
MEN_Z135_MCR_DTR
;
if
(
mctrl
&
TIOCM_OUT1
)
conf_reg
|=
MEN_Z135_MCR_OUT1
;
if
(
mctrl
&
TIOCM_OUT2
)
conf_reg
|=
MEN_Z135_MCR_OUT2
;
if
(
mctrl
&
TIOCM_LOOP
)
conf_reg
|=
MEN_Z135_MCR_LOOP
;
men_z135_reg_set
(
uart
,
MEN_Z135_CONF_REG
,
conf_reg
);
}
/**
* men_z135_get_mctrl() - Get modem control lines
* @port: The UART port
*
* Retruns the current state of modem control inputs.
*/
static
unsigned
int
men_z135_get_mctrl
(
struct
uart_port
*
port
)
{
unsigned
int
mctrl
=
0
;
u32
stat_reg
;
u8
msr
;
stat_reg
=
ioread32
(
port
->
membase
+
MEN_Z135_STAT_REG
);
msr
=
~
((
stat_reg
>>
8
)
&
0xff
);
if
(
msr
&
MEN_Z135_MSR_CTS
)
mctrl
|=
TIOCM_CTS
;
if
(
msr
&
MEN_Z135_MSR_DSR
)
mctrl
|=
TIOCM_DSR
;
if
(
msr
&
MEN_Z135_MSR_RI
)
mctrl
|=
TIOCM_RI
;
if
(
msr
&
MEN_Z135_MSR_DCD
)
mctrl
|=
TIOCM_CAR
;
return
mctrl
;
}
/**
* men_z135_stop_tx() - Stop transmitting characters
* @port: The UART port
*
* Stop transmitting characters. This might be due to CTS line becomming
* inactive or the tty layer indicating we want to stop transmission due to
* an XOFF character.
*/
static
void
men_z135_stop_tx
(
struct
uart_port
*
port
)
{
struct
men_z135_port
*
uart
=
to_men_z135
(
port
);
men_z135_reg_clr
(
uart
,
MEN_Z135_CONF_REG
,
MEN_Z135_IER_TXCIEN
);
}
/**
* men_z135_start_tx() - Start transmitting characters
* @port: The UART port
*
* Start transmitting character. This actually doesn't transmit anything, but
* fires off the TX tasklet.
*/
static
void
men_z135_start_tx
(
struct
uart_port
*
port
)
{
struct
men_z135_port
*
uart
=
to_men_z135
(
port
);
men_z135_handle_tx
(
uart
);
}
/**
* men_z135_stop_rx() - Stop receiving characters
* @port: The UART port
*
* Stop receiving characters; the port is in the process of being closed.
*/
static
void
men_z135_stop_rx
(
struct
uart_port
*
port
)
{
struct
men_z135_port
*
uart
=
to_men_z135
(
port
);
men_z135_reg_clr
(
uart
,
MEN_Z135_CONF_REG
,
MEN_Z135_IER_RXCIEN
);
}
/**
* men_z135_enable_ms() - Enable Modem Status
* port:
*
* Enable Modem Status IRQ.
*/
static
void
men_z135_enable_ms
(
struct
uart_port
*
port
)
{
struct
men_z135_port
*
uart
=
to_men_z135
(
port
);
men_z135_reg_set
(
uart
,
MEN_Z135_CONF_REG
,
MEN_Z135_IER_MSIEN
);
}
static
int
men_z135_startup
(
struct
uart_port
*
port
)
{
struct
men_z135_port
*
uart
=
to_men_z135
(
port
);
int
err
;
u32
conf_reg
=
0
;
err
=
men_z135_request_irq
(
uart
);
if
(
err
)
return
-
ENODEV
;
conf_reg
=
ioread32
(
port
->
membase
+
MEN_Z135_CONF_REG
);
conf_reg
|=
MEN_Z135_ALL_IRQS
;
conf_reg
&=
~
(
0xff
<<
16
);
conf_reg
|=
(
txlvl
<<
16
);
conf_reg
|=
(
rxlvl
<<
20
);
iowrite32
(
conf_reg
,
port
->
membase
+
MEN_Z135_CONF_REG
);
return
0
;
}
static
void
men_z135_shutdown
(
struct
uart_port
*
port
)
{
struct
men_z135_port
*
uart
=
to_men_z135
(
port
);
u32
conf_reg
=
0
;
conf_reg
|=
MEN_Z135_ALL_IRQS
;
men_z135_reg_clr
(
uart
,
MEN_Z135_CONF_REG
,
conf_reg
);
free_irq
(
uart
->
port
.
irq
,
uart
);
}
static
void
men_z135_set_termios
(
struct
uart_port
*
port
,
struct
ktermios
*
termios
,
struct
ktermios
*
old
)
{
unsigned
int
baud
;
u32
conf_reg
;
u32
bd_reg
;
u32
uart_freq
;
u8
lcr
;
conf_reg
=
ioread32
(
port
->
membase
+
MEN_Z135_CONF_REG
);
lcr
=
LCR
(
conf_reg
);
/* byte size */
switch
(
termios
->
c_cflag
&
CSIZE
)
{
case
CS5
:
lcr
|=
MEN_Z135_WL5
;
break
;
case
CS6
:
lcr
|=
MEN_Z135_WL6
;
break
;
case
CS7
:
lcr
|=
MEN_Z135_WL7
;
break
;
case
CS8
:
lcr
|=
MEN_Z135_WL8
;
break
;
}
/* stop bits */
if
(
termios
->
c_cflag
&
CSTOPB
)
lcr
|=
MEN_Z135_NSTB2
<<
MEN_Z135_STB_SHIFT
;
/* parity */
if
(
termios
->
c_cflag
&
PARENB
)
{
lcr
|=
MEN_Z135_PAR_ENA
<<
MEN_Z135_PEN_SHIFT
;
if
(
termios
->
c_cflag
&
PARODD
)
lcr
|=
MEN_Z135_PTY_ODD
<<
MEN_Z135_PTY_SHIFT
;
else
lcr
|=
MEN_Z135_PTY_EVN
<<
MEN_Z135_PTY_SHIFT
;
}
else
lcr
|=
MEN_Z135_PAR_DIS
<<
MEN_Z135_PEN_SHIFT
;
termios
->
c_cflag
&=
~
CMSPAR
;
/* Mark/Space parity is not supported */
conf_reg
|=
lcr
<<
MEN_Z135_LCR_SHIFT
;
iowrite32
(
conf_reg
,
port
->
membase
+
MEN_Z135_CONF_REG
);
uart_freq
=
ioread32
(
port
->
membase
+
MEN_Z135_UART_FREQ
);
if
(
uart_freq
==
0
)
uart_freq
=
MEN_Z135_BASECLK
;
baud
=
uart_get_baud_rate
(
port
,
termios
,
old
,
0
,
uart_freq
/
16
);
spin_lock
(
&
port
->
lock
);
if
(
tty_termios_baud_rate
(
termios
))
tty_termios_encode_baud_rate
(
termios
,
baud
,
baud
);
bd_reg
=
uart_freq
/
(
4
*
baud
);
iowrite32
(
bd_reg
,
port
->
membase
+
MEN_Z135_BAUD_REG
);
uart_update_timeout
(
port
,
termios
->
c_cflag
,
baud
);
spin_unlock
(
&
port
->
lock
);
}
static
const
char
*
men_z135_type
(
struct
uart_port
*
port
)
{
return
KBUILD_MODNAME
;
}
static
void
men_z135_release_port
(
struct
uart_port
*
port
)
{
iounmap
(
port
->
membase
);
port
->
membase
=
NULL
;
release_mem_region
(
port
->
mapbase
,
MEN_Z135_MEM_SIZE
);
}
static
int
men_z135_request_port
(
struct
uart_port
*
port
)
{
int
size
=
MEN_Z135_MEM_SIZE
;
if
(
!
request_mem_region
(
port
->
mapbase
,
size
,
"men_z135_port"
))
return
-
EBUSY
;
port
->
membase
=
ioremap
(
port
->
mapbase
,
MEN_Z135_MEM_SIZE
);
if
(
port
->
membase
==
NULL
)
{
release_mem_region
(
port
->
mapbase
,
MEN_Z135_MEM_SIZE
);
return
-
ENOMEM
;
}
return
0
;
}
static
void
men_z135_config_port
(
struct
uart_port
*
port
,
int
type
)
{
port
->
type
=
PORT_MEN_Z135
;
men_z135_request_port
(
port
);
}
static
int
men_z135_verify_port
(
struct
uart_port
*
port
,
struct
serial_struct
*
serinfo
)
{
return
-
EINVAL
;
}
static
struct
uart_ops
men_z135_ops
=
{
.
tx_empty
=
men_z135_tx_empty
,
.
set_mctrl
=
men_z135_set_mctrl
,
.
get_mctrl
=
men_z135_get_mctrl
,
.
stop_tx
=
men_z135_stop_tx
,
.
start_tx
=
men_z135_start_tx
,
.
stop_rx
=
men_z135_stop_rx
,
.
enable_ms
=
men_z135_enable_ms
,
.
startup
=
men_z135_startup
,
.
shutdown
=
men_z135_shutdown
,
.
set_termios
=
men_z135_set_termios
,
.
type
=
men_z135_type
,
.
release_port
=
men_z135_release_port
,
.
request_port
=
men_z135_request_port
,
.
config_port
=
men_z135_config_port
,
.
verify_port
=
men_z135_verify_port
,
};
static
struct
uart_driver
men_z135_driver
=
{
.
owner
=
THIS_MODULE
,
.
driver_name
=
KBUILD_MODNAME
,
.
dev_name
=
"ttyHSU"
,
.
major
=
0
,
.
minor
=
0
,
.
nr
=
MEN_Z135_MAX_PORTS
,
};
/**
* men_z135_probe() - Probe a z135 instance
* @mdev: The MCB device
* @id: The MCB device ID
*
* men_z135_probe does the basic setup of hardware resources and registers the
* new uart port to the tty layer.
*/
static
int
men_z135_probe
(
struct
mcb_device
*
mdev
,
const
struct
mcb_device_id
*
id
)
{
struct
men_z135_port
*
uart
;
struct
resource
*
mem
;
struct
device
*
dev
;
int
err
;
dev
=
&
mdev
->
dev
;
uart
=
devm_kzalloc
(
dev
,
sizeof
(
struct
men_z135_port
),
GFP_KERNEL
);
if
(
!
uart
)
return
-
ENOMEM
;
uart
->
rxbuf
=
(
unsigned
char
*
)
__get_free_page
(
GFP_KERNEL
);
if
(
!
uart
->
rxbuf
)
return
-
ENOMEM
;
mem
=
&
mdev
->
mem
;
mcb_set_drvdata
(
mdev
,
uart
);
uart
->
port
.
uartclk
=
MEN_Z135_BASECLK
*
16
;
uart
->
port
.
fifosize
=
MEN_Z135_FIFO_SIZE
;
uart
->
port
.
iotype
=
UPIO_MEM
;
uart
->
port
.
ops
=
&
men_z135_ops
;
uart
->
port
.
irq
=
mcb_get_irq
(
mdev
);
uart
->
port
.
iotype
=
UPIO_MEM
;
uart
->
port
.
flags
=
UPF_BOOT_AUTOCONF
|
UPF_IOREMAP
;
uart
->
port
.
line
=
line
++
;
uart
->
port
.
dev
=
dev
;
uart
->
port
.
type
=
PORT_MEN_Z135
;
uart
->
port
.
mapbase
=
mem
->
start
;
uart
->
port
.
membase
=
NULL
;
uart
->
mdev
=
mdev
;
spin_lock_init
(
&
uart
->
port
.
lock
);
spin_lock_init
(
&
uart
->
lock
);
err
=
uart_add_one_port
(
&
men_z135_driver
,
&
uart
->
port
);
if
(
err
)
goto
err
;
return
0
;
err:
free_page
((
unsigned
long
)
uart
->
rxbuf
);
dev_err
(
dev
,
"Failed to add UART: %d
\n
"
,
err
);
return
err
;
}
/**
* men_z135_remove() - Remove a z135 instance from the system
*
* @mdev: The MCB device
*/
static
void
men_z135_remove
(
struct
mcb_device
*
mdev
)
{
struct
men_z135_port
*
uart
=
mcb_get_drvdata
(
mdev
);
line
--
;
uart_remove_one_port
(
&
men_z135_driver
,
&
uart
->
port
);
free_page
((
unsigned
long
)
uart
->
rxbuf
);
}
static
const
struct
mcb_device_id
men_z135_ids
[]
=
{
{
.
device
=
0x87
},
};
MODULE_DEVICE_TABLE
(
mcb
,
men_z135_ids
);
static
struct
mcb_driver
mcb_driver
=
{
.
driver
=
{
.
name
=
"z135-uart"
,
.
owner
=
THIS_MODULE
,
},
.
probe
=
men_z135_probe
,
.
remove
=
men_z135_remove
,
.
id_table
=
men_z135_ids
,
};
/**
* men_z135_init() - Driver Registration Routine
*
* men_z135_init is the first routine called when the driver is loaded. All it
* does is register with the legacy MEN Chameleon subsystem.
*/
static
int
__init
men_z135_init
(
void
)
{
int
err
;
err
=
uart_register_driver
(
&
men_z135_driver
);
if
(
err
)
{
pr_err
(
"Failed to register UART: %d
\n
"
,
err
);
return
err
;
}
err
=
mcb_register_driver
(
&
mcb_driver
);
if
(
err
)
{
pr_err
(
"Failed to register MCB driver: %d
\n
"
,
err
);
uart_unregister_driver
(
&
men_z135_driver
);
return
err
;
}
return
0
;
}
module_init
(
men_z135_init
);
/**
* men_z135_exit() - Driver Exit Routine
*
* men_z135_exit is called just before the driver is removed from memory.
*/
static
void
__exit
men_z135_exit
(
void
)
{
mcb_unregister_driver
(
&
mcb_driver
);
uart_unregister_driver
(
&
men_z135_driver
);
}
module_exit
(
men_z135_exit
);
MODULE_AUTHOR
(
"Johannes Thumshirn <johannes.thumshirn@men.de>"
);
MODULE_LICENSE
(
"GPL v2"
);
MODULE_DESCRIPTION
(
"MEN 16z135 High Speed UART"
);
MODULE_ALIAS
(
"mcb:16z135"
);
drivers/tty/serial/mux.c
View file @
728dd198
...
@@ -29,7 +29,7 @@
...
@@ -29,7 +29,7 @@
#include <asm/irq.h>
#include <asm/irq.h>
#include <asm/parisc-device.h>
#include <asm/parisc-device.h>
#if
def CONFIG_MAGIC_SYSRQ
#if
defined(CONFIG_SERIAL_MUX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#include <linux/sysrq.h>
#include <linux/sysrq.h>
#define SUPPORT_SYSRQ
#define SUPPORT_SYSRQ
#endif
#endif
...
@@ -613,7 +613,7 @@ static void __exit mux_exit(void)
...
@@ -613,7 +613,7 @@ static void __exit mux_exit(void)
{
{
/* Delete the Mux timer. */
/* Delete the Mux timer. */
if
(
port_cnt
>
0
)
{
if
(
port_cnt
>
0
)
{
del_timer
(
&
mux_timer
);
del_timer
_sync
(
&
mux_timer
);
#ifdef CONFIG_SERIAL_MUX_CONSOLE
#ifdef CONFIG_SERIAL_MUX_CONSOLE
unregister_console
(
&
mux_console
);
unregister_console
(
&
mux_console
);
#endif
#endif
...
...
drivers/tty/serial/omap-serial.c
View file @
728dd198
...
@@ -163,10 +163,6 @@ struct uart_omap_port {
...
@@ -163,10 +163,6 @@ struct uart_omap_port {
u8
wakeups_enabled
;
u8
wakeups_enabled
;
u32
features
;
u32
features
;
int
DTR_gpio
;
int
DTR_inverted
;
int
DTR_active
;
struct
serial_rs485
rs485
;
struct
serial_rs485
rs485
;
int
rts_gpio
;
int
rts_gpio
;
...
@@ -184,8 +180,6 @@ static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
...
@@ -184,8 +180,6 @@ static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
/* Forward declaration of functions */
/* Forward declaration of functions */
static
void
serial_omap_mdr1_errataset
(
struct
uart_omap_port
*
up
,
u8
mdr1
);
static
void
serial_omap_mdr1_errataset
(
struct
uart_omap_port
*
up
,
u8
mdr1
);
static
struct
workqueue_struct
*
serial_omap_uart_wq
;
static
inline
unsigned
int
serial_in
(
struct
uart_omap_port
*
up
,
int
offset
)
static
inline
unsigned
int
serial_in
(
struct
uart_omap_port
*
up
,
int
offset
)
{
{
offset
<<=
up
->
port
.
regshift
;
offset
<<=
up
->
port
.
regshift
;
...
@@ -398,11 +392,8 @@ static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
...
@@ -398,11 +392,8 @@ static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
break
;
break
;
}
while
(
--
count
>
0
);
}
while
(
--
count
>
0
);
if
(
uart_circ_chars_pending
(
xmit
)
<
WAKEUP_CHARS
)
{
if
(
uart_circ_chars_pending
(
xmit
)
<
WAKEUP_CHARS
)
spin_unlock
(
&
up
->
port
.
lock
);
uart_write_wakeup
(
&
up
->
port
);
uart_write_wakeup
(
&
up
->
port
);
spin_lock
(
&
up
->
port
.
lock
);
}
if
(
uart_circ_empty
(
xmit
))
if
(
uart_circ_empty
(
xmit
))
serial_omap_stop_tx
(
&
up
->
port
);
serial_omap_stop_tx
(
&
up
->
port
);
...
@@ -697,16 +688,6 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
...
@@ -697,16 +688,6 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
serial_out
(
up
,
UART_MCR
,
up
->
mcr
);
serial_out
(
up
,
UART_MCR
,
up
->
mcr
);
pm_runtime_mark_last_busy
(
up
->
dev
);
pm_runtime_mark_last_busy
(
up
->
dev
);
pm_runtime_put_autosuspend
(
up
->
dev
);
pm_runtime_put_autosuspend
(
up
->
dev
);
if
(
gpio_is_valid
(
up
->
DTR_gpio
)
&&
!!
(
mctrl
&
TIOCM_DTR
)
!=
up
->
DTR_active
)
{
up
->
DTR_active
=
!
up
->
DTR_active
;
if
(
gpio_cansleep
(
up
->
DTR_gpio
))
schedule_work
(
&
up
->
qos_work
);
else
gpio_set_value
(
up
->
DTR_gpio
,
up
->
DTR_active
!=
up
->
DTR_inverted
);
}
}
}
static
void
serial_omap_break_ctl
(
struct
uart_port
*
port
,
int
break_state
)
static
void
serial_omap_break_ctl
(
struct
uart_port
*
port
,
int
break_state
)
...
@@ -850,9 +831,6 @@ static void serial_omap_uart_qos_work(struct work_struct *work)
...
@@ -850,9 +831,6 @@ static void serial_omap_uart_qos_work(struct work_struct *work)
qos_work
);
qos_work
);
pm_qos_update_request
(
&
up
->
pm_qos_request
,
up
->
latency
);
pm_qos_update_request
(
&
up
->
pm_qos_request
,
up
->
latency
);
if
(
gpio_is_valid
(
up
->
DTR_gpio
))
gpio_set_value_cansleep
(
up
->
DTR_gpio
,
up
->
DTR_active
!=
up
->
DTR_inverted
);
}
}
static
void
static
void
...
@@ -1420,7 +1398,7 @@ serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
...
@@ -1420,7 +1398,7 @@ serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
switch
(
cmd
)
{
switch
(
cmd
)
{
case
TIOCSRS485
:
case
TIOCSRS485
:
if
(
copy_from_user
(
&
rs485conf
,
(
struct
serial_rs485
*
)
arg
,
if
(
copy_from_user
(
&
rs485conf
,
(
void
__user
*
)
arg
,
sizeof
(
rs485conf
)))
sizeof
(
rs485conf
)))
return
-
EFAULT
;
return
-
EFAULT
;
...
@@ -1428,7 +1406,7 @@ serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
...
@@ -1428,7 +1406,7 @@ serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
break
;
break
;
case
TIOCGRS485
:
case
TIOCGRS485
:
if
(
copy_to_user
((
struct
serial_rs485
*
)
arg
,
if
(
copy_to_user
((
void
__user
*
)
arg
,
&
(
to_uart_omap_port
(
port
)
->
rs485
),
&
(
to_uart_omap_port
(
port
)
->
rs485
),
sizeof
(
rs485conf
)))
sizeof
(
rs485conf
)))
return
-
EFAULT
;
return
-
EFAULT
;
...
@@ -1614,7 +1592,7 @@ static int serial_omap_probe_rs485(struct uart_omap_port *up,
...
@@ -1614,7 +1592,7 @@ static int serial_omap_probe_rs485(struct uart_omap_port *up,
/* check for tx enable gpio */
/* check for tx enable gpio */
up
->
rts_gpio
=
of_get_named_gpio_flags
(
np
,
"rts-gpio"
,
0
,
&
flags
);
up
->
rts_gpio
=
of_get_named_gpio_flags
(
np
,
"rts-gpio"
,
0
,
&
flags
);
if
(
gpio_is_valid
(
up
->
rts_gpio
))
{
if
(
gpio_is_valid
(
up
->
rts_gpio
))
{
ret
=
gpio_request
(
up
->
rts_gpio
,
"omap-serial"
);
ret
=
devm_gpio_request
(
up
->
dev
,
up
->
rts_gpio
,
"omap-serial"
);
if
(
ret
<
0
)
if
(
ret
<
0
)
return
ret
;
return
ret
;
ret
=
gpio_direction_output
(
up
->
rts_gpio
,
ret
=
gpio_direction_output
(
up
->
rts_gpio
,
...
@@ -1644,10 +1622,13 @@ static int serial_omap_probe_rs485(struct uart_omap_port *up,
...
@@ -1644,10 +1622,13 @@ static int serial_omap_probe_rs485(struct uart_omap_port *up,
static
int
serial_omap_probe
(
struct
platform_device
*
pdev
)
static
int
serial_omap_probe
(
struct
platform_device
*
pdev
)
{
{
struct
uart_omap_port
*
up
;
struct
resource
*
mem
,
*
irq
;
struct
omap_uart_port_info
*
omap_up_info
=
dev_get_platdata
(
&
pdev
->
dev
);
struct
omap_uart_port_info
*
omap_up_info
=
dev_get_platdata
(
&
pdev
->
dev
);
int
ret
,
uartirq
=
0
,
wakeirq
=
0
;
struct
uart_omap_port
*
up
;
struct
resource
*
mem
;
void
__iomem
*
base
;
int
uartirq
=
0
;
int
wakeirq
=
0
;
int
ret
;
/* The optional wakeirq may be specified in the board dts file */
/* The optional wakeirq may be specified in the board dts file */
if
(
pdev
->
dev
.
of_node
)
{
if
(
pdev
->
dev
.
of_node
)
{
...
@@ -1658,48 +1639,19 @@ static int serial_omap_probe(struct platform_device *pdev)
...
@@ -1658,48 +1639,19 @@ static int serial_omap_probe(struct platform_device *pdev)
omap_up_info
=
of_get_uart_port_info
(
&
pdev
->
dev
);
omap_up_info
=
of_get_uart_port_info
(
&
pdev
->
dev
);
pdev
->
dev
.
platform_data
=
omap_up_info
;
pdev
->
dev
.
platform_data
=
omap_up_info
;
}
else
{
}
else
{
irq
=
platform_get_resource
(
pdev
,
IORESOURCE_IRQ
,
0
);
uartirq
=
platform_get_irq
(
pdev
,
0
);
if
(
!
irq
)
{
if
(
uartirq
<
0
)
dev_err
(
&
pdev
->
dev
,
"no irq resource?
\n
"
);
return
-
EPROBE_DEFER
;
return
-
ENODEV
;
}
uartirq
=
irq
->
start
;
}
mem
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
if
(
!
mem
)
{
dev_err
(
&
pdev
->
dev
,
"no mem resource?
\n
"
);
return
-
ENODEV
;
}
if
(
!
devm_request_mem_region
(
&
pdev
->
dev
,
mem
->
start
,
resource_size
(
mem
),
pdev
->
dev
.
driver
->
name
))
{
dev_err
(
&
pdev
->
dev
,
"memory region already claimed
\n
"
);
return
-
EBUSY
;
}
if
(
gpio_is_valid
(
omap_up_info
->
DTR_gpio
)
&&
omap_up_info
->
DTR_present
)
{
ret
=
gpio_request
(
omap_up_info
->
DTR_gpio
,
"omap-serial"
);
if
(
ret
<
0
)
return
ret
;
ret
=
gpio_direction_output
(
omap_up_info
->
DTR_gpio
,
omap_up_info
->
DTR_inverted
);
if
(
ret
<
0
)
return
ret
;
}
}
up
=
devm_kzalloc
(
&
pdev
->
dev
,
sizeof
(
*
up
),
GFP_KERNEL
);
up
=
devm_kzalloc
(
&
pdev
->
dev
,
sizeof
(
*
up
),
GFP_KERNEL
);
if
(
!
up
)
if
(
!
up
)
return
-
ENOMEM
;
return
-
ENOMEM
;
if
(
gpio_is_valid
(
omap_up_info
->
DTR_gpio
)
&&
mem
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
omap_up_info
->
DTR_present
)
{
base
=
devm_ioremap_resource
(
&
pdev
->
dev
,
mem
);
up
->
DTR_gpio
=
omap_up_info
->
DTR_gpio
;
if
(
IS_ERR
(
base
))
up
->
DTR_inverted
=
omap_up_info
->
DTR_inverted
;
return
PTR_ERR
(
base
);
}
else
up
->
DTR_gpio
=
-
EINVAL
;
up
->
DTR_active
=
0
;
up
->
dev
=
&
pdev
->
dev
;
up
->
dev
=
&
pdev
->
dev
;
up
->
port
.
dev
=
&
pdev
->
dev
;
up
->
port
.
dev
=
&
pdev
->
dev
;
...
@@ -1733,14 +1685,7 @@ static int serial_omap_probe(struct platform_device *pdev)
...
@@ -1733,14 +1685,7 @@ static int serial_omap_probe(struct platform_device *pdev)
sprintf
(
up
->
name
,
"OMAP UART%d"
,
up
->
port
.
line
);
sprintf
(
up
->
name
,
"OMAP UART%d"
,
up
->
port
.
line
);
up
->
port
.
mapbase
=
mem
->
start
;
up
->
port
.
mapbase
=
mem
->
start
;
up
->
port
.
membase
=
devm_ioremap
(
&
pdev
->
dev
,
mem
->
start
,
up
->
port
.
membase
=
base
;
resource_size
(
mem
));
if
(
!
up
->
port
.
membase
)
{
dev_err
(
&
pdev
->
dev
,
"can't ioremap UART
\n
"
);
ret
=
-
ENOMEM
;
goto
err_ioremap
;
}
up
->
port
.
flags
=
omap_up_info
->
flags
;
up
->
port
.
flags
=
omap_up_info
->
flags
;
up
->
port
.
uartclk
=
omap_up_info
->
uartclk
;
up
->
port
.
uartclk
=
omap_up_info
->
uartclk
;
if
(
!
up
->
port
.
uartclk
)
{
if
(
!
up
->
port
.
uartclk
)
{
...
@@ -1754,12 +1699,12 @@ static int serial_omap_probe(struct platform_device *pdev)
...
@@ -1754,12 +1699,12 @@ static int serial_omap_probe(struct platform_device *pdev)
up
->
calc_latency
=
PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
up
->
calc_latency
=
PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
pm_qos_add_request
(
&
up
->
pm_qos_request
,
pm_qos_add_request
(
&
up
->
pm_qos_request
,
PM_QOS_CPU_DMA_LATENCY
,
up
->
latency
);
PM_QOS_CPU_DMA_LATENCY
,
up
->
latency
);
serial_omap_uart_wq
=
create_singlethread_workqueue
(
up
->
name
);
INIT_WORK
(
&
up
->
qos_work
,
serial_omap_uart_qos_work
);
INIT_WORK
(
&
up
->
qos_work
,
serial_omap_uart_qos_work
);
platform_set_drvdata
(
pdev
,
up
);
platform_set_drvdata
(
pdev
,
up
);
if
(
omap_up_info
->
autosuspend_timeout
==
0
)
if
(
omap_up_info
->
autosuspend_timeout
==
0
)
omap_up_info
->
autosuspend_timeout
=
-
1
;
omap_up_info
->
autosuspend_timeout
=
-
1
;
device_init_wakeup
(
up
->
dev
,
true
);
device_init_wakeup
(
up
->
dev
,
true
);
pm_runtime_use_autosuspend
(
&
pdev
->
dev
);
pm_runtime_use_autosuspend
(
&
pdev
->
dev
);
pm_runtime_set_autosuspend_delay
(
&
pdev
->
dev
,
pm_runtime_set_autosuspend_delay
(
&
pdev
->
dev
,
...
@@ -1786,7 +1731,6 @@ static int serial_omap_probe(struct platform_device *pdev)
...
@@ -1786,7 +1731,6 @@ static int serial_omap_probe(struct platform_device *pdev)
err_add_port:
err_add_port:
pm_runtime_put
(
&
pdev
->
dev
);
pm_runtime_put
(
&
pdev
->
dev
);
pm_runtime_disable
(
&
pdev
->
dev
);
pm_runtime_disable
(
&
pdev
->
dev
);
err_ioremap:
err_rs485:
err_rs485:
err_port_line:
err_port_line:
dev_err
(
&
pdev
->
dev
,
"[UART%d]: failure [%s]: %d
\n
"
,
dev_err
(
&
pdev
->
dev
,
"[UART%d]: failure [%s]: %d
\n
"
,
...
...
drivers/tty/serial/pch_uart.c
View file @
728dd198
...
@@ -257,6 +257,8 @@ struct eg20t_port {
...
@@ -257,6 +257,8 @@ struct eg20t_port {
dma_addr_t
rx_buf_dma
;
dma_addr_t
rx_buf_dma
;
struct
dentry
*
debugfs
;
struct
dentry
*
debugfs
;
#define IRQ_NAME_SIZE 17
char
irq_name
[
IRQ_NAME_SIZE
];
/* protect the eg20t_port private structure and io access to membase */
/* protect the eg20t_port private structure and io access to membase */
spinlock_t
lock
;
spinlock_t
lock
;
...
@@ -1343,7 +1345,7 @@ static int pch_uart_startup(struct uart_port *port)
...
@@ -1343,7 +1345,7 @@ static int pch_uart_startup(struct uart_port *port)
return
ret
;
return
ret
;
ret
=
request_irq
(
priv
->
port
.
irq
,
pch_uart_interrupt
,
IRQF_SHARED
,
ret
=
request_irq
(
priv
->
port
.
irq
,
pch_uart_interrupt
,
IRQF_SHARED
,
KBUILD_MODNAME
,
priv
);
priv
->
irq_name
,
priv
);
if
(
ret
<
0
)
if
(
ret
<
0
)
return
ret
;
return
ret
;
...
@@ -1588,13 +1590,8 @@ static void pch_uart_put_poll_char(struct uart_port *port,
...
@@ -1588,13 +1590,8 @@ static void pch_uart_put_poll_char(struct uart_port *port,
wait_for_xmitr
(
priv
,
UART_LSR_THRE
);
wait_for_xmitr
(
priv
,
UART_LSR_THRE
);
/*
/*
* Send the character out.
* Send the character out.
* If a LF, also do CR...
*/
*/
iowrite8
(
c
,
priv
->
membase
+
PCH_UART_THR
);
iowrite8
(
c
,
priv
->
membase
+
PCH_UART_THR
);
if
(
c
==
10
)
{
wait_for_xmitr
(
priv
,
UART_LSR_THRE
);
iowrite8
(
13
,
priv
->
membase
+
PCH_UART_THR
);
}
/*
/*
* Finally, wait for transmitter to become empty
* Finally, wait for transmitter to become empty
...
@@ -1818,6 +1815,10 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
...
@@ -1818,6 +1815,10 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
priv
->
port
.
line
=
board
->
line_no
;
priv
->
port
.
line
=
board
->
line_no
;
priv
->
trigger
=
PCH_UART_HAL_TRIGGER_M
;
priv
->
trigger
=
PCH_UART_HAL_TRIGGER_M
;
snprintf
(
priv
->
irq_name
,
IRQ_NAME_SIZE
,
KBUILD_MODNAME
":"
PCH_UART_DRIVER_DEVICE
"%d"
,
priv
->
port
.
line
);
spin_lock_init
(
&
priv
->
port
.
lock
);
spin_lock_init
(
&
priv
->
port
.
lock
);
pci_set_drvdata
(
pdev
,
priv
);
pci_set_drvdata
(
pdev
,
priv
);
...
...
drivers/tty/serial/pxa.c
View file @
728dd198
...
@@ -711,13 +711,8 @@ static void serial_pxa_put_poll_char(struct uart_port *port,
...
@@ -711,13 +711,8 @@ static void serial_pxa_put_poll_char(struct uart_port *port,
wait_for_xmitr
(
up
);
wait_for_xmitr
(
up
);
/*
/*
* Send the character out.
* Send the character out.
* If a LF, also do CR...
*/
*/
serial_out
(
up
,
UART_TX
,
c
);
serial_out
(
up
,
UART_TX
,
c
);
if
(
c
==
10
)
{
wait_for_xmitr
(
up
);
serial_out
(
up
,
UART_TX
,
13
);
}
/*
/*
* Finally, wait for transmitter to become empty
* Finally, wait for transmitter to become empty
...
...
drivers/tty/serial/sc16is7xx.c
0 → 100644
View file @
728dd198
/*
* SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
* Author: Jon Ringle <jringle@gridpoint.com>
*
* Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/uaccess.h>
#define SC16IS7XX_NAME "sc16is7xx"
/* SC16IS7XX register definitions */
#define SC16IS7XX_RHR_REG (0x00)
/* RX FIFO */
#define SC16IS7XX_THR_REG (0x00)
/* TX FIFO */
#define SC16IS7XX_IER_REG (0x01)
/* Interrupt enable */
#define SC16IS7XX_IIR_REG (0x02)
/* Interrupt Identification */
#define SC16IS7XX_FCR_REG (0x02)
/* FIFO control */
#define SC16IS7XX_LCR_REG (0x03)
/* Line Control */
#define SC16IS7XX_MCR_REG (0x04)
/* Modem Control */
#define SC16IS7XX_LSR_REG (0x05)
/* Line Status */
#define SC16IS7XX_MSR_REG (0x06)
/* Modem Status */
#define SC16IS7XX_SPR_REG (0x07)
/* Scratch Pad */
#define SC16IS7XX_TXLVL_REG (0x08)
/* TX FIFO level */
#define SC16IS7XX_RXLVL_REG (0x09)
/* RX FIFO level */
#define SC16IS7XX_IODIR_REG (0x0a)
/* I/O Direction
* - only on 75x/76x
*/
#define SC16IS7XX_IOSTATE_REG (0x0b)
/* I/O State
* - only on 75x/76x
*/
#define SC16IS7XX_IOINTENA_REG (0x0c)
/* I/O Interrupt Enable
* - only on 75x/76x
*/
#define SC16IS7XX_IOCONTROL_REG (0x0e)
/* I/O Control
* - only on 75x/76x
*/
#define SC16IS7XX_EFCR_REG (0x0f)
/* Extra Features Control */
/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
#define SC16IS7XX_TCR_REG (0x06)
/* Transmit control */
#define SC16IS7XX_TLR_REG (0x07)
/* Trigger level */
/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
#define SC16IS7XX_DLL_REG (0x00)
/* Divisor Latch Low */
#define SC16IS7XX_DLH_REG (0x01)
/* Divisor Latch High */
/* Enhanced Register set: Only if (LCR == 0xBF) */
#define SC16IS7XX_EFR_REG (0x02)
/* Enhanced Features */
#define SC16IS7XX_XON1_REG (0x04)
/* Xon1 word */
#define SC16IS7XX_XON2_REG (0x05)
/* Xon2 word */
#define SC16IS7XX_XOFF1_REG (0x06)
/* Xoff1 word */
#define SC16IS7XX_XOFF2_REG (0x07)
/* Xoff2 word */
/* IER register bits */
#define SC16IS7XX_IER_RDI_BIT (1 << 0)
/* Enable RX data interrupt */
#define SC16IS7XX_IER_THRI_BIT (1 << 1)
/* Enable TX holding register
* interrupt */
#define SC16IS7XX_IER_RLSI_BIT (1 << 2)
/* Enable RX line status
* interrupt */
#define SC16IS7XX_IER_MSI_BIT (1 << 3)
/* Enable Modem status
* interrupt */
/* IER register bits - write only if (EFR[4] == 1) */
#define SC16IS7XX_IER_SLEEP_BIT (1 << 4)
/* Enable Sleep mode */
#define SC16IS7XX_IER_XOFFI_BIT (1 << 5)
/* Enable Xoff interrupt */
#define SC16IS7XX_IER_RTSI_BIT (1 << 6)
/* Enable nRTS interrupt */
#define SC16IS7XX_IER_CTSI_BIT (1 << 7)
/* Enable nCTS interrupt */
/* FCR register bits */
#define SC16IS7XX_FCR_FIFO_BIT (1 << 0)
/* Enable FIFO */
#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1)
/* Reset RX FIFO */
#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2)
/* Reset TX FIFO */
#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6)
/* RX Trigger level LSB */
#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7)
/* RX Trigger level MSB */
/* FCR register bits - write only if (EFR[4] == 1) */
#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4)
/* TX Trigger level LSB */
#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5)
/* TX Trigger level MSB */
/* IIR register bits */
#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0)
/* No interrupts pending */
#define SC16IS7XX_IIR_ID_MASK 0x3e
/* Mask for the interrupt ID */
#define SC16IS7XX_IIR_THRI_SRC 0x02
/* TX holding register empty */
#define SC16IS7XX_IIR_RDI_SRC 0x04
/* RX data interrupt */
#define SC16IS7XX_IIR_RLSE_SRC 0x06
/* RX line status error */
#define SC16IS7XX_IIR_RTOI_SRC 0x0c
/* RX time-out interrupt */
#define SC16IS7XX_IIR_MSI_SRC 0x00
/* Modem status interrupt
* - only on 75x/76x
*/
#define SC16IS7XX_IIR_INPIN_SRC 0x30
/* Input pin change of state
* - only on 75x/76x
*/
#define SC16IS7XX_IIR_XOFFI_SRC 0x10
/* Received Xoff */
#define SC16IS7XX_IIR_CTSRTS_SRC 0x20
/* nCTS,nRTS change of state
* from active (LOW)
* to inactive (HIGH)
*/
/* LCR register bits */
#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0)
/* Word length bit 0 */
#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1)
/* Word length bit 1
*
* Word length bits table:
* 00 -> 5 bit words
* 01 -> 6 bit words
* 10 -> 7 bit words
* 11 -> 8 bit words
*/
#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2)
/* STOP length bit
*
* STOP length bit table:
* 0 -> 1 stop bit
* 1 -> 1-1.5 stop bits if
* word length is 5,
* 2 stop bits otherwise
*/
#define SC16IS7XX_LCR_PARITY_BIT (1 << 3)
/* Parity bit enable */
#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4)
/* Even parity bit enable */
#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5)
/* 9-bit multidrop parity */
#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6)
/* TX break enable */
#define SC16IS7XX_LCR_DLAB_BIT (1 << 7)
/* Divisor Latch enable */
#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT
/* Special
* reg set */
#define SC16IS7XX_LCR_CONF_MODE_B 0xBF
/* Enhanced
* reg set */
/* MCR register bits */
#define SC16IS7XX_MCR_DTR_BIT (1 << 0)
/* DTR complement
* - only on 75x/76x
*/
#define SC16IS7XX_MCR_RTS_BIT (1 << 1)
/* RTS complement */
#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2)
/* TCR/TLR register enable */
#define SC16IS7XX_MCR_LOOP_BIT (1 << 4)
/* Enable loopback test mode */
#define SC16IS7XX_MCR_XONANY_BIT (1 << 5)
/* Enable Xon Any
* - write enabled
* if (EFR[4] == 1)
*/
#define SC16IS7XX_MCR_IRDA_BIT (1 << 6)
/* Enable IrDA mode
* - write enabled
* if (EFR[4] == 1)
*/
#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7)
/* Divide clock by 4
* - write enabled
* if (EFR[4] == 1)
*/
/* LSR register bits */
#define SC16IS7XX_LSR_DR_BIT (1 << 0)
/* Receiver data ready */
#define SC16IS7XX_LSR_OE_BIT (1 << 1)
/* Overrun Error */
#define SC16IS7XX_LSR_PE_BIT (1 << 2)
/* Parity Error */
#define SC16IS7XX_LSR_FE_BIT (1 << 3)
/* Frame Error */
#define SC16IS7XX_LSR_BI_BIT (1 << 4)
/* Break Interrupt */
#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E
/* BI, FE, PE, OE bits */
#define SC16IS7XX_LSR_THRE_BIT (1 << 5)
/* TX holding register empty */
#define SC16IS7XX_LSR_TEMT_BIT (1 << 6)
/* Transmitter empty */
#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7)
/* Fifo Error */
/* MSR register bits */
#define SC16IS7XX_MSR_DCTS_BIT (1 << 0)
/* Delta CTS Clear To Send */
#define SC16IS7XX_MSR_DDSR_BIT (1 << 1)
/* Delta DSR Data Set Ready
* or (IO4)
* - only on 75x/76x
*/
#define SC16IS7XX_MSR_DRI_BIT (1 << 2)
/* Delta RI Ring Indicator
* or (IO7)
* - only on 75x/76x
*/
#define SC16IS7XX_MSR_DCD_BIT (1 << 3)
/* Delta CD Carrier Detect
* or (IO6)
* - only on 75x/76x
*/
#define SC16IS7XX_MSR_CTS_BIT (1 << 0)
/* CTS */
#define SC16IS7XX_MSR_DSR_BIT (1 << 1)
/* DSR (IO4)
* - only on 75x/76x
*/
#define SC16IS7XX_MSR_RI_BIT (1 << 2)
/* RI (IO7)
* - only on 75x/76x
*/
#define SC16IS7XX_MSR_CD_BIT (1 << 3)
/* CD (IO6)
* - only on 75x/76x
*/
#define SC16IS7XX_MSR_DELTA_MASK 0x0F
/* Any of the delta bits! */
/*
* TCR register bits
* TCR trigger levels are available from 0 to 60 characters with a granularity
* of four.
* The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
* no built-in hardware check to make sure this condition is met. Also, the TCR
* must be programmed with this condition before auto RTS or software flow
* control is enabled to avoid spurious operation of the device.
*/
#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
/*
* TLR register bits
* If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
* FIFO Control Register (FCR) are used for the transmit and receive FIFO
* trigger levels. Trigger levels from 4 characters to 60 characters are
* available with a granularity of four.
*
* When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
* trigger level setting defined in FCR. If TLR has non-zero trigger level value
* the trigger level defined in FCR is discarded. This applies to both transmit
* FIFO and receive FIFO trigger level setting.
*
* When TLR is used for RX trigger level control, FCR[7:6] should be left at the
* default state, that is, '00'.
*/
#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
/* IOControl register bits (Only 750/760) */
#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0)
/* Enable input latching */
#define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1)
/* Enable GPIO[7:4] */
#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3)
/* Software Reset */
/* EFCR register bits */
#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0)
/* Enable 9-bit or Multidrop
* mode (RS485) */
#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1)
/* Disable receiver */
#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2)
/* Disable transmitter */
#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4)
/* Auto RS485 RTS direction */
#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5)
/* RTS output inversion */
#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7)
/* IrDA mode
* 0 = rate upto 115.2 kbit/s
* - Only 750/760
* 1 = rate upto 1.152 Mbit/s
* - Only 760
*/
/* EFR register bits */
#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6)
/* Auto RTS flow ctrl enable */
#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7)
/* Auto CTS flow ctrl enable */
#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5)
/* Enable Xoff2 detection */
#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4)
/* Enable enhanced functions
* and writing to IER[7:4],
* FCR[5:4], MCR[7:5]
*/
#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3)
/* SWFLOW bit 3 */
#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2)
/* SWFLOW bit 2
*
* SWFLOW bits 3 & 2 table:
* 00 -> no transmitter flow
* control
* 01 -> transmitter generates
* XON2 and XOFF2
* 10 -> transmitter generates
* XON1 and XOFF1
* 11 -> transmitter generates
* XON1, XON2, XOFF1 and
* XOFF2
*/
#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1)
/* SWFLOW bit 2 */
#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0)
/* SWFLOW bit 3
*
* SWFLOW bits 3 & 2 table:
* 00 -> no received flow
* control
* 01 -> receiver compares
* XON2 and XOFF2
* 10 -> receiver compares
* XON1 and XOFF1
* 11 -> receiver compares
* XON1, XON2, XOFF1 and
* XOFF2
*/
/* Misc definitions */
#define SC16IS7XX_FIFO_SIZE (64)
#define SC16IS7XX_REG_SHIFT 2
struct
sc16is7xx_devtype
{
char
name
[
10
];
int
nr_gpio
;
int
nr_uart
;
};
struct
sc16is7xx_one
{
struct
uart_port
port
;
struct
work_struct
tx_work
;
struct
work_struct
md_work
;
struct
serial_rs485
rs485
;
};
struct
sc16is7xx_port
{
struct
uart_driver
uart
;
struct
sc16is7xx_devtype
*
devtype
;
struct
regmap
*
regmap
;
struct
mutex
mutex
;
struct
clk
*
clk
;
#ifdef CONFIG_GPIOLIB
struct
gpio_chip
gpio
;
#endif
struct
sc16is7xx_one
p
[
0
];
};
#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
static
u8
sc16is7xx_port_read
(
struct
uart_port
*
port
,
u8
reg
)
{
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
port
->
dev
);
unsigned
int
val
=
0
;
regmap_read
(
s
->
regmap
,
(
reg
<<
SC16IS7XX_REG_SHIFT
)
|
port
->
line
,
&
val
);
return
val
;
}
static
void
sc16is7xx_port_write
(
struct
uart_port
*
port
,
u8
reg
,
u8
val
)
{
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
port
->
dev
);
regmap_write
(
s
->
regmap
,
(
reg
<<
SC16IS7XX_REG_SHIFT
)
|
port
->
line
,
val
);
}
static
void
sc16is7xx_port_update
(
struct
uart_port
*
port
,
u8
reg
,
u8
mask
,
u8
val
)
{
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
port
->
dev
);
regmap_update_bits
(
s
->
regmap
,
(
reg
<<
SC16IS7XX_REG_SHIFT
)
|
port
->
line
,
mask
,
val
);
}
static
void
sc16is7xx_power
(
struct
uart_port
*
port
,
int
on
)
{
sc16is7xx_port_update
(
port
,
SC16IS7XX_IER_REG
,
SC16IS7XX_IER_SLEEP_BIT
,
on
?
0
:
SC16IS7XX_IER_SLEEP_BIT
);
}
static
const
struct
sc16is7xx_devtype
sc16is74x_devtype
=
{
.
name
=
"SC16IS74X"
,
.
nr_gpio
=
0
,
.
nr_uart
=
1
,
};
static
const
struct
sc16is7xx_devtype
sc16is750_devtype
=
{
.
name
=
"SC16IS750"
,
.
nr_gpio
=
8
,
.
nr_uart
=
1
,
};
static
const
struct
sc16is7xx_devtype
sc16is752_devtype
=
{
.
name
=
"SC16IS752"
,
.
nr_gpio
=
8
,
.
nr_uart
=
2
,
};
static
const
struct
sc16is7xx_devtype
sc16is760_devtype
=
{
.
name
=
"SC16IS760"
,
.
nr_gpio
=
8
,
.
nr_uart
=
1
,
};
static
const
struct
sc16is7xx_devtype
sc16is762_devtype
=
{
.
name
=
"SC16IS762"
,
.
nr_gpio
=
8
,
.
nr_uart
=
2
,
};
static
bool
sc16is7xx_regmap_volatile
(
struct
device
*
dev
,
unsigned
int
reg
)
{
switch
(
reg
>>
SC16IS7XX_REG_SHIFT
)
{
case
SC16IS7XX_RHR_REG
:
case
SC16IS7XX_IIR_REG
:
case
SC16IS7XX_LSR_REG
:
case
SC16IS7XX_MSR_REG
:
case
SC16IS7XX_TXLVL_REG
:
case
SC16IS7XX_RXLVL_REG
:
case
SC16IS7XX_IOSTATE_REG
:
return
true
;
default:
break
;
}
return
false
;
}
static
bool
sc16is7xx_regmap_precious
(
struct
device
*
dev
,
unsigned
int
reg
)
{
switch
(
reg
>>
SC16IS7XX_REG_SHIFT
)
{
case
SC16IS7XX_RHR_REG
:
return
true
;
default:
break
;
}
return
false
;
}
static
int
sc16is7xx_set_baud
(
struct
uart_port
*
port
,
int
baud
)
{
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
port
->
dev
);
u8
lcr
;
u8
prescaler
=
0
;
unsigned
long
clk
=
port
->
uartclk
,
div
=
clk
/
16
/
baud
;
if
(
div
>
0xffff
)
{
prescaler
=
SC16IS7XX_MCR_CLKSEL_BIT
;
div
/=
4
;
}
lcr
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_LCR_REG
);
/* Open the LCR divisors for configuration */
sc16is7xx_port_write
(
port
,
SC16IS7XX_LCR_REG
,
SC16IS7XX_LCR_CONF_MODE_B
);
/* Enable enhanced features */
regcache_cache_bypass
(
s
->
regmap
,
true
);
sc16is7xx_port_write
(
port
,
SC16IS7XX_EFR_REG
,
SC16IS7XX_EFR_ENABLE_BIT
);
regcache_cache_bypass
(
s
->
regmap
,
false
);
/* Put LCR back to the normal mode */
sc16is7xx_port_write
(
port
,
SC16IS7XX_LCR_REG
,
lcr
);
sc16is7xx_port_update
(
port
,
SC16IS7XX_MCR_REG
,
SC16IS7XX_MCR_CLKSEL_BIT
,
prescaler
);
/* Open the LCR divisors for configuration */
sc16is7xx_port_write
(
port
,
SC16IS7XX_LCR_REG
,
SC16IS7XX_LCR_CONF_MODE_A
);
/* Write the new divisor */
regcache_cache_bypass
(
s
->
regmap
,
true
);
sc16is7xx_port_write
(
port
,
SC16IS7XX_DLH_REG
,
div
/
256
);
sc16is7xx_port_write
(
port
,
SC16IS7XX_DLL_REG
,
div
%
256
);
regcache_cache_bypass
(
s
->
regmap
,
false
);
/* Put LCR back to the normal mode */
sc16is7xx_port_write
(
port
,
SC16IS7XX_LCR_REG
,
lcr
);
return
DIV_ROUND_CLOSEST
(
clk
/
16
,
div
);
}
static
void
sc16is7xx_handle_rx
(
struct
uart_port
*
port
,
unsigned
int
rxlen
,
unsigned
int
iir
)
{
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
port
->
dev
);
unsigned
int
lsr
=
0
,
ch
,
flag
,
bytes_read
,
i
;
u8
buf
[
port
->
fifosize
];
bool
read_lsr
=
(
iir
==
SC16IS7XX_IIR_RLSE_SRC
)
?
true
:
false
;
if
(
unlikely
(
rxlen
>=
port
->
fifosize
))
{
dev_warn_ratelimited
(
port
->
dev
,
"Port %i: Possible RX FIFO overrun: %d
\n
"
,
port
->
line
,
rxlen
);
port
->
icount
.
buf_overrun
++
;
/* Ensure sanity of RX level */
rxlen
=
port
->
fifosize
;
}
while
(
rxlen
)
{
/* Only read lsr if there are possible errors in FIFO */
if
(
read_lsr
)
{
lsr
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_LSR_REG
);
if
(
!
(
lsr
&
SC16IS7XX_LSR_FIFOE_BIT
))
read_lsr
=
false
;
/* No errors left in FIFO */
}
else
lsr
=
0
;
if
(
read_lsr
)
{
buf
[
0
]
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_RHR_REG
);
bytes_read
=
1
;
}
else
{
regcache_cache_bypass
(
s
->
regmap
,
true
);
regmap_raw_read
(
s
->
regmap
,
SC16IS7XX_RHR_REG
,
buf
,
rxlen
);
regcache_cache_bypass
(
s
->
regmap
,
false
);
bytes_read
=
rxlen
;
}
lsr
&=
SC16IS7XX_LSR_BRK_ERROR_MASK
;
port
->
icount
.
rx
++
;
flag
=
TTY_NORMAL
;
if
(
unlikely
(
lsr
))
{
if
(
lsr
&
SC16IS7XX_LSR_BI_BIT
)
{
port
->
icount
.
brk
++
;
if
(
uart_handle_break
(
port
))
continue
;
}
else
if
(
lsr
&
SC16IS7XX_LSR_PE_BIT
)
port
->
icount
.
parity
++
;
else
if
(
lsr
&
SC16IS7XX_LSR_FE_BIT
)
port
->
icount
.
frame
++
;
else
if
(
lsr
&
SC16IS7XX_LSR_OE_BIT
)
port
->
icount
.
overrun
++
;
lsr
&=
port
->
read_status_mask
;
if
(
lsr
&
SC16IS7XX_LSR_BI_BIT
)
flag
=
TTY_BREAK
;
else
if
(
lsr
&
SC16IS7XX_LSR_PE_BIT
)
flag
=
TTY_PARITY
;
else
if
(
lsr
&
SC16IS7XX_LSR_FE_BIT
)
flag
=
TTY_FRAME
;
else
if
(
lsr
&
SC16IS7XX_LSR_OE_BIT
)
flag
=
TTY_OVERRUN
;
}
for
(
i
=
0
;
i
<
bytes_read
;
++
i
)
{
ch
=
buf
[
i
];
if
(
uart_handle_sysrq_char
(
port
,
ch
))
continue
;
if
(
lsr
&
port
->
ignore_status_mask
)
continue
;
uart_insert_char
(
port
,
lsr
,
SC16IS7XX_LSR_OE_BIT
,
ch
,
flag
);
}
rxlen
-=
bytes_read
;
}
tty_flip_buffer_push
(
&
port
->
state
->
port
);
}
static
void
sc16is7xx_handle_tx
(
struct
uart_port
*
port
)
{
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
port
->
dev
);
struct
circ_buf
*
xmit
=
&
port
->
state
->
xmit
;
unsigned
int
txlen
,
to_send
,
i
;
u8
buf
[
port
->
fifosize
];
if
(
unlikely
(
port
->
x_char
))
{
sc16is7xx_port_write
(
port
,
SC16IS7XX_THR_REG
,
port
->
x_char
);
port
->
icount
.
tx
++
;
port
->
x_char
=
0
;
return
;
}
if
(
uart_circ_empty
(
xmit
)
||
uart_tx_stopped
(
port
))
return
;
/* Get length of data pending in circular buffer */
to_send
=
uart_circ_chars_pending
(
xmit
);
if
(
likely
(
to_send
))
{
/* Limit to size of TX FIFO */
txlen
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_TXLVL_REG
);
to_send
=
(
to_send
>
txlen
)
?
txlen
:
to_send
;
/* Add data to send */
port
->
icount
.
tx
+=
to_send
;
/* Convert to linear buffer */
for
(
i
=
0
;
i
<
to_send
;
++
i
)
{
buf
[
i
]
=
xmit
->
buf
[
xmit
->
tail
];
xmit
->
tail
=
(
xmit
->
tail
+
1
)
&
(
UART_XMIT_SIZE
-
1
);
}
regcache_cache_bypass
(
s
->
regmap
,
true
);
regmap_raw_write
(
s
->
regmap
,
SC16IS7XX_THR_REG
,
buf
,
to_send
);
regcache_cache_bypass
(
s
->
regmap
,
false
);
}
if
(
uart_circ_chars_pending
(
xmit
)
<
WAKEUP_CHARS
)
uart_write_wakeup
(
port
);
}
static
void
sc16is7xx_port_irq
(
struct
sc16is7xx_port
*
s
,
int
portno
)
{
struct
uart_port
*
port
=
&
s
->
p
[
portno
].
port
;
do
{
unsigned
int
iir
,
msr
,
rxlen
;
iir
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_IIR_REG
);
if
(
iir
&
SC16IS7XX_IIR_NO_INT_BIT
)
break
;
iir
&=
SC16IS7XX_IIR_ID_MASK
;
switch
(
iir
)
{
case
SC16IS7XX_IIR_RDI_SRC
:
case
SC16IS7XX_IIR_RLSE_SRC
:
case
SC16IS7XX_IIR_RTOI_SRC
:
case
SC16IS7XX_IIR_XOFFI_SRC
:
rxlen
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_RXLVL_REG
);
if
(
rxlen
)
sc16is7xx_handle_rx
(
port
,
rxlen
,
iir
);
break
;
case
SC16IS7XX_IIR_CTSRTS_SRC
:
msr
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_MSR_REG
);
uart_handle_cts_change
(
port
,
!!
(
msr
&
SC16IS7XX_MSR_CTS_BIT
));
break
;
case
SC16IS7XX_IIR_THRI_SRC
:
mutex_lock
(
&
s
->
mutex
);
sc16is7xx_handle_tx
(
port
);
mutex_unlock
(
&
s
->
mutex
);
break
;
default:
dev_err_ratelimited
(
port
->
dev
,
"Port %i: Unexpected interrupt: %x"
,
port
->
line
,
iir
);
break
;
}
}
while
(
1
);
}
static
irqreturn_t
sc16is7xx_ist
(
int
irq
,
void
*
dev_id
)
{
struct
sc16is7xx_port
*
s
=
(
struct
sc16is7xx_port
*
)
dev_id
;
int
i
;
for
(
i
=
0
;
i
<
s
->
uart
.
nr
;
++
i
)
sc16is7xx_port_irq
(
s
,
i
);
return
IRQ_HANDLED
;
}
static
void
sc16is7xx_wq_proc
(
struct
work_struct
*
ws
)
{
struct
sc16is7xx_one
*
one
=
to_sc16is7xx_one
(
ws
,
tx_work
);
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
one
->
port
.
dev
);
mutex_lock
(
&
s
->
mutex
);
sc16is7xx_handle_tx
(
&
one
->
port
);
mutex_unlock
(
&
s
->
mutex
);
}
static
void
sc16is7xx_stop_tx
(
struct
uart_port
*
port
)
{
struct
sc16is7xx_one
*
one
=
to_sc16is7xx_one
(
port
,
port
);
struct
circ_buf
*
xmit
=
&
one
->
port
.
state
->
xmit
;
/* handle rs485 */
if
(
one
->
rs485
.
flags
&
SER_RS485_ENABLED
)
{
/* do nothing if current tx not yet completed */
int
lsr
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_LSR_REG
);
if
(
!
(
lsr
&
SC16IS7XX_LSR_TEMT_BIT
))
return
;
if
(
uart_circ_empty
(
xmit
)
&&
(
one
->
rs485
.
delay_rts_after_send
>
0
))
mdelay
(
one
->
rs485
.
delay_rts_after_send
);
}
sc16is7xx_port_update
(
port
,
SC16IS7XX_IER_REG
,
SC16IS7XX_IER_THRI_BIT
,
0
);
}
static
void
sc16is7xx_stop_rx
(
struct
uart_port
*
port
)
{
struct
sc16is7xx_one
*
one
=
to_sc16is7xx_one
(
port
,
port
);
one
->
port
.
read_status_mask
&=
~
SC16IS7XX_LSR_DR_BIT
;
sc16is7xx_port_update
(
port
,
SC16IS7XX_IER_REG
,
SC16IS7XX_LSR_DR_BIT
,
0
);
}
static
void
sc16is7xx_start_tx
(
struct
uart_port
*
port
)
{
struct
sc16is7xx_one
*
one
=
to_sc16is7xx_one
(
port
,
port
);
/* handle rs485 */
if
((
one
->
rs485
.
flags
&
SER_RS485_ENABLED
)
&&
(
one
->
rs485
.
delay_rts_before_send
>
0
))
{
mdelay
(
one
->
rs485
.
delay_rts_before_send
);
}
if
(
!
work_pending
(
&
one
->
tx_work
))
schedule_work
(
&
one
->
tx_work
);
}
static
unsigned
int
sc16is7xx_tx_empty
(
struct
uart_port
*
port
)
{
unsigned
int
lvl
,
lsr
;
lvl
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_TXLVL_REG
);
lsr
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_LSR_REG
);
return
((
lsr
&
SC16IS7XX_LSR_THRE_BIT
)
&&
!
lvl
)
?
TIOCSER_TEMT
:
0
;
}
static
unsigned
int
sc16is7xx_get_mctrl
(
struct
uart_port
*
port
)
{
/* DCD and DSR are not wired and CTS/RTS is handled automatically
* so just indicate DSR and CAR asserted
*/
return
TIOCM_DSR
|
TIOCM_CAR
;
}
static
void
sc16is7xx_md_proc
(
struct
work_struct
*
ws
)
{
struct
sc16is7xx_one
*
one
=
to_sc16is7xx_one
(
ws
,
md_work
);
sc16is7xx_port_update
(
&
one
->
port
,
SC16IS7XX_MCR_REG
,
SC16IS7XX_MCR_LOOP_BIT
,
(
one
->
port
.
mctrl
&
TIOCM_LOOP
)
?
SC16IS7XX_MCR_LOOP_BIT
:
0
);
}
static
void
sc16is7xx_set_mctrl
(
struct
uart_port
*
port
,
unsigned
int
mctrl
)
{
struct
sc16is7xx_one
*
one
=
to_sc16is7xx_one
(
port
,
port
);
schedule_work
(
&
one
->
md_work
);
}
static
void
sc16is7xx_break_ctl
(
struct
uart_port
*
port
,
int
break_state
)
{
sc16is7xx_port_update
(
port
,
SC16IS7XX_LCR_REG
,
SC16IS7XX_LCR_TXBREAK_BIT
,
break_state
?
SC16IS7XX_LCR_TXBREAK_BIT
:
0
);
}
static
void
sc16is7xx_set_termios
(
struct
uart_port
*
port
,
struct
ktermios
*
termios
,
struct
ktermios
*
old
)
{
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
port
->
dev
);
unsigned
int
lcr
,
flow
=
0
;
int
baud
;
/* Mask termios capabilities we don't support */
termios
->
c_cflag
&=
~
CMSPAR
;
/* Word size */
switch
(
termios
->
c_cflag
&
CSIZE
)
{
case
CS5
:
lcr
=
SC16IS7XX_LCR_WORD_LEN_5
;
break
;
case
CS6
:
lcr
=
SC16IS7XX_LCR_WORD_LEN_6
;
break
;
case
CS7
:
lcr
=
SC16IS7XX_LCR_WORD_LEN_7
;
break
;
case
CS8
:
lcr
=
SC16IS7XX_LCR_WORD_LEN_8
;
break
;
default:
lcr
=
SC16IS7XX_LCR_WORD_LEN_8
;
termios
->
c_cflag
&=
~
CSIZE
;
termios
->
c_cflag
|=
CS8
;
break
;
}
/* Parity */
if
(
termios
->
c_cflag
&
PARENB
)
{
lcr
|=
SC16IS7XX_LCR_PARITY_BIT
;
if
(
!
(
termios
->
c_cflag
&
PARODD
))
lcr
|=
SC16IS7XX_LCR_EVENPARITY_BIT
;
}
/* Stop bits */
if
(
termios
->
c_cflag
&
CSTOPB
)
lcr
|=
SC16IS7XX_LCR_STOPLEN_BIT
;
/* 2 stops */
/* Set read status mask */
port
->
read_status_mask
=
SC16IS7XX_LSR_OE_BIT
;
if
(
termios
->
c_iflag
&
INPCK
)
port
->
read_status_mask
|=
SC16IS7XX_LSR_PE_BIT
|
SC16IS7XX_LSR_FE_BIT
;
if
(
termios
->
c_iflag
&
(
BRKINT
|
PARMRK
))
port
->
read_status_mask
|=
SC16IS7XX_LSR_BI_BIT
;
/* Set status ignore mask */
port
->
ignore_status_mask
=
0
;
if
(
termios
->
c_iflag
&
IGNBRK
)
port
->
ignore_status_mask
|=
SC16IS7XX_LSR_BI_BIT
;
if
(
!
(
termios
->
c_cflag
&
CREAD
))
port
->
ignore_status_mask
|=
SC16IS7XX_LSR_BRK_ERROR_MASK
;
sc16is7xx_port_write
(
port
,
SC16IS7XX_LCR_REG
,
SC16IS7XX_LCR_CONF_MODE_B
);
/* Configure flow control */
regcache_cache_bypass
(
s
->
regmap
,
true
);
sc16is7xx_port_write
(
port
,
SC16IS7XX_XON1_REG
,
termios
->
c_cc
[
VSTART
]);
sc16is7xx_port_write
(
port
,
SC16IS7XX_XOFF1_REG
,
termios
->
c_cc
[
VSTOP
]);
if
(
termios
->
c_cflag
&
CRTSCTS
)
flow
|=
SC16IS7XX_EFR_AUTOCTS_BIT
|
SC16IS7XX_EFR_AUTORTS_BIT
;
if
(
termios
->
c_iflag
&
IXON
)
flow
|=
SC16IS7XX_EFR_SWFLOW3_BIT
;
if
(
termios
->
c_iflag
&
IXOFF
)
flow
|=
SC16IS7XX_EFR_SWFLOW1_BIT
;
sc16is7xx_port_write
(
port
,
SC16IS7XX_EFR_REG
,
flow
);
regcache_cache_bypass
(
s
->
regmap
,
false
);
/* Update LCR register */
sc16is7xx_port_write
(
port
,
SC16IS7XX_LCR_REG
,
lcr
);
/* Get baud rate generator configuration */
baud
=
uart_get_baud_rate
(
port
,
termios
,
old
,
port
->
uartclk
/
16
/
4
/
0xffff
,
port
->
uartclk
/
16
);
/* Setup baudrate generator */
baud
=
sc16is7xx_set_baud
(
port
,
baud
);
/* Update timeout according to new baud rate */
uart_update_timeout
(
port
,
termios
->
c_cflag
,
baud
);
}
#if defined(TIOCSRS485) && defined(TIOCGRS485)
static
void
sc16is7xx_config_rs485
(
struct
uart_port
*
port
,
struct
serial_rs485
*
rs485
)
{
struct
sc16is7xx_one
*
one
=
to_sc16is7xx_one
(
port
,
port
);
one
->
rs485
=
*
rs485
;
if
(
one
->
rs485
.
flags
&
SER_RS485_ENABLED
)
{
sc16is7xx_port_update
(
port
,
SC16IS7XX_EFCR_REG
,
SC16IS7XX_EFCR_AUTO_RS485_BIT
,
SC16IS7XX_EFCR_AUTO_RS485_BIT
);
}
else
{
sc16is7xx_port_update
(
port
,
SC16IS7XX_EFCR_REG
,
SC16IS7XX_EFCR_AUTO_RS485_BIT
,
0
);
}
}
#endif
static
int
sc16is7xx_ioctl
(
struct
uart_port
*
port
,
unsigned
int
cmd
,
unsigned
long
arg
)
{
#if defined(TIOCSRS485) && defined(TIOCGRS485)
struct
serial_rs485
rs485
;
switch
(
cmd
)
{
case
TIOCSRS485
:
if
(
copy_from_user
(
&
rs485
,
(
void
__user
*
)
arg
,
sizeof
(
rs485
)))
return
-
EFAULT
;
sc16is7xx_config_rs485
(
port
,
&
rs485
);
return
0
;
case
TIOCGRS485
:
if
(
copy_to_user
((
void
__user
*
)
arg
,
&
(
to_sc16is7xx_one
(
port
,
port
)
->
rs485
),
sizeof
(
rs485
)))
return
-
EFAULT
;
return
0
;
default:
break
;
}
#endif
return
-
ENOIOCTLCMD
;
}
static
int
sc16is7xx_startup
(
struct
uart_port
*
port
)
{
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
port
->
dev
);
unsigned
int
val
;
sc16is7xx_power
(
port
,
1
);
/* Reset FIFOs*/
val
=
SC16IS7XX_FCR_RXRESET_BIT
|
SC16IS7XX_FCR_TXRESET_BIT
;
sc16is7xx_port_write
(
port
,
SC16IS7XX_FCR_REG
,
val
);
udelay
(
5
);
sc16is7xx_port_write
(
port
,
SC16IS7XX_FCR_REG
,
SC16IS7XX_FCR_FIFO_BIT
);
/* Enable EFR */
sc16is7xx_port_write
(
port
,
SC16IS7XX_LCR_REG
,
SC16IS7XX_LCR_CONF_MODE_B
);
regcache_cache_bypass
(
s
->
regmap
,
true
);
/* Enable write access to enhanced features and internal clock div */
sc16is7xx_port_write
(
port
,
SC16IS7XX_EFR_REG
,
SC16IS7XX_EFR_ENABLE_BIT
);
/* Enable TCR/TLR */
sc16is7xx_port_update
(
port
,
SC16IS7XX_MCR_REG
,
SC16IS7XX_MCR_TCRTLR_BIT
,
SC16IS7XX_MCR_TCRTLR_BIT
);
/* Configure flow control levels */
/* Flow control halt level 48, resume level 24 */
sc16is7xx_port_write
(
port
,
SC16IS7XX_TCR_REG
,
SC16IS7XX_TCR_RX_RESUME
(
24
)
|
SC16IS7XX_TCR_RX_HALT
(
48
));
regcache_cache_bypass
(
s
->
regmap
,
false
);
/* Now, initialize the UART */
sc16is7xx_port_write
(
port
,
SC16IS7XX_LCR_REG
,
SC16IS7XX_LCR_WORD_LEN_8
);
/* Enable the Rx and Tx FIFO */
sc16is7xx_port_update
(
port
,
SC16IS7XX_EFCR_REG
,
SC16IS7XX_EFCR_RXDISABLE_BIT
|
SC16IS7XX_EFCR_TXDISABLE_BIT
,
0
);
/* Enable RX, TX, CTS change interrupts */
val
=
SC16IS7XX_IER_RDI_BIT
|
SC16IS7XX_IER_THRI_BIT
|
SC16IS7XX_IER_CTSI_BIT
;
sc16is7xx_port_write
(
port
,
SC16IS7XX_IER_REG
,
val
);
return
0
;
}
static
void
sc16is7xx_shutdown
(
struct
uart_port
*
port
)
{
/* Disable all interrupts */
sc16is7xx_port_write
(
port
,
SC16IS7XX_IER_REG
,
0
);
/* Disable TX/RX */
sc16is7xx_port_write
(
port
,
SC16IS7XX_EFCR_REG
,
SC16IS7XX_EFCR_RXDISABLE_BIT
|
SC16IS7XX_EFCR_TXDISABLE_BIT
);
sc16is7xx_power
(
port
,
0
);
}
static
const
char
*
sc16is7xx_type
(
struct
uart_port
*
port
)
{
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
port
->
dev
);
return
(
port
->
type
==
PORT_SC16IS7XX
)
?
s
->
devtype
->
name
:
NULL
;
}
static
int
sc16is7xx_request_port
(
struct
uart_port
*
port
)
{
/* Do nothing */
return
0
;
}
static
void
sc16is7xx_config_port
(
struct
uart_port
*
port
,
int
flags
)
{
if
(
flags
&
UART_CONFIG_TYPE
)
port
->
type
=
PORT_SC16IS7XX
;
}
static
int
sc16is7xx_verify_port
(
struct
uart_port
*
port
,
struct
serial_struct
*
s
)
{
if
((
s
->
type
!=
PORT_UNKNOWN
)
&&
(
s
->
type
!=
PORT_SC16IS7XX
))
return
-
EINVAL
;
if
(
s
->
irq
!=
port
->
irq
)
return
-
EINVAL
;
return
0
;
}
static
void
sc16is7xx_pm
(
struct
uart_port
*
port
,
unsigned
int
state
,
unsigned
int
oldstate
)
{
sc16is7xx_power
(
port
,
(
state
==
UART_PM_STATE_ON
)
?
1
:
0
);
}
static
void
sc16is7xx_null_void
(
struct
uart_port
*
port
)
{
/* Do nothing */
}
static
const
struct
uart_ops
sc16is7xx_ops
=
{
.
tx_empty
=
sc16is7xx_tx_empty
,
.
set_mctrl
=
sc16is7xx_set_mctrl
,
.
get_mctrl
=
sc16is7xx_get_mctrl
,
.
stop_tx
=
sc16is7xx_stop_tx
,
.
start_tx
=
sc16is7xx_start_tx
,
.
stop_rx
=
sc16is7xx_stop_rx
,
.
enable_ms
=
sc16is7xx_null_void
,
.
break_ctl
=
sc16is7xx_break_ctl
,
.
startup
=
sc16is7xx_startup
,
.
shutdown
=
sc16is7xx_shutdown
,
.
set_termios
=
sc16is7xx_set_termios
,
.
type
=
sc16is7xx_type
,
.
request_port
=
sc16is7xx_request_port
,
.
release_port
=
sc16is7xx_null_void
,
.
config_port
=
sc16is7xx_config_port
,
.
verify_port
=
sc16is7xx_verify_port
,
.
ioctl
=
sc16is7xx_ioctl
,
.
pm
=
sc16is7xx_pm
,
};
#ifdef CONFIG_GPIOLIB
static
int
sc16is7xx_gpio_get
(
struct
gpio_chip
*
chip
,
unsigned
offset
)
{
unsigned
int
val
;
struct
sc16is7xx_port
*
s
=
container_of
(
chip
,
struct
sc16is7xx_port
,
gpio
);
struct
uart_port
*
port
=
&
s
->
p
[
0
].
port
;
val
=
sc16is7xx_port_read
(
port
,
SC16IS7XX_IOSTATE_REG
);
return
!!
(
val
&
BIT
(
offset
));
}
static
void
sc16is7xx_gpio_set
(
struct
gpio_chip
*
chip
,
unsigned
offset
,
int
val
)
{
struct
sc16is7xx_port
*
s
=
container_of
(
chip
,
struct
sc16is7xx_port
,
gpio
);
struct
uart_port
*
port
=
&
s
->
p
[
0
].
port
;
sc16is7xx_port_update
(
port
,
SC16IS7XX_IOSTATE_REG
,
BIT
(
offset
),
val
?
BIT
(
offset
)
:
0
);
}
static
int
sc16is7xx_gpio_direction_input
(
struct
gpio_chip
*
chip
,
unsigned
offset
)
{
struct
sc16is7xx_port
*
s
=
container_of
(
chip
,
struct
sc16is7xx_port
,
gpio
);
struct
uart_port
*
port
=
&
s
->
p
[
0
].
port
;
sc16is7xx_port_update
(
port
,
SC16IS7XX_IODIR_REG
,
BIT
(
offset
),
0
);
return
0
;
}
static
int
sc16is7xx_gpio_direction_output
(
struct
gpio_chip
*
chip
,
unsigned
offset
,
int
val
)
{
struct
sc16is7xx_port
*
s
=
container_of
(
chip
,
struct
sc16is7xx_port
,
gpio
);
struct
uart_port
*
port
=
&
s
->
p
[
0
].
port
;
sc16is7xx_port_update
(
port
,
SC16IS7XX_IOSTATE_REG
,
BIT
(
offset
),
val
?
BIT
(
offset
)
:
0
);
sc16is7xx_port_update
(
port
,
SC16IS7XX_IODIR_REG
,
BIT
(
offset
),
BIT
(
offset
));
return
0
;
}
#endif
static
int
sc16is7xx_probe
(
struct
device
*
dev
,
struct
sc16is7xx_devtype
*
devtype
,
struct
regmap
*
regmap
,
int
irq
,
unsigned
long
flags
)
{
unsigned
long
freq
,
*
pfreq
=
dev_get_platdata
(
dev
);
struct
clk
*
clk
;
int
i
,
ret
;
struct
sc16is7xx_port
*
s
;
if
(
IS_ERR
(
regmap
))
return
PTR_ERR
(
regmap
);
/* Alloc port structure */
s
=
devm_kzalloc
(
dev
,
sizeof
(
*
s
)
+
sizeof
(
struct
sc16is7xx_one
)
*
devtype
->
nr_uart
,
GFP_KERNEL
);
if
(
!
s
)
{
dev_err
(
dev
,
"Error allocating port structure
\n
"
);
return
-
ENOMEM
;
}
clk
=
devm_clk_get
(
dev
,
NULL
);
if
(
IS_ERR
(
clk
))
{
if
(
pfreq
)
freq
=
*
pfreq
;
else
return
PTR_ERR
(
clk
);
}
else
{
freq
=
clk_get_rate
(
clk
);
}
s
->
regmap
=
regmap
;
s
->
devtype
=
devtype
;
dev_set_drvdata
(
dev
,
s
);
/* Register UART driver */
s
->
uart
.
owner
=
THIS_MODULE
;
s
->
uart
.
dev_name
=
"ttySC"
;
s
->
uart
.
nr
=
devtype
->
nr_uart
;
ret
=
uart_register_driver
(
&
s
->
uart
);
if
(
ret
)
{
dev_err
(
dev
,
"Registering UART driver failed
\n
"
);
goto
out_clk
;
}
#ifdef CONFIG_GPIOLIB
if
(
devtype
->
nr_gpio
)
{
/* Setup GPIO cotroller */
s
->
gpio
.
owner
=
THIS_MODULE
;
s
->
gpio
.
dev
=
dev
;
s
->
gpio
.
label
=
dev_name
(
dev
);
s
->
gpio
.
direction_input
=
sc16is7xx_gpio_direction_input
;
s
->
gpio
.
get
=
sc16is7xx_gpio_get
;
s
->
gpio
.
direction_output
=
sc16is7xx_gpio_direction_output
;
s
->
gpio
.
set
=
sc16is7xx_gpio_set
;
s
->
gpio
.
base
=
-
1
;
s
->
gpio
.
ngpio
=
devtype
->
nr_gpio
;
s
->
gpio
.
can_sleep
=
1
;
ret
=
gpiochip_add
(
&
s
->
gpio
);
if
(
ret
)
goto
out_uart
;
}
#endif
mutex_init
(
&
s
->
mutex
);
for
(
i
=
0
;
i
<
devtype
->
nr_uart
;
++
i
)
{
/* Initialize port data */
s
->
p
[
i
].
port
.
line
=
i
;
s
->
p
[
i
].
port
.
dev
=
dev
;
s
->
p
[
i
].
port
.
irq
=
irq
;
s
->
p
[
i
].
port
.
type
=
PORT_SC16IS7XX
;
s
->
p
[
i
].
port
.
fifosize
=
SC16IS7XX_FIFO_SIZE
;
s
->
p
[
i
].
port
.
flags
=
UPF_FIXED_TYPE
|
UPF_LOW_LATENCY
;
s
->
p
[
i
].
port
.
iotype
=
UPIO_PORT
;
s
->
p
[
i
].
port
.
uartclk
=
freq
;
s
->
p
[
i
].
port
.
ops
=
&
sc16is7xx_ops
;
/* Disable all interrupts */
sc16is7xx_port_write
(
&
s
->
p
[
i
].
port
,
SC16IS7XX_IER_REG
,
0
);
/* Disable TX/RX */
sc16is7xx_port_write
(
&
s
->
p
[
i
].
port
,
SC16IS7XX_EFCR_REG
,
SC16IS7XX_EFCR_RXDISABLE_BIT
|
SC16IS7XX_EFCR_TXDISABLE_BIT
);
/* Initialize queue for start TX */
INIT_WORK
(
&
s
->
p
[
i
].
tx_work
,
sc16is7xx_wq_proc
);
/* Initialize queue for changing mode */
INIT_WORK
(
&
s
->
p
[
i
].
md_work
,
sc16is7xx_md_proc
);
/* Register port */
uart_add_one_port
(
&
s
->
uart
,
&
s
->
p
[
i
].
port
);
/* Go to suspend mode */
sc16is7xx_power
(
&
s
->
p
[
i
].
port
,
0
);
}
/* Setup interrupt */
ret
=
devm_request_threaded_irq
(
dev
,
irq
,
NULL
,
sc16is7xx_ist
,
IRQF_ONESHOT
|
flags
,
dev_name
(
dev
),
s
);
if
(
!
ret
)
return
0
;
mutex_destroy
(
&
s
->
mutex
);
#ifdef CONFIG_GPIOLIB
if
(
devtype
->
nr_gpio
)
WARN_ON
(
gpiochip_remove
(
&
s
->
gpio
));
out_uart:
#endif
uart_unregister_driver
(
&
s
->
uart
);
out_clk:
if
(
!
IS_ERR
(
s
->
clk
))
clk_disable_unprepare
(
s
->
clk
);
return
ret
;
}
static
int
sc16is7xx_remove
(
struct
device
*
dev
)
{
struct
sc16is7xx_port
*
s
=
dev_get_drvdata
(
dev
);
int
i
,
ret
=
0
;
#ifdef CONFIG_GPIOLIB
if
(
s
->
devtype
->
nr_gpio
)
{
ret
=
gpiochip_remove
(
&
s
->
gpio
);
if
(
ret
)
return
ret
;
}
#endif
for
(
i
=
0
;
i
<
s
->
uart
.
nr
;
i
++
)
{
cancel_work_sync
(
&
s
->
p
[
i
].
tx_work
);
cancel_work_sync
(
&
s
->
p
[
i
].
md_work
);
uart_remove_one_port
(
&
s
->
uart
,
&
s
->
p
[
i
].
port
);
sc16is7xx_power
(
&
s
->
p
[
i
].
port
,
0
);
}
mutex_destroy
(
&
s
->
mutex
);
uart_unregister_driver
(
&
s
->
uart
);
if
(
!
IS_ERR
(
s
->
clk
))
clk_disable_unprepare
(
s
->
clk
);
return
ret
;
}
static
const
struct
of_device_id
__maybe_unused
sc16is7xx_dt_ids
[]
=
{
{
.
compatible
=
"nxp,sc16is740"
,
.
data
=
&
sc16is74x_devtype
,
},
{
.
compatible
=
"nxp,sc16is741"
,
.
data
=
&
sc16is74x_devtype
,
},
{
.
compatible
=
"nxp,sc16is750"
,
.
data
=
&
sc16is750_devtype
,
},
{
.
compatible
=
"nxp,sc16is752"
,
.
data
=
&
sc16is752_devtype
,
},
{
.
compatible
=
"nxp,sc16is760"
,
.
data
=
&
sc16is760_devtype
,
},
{
.
compatible
=
"nxp,sc16is762"
,
.
data
=
&
sc16is762_devtype
,
},
{
}
};
MODULE_DEVICE_TABLE
(
of
,
sc16is7xx_dt_ids
);
static
struct
regmap_config
regcfg
=
{
.
reg_bits
=
7
,
.
pad_bits
=
1
,
.
val_bits
=
8
,
.
cache_type
=
REGCACHE_RBTREE
,
.
volatile_reg
=
sc16is7xx_regmap_volatile
,
.
precious_reg
=
sc16is7xx_regmap_precious
,
};
#ifdef CONFIG_REGMAP_I2C
static
int
sc16is7xx_i2c_probe
(
struct
i2c_client
*
i2c
,
const
struct
i2c_device_id
*
id
)
{
struct
sc16is7xx_devtype
*
devtype
;
unsigned
long
flags
=
0
;
struct
regmap
*
regmap
;
if
(
i2c
->
dev
.
of_node
)
{
const
struct
of_device_id
*
of_id
=
of_match_device
(
sc16is7xx_dt_ids
,
&
i2c
->
dev
);
devtype
=
(
struct
sc16is7xx_devtype
*
)
of_id
->
data
;
}
else
{
devtype
=
(
struct
sc16is7xx_devtype
*
)
id
->
driver_data
;
flags
=
IRQF_TRIGGER_FALLING
;
}
regcfg
.
max_register
=
(
0xf
<<
SC16IS7XX_REG_SHIFT
)
|
(
devtype
->
nr_uart
-
1
);
regmap
=
devm_regmap_init_i2c
(
i2c
,
&
regcfg
);
return
sc16is7xx_probe
(
&
i2c
->
dev
,
devtype
,
regmap
,
i2c
->
irq
,
flags
);
}
static
int
sc16is7xx_i2c_remove
(
struct
i2c_client
*
client
)
{
return
sc16is7xx_remove
(
&
client
->
dev
);
}
static
const
struct
i2c_device_id
sc16is7xx_i2c_id_table
[]
=
{
{
"sc16is74x"
,
(
kernel_ulong_t
)
&
sc16is74x_devtype
,
},
{
"sc16is750"
,
(
kernel_ulong_t
)
&
sc16is750_devtype
,
},
{
"sc16is752"
,
(
kernel_ulong_t
)
&
sc16is752_devtype
,
},
{
"sc16is760"
,
(
kernel_ulong_t
)
&
sc16is760_devtype
,
},
{
"sc16is762"
,
(
kernel_ulong_t
)
&
sc16is762_devtype
,
},
{
}
};
MODULE_DEVICE_TABLE
(
i2c
,
sc16is7xx_i2c_id_table
);
static
struct
i2c_driver
sc16is7xx_i2c_uart_driver
=
{
.
driver
=
{
.
name
=
SC16IS7XX_NAME
,
.
owner
=
THIS_MODULE
,
.
of_match_table
=
of_match_ptr
(
sc16is7xx_dt_ids
),
},
.
probe
=
sc16is7xx_i2c_probe
,
.
remove
=
sc16is7xx_i2c_remove
,
.
id_table
=
sc16is7xx_i2c_id_table
,
};
module_i2c_driver
(
sc16is7xx_i2c_uart_driver
);
MODULE_ALIAS
(
"i2c:sc16is7xx"
);
#endif
MODULE_LICENSE
(
"GPL"
);
MODULE_AUTHOR
(
"Jon Ringle <jringle@gridpoint.com>"
);
MODULE_DESCRIPTION
(
"SC16IS7XX serial driver"
);
drivers/tty/serial/serial_core.c
View file @
728dd198
...
@@ -2239,6 +2239,9 @@ static void uart_poll_put_char(struct tty_driver *driver, int line, char ch)
...
@@ -2239,6 +2239,9 @@ static void uart_poll_put_char(struct tty_driver *driver, int line, char ch)
return
;
return
;
port
=
state
->
uart_port
;
port
=
state
->
uart_port
;
if
(
ch
==
'\n'
)
port
->
ops
->
poll_put_char
(
port
,
'\r'
);
port
->
ops
->
poll_put_char
(
port
,
ch
);
port
->
ops
->
poll_put_char
(
port
,
ch
);
}
}
#endif
#endif
...
...
drivers/tty/serial/serial_txx9.c
View file @
728dd198
...
@@ -535,13 +535,8 @@ static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c)
...
@@ -535,13 +535,8 @@ static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c)
wait_for_xmitr
(
up
);
wait_for_xmitr
(
up
);
/*
/*
* Send the character out.
* Send the character out.
* If a LF, also do CR...
*/
*/
sio_out
(
up
,
TXX9_SITFIFO
,
c
);
sio_out
(
up
,
TXX9_SITFIFO
,
c
);
if
(
c
==
10
)
{
wait_for_xmitr
(
up
);
sio_out
(
up
,
TXX9_SITFIFO
,
13
);
}
/*
/*
* Finally, wait for transmitter to become empty
* Finally, wait for transmitter to become empty
...
...
drivers/tty/serial/xilinx_uartps.c
View file @
728dd198
/*
/*
*
Xilinx PS UART driver
*
Cadence UART driver (found in Xilinx Zynq)
*
*
* 2011 - 201
3
(C) Xilinx Inc.
* 2011 - 201
4
(C) Xilinx Inc.
*
*
* This program is free software; you can redistribute it
* This program is free software; you can redistribute it
* and/or modify it under the terms of the GNU General Public
* and/or modify it under the terms of the GNU General Public
...
@@ -9,6 +9,9 @@
...
@@ -9,6 +9,9 @@
* either version 2 of the License, or (at your option) any
* either version 2 of the License, or (at your option) any
* later version.
* later version.
*
*
* This driver has originally been pushed by Xilinx using a Zynq-branding. This
* still shows in the naming of this file, the kconfig symbols and some symbols
* in the code.
*/
*/
#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
...
@@ -28,16 +31,16 @@
...
@@ -28,16 +31,16 @@
#include <linux/of.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/module.h>
#define
XUARTPS
_TTY_NAME "ttyPS"
#define
CDNS_UART
_TTY_NAME "ttyPS"
#define
XUARTPS
_NAME "xuartps"
#define
CDNS_UART
_NAME "xuartps"
#define
XUARTPS
_MAJOR 0
/* use dynamic node allocation */
#define
CDNS_UART
_MAJOR 0
/* use dynamic node allocation */
#define
XUARTPS
_MINOR 0
/* works best with devtmpfs */
#define
CDNS_UART
_MINOR 0
/* works best with devtmpfs */
#define
XUARTPS
_NR_PORTS 2
#define
CDNS_UART
_NR_PORTS 2
#define
XUARTPS
_FIFO_SIZE 64
/* FIFO size */
#define
CDNS_UART
_FIFO_SIZE 64
/* FIFO size */
#define
XUARTPS
_REGISTER_SPACE 0xFFF
#define
CDNS_UART
_REGISTER_SPACE 0xFFF
#define
xuartps
_readl(offset) ioread32(port->membase + offset)
#define
cdns_uart
_readl(offset) ioread32(port->membase + offset)
#define
xuartps
_writel(val, offset) iowrite32(val, port->membase + offset)
#define
cdns_uart
_writel(val, offset) iowrite32(val, port->membase + offset)
/* Rx Trigger level */
/* Rx Trigger level */
static
int
rx_trigger_level
=
56
;
static
int
rx_trigger_level
=
56
;
...
@@ -49,77 +52,62 @@ static int rx_timeout = 10;
...
@@ -49,77 +52,62 @@ static int rx_timeout = 10;
module_param
(
rx_timeout
,
uint
,
S_IRUGO
);
module_param
(
rx_timeout
,
uint
,
S_IRUGO
);
MODULE_PARM_DESC
(
rx_timeout
,
"Rx timeout, 1-255"
);
MODULE_PARM_DESC
(
rx_timeout
,
"Rx timeout, 1-255"
);
/********************************Register Map********************************/
/* Register offsets for the UART. */
/** UART
#define CDNS_UART_CR_OFFSET 0x00
/* Control Register */
*
#define CDNS_UART_MR_OFFSET 0x04
/* Mode Register */
* Register offsets for the UART.
#define CDNS_UART_IER_OFFSET 0x08
/* Interrupt Enable */
*
#define CDNS_UART_IDR_OFFSET 0x0C
/* Interrupt Disable */
*/
#define CDNS_UART_IMR_OFFSET 0x10
/* Interrupt Mask */
#define XUARTPS_CR_OFFSET 0x00
/* Control Register [8:0] */
#define CDNS_UART_ISR_OFFSET 0x14
/* Interrupt Status */
#define XUARTPS_MR_OFFSET 0x04
/* Mode Register [10:0] */
#define CDNS_UART_BAUDGEN_OFFSET 0x18
/* Baud Rate Generator */
#define XUARTPS_IER_OFFSET 0x08
/* Interrupt Enable [10:0] */
#define CDNS_UART_RXTOUT_OFFSET 0x1C
/* RX Timeout */
#define XUARTPS_IDR_OFFSET 0x0C
/* Interrupt Disable [10:0] */
#define CDNS_UART_RXWM_OFFSET 0x20
/* RX FIFO Trigger Level */
#define XUARTPS_IMR_OFFSET 0x10
/* Interrupt Mask [10:0] */
#define CDNS_UART_MODEMCR_OFFSET 0x24
/* Modem Control */
#define XUARTPS_ISR_OFFSET 0x14
/* Interrupt Status [10:0]*/
#define CDNS_UART_MODEMSR_OFFSET 0x28
/* Modem Status */
#define XUARTPS_BAUDGEN_OFFSET 0x18
/* Baud Rate Generator [15:0] */
#define CDNS_UART_SR_OFFSET 0x2C
/* Channel Status */
#define XUARTPS_RXTOUT_OFFSET 0x1C
/* RX Timeout [7:0] */
#define CDNS_UART_FIFO_OFFSET 0x30
/* FIFO */
#define XUARTPS_RXWM_OFFSET 0x20
/* RX FIFO Trigger Level [5:0] */
#define CDNS_UART_BAUDDIV_OFFSET 0x34
/* Baud Rate Divider */
#define XUARTPS_MODEMCR_OFFSET 0x24
/* Modem Control [5:0] */
#define CDNS_UART_FLOWDEL_OFFSET 0x38
/* Flow Delay */
#define XUARTPS_MODEMSR_OFFSET 0x28
/* Modem Status [8:0] */
#define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C
/* IR Min Received Pulse Width */
#define XUARTPS_SR_OFFSET 0x2C
/* Channel Status [11:0] */
#define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40
/* IR Transmitted pulse Width */
#define XUARTPS_FIFO_OFFSET 0x30
/* FIFO [15:0] or [7:0] */
#define CDNS_UART_TXWM_OFFSET 0x44
/* TX FIFO Trigger Level */
#define XUARTPS_BAUDDIV_OFFSET 0x34
/* Baud Rate Divider [7:0] */
#define XUARTPS_FLOWDEL_OFFSET 0x38
/* Flow Delay [15:0] */
/* Control Register Bit Definitions */
#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C
/* IR Minimum Received Pulse
#define CDNS_UART_CR_STOPBRK 0x00000100
/* Stop TX break */
Width [15:0] */
#define CDNS_UART_CR_STARTBRK 0x00000080
/* Set TX break */
#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40
/* IR Transmitted pulse
#define CDNS_UART_CR_TX_DIS 0x00000020
/* TX disabled. */
Width [7:0] */
#define CDNS_UART_CR_TX_EN 0x00000010
/* TX enabled */
#define XUARTPS_TXWM_OFFSET 0x44
/* TX FIFO Trigger Level [5:0] */
#define CDNS_UART_CR_RX_DIS 0x00000008
/* RX disabled. */
#define CDNS_UART_CR_RX_EN 0x00000004
/* RX enabled */
/** Control Register
#define CDNS_UART_CR_TXRST 0x00000002
/* TX logic reset */
*
#define CDNS_UART_CR_RXRST 0x00000001
/* RX logic reset */
* The Control register (CR) controls the major functions of the device.
#define CDNS_UART_CR_RST_TO 0x00000040
/* Restart Timeout Counter */
*
* Control Register Bit Definitions
/*
*/
* Mode Register:
#define XUARTPS_CR_STOPBRK 0x00000100
/* Stop TX break */
#define XUARTPS_CR_STARTBRK 0x00000080
/* Set TX break */
#define XUARTPS_CR_TX_DIS 0x00000020
/* TX disabled. */
#define XUARTPS_CR_TX_EN 0x00000010
/* TX enabled */
#define XUARTPS_CR_RX_DIS 0x00000008
/* RX disabled. */
#define XUARTPS_CR_RX_EN 0x00000004
/* RX enabled */
#define XUARTPS_CR_TXRST 0x00000002
/* TX logic reset */
#define XUARTPS_CR_RXRST 0x00000001
/* RX logic reset */
#define XUARTPS_CR_RST_TO 0x00000040
/* Restart Timeout Counter */
/** Mode Register
*
* The mode register (MR) defines the mode of transfer as well as the data
* The mode register (MR) defines the mode of transfer as well as the data
* format. If this register is modified during transmission or reception,
* format. If this register is modified during transmission or reception,
* data validity cannot be guaranteed.
* data validity cannot be guaranteed.
*
* Mode Register Bit Definitions
*
*/
*/
#define
XUARTPS
_MR_CLKSEL 0x00000001
/* Pre-scalar selection */
#define
CDNS_UART
_MR_CLKSEL 0x00000001
/* Pre-scalar selection */
#define
XUARTPS
_MR_CHMODE_L_LOOP 0x00000200
/* Local loop back mode */
#define
CDNS_UART
_MR_CHMODE_L_LOOP 0x00000200
/* Local loop back mode */
#define
XUARTPS_MR_CHMODE_NORM
0x00000000
/* Normal mode */
#define
CDNS_UART_MR_CHMODE_NORM
0x00000000
/* Normal mode */
#define
XUARTPS
_MR_STOPMODE_2_BIT 0x00000080
/* 2 stop bits */
#define
CDNS_UART
_MR_STOPMODE_2_BIT 0x00000080
/* 2 stop bits */
#define
XUARTPS
_MR_STOPMODE_1_BIT 0x00000000
/* 1 stop bit */
#define
CDNS_UART
_MR_STOPMODE_1_BIT 0x00000000
/* 1 stop bit */
#define
XUARTPS_MR_PARITY_NONE
0x00000020
/* No parity mode */
#define
CDNS_UART_MR_PARITY_NONE
0x00000020
/* No parity mode */
#define
XUARTPS_MR_PARITY_MARK
0x00000018
/* Mark parity mode */
#define
CDNS_UART_MR_PARITY_MARK
0x00000018
/* Mark parity mode */
#define
XUARTPS_MR_PARITY_SPACE
0x00000010
/* Space parity mode */
#define
CDNS_UART_MR_PARITY_SPACE
0x00000010
/* Space parity mode */
#define
XUARTPS
_MR_PARITY_ODD 0x00000008
/* Odd parity mode */
#define
CDNS_UART
_MR_PARITY_ODD 0x00000008
/* Odd parity mode */
#define
XUARTPS_MR_PARITY_EVEN
0x00000000
/* Even parity mode */
#define
CDNS_UART_MR_PARITY_EVEN
0x00000000
/* Even parity mode */
#define
XUARTPS
_MR_CHARLEN_6_BIT 0x00000006
/* 6 bits data */
#define
CDNS_UART
_MR_CHARLEN_6_BIT 0x00000006
/* 6 bits data */
#define
XUARTPS
_MR_CHARLEN_7_BIT 0x00000004
/* 7 bits data */
#define
CDNS_UART
_MR_CHARLEN_7_BIT 0x00000004
/* 7 bits data */
#define
XUARTPS
_MR_CHARLEN_8_BIT 0x00000000
/* 8 bits data */
#define
CDNS_UART
_MR_CHARLEN_8_BIT 0x00000000
/* 8 bits data */
/*
* Interrupt Registers
/*
*
*
Interrupt Registers:
* Interrupt control logic uses the interrupt enable register (IER) and the
* Interrupt control logic uses the interrupt enable register (IER) and the
* interrupt disable register (IDR) to set the value of the bits in the
* interrupt disable register (IDR) to set the value of the bits in the
* interrupt mask register (IMR). The IMR determines whether to pass an
* interrupt mask register (IMR). The IMR determines whether to pass an
...
@@ -127,65 +115,65 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
...
@@ -127,65 +115,65 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
* Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
* Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
* interrupt. IMR and ISR are read only, and IER and IDR are write only.
* interrupt. IMR and ISR are read only, and IER and IDR are write only.
* Reading either IER or IDR returns 0x00.
* Reading either IER or IDR returns 0x00.
*
* All four registers have the same bit definitions.
* All four registers have the same bit definitions.
*/
*/
#define
XUARTPS
_IXR_TOUT 0x00000100
/* RX Timeout error interrupt */
#define
CDNS_UART
_IXR_TOUT 0x00000100
/* RX Timeout error interrupt */
#define
XUARTPS
_IXR_PARITY 0x00000080
/* Parity error interrupt */
#define
CDNS_UART
_IXR_PARITY 0x00000080
/* Parity error interrupt */
#define
XUARTPS
_IXR_FRAMING 0x00000040
/* Framing error interrupt */
#define
CDNS_UART
_IXR_FRAMING 0x00000040
/* Framing error interrupt */
#define
XUARTPS
_IXR_OVERRUN 0x00000020
/* Overrun error interrupt */
#define
CDNS_UART
_IXR_OVERRUN 0x00000020
/* Overrun error interrupt */
#define
XUARTPS
_IXR_TXFULL 0x00000010
/* TX FIFO Full interrupt */
#define
CDNS_UART
_IXR_TXFULL 0x00000010
/* TX FIFO Full interrupt */
#define
XUARTPS
_IXR_TXEMPTY 0x00000008
/* TX FIFO empty interrupt */
#define
CDNS_UART
_IXR_TXEMPTY 0x00000008
/* TX FIFO empty interrupt */
#define
XUARTPS
_ISR_RXEMPTY 0x00000002
/* RX FIFO empty interrupt */
#define
CDNS_UART
_ISR_RXEMPTY 0x00000002
/* RX FIFO empty interrupt */
#define
XUARTPS
_IXR_RXTRIG 0x00000001
/* RX FIFO trigger interrupt */
#define
CDNS_UART
_IXR_RXTRIG 0x00000001
/* RX FIFO trigger interrupt */
#define
XUARTPS
_IXR_RXFULL 0x00000004
/* RX FIFO full interrupt. */
#define
CDNS_UART
_IXR_RXFULL 0x00000004
/* RX FIFO full interrupt. */
#define
XUARTPS
_IXR_RXEMPTY 0x00000002
/* RX FIFO empty interrupt. */
#define
CDNS_UART
_IXR_RXEMPTY 0x00000002
/* RX FIFO empty interrupt. */
#define
XUARTPS
_IXR_MASK 0x00001FFF
/* Valid bit mask */
#define
CDNS_UART
_IXR_MASK 0x00001FFF
/* Valid bit mask */
/* Goes in read_status_mask for break detection as the HW doesn't do it*/
/* Goes in read_status_mask for break detection as the HW doesn't do it*/
#define
XUARTPS_IXR_BRK
0x80000000
#define
CDNS_UART_IXR_BRK
0x80000000
/*
* Channel Status Register
/*
*
*
Channel Status Register:
* The channel status register (CSR) is provided to enable the control logic
* The channel status register (CSR) is provided to enable the control logic
* to monitor the status of bits in the channel interrupt status register,
* to monitor the status of bits in the channel interrupt status register,
* even if these are masked out by the interrupt mask register.
* even if these are masked out by the interrupt mask register.
*/
*/
#define
XUARTPS
_SR_RXEMPTY 0x00000002
/* RX FIFO empty */
#define
CDNS_UART
_SR_RXEMPTY 0x00000002
/* RX FIFO empty */
#define
XUARTPS
_SR_TXEMPTY 0x00000008
/* TX FIFO empty */
#define
CDNS_UART
_SR_TXEMPTY 0x00000008
/* TX FIFO empty */
#define
XUARTPS
_SR_TXFULL 0x00000010
/* TX FIFO full */
#define
CDNS_UART
_SR_TXFULL 0x00000010
/* TX FIFO full */
#define
XUARTPS
_SR_RXTRIG 0x00000001
/* Rx Trigger */
#define
CDNS_UART
_SR_RXTRIG 0x00000001
/* Rx Trigger */
/* baud dividers min/max values */
/* baud dividers min/max values */
#define
XUARTPS
_BDIV_MIN 4
#define
CDNS_UART
_BDIV_MIN 4
#define
XUARTPS
_BDIV_MAX 255
#define
CDNS_UART
_BDIV_MAX 255
#define
XUARTPS_CD_MAX
65535
#define
CDNS_UART_CD_MAX
65535
/**
/**
* struct
xuartps
- device data
* struct
cdns_uart
- device data
* @port Pointer to the UART port
* @port
:
Pointer to the UART port
* @
refclk
Reference clock
* @
uartclk:
Reference clock
* @
aperclk
APB clock
* @
pclk:
APB clock
* @baud Current baud rate
* @baud
:
Current baud rate
* @clk_rate_change_nb Notifier block for clock changes
* @clk_rate_change_nb
:
Notifier block for clock changes
*/
*/
struct
xuartps
{
struct
cdns_uart
{
struct
uart_port
*
port
;
struct
uart_port
*
port
;
struct
clk
*
ref
clk
;
struct
clk
*
uart
clk
;
struct
clk
*
aper
clk
;
struct
clk
*
p
clk
;
unsigned
int
baud
;
unsigned
int
baud
;
struct
notifier_block
clk_rate_change_nb
;
struct
notifier_block
clk_rate_change_nb
;
};
};
#define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb);
#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
clk_rate_change_nb);
/**
/**
*
xuartps
_isr - Interrupt handler
*
cdns_uart
_isr - Interrupt handler
* @irq: Irq number
* @irq: Irq number
* @dev_id: Id of the port
* @dev_id: Id of the port
*
*
* Return
s
IRQHANDLED
* Return
:
IRQHANDLED
*
*
/
*/
static
irqreturn_t
xuartps
_isr
(
int
irq
,
void
*
dev_id
)
static
irqreturn_t
cdns_uart
_isr
(
int
irq
,
void
*
dev_id
)
{
{
struct
uart_port
*
port
=
(
struct
uart_port
*
)
dev_id
;
struct
uart_port
*
port
=
(
struct
uart_port
*
)
dev_id
;
unsigned
long
flags
;
unsigned
long
flags
;
...
@@ -198,43 +186,42 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
...
@@ -198,43 +186,42 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
/* Read the interrupt status register to determine which
/* Read the interrupt status register to determine which
* interrupt(s) is/are active.
* interrupt(s) is/are active.
*/
*/
isrstatus
=
xuartps_readl
(
XUARTPS
_ISR_OFFSET
);
isrstatus
=
cdns_uart_readl
(
CDNS_UART
_ISR_OFFSET
);
/*
/*
* There is no hardware break detection, so we interpret framing
* There is no hardware break detection, so we interpret framing
* error with all-zeros data as a break sequence. Most of the time,
* error with all-zeros data as a break sequence. Most of the time,
* there's another non-zero byte at the end of the sequence.
* there's another non-zero byte at the end of the sequence.
*/
*/
if
(
isrstatus
&
CDNS_UART_IXR_FRAMING
)
{
if
(
isrstatus
&
XUARTPS_IXR_FRAMING
)
{
while
(
!
(
cdns_uart_readl
(
CDNS_UART_SR_OFFSET
)
&
while
(
!
(
xuartps_readl
(
XUARTPS_SR_OFFSET
)
&
CDNS_UART_SR_RXEMPTY
))
{
XUARTPS_SR_RXEMPTY
))
{
if
(
!
cdns_uart_readl
(
CDNS_UART_FIFO_OFFSET
))
{
if
(
!
xuartps_readl
(
XUARTPS_FIFO_OFFSET
))
{
port
->
read_status_mask
|=
CDNS_UART_IXR_BRK
;
port
->
read_status_mask
|=
XUARTPS_IXR_BRK
;
isrstatus
&=
~
CDNS_UART_IXR_FRAMING
;
isrstatus
&=
~
XUARTPS_IXR_FRAMING
;
}
}
}
}
xuartps_writel
(
XUARTPS_IXR_FRAMING
,
XUARTPS
_ISR_OFFSET
);
cdns_uart_writel
(
CDNS_UART_IXR_FRAMING
,
CDNS_UART
_ISR_OFFSET
);
}
}
/* drop byte with parity error if IGNPAR specified */
/* drop byte with parity error if IGNPAR specified */
if
(
isrstatus
&
port
->
ignore_status_mask
&
XUARTPS
_IXR_PARITY
)
if
(
isrstatus
&
port
->
ignore_status_mask
&
CDNS_UART
_IXR_PARITY
)
isrstatus
&=
~
(
XUARTPS_IXR_RXTRIG
|
XUARTPS
_IXR_TOUT
);
isrstatus
&=
~
(
CDNS_UART_IXR_RXTRIG
|
CDNS_UART
_IXR_TOUT
);
isrstatus
&=
port
->
read_status_mask
;
isrstatus
&=
port
->
read_status_mask
;
isrstatus
&=
~
port
->
ignore_status_mask
;
isrstatus
&=
~
port
->
ignore_status_mask
;
if
((
isrstatus
&
XUARTPS
_IXR_TOUT
)
||
if
((
isrstatus
&
CDNS_UART
_IXR_TOUT
)
||
(
isrstatus
&
XUARTPS
_IXR_RXTRIG
))
{
(
isrstatus
&
CDNS_UART
_IXR_RXTRIG
))
{
/* Receive Timeout Interrupt */
/* Receive Timeout Interrupt */
while
((
xuartps_readl
(
XUARTPS
_SR_OFFSET
)
&
while
((
cdns_uart_readl
(
CDNS_UART
_SR_OFFSET
)
&
XUARTPS_SR_RXEMPTY
)
!=
XUARTPS
_SR_RXEMPTY
)
{
CDNS_UART_SR_RXEMPTY
)
!=
CDNS_UART
_SR_RXEMPTY
)
{
data
=
xuartps_readl
(
XUARTPS
_FIFO_OFFSET
);
data
=
cdns_uart_readl
(
CDNS_UART
_FIFO_OFFSET
);
/* Non-NULL byte after BREAK is garbage (99%) */
/* Non-NULL byte after BREAK is garbage (99%) */
if
(
data
&&
(
port
->
read_status_mask
&
if
(
data
&&
(
port
->
read_status_mask
&
XUARTPS
_IXR_BRK
))
{
CDNS_UART
_IXR_BRK
))
{
port
->
read_status_mask
&=
~
XUARTPS
_IXR_BRK
;
port
->
read_status_mask
&=
~
CDNS_UART
_IXR_BRK
;
port
->
icount
.
brk
++
;
port
->
icount
.
brk
++
;
if
(
uart_handle_break
(
port
))
if
(
uart_handle_break
(
port
))
continue
;
continue
;
...
@@ -258,16 +245,17 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
...
@@ -258,16 +245,17 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
port
->
icount
.
rx
++
;
port
->
icount
.
rx
++
;
if
(
isrstatus
&
XUARTPS
_IXR_PARITY
)
{
if
(
isrstatus
&
CDNS_UART
_IXR_PARITY
)
{
port
->
icount
.
parity
++
;
port
->
icount
.
parity
++
;
status
=
TTY_PARITY
;
status
=
TTY_PARITY
;
}
else
if
(
isrstatus
&
XUARTPS
_IXR_FRAMING
)
{
}
else
if
(
isrstatus
&
CDNS_UART
_IXR_FRAMING
)
{
port
->
icount
.
frame
++
;
port
->
icount
.
frame
++
;
status
=
TTY_FRAME
;
status
=
TTY_FRAME
;
}
else
if
(
isrstatus
&
XUARTPS_IXR_OVERRUN
)
}
else
if
(
isrstatus
&
CDNS_UART_IXR_OVERRUN
)
{
port
->
icount
.
overrun
++
;
port
->
icount
.
overrun
++
;
}
uart_insert_char
(
port
,
isrstatus
,
XUARTPS
_IXR_OVERRUN
,
uart_insert_char
(
port
,
isrstatus
,
CDNS_UART
_IXR_OVERRUN
,
data
,
status
);
data
,
status
);
}
}
spin_unlock
(
&
port
->
lock
);
spin_unlock
(
&
port
->
lock
);
...
@@ -276,10 +264,10 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
...
@@ -276,10 +264,10 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
}
}
/* Dispatch an appropriate handler */
/* Dispatch an appropriate handler */
if
((
isrstatus
&
XUARTPS_IXR_TXEMPTY
)
==
XUARTPS
_IXR_TXEMPTY
)
{
if
((
isrstatus
&
CDNS_UART_IXR_TXEMPTY
)
==
CDNS_UART
_IXR_TXEMPTY
)
{
if
(
uart_circ_empty
(
&
port
->
state
->
xmit
))
{
if
(
uart_circ_empty
(
&
port
->
state
->
xmit
))
{
xuartps_writel
(
XUARTPS
_IXR_TXEMPTY
,
cdns_uart_writel
(
CDNS_UART
_IXR_TXEMPTY
,
XUARTPS
_IDR_OFFSET
);
CDNS_UART
_IDR_OFFSET
);
}
else
{
}
else
{
numbytes
=
port
->
fifosize
;
numbytes
=
port
->
fifosize
;
/* Break if no more data available in the UART buffer */
/* Break if no more data available in the UART buffer */
...
@@ -287,12 +275,12 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
...
@@ -287,12 +275,12 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
if
(
uart_circ_empty
(
&
port
->
state
->
xmit
))
if
(
uart_circ_empty
(
&
port
->
state
->
xmit
))
break
;
break
;
/* Get the data from the UART circular buffer
/* Get the data from the UART circular buffer
* and write it to the
xuartps
's TX_FIFO
* and write it to the
cdns_uart
's TX_FIFO
* register.
* register.
*/
*/
xuartps
_writel
(
cdns_uart
_writel
(
port
->
state
->
xmit
.
buf
[
port
->
state
->
xmit
.
port
->
state
->
xmit
.
buf
[
port
->
state
->
xmit
.
tail
],
XUARTPS
_FIFO_OFFSET
);
tail
],
CDNS_UART
_FIFO_OFFSET
);
port
->
icount
.
tx
++
;
port
->
icount
.
tx
++
;
...
@@ -300,7 +288,7 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
...
@@ -300,7 +288,7 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
* the buffer if it reaches limit.
* the buffer if it reaches limit.
*/
*/
port
->
state
->
xmit
.
tail
=
port
->
state
->
xmit
.
tail
=
(
port
->
state
->
xmit
.
tail
+
1
)
&
\
(
port
->
state
->
xmit
.
tail
+
1
)
&
(
UART_XMIT_SIZE
-
1
);
(
UART_XMIT_SIZE
-
1
);
}
}
...
@@ -310,7 +298,7 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
...
@@ -310,7 +298,7 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
}
}
}
}
xuartps_writel
(
isrstatus
,
XUARTPS
_ISR_OFFSET
);
cdns_uart_writel
(
isrstatus
,
CDNS_UART
_ISR_OFFSET
);
/* be sure to release the lock and tty before leaving */
/* be sure to release the lock and tty before leaving */
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
...
@@ -319,13 +307,13 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
...
@@ -319,13 +307,13 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
}
}
/**
/**
*
xuartps
_calc_baud_divs - Calculate baud rate divisors
*
cdns_uart
_calc_baud_divs - Calculate baud rate divisors
* @clk: UART module input clock
* @clk: UART module input clock
* @baud: Desired baud rate
* @baud: Desired baud rate
* @rbdiv: BDIV value (return value)
* @rbdiv: BDIV value (return value)
* @rcd: CD value (return value)
* @rcd: CD value (return value)
* @div8: Value for clk_sel bit in mod (return value)
* @div8: Value for clk_sel bit in mod (return value)
* Return
s
baud rate, requested baud when possible, or actual baud when there
* Return
:
baud rate, requested baud when possible, or actual baud when there
* was too much error, zero if no valid divisors are found.
* was too much error, zero if no valid divisors are found.
*
*
* Formula to obtain baud rate is
* Formula to obtain baud rate is
...
@@ -338,8 +326,8 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
...
@@ -338,8 +326,8 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
* baud rate generate register
* baud rate generate register
* baud rate clock divisor register
* baud rate clock divisor register
*/
*/
static
unsigned
int
xuartps_calc_baud_divs
(
unsigned
int
clk
,
unsigned
int
baud
,
static
unsigned
int
cdns_uart_calc_baud_divs
(
unsigned
int
clk
,
u32
*
rbdiv
,
u32
*
rcd
,
int
*
div8
)
u
nsigned
int
baud
,
u
32
*
rbdiv
,
u32
*
rcd
,
int
*
div8
)
{
{
u32
cd
,
bdiv
;
u32
cd
,
bdiv
;
unsigned
int
calc_baud
;
unsigned
int
calc_baud
;
...
@@ -347,16 +335,16 @@ static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
...
@@ -347,16 +335,16 @@ static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
unsigned
int
bauderror
;
unsigned
int
bauderror
;
unsigned
int
besterror
=
~
0
;
unsigned
int
besterror
=
~
0
;
if
(
baud
<
clk
/
((
XUARTPS_BDIV_MAX
+
1
)
*
XUARTPS
_CD_MAX
))
{
if
(
baud
<
clk
/
((
CDNS_UART_BDIV_MAX
+
1
)
*
CDNS_UART
_CD_MAX
))
{
*
div8
=
1
;
*
div8
=
1
;
clk
/=
8
;
clk
/=
8
;
}
else
{
}
else
{
*
div8
=
0
;
*
div8
=
0
;
}
}
for
(
bdiv
=
XUARTPS_BDIV_MIN
;
bdiv
<=
XUARTPS
_BDIV_MAX
;
bdiv
++
)
{
for
(
bdiv
=
CDNS_UART_BDIV_MIN
;
bdiv
<=
CDNS_UART
_BDIV_MAX
;
bdiv
++
)
{
cd
=
DIV_ROUND_CLOSEST
(
clk
,
baud
*
(
bdiv
+
1
));
cd
=
DIV_ROUND_CLOSEST
(
clk
,
baud
*
(
bdiv
+
1
));
if
(
cd
<
1
||
cd
>
XUARTPS
_CD_MAX
)
if
(
cd
<
1
||
cd
>
CDNS_UART
_CD_MAX
)
continue
;
continue
;
calc_baud
=
clk
/
(
cd
*
(
bdiv
+
1
));
calc_baud
=
clk
/
(
cd
*
(
bdiv
+
1
));
...
@@ -381,47 +369,47 @@ static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
...
@@ -381,47 +369,47 @@ static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
}
}
/**
/**
*
xuartps
_set_baud_rate - Calculate and set the baud rate
*
cdns_uart
_set_baud_rate - Calculate and set the baud rate
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
* @baud: Baud rate to set
* @baud: Baud rate to set
* Return
s
baud rate, requested baud when possible, or actual baud when there
* Return
:
baud rate, requested baud when possible, or actual baud when there
* was too much error, zero if no valid divisors are found.
* was too much error, zero if no valid divisors are found.
*/
*/
static
unsigned
int
xuartps
_set_baud_rate
(
struct
uart_port
*
port
,
static
unsigned
int
cdns_uart
_set_baud_rate
(
struct
uart_port
*
port
,
unsigned
int
baud
)
unsigned
int
baud
)
{
{
unsigned
int
calc_baud
;
unsigned
int
calc_baud
;
u32
cd
=
0
,
bdiv
=
0
;
u32
cd
=
0
,
bdiv
=
0
;
u32
mreg
;
u32
mreg
;
int
div8
;
int
div8
;
struct
xuartps
*
xuartps
=
port
->
private_data
;
struct
cdns_uart
*
cdns_uart
=
port
->
private_data
;
calc_baud
=
xuartps
_calc_baud_divs
(
port
->
uartclk
,
baud
,
&
bdiv
,
&
cd
,
calc_baud
=
cdns_uart
_calc_baud_divs
(
port
->
uartclk
,
baud
,
&
bdiv
,
&
cd
,
&
div8
);
&
div8
);
/* Write new divisors to hardware */
/* Write new divisors to hardware */
mreg
=
xuartps_readl
(
XUARTPS
_MR_OFFSET
);
mreg
=
cdns_uart_readl
(
CDNS_UART
_MR_OFFSET
);
if
(
div8
)
if
(
div8
)
mreg
|=
XUARTPS
_MR_CLKSEL
;
mreg
|=
CDNS_UART
_MR_CLKSEL
;
else
else
mreg
&=
~
XUARTPS
_MR_CLKSEL
;
mreg
&=
~
CDNS_UART
_MR_CLKSEL
;
xuartps_writel
(
mreg
,
XUARTPS
_MR_OFFSET
);
cdns_uart_writel
(
mreg
,
CDNS_UART
_MR_OFFSET
);
xuartps_writel
(
cd
,
XUARTPS
_BAUDGEN_OFFSET
);
cdns_uart_writel
(
cd
,
CDNS_UART
_BAUDGEN_OFFSET
);
xuartps_writel
(
bdiv
,
XUARTPS
_BAUDDIV_OFFSET
);
cdns_uart_writel
(
bdiv
,
CDNS_UART
_BAUDDIV_OFFSET
);
xuartps
->
baud
=
baud
;
cdns_uart
->
baud
=
baud
;
return
calc_baud
;
return
calc_baud
;
}
}
#ifdef CONFIG_COMMON_CLK
#ifdef CONFIG_COMMON_CLK
/**
/**
*
xuartps
_clk_notitifer_cb - Clock notifier callback
*
cdns_uart
_clk_notitifer_cb - Clock notifier callback
* @nb: Notifier block
* @nb: Notifier block
* @event: Notify event
* @event: Notify event
* @data: Notifier data
* @data: Notifier data
* Return
s NOTIFY_OK
on success, NOTIFY_BAD on error.
* Return
: NOTIFY_OK or NOTIFY_DONE
on success, NOTIFY_BAD on error.
*/
*/
static
int
xuartps
_clk_notifier_cb
(
struct
notifier_block
*
nb
,
static
int
cdns_uart
_clk_notifier_cb
(
struct
notifier_block
*
nb
,
unsigned
long
event
,
void
*
data
)
unsigned
long
event
,
void
*
data
)
{
{
u32
ctrl_reg
;
u32
ctrl_reg
;
...
@@ -429,35 +417,36 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
...
@@ -429,35 +417,36 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
int
locked
=
0
;
int
locked
=
0
;
struct
clk_notifier_data
*
ndata
=
data
;
struct
clk_notifier_data
*
ndata
=
data
;
unsigned
long
flags
=
0
;
unsigned
long
flags
=
0
;
struct
xuartps
*
xuartps
=
to_xuartps
(
nb
);
struct
cdns_uart
*
cdns_uart
=
to_cdns_uart
(
nb
);
port
=
xuartps
->
port
;
port
=
cdns_uart
->
port
;
if
(
port
->
suspended
)
if
(
port
->
suspended
)
return
NOTIFY_OK
;
return
NOTIFY_OK
;
switch
(
event
)
{
switch
(
event
)
{
case
PRE_RATE_CHANGE
:
case
PRE_RATE_CHANGE
:
{
{
u32
bdiv
;
u32
bdiv
,
cd
;
u32
cd
;
int
div8
;
int
div8
;
/*
/*
* Find out if current baud-rate can be achieved with new clock
* Find out if current baud-rate can be achieved with new clock
* frequency.
* frequency.
*/
*/
if
(
!
xuartps_calc_baud_divs
(
ndata
->
new_rate
,
xuartps
->
baud
,
if
(
!
cdns_uart_calc_baud_divs
(
ndata
->
new_rate
,
cdns_uart
->
baud
,
&
bdiv
,
&
cd
,
&
div8
))
&
bdiv
,
&
cd
,
&
div8
))
{
dev_warn
(
port
->
dev
,
"clock rate change rejected
\n
"
);
return
NOTIFY_BAD
;
return
NOTIFY_BAD
;
}
spin_lock_irqsave
(
&
xuartps
->
port
->
lock
,
flags
);
spin_lock_irqsave
(
&
cdns_uart
->
port
->
lock
,
flags
);
/* Disable the TX and RX to set baud rate */
/* Disable the TX and RX to set baud rate */
xuartps_writel
(
xuartps_readl
(
XUARTPS_CR_OFFSET
)
|
ctrl_reg
=
cdns_uart_readl
(
CDNS_UART_CR_OFFSET
);
(
XUARTPS_CR_TX_DIS
|
XUARTPS_CR_RX_DIS
),
ctrl_reg
|=
CDNS_UART_CR_TX_DIS
|
CDNS_UART_CR_RX_DIS
;
XUARTPS
_CR_OFFSET
);
cdns_uart_writel
(
ctrl_reg
,
CDNS_UART
_CR_OFFSET
);
spin_unlock_irqrestore
(
&
xuartps
->
port
->
lock
,
flags
);
spin_unlock_irqrestore
(
&
cdns_uart
->
port
->
lock
,
flags
);
return
NOTIFY_OK
;
return
NOTIFY_OK
;
}
}
...
@@ -467,25 +456,25 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
...
@@ -467,25 +456,25 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
* frequency.
* frequency.
*/
*/
spin_lock_irqsave
(
&
xuartps
->
port
->
lock
,
flags
);
spin_lock_irqsave
(
&
cdns_uart
->
port
->
lock
,
flags
);
locked
=
1
;
locked
=
1
;
port
->
uartclk
=
ndata
->
new_rate
;
port
->
uartclk
=
ndata
->
new_rate
;
xuartps
->
baud
=
xuartps_set_baud_rate
(
xuartps
->
port
,
cdns_uart
->
baud
=
cdns_uart_set_baud_rate
(
cdns_uart
->
port
,
xuartps
->
baud
);
cdns_uart
->
baud
);
/* fall through */
/* fall through */
case
ABORT_RATE_CHANGE
:
case
ABORT_RATE_CHANGE
:
if
(
!
locked
)
if
(
!
locked
)
spin_lock_irqsave
(
&
xuartps
->
port
->
lock
,
flags
);
spin_lock_irqsave
(
&
cdns_uart
->
port
->
lock
,
flags
);
/* Set TX/RX Reset */
/* Set TX/RX Reset */
xuartps_writel
(
xuartps_readl
(
XUARTPS_CR_OFFSET
)
|
ctrl_reg
=
cdns_uart_readl
(
CDNS_UART_CR_OFFSET
);
(
XUARTPS_CR_TXRST
|
XUARTPS_CR_RXRST
),
ctrl_reg
|=
CDNS_UART_CR_TXRST
|
CDNS_UART_CR_RXRST
;
XUARTPS
_CR_OFFSET
);
cdns_uart_writel
(
ctrl_reg
,
CDNS_UART
_CR_OFFSET
);
while
(
xuartps_readl
(
XUARTPS
_CR_OFFSET
)
&
while
(
cdns_uart_readl
(
CDNS_UART
_CR_OFFSET
)
&
(
XUARTPS_CR_TXRST
|
XUARTPS
_CR_RXRST
))
(
CDNS_UART_CR_TXRST
|
CDNS_UART
_CR_RXRST
))
cpu_relax
();
cpu_relax
();
/*
/*
...
@@ -493,14 +482,13 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
...
@@ -493,14 +482,13 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
* enable bit and RX enable bit to enable the transmitter and
* enable bit and RX enable bit to enable the transmitter and
* receiver.
* receiver.
*/
*/
xuartps_writel
(
rx_timeout
,
XUARTPS_RXTOUT_OFFSET
);
cdns_uart_writel
(
rx_timeout
,
CDNS_UART_RXTOUT_OFFSET
);
ctrl_reg
=
xuartps_readl
(
XUARTPS_CR_OFFSET
);
ctrl_reg
=
cdns_uart_readl
(
CDNS_UART_CR_OFFSET
);
xuartps_writel
(
ctrl_reg
&=
~
(
CDNS_UART_CR_TX_DIS
|
CDNS_UART_CR_RX_DIS
);
(
ctrl_reg
&
~
(
XUARTPS_CR_TX_DIS
|
XUARTPS_CR_RX_DIS
))
|
ctrl_reg
|=
CDNS_UART_CR_TX_EN
|
CDNS_UART_CR_RX_EN
;
(
XUARTPS_CR_TX_EN
|
XUARTPS_CR_RX_EN
),
cdns_uart_writel
(
ctrl_reg
,
CDNS_UART_CR_OFFSET
);
XUARTPS_CR_OFFSET
);
spin_unlock_irqrestore
(
&
xuartps
->
port
->
lock
,
flags
);
spin_unlock_irqrestore
(
&
cdns_uart
->
port
->
lock
,
flags
);
return
NOTIFY_OK
;
return
NOTIFY_OK
;
default:
default:
...
@@ -509,40 +497,36 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
...
@@ -509,40 +497,36 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
}
}
#endif
#endif
/*----------------------Uart Operations---------------------------*/
/**
/**
*
xuartps
_start_tx - Start transmitting bytes
*
cdns_uart
_start_tx - Start transmitting bytes
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*/
**/
static
void
cdns_uart_start_tx
(
struct
uart_port
*
port
)
static
void
xuartps_start_tx
(
struct
uart_port
*
port
)
{
{
unsigned
int
status
,
numbytes
=
port
->
fifosize
;
unsigned
int
status
,
numbytes
=
port
->
fifosize
;
if
(
uart_circ_empty
(
&
port
->
state
->
xmit
)
||
uart_tx_stopped
(
port
))
if
(
uart_circ_empty
(
&
port
->
state
->
xmit
)
||
uart_tx_stopped
(
port
))
return
;
return
;
status
=
xuartps_readl
(
XUARTPS
_CR_OFFSET
);
status
=
cdns_uart_readl
(
CDNS_UART
_CR_OFFSET
);
/* Set the TX enable bit and clear the TX disable bit to enable the
/* Set the TX enable bit and clear the TX disable bit to enable the
* transmitter.
* transmitter.
*/
*/
xuartps_writel
((
status
&
~
XUARTPS_CR_TX_DIS
)
|
XUARTPS_CR_TX_EN
,
cdns_uart_writel
((
status
&
~
CDNS_UART_CR_TX_DIS
)
|
CDNS_UART_CR_TX_EN
,
XUARTPS_CR_OFFSET
);
CDNS_UART_CR_OFFSET
);
while
(
numbytes
--
&&
((
xuartps_readl
(
XUARTPS_SR_OFFSET
)
&
XUARTPS_SR_TXFULL
))
!=
XUARTPS_SR_TXFULL
)
{
while
(
numbytes
--
&&
((
cdns_uart_readl
(
CDNS_UART_SR_OFFSET
)
&
CDNS_UART_SR_TXFULL
))
!=
CDNS_UART_SR_TXFULL
)
{
/* Break if no more data available in the UART buffer */
/* Break if no more data available in the UART buffer */
if
(
uart_circ_empty
(
&
port
->
state
->
xmit
))
if
(
uart_circ_empty
(
&
port
->
state
->
xmit
))
break
;
break
;
/* Get the data from the UART circular buffer and
/* Get the data from the UART circular buffer and
* write it to the
xuartps
's TX_FIFO register.
* write it to the
cdns_uart
's TX_FIFO register.
*/
*/
xuartps
_writel
(
cdns_uart
_writel
(
port
->
state
->
xmit
.
buf
[
port
->
state
->
xmit
.
tail
],
port
->
state
->
xmit
.
buf
[
port
->
state
->
xmit
.
tail
],
XUARTPS
_FIFO_OFFSET
);
CDNS_UART
_FIFO_OFFSET
);
port
->
icount
.
tx
++
;
port
->
icount
.
tx
++
;
/* Adjust the tail of the UART buffer and wrap
/* Adjust the tail of the UART buffer and wrap
...
@@ -551,94 +535,90 @@ static void xuartps_start_tx(struct uart_port *port)
...
@@ -551,94 +535,90 @@ static void xuartps_start_tx(struct uart_port *port)
port
->
state
->
xmit
.
tail
=
(
port
->
state
->
xmit
.
tail
+
1
)
&
port
->
state
->
xmit
.
tail
=
(
port
->
state
->
xmit
.
tail
+
1
)
&
(
UART_XMIT_SIZE
-
1
);
(
UART_XMIT_SIZE
-
1
);
}
}
xuartps_writel
(
XUARTPS_IXR_TXEMPTY
,
XUARTPS
_ISR_OFFSET
);
cdns_uart_writel
(
CDNS_UART_IXR_TXEMPTY
,
CDNS_UART
_ISR_OFFSET
);
/* Enable the TX Empty interrupt */
/* Enable the TX Empty interrupt */
xuartps_writel
(
XUARTPS_IXR_TXEMPTY
,
XUARTPS
_IER_OFFSET
);
cdns_uart_writel
(
CDNS_UART_IXR_TXEMPTY
,
CDNS_UART
_IER_OFFSET
);
if
(
uart_circ_chars_pending
(
&
port
->
state
->
xmit
)
<
WAKEUP_CHARS
)
if
(
uart_circ_chars_pending
(
&
port
->
state
->
xmit
)
<
WAKEUP_CHARS
)
uart_write_wakeup
(
port
);
uart_write_wakeup
(
port
);
}
}
/**
/**
*
xuartps
_stop_tx - Stop TX
*
cdns_uart
_stop_tx - Stop TX
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*/
**/
static
void
cdns_uart_stop_tx
(
struct
uart_port
*
port
)
static
void
xuartps_stop_tx
(
struct
uart_port
*
port
)
{
{
unsigned
int
regval
;
unsigned
int
regval
;
regval
=
xuartps_readl
(
XUARTPS
_CR_OFFSET
);
regval
=
cdns_uart_readl
(
CDNS_UART
_CR_OFFSET
);
regval
|=
XUARTPS
_CR_TX_DIS
;
regval
|=
CDNS_UART
_CR_TX_DIS
;
/* Disable the transmitter */
/* Disable the transmitter */
xuartps_writel
(
regval
,
XUARTPS
_CR_OFFSET
);
cdns_uart_writel
(
regval
,
CDNS_UART
_CR_OFFSET
);
}
}
/**
/**
*
xuartps
_stop_rx - Stop RX
*
cdns_uart
_stop_rx - Stop RX
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*/
**/
static
void
cdns_uart_stop_rx
(
struct
uart_port
*
port
)
static
void
xuartps_stop_rx
(
struct
uart_port
*
port
)
{
{
unsigned
int
regval
;
unsigned
int
regval
;
regval
=
xuartps_readl
(
XUARTPS
_CR_OFFSET
);
regval
=
cdns_uart_readl
(
CDNS_UART
_CR_OFFSET
);
regval
|=
XUARTPS
_CR_RX_DIS
;
regval
|=
CDNS_UART
_CR_RX_DIS
;
/* Disable the receiver */
/* Disable the receiver */
xuartps_writel
(
regval
,
XUARTPS
_CR_OFFSET
);
cdns_uart_writel
(
regval
,
CDNS_UART
_CR_OFFSET
);
}
}
/**
/**
*
xuartps
_tx_empty - Check whether TX is empty
*
cdns_uart
_tx_empty - Check whether TX is empty
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*
* Return
s
TIOCSER_TEMT on success, 0 otherwise
* Return
:
TIOCSER_TEMT on success, 0 otherwise
*
*
/
*/
static
unsigned
int
xuartps
_tx_empty
(
struct
uart_port
*
port
)
static
unsigned
int
cdns_uart
_tx_empty
(
struct
uart_port
*
port
)
{
{
unsigned
int
status
;
unsigned
int
status
;
status
=
xuartps_readl
(
XUARTPS_ISR_OFFSET
)
&
XUARTPS
_IXR_TXEMPTY
;
status
=
cdns_uart_readl
(
CDNS_UART_ISR_OFFSET
)
&
CDNS_UART
_IXR_TXEMPTY
;
return
status
?
TIOCSER_TEMT
:
0
;
return
status
?
TIOCSER_TEMT
:
0
;
}
}
/**
/**
*
xuartps
_break_ctl - Based on the input ctl we have to start or stop
*
cdns_uart
_break_ctl - Based on the input ctl we have to start or stop
* transmitting char breaks
* transmitting char breaks
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
* @ctl: Value based on which start or stop decision is taken
* @ctl: Value based on which start or stop decision is taken
*
*/
**/
static
void
cdns_uart_break_ctl
(
struct
uart_port
*
port
,
int
ctl
)
static
void
xuartps_break_ctl
(
struct
uart_port
*
port
,
int
ctl
)
{
{
unsigned
int
status
;
unsigned
int
status
;
unsigned
long
flags
;
unsigned
long
flags
;
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
status
=
xuartps_readl
(
XUARTPS
_CR_OFFSET
);
status
=
cdns_uart_readl
(
CDNS_UART
_CR_OFFSET
);
if
(
ctl
==
-
1
)
if
(
ctl
==
-
1
)
xuartps_writel
(
XUARTPS
_CR_STARTBRK
|
status
,
cdns_uart_writel
(
CDNS_UART
_CR_STARTBRK
|
status
,
XUARTPS
_CR_OFFSET
);
CDNS_UART
_CR_OFFSET
);
else
{
else
{
if
((
status
&
XUARTPS
_CR_STOPBRK
)
==
0
)
if
((
status
&
CDNS_UART
_CR_STOPBRK
)
==
0
)
xuartps_writel
(
XUARTPS
_CR_STOPBRK
|
status
,
cdns_uart_writel
(
CDNS_UART
_CR_STOPBRK
|
status
,
XUARTPS
_CR_OFFSET
);
CDNS_UART
_CR_OFFSET
);
}
}
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
}
}
/**
/**
*
xuartps
_set_termios - termios operations, handling data length, parity,
*
cdns_uart
_set_termios - termios operations, handling data length, parity,
* stop bits, flow control, baud rate
* stop bits, flow control, baud rate
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
* @termios: Handle to the input termios structure
* @termios: Handle to the input termios structure
* @old: Values of the previously saved termios structure
* @old: Values of the previously saved termios structure
*
*/
**/
static
void
cdns_uart_set_termios
(
struct
uart_port
*
port
,
static
void
xuartps_set_termios
(
struct
uart_port
*
port
,
struct
ktermios
*
termios
,
struct
ktermios
*
old
)
struct
ktermios
*
termios
,
struct
ktermios
*
old
)
{
{
unsigned
int
cval
=
0
;
unsigned
int
cval
=
0
;
...
@@ -649,81 +629,79 @@ static void xuartps_set_termios(struct uart_port *port,
...
@@ -649,81 +629,79 @@ static void xuartps_set_termios(struct uart_port *port,
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
/* Empty the receive FIFO 1st before making changes */
/* Empty the receive FIFO 1st before making changes */
while
((
xuartps_readl
(
XUARTPS
_SR_OFFSET
)
&
while
((
cdns_uart_readl
(
CDNS_UART
_SR_OFFSET
)
&
XUARTPS_SR_RXEMPTY
)
!=
XUARTPS
_SR_RXEMPTY
)
{
CDNS_UART_SR_RXEMPTY
)
!=
CDNS_UART
_SR_RXEMPTY
)
{
xuartps_readl
(
XUARTPS
_FIFO_OFFSET
);
cdns_uart_readl
(
CDNS_UART
_FIFO_OFFSET
);
}
}
/* Disable the TX and RX to set baud rate */
/* Disable the TX and RX to set baud rate */
xuartps_writel
(
xuartps_readl
(
XUARTPS_CR_OFFSET
)
|
ctrl_reg
=
cdns_uart_readl
(
CDNS_UART_CR_OFFSET
);
(
XUARTPS_CR_TX_DIS
|
XUARTPS_CR_RX_DIS
),
ctrl_reg
|=
CDNS_UART_CR_TX_DIS
|
CDNS_UART_CR_RX_DIS
;
XUARTPS
_CR_OFFSET
);
cdns_uart_writel
(
ctrl_reg
,
CDNS_UART
_CR_OFFSET
);
/*
/*
* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
* min and max baud should be calculated here based on port->uartclk.
* min and max baud should be calculated here based on port->uartclk.
* this way we get a valid baud and can safely call set_baud()
* this way we get a valid baud and can safely call set_baud()
*/
*/
minbaud
=
port
->
uartclk
/
((
XUARTPS_BDIV_MAX
+
1
)
*
XUARTPS_CD_MAX
*
8
);
minbaud
=
port
->
uartclk
/
maxbaud
=
port
->
uartclk
/
(
XUARTPS_BDIV_MIN
+
1
);
((
CDNS_UART_BDIV_MAX
+
1
)
*
CDNS_UART_CD_MAX
*
8
);
maxbaud
=
port
->
uartclk
/
(
CDNS_UART_BDIV_MIN
+
1
);
baud
=
uart_get_baud_rate
(
port
,
termios
,
old
,
minbaud
,
maxbaud
);
baud
=
uart_get_baud_rate
(
port
,
termios
,
old
,
minbaud
,
maxbaud
);
baud
=
xuartps
_set_baud_rate
(
port
,
baud
);
baud
=
cdns_uart
_set_baud_rate
(
port
,
baud
);
if
(
tty_termios_baud_rate
(
termios
))
if
(
tty_termios_baud_rate
(
termios
))
tty_termios_encode_baud_rate
(
termios
,
baud
,
baud
);
tty_termios_encode_baud_rate
(
termios
,
baud
,
baud
);
/*
/* Update the per-port timeout. */
* Update the per-port timeout.
*/
uart_update_timeout
(
port
,
termios
->
c_cflag
,
baud
);
uart_update_timeout
(
port
,
termios
->
c_cflag
,
baud
);
/* Set TX/RX Reset */
/* Set TX/RX Reset */
xuartps_writel
(
xuartps_readl
(
XUARTPS_CR_OFFSET
)
|
ctrl_reg
=
cdns_uart_readl
(
CDNS_UART_CR_OFFSET
);
(
XUARTPS_CR_TXRST
|
XUARTPS_CR_RXRST
),
ctrl_reg
|=
CDNS_UART_CR_TXRST
|
CDNS_UART_CR_RXRST
;
XUARTPS
_CR_OFFSET
);
cdns_uart_writel
(
ctrl_reg
,
CDNS_UART
_CR_OFFSET
);
ctrl_reg
=
xuartps_readl
(
XUARTPS_CR_OFFSET
);
/*
* Clear the RX disable and TX disable bits and then set the TX enable
/* Clear the RX disable and TX disable bits and then set the TX enable
* bit and RX enable bit to enable the transmitter and receiver.
* bit and RX enable bit to enable the transmitter and receiver.
*/
*/
xuartps_writel
(
ctrl_reg
=
cdns_uart_readl
(
CDNS_UART_CR_OFFSET
);
(
ctrl_reg
&
~
(
XUARTPS_CR_TX_DIS
|
XUARTPS_CR_RX_DIS
))
ctrl_reg
&=
~
(
CDNS_UART_CR_TX_DIS
|
CDNS_UART_CR_RX_DIS
);
|
(
XUARTPS_CR_TX_EN
|
XUARTPS_CR_RX_EN
),
ctrl_reg
|=
CDNS_UART_CR_TX_EN
|
CDNS_UART_CR_RX_EN
;
XUARTPS
_CR_OFFSET
);
cdns_uart_writel
(
ctrl_reg
,
CDNS_UART
_CR_OFFSET
);
xuartps_writel
(
rx_timeout
,
XUARTPS
_RXTOUT_OFFSET
);
cdns_uart_writel
(
rx_timeout
,
CDNS_UART
_RXTOUT_OFFSET
);
port
->
read_status_mask
=
XUARTPS_IXR_TXEMPTY
|
XUARTPS
_IXR_RXTRIG
|
port
->
read_status_mask
=
CDNS_UART_IXR_TXEMPTY
|
CDNS_UART
_IXR_RXTRIG
|
XUARTPS_IXR_OVERRUN
|
XUARTPS
_IXR_TOUT
;
CDNS_UART_IXR_OVERRUN
|
CDNS_UART
_IXR_TOUT
;
port
->
ignore_status_mask
=
0
;
port
->
ignore_status_mask
=
0
;
if
(
termios
->
c_iflag
&
INPCK
)
if
(
termios
->
c_iflag
&
INPCK
)
port
->
read_status_mask
|=
XUARTPS
_IXR_PARITY
|
port
->
read_status_mask
|=
CDNS_UART
_IXR_PARITY
|
XUARTPS
_IXR_FRAMING
;
CDNS_UART
_IXR_FRAMING
;
if
(
termios
->
c_iflag
&
IGNPAR
)
if
(
termios
->
c_iflag
&
IGNPAR
)
port
->
ignore_status_mask
|=
XUARTPS
_IXR_PARITY
|
port
->
ignore_status_mask
|=
CDNS_UART
_IXR_PARITY
|
XUARTPS_IXR_FRAMING
|
XUARTPS
_IXR_OVERRUN
;
CDNS_UART_IXR_FRAMING
|
CDNS_UART
_IXR_OVERRUN
;
/* ignore all characters if CREAD is not set */
/* ignore all characters if CREAD is not set */
if
((
termios
->
c_cflag
&
CREAD
)
==
0
)
if
((
termios
->
c_cflag
&
CREAD
)
==
0
)
port
->
ignore_status_mask
|=
XUARTPS
_IXR_RXTRIG
|
port
->
ignore_status_mask
|=
CDNS_UART
_IXR_RXTRIG
|
XUARTPS_IXR_TOUT
|
XUARTPS
_IXR_PARITY
|
CDNS_UART_IXR_TOUT
|
CDNS_UART
_IXR_PARITY
|
XUARTPS_IXR_FRAMING
|
XUARTPS
_IXR_OVERRUN
;
CDNS_UART_IXR_FRAMING
|
CDNS_UART
_IXR_OVERRUN
;
mode_reg
=
xuartps_readl
(
XUARTPS
_MR_OFFSET
);
mode_reg
=
cdns_uart_readl
(
CDNS_UART
_MR_OFFSET
);
/* Handling Data Size */
/* Handling Data Size */
switch
(
termios
->
c_cflag
&
CSIZE
)
{
switch
(
termios
->
c_cflag
&
CSIZE
)
{
case
CS6
:
case
CS6
:
cval
|=
XUARTPS
_MR_CHARLEN_6_BIT
;
cval
|=
CDNS_UART
_MR_CHARLEN_6_BIT
;
break
;
break
;
case
CS7
:
case
CS7
:
cval
|=
XUARTPS
_MR_CHARLEN_7_BIT
;
cval
|=
CDNS_UART
_MR_CHARLEN_7_BIT
;
break
;
break
;
default:
default:
case
CS8
:
case
CS8
:
cval
|=
XUARTPS
_MR_CHARLEN_8_BIT
;
cval
|=
CDNS_UART
_MR_CHARLEN_8_BIT
;
termios
->
c_cflag
&=
~
CSIZE
;
termios
->
c_cflag
&=
~
CSIZE
;
termios
->
c_cflag
|=
CS8
;
termios
->
c_cflag
|=
CS8
;
break
;
break
;
...
@@ -731,134 +709,135 @@ static void xuartps_set_termios(struct uart_port *port,
...
@@ -731,134 +709,135 @@ static void xuartps_set_termios(struct uart_port *port,
/* Handling Parity and Stop Bits length */
/* Handling Parity and Stop Bits length */
if
(
termios
->
c_cflag
&
CSTOPB
)
if
(
termios
->
c_cflag
&
CSTOPB
)
cval
|=
XUARTPS
_MR_STOPMODE_2_BIT
;
/* 2 STOP bits */
cval
|=
CDNS_UART
_MR_STOPMODE_2_BIT
;
/* 2 STOP bits */
else
else
cval
|=
XUARTPS
_MR_STOPMODE_1_BIT
;
/* 1 STOP bit */
cval
|=
CDNS_UART
_MR_STOPMODE_1_BIT
;
/* 1 STOP bit */
if
(
termios
->
c_cflag
&
PARENB
)
{
if
(
termios
->
c_cflag
&
PARENB
)
{
/* Mark or Space parity */
/* Mark or Space parity */
if
(
termios
->
c_cflag
&
CMSPAR
)
{
if
(
termios
->
c_cflag
&
CMSPAR
)
{
if
(
termios
->
c_cflag
&
PARODD
)
if
(
termios
->
c_cflag
&
PARODD
)
cval
|=
XUARTPS
_MR_PARITY_MARK
;
cval
|=
CDNS_UART
_MR_PARITY_MARK
;
else
else
cval
|=
XUARTPS
_MR_PARITY_SPACE
;
cval
|=
CDNS_UART
_MR_PARITY_SPACE
;
}
else
{
}
else
{
if
(
termios
->
c_cflag
&
PARODD
)
if
(
termios
->
c_cflag
&
PARODD
)
cval
|=
XUARTPS
_MR_PARITY_ODD
;
cval
|=
CDNS_UART
_MR_PARITY_ODD
;
else
else
cval
|=
XUARTPS
_MR_PARITY_EVEN
;
cval
|=
CDNS_UART
_MR_PARITY_EVEN
;
}
}
}
else
{
}
else
{
cval
|=
XUARTPS
_MR_PARITY_NONE
;
cval
|=
CDNS_UART
_MR_PARITY_NONE
;
}
}
cval
|=
mode_reg
&
1
;
cval
|=
mode_reg
&
1
;
xuartps_writel
(
cval
,
XUARTPS
_MR_OFFSET
);
cdns_uart_writel
(
cval
,
CDNS_UART
_MR_OFFSET
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
}
}
/**
/**
*
xuartps_startup - Called when an application opens a xuartps
port
*
cdns_uart_startup - Called when an application opens a cdns_uart
port
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*
* Return
s 0 on success, negative error
otherwise
* Return
: 0 on success, negative errno
otherwise
*
*
/
*/
static
int
xuartps
_startup
(
struct
uart_port
*
port
)
static
int
cdns_uart
_startup
(
struct
uart_port
*
port
)
{
{
unsigned
int
retval
=
0
,
status
=
0
;
unsigned
int
retval
=
0
,
status
=
0
;
retval
=
request_irq
(
port
->
irq
,
xuartps_isr
,
0
,
XUARTPS
_NAME
,
retval
=
request_irq
(
port
->
irq
,
cdns_uart_isr
,
0
,
CDNS_UART
_NAME
,
(
void
*
)
port
);
(
void
*
)
port
);
if
(
retval
)
if
(
retval
)
return
retval
;
return
retval
;
/* Disable the TX and RX */
/* Disable the TX and RX */
xuartps_writel
(
XUARTPS_CR_TX_DIS
|
XUARTPS
_CR_RX_DIS
,
cdns_uart_writel
(
CDNS_UART_CR_TX_DIS
|
CDNS_UART
_CR_RX_DIS
,
XUARTPS
_CR_OFFSET
);
CDNS_UART
_CR_OFFSET
);
/* Set the Control Register with TX/RX Enable, TX/RX Reset,
/* Set the Control Register with TX/RX Enable, TX/RX Reset,
* no break chars.
* no break chars.
*/
*/
xuartps_writel
(
XUARTPS_CR_TXRST
|
XUARTPS
_CR_RXRST
,
cdns_uart_writel
(
CDNS_UART_CR_TXRST
|
CDNS_UART
_CR_RXRST
,
XUARTPS
_CR_OFFSET
);
CDNS_UART
_CR_OFFSET
);
status
=
xuartps_readl
(
XUARTPS
_CR_OFFSET
);
status
=
cdns_uart_readl
(
CDNS_UART
_CR_OFFSET
);
/* Clear the RX disable and TX disable bits and then set the TX enable
/* Clear the RX disable and TX disable bits and then set the TX enable
* bit and RX enable bit to enable the transmitter and receiver.
* bit and RX enable bit to enable the transmitter and receiver.
*/
*/
xuartps_writel
((
status
&
~
(
XUARTPS_CR_TX_DIS
|
XUARTPS
_CR_RX_DIS
))
cdns_uart_writel
((
status
&
~
(
CDNS_UART_CR_TX_DIS
|
CDNS_UART
_CR_RX_DIS
))
|
(
XUARTPS_CR_TX_EN
|
XUARTPS
_CR_RX_EN
|
|
(
CDNS_UART_CR_TX_EN
|
CDNS_UART
_CR_RX_EN
|
XUARTPS_CR_STOPBRK
),
XUARTPS
_CR_OFFSET
);
CDNS_UART_CR_STOPBRK
),
CDNS_UART
_CR_OFFSET
);
/* Set the Mode Register with normal mode,8 data bits,1 stop bit,
/* Set the Mode Register with normal mode,8 data bits,1 stop bit,
* no parity.
* no parity.
*/
*/
xuartps_writel
(
XUARTPS_MR_CHMODE_NORM
|
XUARTPS
_MR_STOPMODE_1_BIT
cdns_uart_writel
(
CDNS_UART_MR_CHMODE_NORM
|
CDNS_UART
_MR_STOPMODE_1_BIT
|
XUARTPS_MR_PARITY_NONE
|
XUARTPS
_MR_CHARLEN_8_BIT
,
|
CDNS_UART_MR_PARITY_NONE
|
CDNS_UART
_MR_CHARLEN_8_BIT
,
XUARTPS
_MR_OFFSET
);
CDNS_UART
_MR_OFFSET
);
/*
/*
* Set the RX FIFO Trigger level to use most of the FIFO, but it
* Set the RX FIFO Trigger level to use most of the FIFO, but it
* can be tuned with a module parameter
* can be tuned with a module parameter
*/
*/
xuartps_writel
(
rx_trigger_level
,
XUARTPS
_RXWM_OFFSET
);
cdns_uart_writel
(
rx_trigger_level
,
CDNS_UART
_RXWM_OFFSET
);
/*
/*
* Receive Timeout register is enabled but it
* Receive Timeout register is enabled but it
* can be tuned with a module parameter
* can be tuned with a module parameter
*/
*/
xuartps_writel
(
rx_timeout
,
XUARTPS
_RXTOUT_OFFSET
);
cdns_uart_writel
(
rx_timeout
,
CDNS_UART
_RXTOUT_OFFSET
);
/* Clear out any pending interrupts before enabling them */
/* Clear out any pending interrupts before enabling them */
xuartps_writel
(
xuartps_readl
(
XUARTPS_ISR_OFFSET
),
XUARTPS_ISR_OFFSET
);
cdns_uart_writel
(
cdns_uart_readl
(
CDNS_UART_ISR_OFFSET
),
CDNS_UART_ISR_OFFSET
);
/* Set the Interrupt Registers with desired interrupts */
/* Set the Interrupt Registers with desired interrupts */
xuartps_writel
(
XUARTPS_IXR_TXEMPTY
|
XUARTPS_IXR_PARITY
|
cdns_uart_writel
(
CDNS_UART_IXR_TXEMPTY
|
CDNS_UART_IXR_PARITY
|
XUARTPS_IXR_FRAMING
|
XUARTPS_IXR_OVERRUN
|
CDNS_UART_IXR_FRAMING
|
CDNS_UART_IXR_OVERRUN
|
XUARTPS_IXR_RXTRIG
|
XUARTPS_IXR_TOUT
,
XUARTPS_IER_OFFSET
);
CDNS_UART_IXR_RXTRIG
|
CDNS_UART_IXR_TOUT
,
CDNS_UART_IER_OFFSET
);
return
retval
;
return
retval
;
}
}
/**
/**
*
xuartps_shutdown - Called when an application closes a xuartps
port
*
cdns_uart_shutdown - Called when an application closes a cdns_uart
port
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*/
**/
static
void
cdns_uart_shutdown
(
struct
uart_port
*
port
)
static
void
xuartps_shutdown
(
struct
uart_port
*
port
)
{
{
int
status
;
int
status
;
/* Disable interrupts */
/* Disable interrupts */
status
=
xuartps_readl
(
XUARTPS
_IMR_OFFSET
);
status
=
cdns_uart_readl
(
CDNS_UART
_IMR_OFFSET
);
xuartps_writel
(
status
,
XUARTPS
_IDR_OFFSET
);
cdns_uart_writel
(
status
,
CDNS_UART
_IDR_OFFSET
);
/* Disable the TX and RX */
/* Disable the TX and RX */
xuartps_writel
(
XUARTPS_CR_TX_DIS
|
XUARTPS
_CR_RX_DIS
,
cdns_uart_writel
(
CDNS_UART_CR_TX_DIS
|
CDNS_UART
_CR_RX_DIS
,
XUARTPS
_CR_OFFSET
);
CDNS_UART
_CR_OFFSET
);
free_irq
(
port
->
irq
,
port
);
free_irq
(
port
->
irq
,
port
);
}
}
/**
/**
*
xuartps_type - Set UART type to xuartps
port
*
cdns_uart_type - Set UART type to cdns_uart
port
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*
* Return
s
string on success, NULL otherwise
* Return
:
string on success, NULL otherwise
*
*
/
*/
static
const
char
*
xuartps
_type
(
struct
uart_port
*
port
)
static
const
char
*
cdns_uart
_type
(
struct
uart_port
*
port
)
{
{
return
port
->
type
==
PORT_XUARTPS
?
XUARTPS
_NAME
:
NULL
;
return
port
->
type
==
PORT_XUARTPS
?
CDNS_UART
_NAME
:
NULL
;
}
}
/**
/**
*
xuartps
_verify_port - Verify the port params
*
cdns_uart
_verify_port - Verify the port params
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
* @ser: Handle to the structure whose members are compared
* @ser: Handle to the structure whose members are compared
*
*
* Return
s 0 if success otherwise -EINVAL
* Return
: 0 on success, negative errno otherwise.
*
*
/
*/
static
int
xuartps
_verify_port
(
struct
uart_port
*
port
,
static
int
cdns_uart
_verify_port
(
struct
uart_port
*
port
,
struct
serial_struct
*
ser
)
struct
serial_struct
*
ser
)
{
{
if
(
ser
->
type
!=
PORT_UNKNOWN
&&
ser
->
type
!=
PORT_XUARTPS
)
if
(
ser
->
type
!=
PORT_UNKNOWN
&&
ser
->
type
!=
PORT_XUARTPS
)
...
@@ -875,187 +854,170 @@ static int xuartps_verify_port(struct uart_port *port,
...
@@ -875,187 +854,170 @@ static int xuartps_verify_port(struct uart_port *port,
}
}
/**
/**
*
xuartps_request_port - Claim the memory region attached to xuartps
port,
*
cdns_uart_request_port - Claim the memory region attached to cdns_uart
port,
* called when the driver adds a
xuartps
port via
* called when the driver adds a
cdns_uart
port via
* uart_add_one_port()
* uart_add_one_port()
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*
* Return
s 0, -ENOMEM if request fails
* Return
: 0 on success, negative errno otherwise.
*
*
/
*/
static
int
xuartps
_request_port
(
struct
uart_port
*
port
)
static
int
cdns_uart
_request_port
(
struct
uart_port
*
port
)
{
{
if
(
!
request_mem_region
(
port
->
mapbase
,
XUARTPS
_REGISTER_SPACE
,
if
(
!
request_mem_region
(
port
->
mapbase
,
CDNS_UART
_REGISTER_SPACE
,
XUARTPS
_NAME
))
{
CDNS_UART
_NAME
))
{
return
-
ENOMEM
;
return
-
ENOMEM
;
}
}
port
->
membase
=
ioremap
(
port
->
mapbase
,
XUARTPS
_REGISTER_SPACE
);
port
->
membase
=
ioremap
(
port
->
mapbase
,
CDNS_UART
_REGISTER_SPACE
);
if
(
!
port
->
membase
)
{
if
(
!
port
->
membase
)
{
dev_err
(
port
->
dev
,
"Unable to map registers
\n
"
);
dev_err
(
port
->
dev
,
"Unable to map registers
\n
"
);
release_mem_region
(
port
->
mapbase
,
XUARTPS
_REGISTER_SPACE
);
release_mem_region
(
port
->
mapbase
,
CDNS_UART
_REGISTER_SPACE
);
return
-
ENOMEM
;
return
-
ENOMEM
;
}
}
return
0
;
return
0
;
}
}
/**
/**
* xuartps_release_port - Release the memory region attached to a xuartps
* cdns_uart_release_port - Release UART port
* port, called when the driver removes a xuartps
* port via uart_remove_one_port().
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*
**/
* Release the memory region attached to a cdns_uart port. Called when the
static
void
xuartps_release_port
(
struct
uart_port
*
port
)
* driver removes a cdns_uart port via uart_remove_one_port().
*/
static
void
cdns_uart_release_port
(
struct
uart_port
*
port
)
{
{
release_mem_region
(
port
->
mapbase
,
XUARTPS
_REGISTER_SPACE
);
release_mem_region
(
port
->
mapbase
,
CDNS_UART
_REGISTER_SPACE
);
iounmap
(
port
->
membase
);
iounmap
(
port
->
membase
);
port
->
membase
=
NULL
;
port
->
membase
=
NULL
;
}
}
/**
/**
* xuartps_config_port - Configure xuartps, called when the driver adds a
* cdns_uart_config_port - Configure UART port
* xuartps port
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
* @flags: If any
* @flags: If any
*
*/
**/
static
void
cdns_uart_config_port
(
struct
uart_port
*
port
,
int
flags
)
static
void
xuartps_config_port
(
struct
uart_port
*
port
,
int
flags
)
{
{
if
(
flags
&
UART_CONFIG_TYPE
&&
xuartps
_request_port
(
port
)
==
0
)
if
(
flags
&
UART_CONFIG_TYPE
&&
cdns_uart
_request_port
(
port
)
==
0
)
port
->
type
=
PORT_XUARTPS
;
port
->
type
=
PORT_XUARTPS
;
}
}
/**
/**
* xuartps_get_mctrl - Get the modem control state
* cdns_uart_get_mctrl - Get the modem control state
*
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*
* Returns the modem control state
* Return: the modem control state
*
*/
**/
static
unsigned
int
cdns_uart_get_mctrl
(
struct
uart_port
*
port
)
static
unsigned
int
xuartps_get_mctrl
(
struct
uart_port
*
port
)
{
{
return
TIOCM_CTS
|
TIOCM_DSR
|
TIOCM_CAR
;
return
TIOCM_CTS
|
TIOCM_DSR
|
TIOCM_CAR
;
}
}
static
void
xuartps
_set_mctrl
(
struct
uart_port
*
port
,
unsigned
int
mctrl
)
static
void
cdns_uart
_set_mctrl
(
struct
uart_port
*
port
,
unsigned
int
mctrl
)
{
{
/* N/A */
/* N/A */
}
}
static
void
xuartps
_enable_ms
(
struct
uart_port
*
port
)
static
void
cdns_uart
_enable_ms
(
struct
uart_port
*
port
)
{
{
/* N/A */
/* N/A */
}
}
#ifdef CONFIG_CONSOLE_POLL
#ifdef CONFIG_CONSOLE_POLL
static
int
xuartps
_poll_get_char
(
struct
uart_port
*
port
)
static
int
cdns_uart
_poll_get_char
(
struct
uart_port
*
port
)
{
{
u32
imr
;
u32
imr
;
int
c
;
int
c
;
/* Disable all interrupts */
/* Disable all interrupts */
imr
=
xuartps_readl
(
XUARTPS
_IMR_OFFSET
);
imr
=
cdns_uart_readl
(
CDNS_UART
_IMR_OFFSET
);
xuartps_writel
(
imr
,
XUARTPS
_IDR_OFFSET
);
cdns_uart_writel
(
imr
,
CDNS_UART
_IDR_OFFSET
);
/* Check if FIFO is empty */
/* Check if FIFO is empty */
if
(
xuartps_readl
(
XUARTPS_SR_OFFSET
)
&
XUARTPS
_SR_RXEMPTY
)
if
(
cdns_uart_readl
(
CDNS_UART_SR_OFFSET
)
&
CDNS_UART
_SR_RXEMPTY
)
c
=
NO_POLL_CHAR
;
c
=
NO_POLL_CHAR
;
else
/* Read a character */
else
/* Read a character */
c
=
(
unsigned
char
)
xuartps_readl
(
XUARTPS
_FIFO_OFFSET
);
c
=
(
unsigned
char
)
cdns_uart_readl
(
CDNS_UART
_FIFO_OFFSET
);
/* Enable interrupts */
/* Enable interrupts */
xuartps_writel
(
imr
,
XUARTPS
_IER_OFFSET
);
cdns_uart_writel
(
imr
,
CDNS_UART
_IER_OFFSET
);
return
c
;
return
c
;
}
}
static
void
xuartps
_poll_put_char
(
struct
uart_port
*
port
,
unsigned
char
c
)
static
void
cdns_uart
_poll_put_char
(
struct
uart_port
*
port
,
unsigned
char
c
)
{
{
u32
imr
;
u32
imr
;
/* Disable all interrupts */
/* Disable all interrupts */
imr
=
xuartps_readl
(
XUARTPS
_IMR_OFFSET
);
imr
=
cdns_uart_readl
(
CDNS_UART
_IMR_OFFSET
);
xuartps_writel
(
imr
,
XUARTPS
_IDR_OFFSET
);
cdns_uart_writel
(
imr
,
CDNS_UART
_IDR_OFFSET
);
/* Wait until FIFO is empty */
/* Wait until FIFO is empty */
while
(
!
(
xuartps_readl
(
XUARTPS_SR_OFFSET
)
&
XUARTPS
_SR_TXEMPTY
))
while
(
!
(
cdns_uart_readl
(
CDNS_UART_SR_OFFSET
)
&
CDNS_UART
_SR_TXEMPTY
))
cpu_relax
();
cpu_relax
();
/* Write a character */
/* Write a character */
xuartps_writel
(
c
,
XUARTPS
_FIFO_OFFSET
);
cdns_uart_writel
(
c
,
CDNS_UART
_FIFO_OFFSET
);
/* Wait until FIFO is empty */
/* Wait until FIFO is empty */
while
(
!
(
xuartps_readl
(
XUARTPS_SR_OFFSET
)
&
XUARTPS
_SR_TXEMPTY
))
while
(
!
(
cdns_uart_readl
(
CDNS_UART_SR_OFFSET
)
&
CDNS_UART
_SR_TXEMPTY
))
cpu_relax
();
cpu_relax
();
/* Enable interrupts */
/* Enable interrupts */
xuartps_writel
(
imr
,
XUARTPS
_IER_OFFSET
);
cdns_uart_writel
(
imr
,
CDNS_UART
_IER_OFFSET
);
return
;
return
;
}
}
#endif
#endif
/** The UART operations structure
static
struct
uart_ops
cdns_uart_ops
=
{
*/
.
set_mctrl
=
cdns_uart_set_mctrl
,
static
struct
uart_ops
xuartps_ops
=
{
.
get_mctrl
=
cdns_uart_get_mctrl
,
.
set_mctrl
=
xuartps_set_mctrl
,
.
enable_ms
=
cdns_uart_enable_ms
,
.
get_mctrl
=
xuartps_get_mctrl
,
.
start_tx
=
cdns_uart_start_tx
,
.
enable_ms
=
xuartps_enable_ms
,
.
stop_tx
=
cdns_uart_stop_tx
,
.
stop_rx
=
cdns_uart_stop_rx
,
.
start_tx
=
xuartps_start_tx
,
/* Start transmitting */
.
tx_empty
=
cdns_uart_tx_empty
,
.
stop_tx
=
xuartps_stop_tx
,
/* Stop transmission */
.
break_ctl
=
cdns_uart_break_ctl
,
.
stop_rx
=
xuartps_stop_rx
,
/* Stop reception */
.
set_termios
=
cdns_uart_set_termios
,
.
tx_empty
=
xuartps_tx_empty
,
/* Transmitter busy? */
.
startup
=
cdns_uart_startup
,
.
break_ctl
=
xuartps_break_ctl
,
/* Start/stop
.
shutdown
=
cdns_uart_shutdown
,
* transmitting break
.
type
=
cdns_uart_type
,
*/
.
verify_port
=
cdns_uart_verify_port
,
.
set_termios
=
xuartps_set_termios
,
/* Set termios */
.
request_port
=
cdns_uart_request_port
,
.
startup
=
xuartps_startup
,
/* App opens xuartps */
.
release_port
=
cdns_uart_release_port
,
.
shutdown
=
xuartps_shutdown
,
/* App closes xuartps */
.
config_port
=
cdns_uart_config_port
,
.
type
=
xuartps_type
,
/* Set UART type */
.
verify_port
=
xuartps_verify_port
,
/* Verification of port
* params
*/
.
request_port
=
xuartps_request_port
,
/* Claim resources
* associated with a
* xuartps port
*/
.
release_port
=
xuartps_release_port
,
/* Release resources
* associated with a
* xuartps port
*/
.
config_port
=
xuartps_config_port
,
/* Configure when driver
* adds a xuartps port
*/
#ifdef CONFIG_CONSOLE_POLL
#ifdef CONFIG_CONSOLE_POLL
.
poll_get_char
=
xuartps
_poll_get_char
,
.
poll_get_char
=
cdns_uart
_poll_get_char
,
.
poll_put_char
=
xuartps
_poll_put_char
,
.
poll_put_char
=
cdns_uart
_poll_put_char
,
#endif
#endif
};
};
static
struct
uart_port
xuartps
_port
[
2
];
static
struct
uart_port
cdns_uart
_port
[
2
];
/**
/**
*
xuartps_get_port - Configure the port from the platform device resource
*
cdns_uart_get_port - Configure the port from platform device resource info
*
info
*
@id: Port id
*
*
* Return
s
a pointer to a uart_port or NULL for failure
* Return
:
a pointer to a uart_port or NULL for failure
*
*
/
*/
static
struct
uart_port
*
xuartps_get_port
(
vo
id
)
static
struct
uart_port
*
cdns_uart_get_port
(
int
id
)
{
{
struct
uart_port
*
port
;
struct
uart_port
*
port
;
int
id
;
/* Try the given port id if failed use default method */
if
(
cdns_uart_port
[
id
].
mapbase
!=
0
)
{
/* Find the next unused port */
/* Find the next unused port */
for
(
id
=
0
;
id
<
XUARTPS
_NR_PORTS
;
id
++
)
for
(
id
=
0
;
id
<
CDNS_UART
_NR_PORTS
;
id
++
)
if
(
xuartps
_port
[
id
].
mapbase
==
0
)
if
(
cdns_uart
_port
[
id
].
mapbase
==
0
)
break
;
break
;
}
if
(
id
>=
XUARTPS
_NR_PORTS
)
if
(
id
>=
CDNS_UART
_NR_PORTS
)
return
NULL
;
return
NULL
;
port
=
&
xuartps
_port
[
id
];
port
=
&
cdns_uart
_port
[
id
];
/* At this point, we've got an empty uart_port struct, initialize it */
/* At this point, we've got an empty uart_port struct, initialize it */
spin_lock_init
(
&
port
->
lock
);
spin_lock_init
(
&
port
->
lock
);
...
@@ -1065,50 +1027,46 @@ static struct uart_port *xuartps_get_port(void)
...
@@ -1065,50 +1027,46 @@ static struct uart_port *xuartps_get_port(void)
port
->
type
=
PORT_UNKNOWN
;
port
->
type
=
PORT_UNKNOWN
;
port
->
iotype
=
UPIO_MEM32
;
port
->
iotype
=
UPIO_MEM32
;
port
->
flags
=
UPF_BOOT_AUTOCONF
;
port
->
flags
=
UPF_BOOT_AUTOCONF
;
port
->
ops
=
&
xuartps
_ops
;
port
->
ops
=
&
cdns_uart
_ops
;
port
->
fifosize
=
XUARTPS
_FIFO_SIZE
;
port
->
fifosize
=
CDNS_UART
_FIFO_SIZE
;
port
->
line
=
id
;
port
->
line
=
id
;
port
->
dev
=
NULL
;
port
->
dev
=
NULL
;
return
port
;
return
port
;
}
}
/*-----------------------Console driver operations--------------------------*/
#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
/**
/**
*
xuartps
_console_wait_tx - Wait for the TX to be full
*
cdns_uart
_console_wait_tx - Wait for the TX to be full
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
*
*/
**/
static
void
cdns_uart_console_wait_tx
(
struct
uart_port
*
port
)
static
void
xuartps_console_wait_tx
(
struct
uart_port
*
port
)
{
{
while
((
xuartps_readl
(
XUARTPS_SR_OFFSET
)
&
XUARTPS
_SR_TXEMPTY
)
while
((
cdns_uart_readl
(
CDNS_UART_SR_OFFSET
)
&
CDNS_UART
_SR_TXEMPTY
)
!=
XUARTPS
_SR_TXEMPTY
)
!=
CDNS_UART
_SR_TXEMPTY
)
barrier
();
barrier
();
}
}
/**
/**
*
xuartps
_console_putchar - write the character to the FIFO buffer
*
cdns_uart
_console_putchar - write the character to the FIFO buffer
* @port: Handle to the uart port structure
* @port: Handle to the uart port structure
* @ch: Character to be written
* @ch: Character to be written
*
*/
**/
static
void
cdns_uart_console_putchar
(
struct
uart_port
*
port
,
int
ch
)
static
void
xuartps_console_putchar
(
struct
uart_port
*
port
,
int
ch
)
{
{
xuartps
_console_wait_tx
(
port
);
cdns_uart
_console_wait_tx
(
port
);
xuartps_writel
(
ch
,
XUARTPS
_FIFO_OFFSET
);
cdns_uart_writel
(
ch
,
CDNS_UART
_FIFO_OFFSET
);
}
}
/**
/**
*
xuartps
_console_write - perform write operation
*
cdns_uart
_console_write - perform write operation
* @
port: Handle to the uart port structur
e
* @
co: Console handl
e
* @s: Pointer to character array
* @s: Pointer to character array
* @count: No of characters
* @count: No of characters
*
*
/
*/
static
void
xuartps
_console_write
(
struct
console
*
co
,
const
char
*
s
,
static
void
cdns_uart
_console_write
(
struct
console
*
co
,
const
char
*
s
,
unsigned
int
count
)
unsigned
int
count
)
{
{
struct
uart_port
*
port
=
&
xuartps
_port
[
co
->
index
];
struct
uart_port
*
port
=
&
cdns_uart
_port
[
co
->
index
];
unsigned
long
flags
;
unsigned
long
flags
;
unsigned
int
imr
,
ctrl
;
unsigned
int
imr
,
ctrl
;
int
locked
=
1
;
int
locked
=
1
;
...
@@ -1119,49 +1077,45 @@ static void xuartps_console_write(struct console *co, const char *s,
...
@@ -1119,49 +1077,45 @@ static void xuartps_console_write(struct console *co, const char *s,
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
/* save and disable interrupt */
/* save and disable interrupt */
imr
=
xuartps_readl
(
XUARTPS
_IMR_OFFSET
);
imr
=
cdns_uart_readl
(
CDNS_UART
_IMR_OFFSET
);
xuartps_writel
(
imr
,
XUARTPS
_IDR_OFFSET
);
cdns_uart_writel
(
imr
,
CDNS_UART
_IDR_OFFSET
);
/*
/*
* Make sure that the tx part is enabled. Set the TX enable bit and
* Make sure that the tx part is enabled. Set the TX enable bit and
* clear the TX disable bit to enable the transmitter.
* clear the TX disable bit to enable the transmitter.
*/
*/
ctrl
=
xuartps_readl
(
XUARTPS
_CR_OFFSET
);
ctrl
=
cdns_uart_readl
(
CDNS_UART
_CR_OFFSET
);
xuartps_writel
((
ctrl
&
~
XUARTPS_CR_TX_DIS
)
|
XUARTPS
_CR_TX_EN
,
cdns_uart_writel
((
ctrl
&
~
CDNS_UART_CR_TX_DIS
)
|
CDNS_UART
_CR_TX_EN
,
XUARTPS
_CR_OFFSET
);
CDNS_UART
_CR_OFFSET
);
uart_console_write
(
port
,
s
,
count
,
xuartps
_console_putchar
);
uart_console_write
(
port
,
s
,
count
,
cdns_uart
_console_putchar
);
xuartps
_console_wait_tx
(
port
);
cdns_uart
_console_wait_tx
(
port
);
xuartps_writel
(
ctrl
,
XUARTPS
_CR_OFFSET
);
cdns_uart_writel
(
ctrl
,
CDNS_UART
_CR_OFFSET
);
/* restore interrupt state, it seems like there may be a h/w bug
/* restore interrupt state */
* in that the interrupt enable register should not need to be
cdns_uart_writel
(
imr
,
CDNS_UART_IER_OFFSET
);
* written based on the data sheet
*/
xuartps_writel
(
~
imr
,
XUARTPS_IDR_OFFSET
);
xuartps_writel
(
imr
,
XUARTPS_IER_OFFSET
);
if
(
locked
)
if
(
locked
)
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
}
}
/**
/**
*
xuartps
_console_setup - Initialize the uart to default config
*
cdns_uart
_console_setup - Initialize the uart to default config
* @co: Console handle
* @co: Console handle
* @options: Initial settings of uart
* @options: Initial settings of uart
*
*
* Return
s 0, -ENODEV if no device
* Return
: 0 on success, negative errno otherwise.
*
*
/
*/
static
int
__init
xuartps
_console_setup
(
struct
console
*
co
,
char
*
options
)
static
int
__init
cdns_uart
_console_setup
(
struct
console
*
co
,
char
*
options
)
{
{
struct
uart_port
*
port
=
&
xuartps
_port
[
co
->
index
];
struct
uart_port
*
port
=
&
cdns_uart
_port
[
co
->
index
];
int
baud
=
9600
;
int
baud
=
9600
;
int
bits
=
8
;
int
bits
=
8
;
int
parity
=
'n'
;
int
parity
=
'n'
;
int
flow
=
'n'
;
int
flow
=
'n'
;
if
(
co
->
index
<
0
||
co
->
index
>=
XUARTPS
_NR_PORTS
)
if
(
co
->
index
<
0
||
co
->
index
>=
CDNS_UART
_NR_PORTS
)
return
-
EINVAL
;
return
-
EINVAL
;
if
(
!
port
->
mapbase
)
{
if
(
!
port
->
mapbase
)
{
...
@@ -1175,55 +1129,53 @@ static int __init xuartps_console_setup(struct console *co, char *options)
...
@@ -1175,55 +1129,53 @@ static int __init xuartps_console_setup(struct console *co, char *options)
return
uart_set_options
(
port
,
co
,
baud
,
parity
,
bits
,
flow
);
return
uart_set_options
(
port
,
co
,
baud
,
parity
,
bits
,
flow
);
}
}
static
struct
uart_driver
xuartps
_uart_driver
;
static
struct
uart_driver
cdns_uart
_uart_driver
;
static
struct
console
xuartps
_console
=
{
static
struct
console
cdns_uart
_console
=
{
.
name
=
XUARTPS
_TTY_NAME
,
.
name
=
CDNS_UART
_TTY_NAME
,
.
write
=
xuartps
_console_write
,
.
write
=
cdns_uart
_console_write
,
.
device
=
uart_console_device
,
.
device
=
uart_console_device
,
.
setup
=
xuartps
_console_setup
,
.
setup
=
cdns_uart
_console_setup
,
.
flags
=
CON_PRINTBUFFER
,
.
flags
=
CON_PRINTBUFFER
,
.
index
=
-
1
,
/* Specified on the cmdline (e.g. console=ttyPS ) */
.
index
=
-
1
,
/* Specified on the cmdline (e.g. console=ttyPS ) */
.
data
=
&
xuartps
_uart_driver
,
.
data
=
&
cdns_uart
_uart_driver
,
};
};
/**
/**
*
xuartps
_console_init - Initialization call
*
cdns_uart
_console_init - Initialization call
*
*
* Return
s 0 on success, negative error
otherwise
* Return
: 0 on success, negative errno
otherwise
*
*
/
*/
static
int
__init
xuartps
_console_init
(
void
)
static
int
__init
cdns_uart
_console_init
(
void
)
{
{
register_console
(
&
xuartps
_console
);
register_console
(
&
cdns_uart
_console
);
return
0
;
return
0
;
}
}
console_initcall
(
xuartps
_console_init
);
console_initcall
(
cdns_uart
_console_init
);
#endif
/* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
#endif
/* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
/** Structure Definitions
static
struct
uart_driver
cdns_uart_uart_driver
=
{
*/
.
owner
=
THIS_MODULE
,
static
struct
uart_driver
xuartps_uart_driver
=
{
.
driver_name
=
CDNS_UART_NAME
,
.
owner
=
THIS_MODULE
,
/* Owner */
.
dev_name
=
CDNS_UART_TTY_NAME
,
.
driver_name
=
XUARTPS_NAME
,
/* Driver name */
.
major
=
CDNS_UART_MAJOR
,
.
dev_name
=
XUARTPS_TTY_NAME
,
/* Node name */
.
minor
=
CDNS_UART_MINOR
,
.
major
=
XUARTPS_MAJOR
,
/* Major number */
.
nr
=
CDNS_UART_NR_PORTS
,
.
minor
=
XUARTPS_MINOR
,
/* Minor number */
.
nr
=
XUARTPS_NR_PORTS
,
/* Number of UART ports */
#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
.
cons
=
&
xuartps_console
,
/* Console */
.
cons
=
&
cdns_uart_console
,
#endif
#endif
};
};
#ifdef CONFIG_PM_SLEEP
#ifdef CONFIG_PM_SLEEP
/**
/**
*
xuartps
_suspend - suspend event
*
cdns_uart
_suspend - suspend event
* @device: Pointer to the device structure
* @device: Pointer to the device structure
*
*
* Return
s
0
* Return
:
0
*/
*/
static
int
xuartps
_suspend
(
struct
device
*
device
)
static
int
cdns_uart
_suspend
(
struct
device
*
device
)
{
{
struct
uart_port
*
port
=
dev_get_drvdata
(
device
);
struct
uart_port
*
port
=
dev_get_drvdata
(
device
);
struct
tty_struct
*
tty
;
struct
tty_struct
*
tty
;
...
@@ -1242,23 +1194,24 @@ static int xuartps_suspend(struct device *device)
...
@@ -1242,23 +1194,24 @@ static int xuartps_suspend(struct device *device)
* Call the API provided in serial_core.c file which handles
* Call the API provided in serial_core.c file which handles
* the suspend.
* the suspend.
*/
*/
uart_suspend_port
(
&
xuartps
_uart_driver
,
port
);
uart_suspend_port
(
&
cdns_uart
_uart_driver
,
port
);
if
(
console_suspend_enabled
&&
!
may_wake
)
{
if
(
console_suspend_enabled
&&
!
may_wake
)
{
struct
xuartps
*
xuartps
=
port
->
private_data
;
struct
cdns_uart
*
cdns_uart
=
port
->
private_data
;
clk_disable
(
xuartps
->
ref
clk
);
clk_disable
(
cdns_uart
->
uart
clk
);
clk_disable
(
xuartps
->
aper
clk
);
clk_disable
(
cdns_uart
->
p
clk
);
}
else
{
}
else
{
unsigned
long
flags
=
0
;
unsigned
long
flags
=
0
;
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
/* Empty the receive FIFO 1st before making changes */
/* Empty the receive FIFO 1st before making changes */
while
(
!
(
xuartps_readl
(
XUARTPS_SR_OFFSET
)
&
XUARTPS_SR_RXEMPTY
))
while
(
!
(
cdns_uart_readl
(
CDNS_UART_SR_OFFSET
)
&
xuartps_readl
(
XUARTPS_FIFO_OFFSET
);
CDNS_UART_SR_RXEMPTY
))
cdns_uart_readl
(
CDNS_UART_FIFO_OFFSET
);
/* set RX trigger level to 1 */
/* set RX trigger level to 1 */
xuartps_writel
(
1
,
XUARTPS
_RXWM_OFFSET
);
cdns_uart_writel
(
1
,
CDNS_UART
_RXWM_OFFSET
);
/* disable RX timeout interrups */
/* disable RX timeout interrups */
xuartps_writel
(
XUARTPS_IXR_TOUT
,
XUARTPS
_IDR_OFFSET
);
cdns_uart_writel
(
CDNS_UART_IXR_TOUT
,
CDNS_UART
_IDR_OFFSET
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
}
}
...
@@ -1266,12 +1219,12 @@ static int xuartps_suspend(struct device *device)
...
@@ -1266,12 +1219,12 @@ static int xuartps_suspend(struct device *device)
}
}
/**
/**
*
xuartps
_resume - Resume after a previous suspend
*
cdns_uart
_resume - Resume after a previous suspend
* @device: Pointer to the device structure
* @device: Pointer to the device structure
*
*
* Return
s
0
* Return
:
0
*/
*/
static
int
xuartps
_resume
(
struct
device
*
device
)
static
int
cdns_uart
_resume
(
struct
device
*
device
)
{
{
struct
uart_port
*
port
=
dev_get_drvdata
(
device
);
struct
uart_port
*
port
=
dev_get_drvdata
(
device
);
unsigned
long
flags
=
0
;
unsigned
long
flags
=
0
;
...
@@ -1289,87 +1242,95 @@ static int xuartps_resume(struct device *device)
...
@@ -1289,87 +1242,95 @@ static int xuartps_resume(struct device *device)
}
}
if
(
console_suspend_enabled
&&
!
may_wake
)
{
if
(
console_suspend_enabled
&&
!
may_wake
)
{
struct
xuartps
*
xuartps
=
port
->
private_data
;
struct
cdns_uart
*
cdns_uart
=
port
->
private_data
;
clk_enable
(
xuartps
->
aper
clk
);
clk_enable
(
cdns_uart
->
p
clk
);
clk_enable
(
xuartps
->
ref
clk
);
clk_enable
(
cdns_uart
->
uart
clk
);
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
/* Set TX/RX Reset */
/* Set TX/RX Reset */
xuartps_writel
(
xuartps_readl
(
XUARTPS_CR_OFFSET
)
|
ctrl_reg
=
cdns_uart_readl
(
CDNS_UART_CR_OFFSET
);
(
XUARTPS_CR_TXRST
|
XUARTPS_CR_RXRST
),
ctrl_reg
|=
CDNS_UART_CR_TXRST
|
CDNS_UART_CR_RXRST
;
XUARTPS
_CR_OFFSET
);
cdns_uart_writel
(
ctrl_reg
,
CDNS_UART
_CR_OFFSET
);
while
(
xuartps_readl
(
XUARTPS
_CR_OFFSET
)
&
while
(
cdns_uart_readl
(
CDNS_UART
_CR_OFFSET
)
&
(
XUARTPS_CR_TXRST
|
XUARTPS
_CR_RXRST
))
(
CDNS_UART_CR_TXRST
|
CDNS_UART
_CR_RXRST
))
cpu_relax
();
cpu_relax
();
/* restore rx timeout value */
/* restore rx timeout value */
xuartps_writel
(
rx_timeout
,
XUARTPS
_RXTOUT_OFFSET
);
cdns_uart_writel
(
rx_timeout
,
CDNS_UART
_RXTOUT_OFFSET
);
/* Enable Tx/Rx */
/* Enable Tx/Rx */
ctrl_reg
=
xuartps_readl
(
XUARTPS_CR_OFFSET
);
ctrl_reg
=
cdns_uart_readl
(
CDNS_UART_CR_OFFSET
);
xuartps_writel
(
ctrl_reg
&=
~
(
CDNS_UART_CR_TX_DIS
|
CDNS_UART_CR_RX_DIS
);
(
ctrl_reg
&
~
(
XUARTPS_CR_TX_DIS
|
XUARTPS_CR_RX_DIS
))
|
ctrl_reg
|=
CDNS_UART_CR_TX_EN
|
CDNS_UART_CR_RX_EN
;
(
XUARTPS_CR_TX_EN
|
XUARTPS_CR_RX_EN
),
cdns_uart_writel
(
ctrl_reg
,
CDNS_UART_CR_OFFSET
);
XUARTPS_CR_OFFSET
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
}
else
{
}
else
{
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
spin_lock_irqsave
(
&
port
->
lock
,
flags
);
/* restore original rx trigger level */
/* restore original rx trigger level */
xuartps_writel
(
rx_trigger_level
,
XUARTPS
_RXWM_OFFSET
);
cdns_uart_writel
(
rx_trigger_level
,
CDNS_UART
_RXWM_OFFSET
);
/* enable RX timeout interrupt */
/* enable RX timeout interrupt */
xuartps_writel
(
XUARTPS_IXR_TOUT
,
XUARTPS
_IER_OFFSET
);
cdns_uart_writel
(
CDNS_UART_IXR_TOUT
,
CDNS_UART
_IER_OFFSET
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
spin_unlock_irqrestore
(
&
port
->
lock
,
flags
);
}
}
return
uart_resume_port
(
&
xuartps
_uart_driver
,
port
);
return
uart_resume_port
(
&
cdns_uart
_uart_driver
,
port
);
}
}
#endif
/* ! CONFIG_PM_SLEEP */
#endif
/* ! CONFIG_PM_SLEEP */
static
SIMPLE_DEV_PM_OPS
(
xuartps_dev_pm_ops
,
xuartps_suspend
,
xuartps_resume
);
static
SIMPLE_DEV_PM_OPS
(
cdns_uart_dev_pm_ops
,
cdns_uart_suspend
,
cdns_uart_resume
);
/* ---------------------------------------------------------------------
* Platform bus binding
*/
/**
/**
*
xuartps
_probe - Platform driver probe
*
cdns_uart
_probe - Platform driver probe
* @pdev: Pointer to the platform device structure
* @pdev: Pointer to the platform device structure
*
*
* Return
s 0 on success, negative error
otherwise
* Return
: 0 on success, negative errno
otherwise
*
*
/
*/
static
int
xuartps
_probe
(
struct
platform_device
*
pdev
)
static
int
cdns_uart
_probe
(
struct
platform_device
*
pdev
)
{
{
int
rc
;
int
rc
,
id
;
struct
uart_port
*
port
;
struct
uart_port
*
port
;
struct
resource
*
res
,
*
res2
;
struct
resource
*
res
,
*
res2
;
struct
xuartps
*
xuartps
_data
;
struct
cdns_uart
*
cdns_uart
_data
;
xuartps_data
=
devm_kzalloc
(
&
pdev
->
dev
,
sizeof
(
*
xuartps
_data
),
cdns_uart_data
=
devm_kzalloc
(
&
pdev
->
dev
,
sizeof
(
*
cdns_uart
_data
),
GFP_KERNEL
);
GFP_KERNEL
);
if
(
!
xuartps
_data
)
if
(
!
cdns_uart
_data
)
return
-
ENOMEM
;
return
-
ENOMEM
;
xuartps_data
->
aperclk
=
devm_clk_get
(
&
pdev
->
dev
,
"aper_clk"
);
cdns_uart_data
->
pclk
=
devm_clk_get
(
&
pdev
->
dev
,
"pclk"
);
if
(
IS_ERR
(
xuartps_data
->
aperclk
))
{
if
(
IS_ERR
(
cdns_uart_data
->
pclk
))
{
dev_err
(
&
pdev
->
dev
,
"aper_clk clock not found.
\n
"
);
cdns_uart_data
->
pclk
=
devm_clk_get
(
&
pdev
->
dev
,
"aper_clk"
);
return
PTR_ERR
(
xuartps_data
->
aperclk
);
if
(
!
IS_ERR
(
cdns_uart_data
->
pclk
))
dev_err
(
&
pdev
->
dev
,
"clock name 'aper_clk' is deprecated.
\n
"
);
}
}
xuartps_data
->
refclk
=
devm_clk_get
(
&
pdev
->
dev
,
"ref_clk"
);
if
(
IS_ERR
(
cdns_uart_data
->
pclk
))
{
if
(
IS_ERR
(
xuartps_data
->
refclk
))
{
dev_err
(
&
pdev
->
dev
,
"pclk clock not found.
\n
"
);
dev_err
(
&
pdev
->
dev
,
"ref_clk clock not found.
\n
"
);
return
PTR_ERR
(
cdns_uart_data
->
pclk
);
return
PTR_ERR
(
xuartps_data
->
refclk
);
}
}
rc
=
clk_prepare_enable
(
xuartps_data
->
aperclk
);
cdns_uart_data
->
uartclk
=
devm_clk_get
(
&
pdev
->
dev
,
"uart_clk"
);
if
(
IS_ERR
(
cdns_uart_data
->
uartclk
))
{
cdns_uart_data
->
uartclk
=
devm_clk_get
(
&
pdev
->
dev
,
"ref_clk"
);
if
(
!
IS_ERR
(
cdns_uart_data
->
uartclk
))
dev_err
(
&
pdev
->
dev
,
"clock name 'ref_clk' is deprecated.
\n
"
);
}
if
(
IS_ERR
(
cdns_uart_data
->
uartclk
))
{
dev_err
(
&
pdev
->
dev
,
"uart_clk clock not found.
\n
"
);
return
PTR_ERR
(
cdns_uart_data
->
uartclk
);
}
rc
=
clk_prepare_enable
(
cdns_uart_data
->
pclk
);
if
(
rc
)
{
if
(
rc
)
{
dev_err
(
&
pdev
->
dev
,
"Unable to enable
APER
clock.
\n
"
);
dev_err
(
&
pdev
->
dev
,
"Unable to enable
pclk
clock.
\n
"
);
return
rc
;
return
rc
;
}
}
rc
=
clk_prepare_enable
(
xuartps_data
->
ref
clk
);
rc
=
clk_prepare_enable
(
cdns_uart_data
->
uart
clk
);
if
(
rc
)
{
if
(
rc
)
{
dev_err
(
&
pdev
->
dev
,
"Unable to enable device clock.
\n
"
);
dev_err
(
&
pdev
->
dev
,
"Unable to enable device clock.
\n
"
);
goto
err_out_clk_dis_
aper
;
goto
err_out_clk_dis_
pclk
;
}
}
res
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
res
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
...
@@ -1385,15 +1346,19 @@ static int xuartps_probe(struct platform_device *pdev)
...
@@ -1385,15 +1346,19 @@ static int xuartps_probe(struct platform_device *pdev)
}
}
#ifdef CONFIG_COMMON_CLK
#ifdef CONFIG_COMMON_CLK
xuartps
_data
->
clk_rate_change_nb
.
notifier_call
=
cdns_uart
_data
->
clk_rate_change_nb
.
notifier_call
=
xuartps
_clk_notifier_cb
;
cdns_uart
_clk_notifier_cb
;
if
(
clk_notifier_register
(
xuartps_data
->
ref
clk
,
if
(
clk_notifier_register
(
cdns_uart_data
->
uart
clk
,
&
xuartps
_data
->
clk_rate_change_nb
))
&
cdns_uart
_data
->
clk_rate_change_nb
))
dev_warn
(
&
pdev
->
dev
,
"Unable to register clock notifier.
\n
"
);
dev_warn
(
&
pdev
->
dev
,
"Unable to register clock notifier.
\n
"
);
#endif
#endif
/* Look for a serialN alias */
id
=
of_alias_get_id
(
pdev
->
dev
.
of_node
,
"serial"
);
if
(
id
<
0
)
id
=
0
;
/* Initialize the port structure */
/* Initialize the port structure */
port
=
xuartps_get_port
(
);
port
=
cdns_uart_get_port
(
id
);
if
(
!
port
)
{
if
(
!
port
)
{
dev_err
(
&
pdev
->
dev
,
"Cannot get uart_port structure
\n
"
);
dev_err
(
&
pdev
->
dev
,
"Cannot get uart_port structure
\n
"
);
...
@@ -1407,11 +1372,11 @@ static int xuartps_probe(struct platform_device *pdev)
...
@@ -1407,11 +1372,11 @@ static int xuartps_probe(struct platform_device *pdev)
port
->
mapbase
=
res
->
start
;
port
->
mapbase
=
res
->
start
;
port
->
irq
=
res2
->
start
;
port
->
irq
=
res2
->
start
;
port
->
dev
=
&
pdev
->
dev
;
port
->
dev
=
&
pdev
->
dev
;
port
->
uartclk
=
clk_get_rate
(
xuartps_data
->
ref
clk
);
port
->
uartclk
=
clk_get_rate
(
cdns_uart_data
->
uart
clk
);
port
->
private_data
=
xuartps
_data
;
port
->
private_data
=
cdns_uart
_data
;
xuartps
_data
->
port
=
port
;
cdns_uart
_data
->
port
=
port
;
platform_set_drvdata
(
pdev
,
port
);
platform_set_drvdata
(
pdev
,
port
);
rc
=
uart_add_one_port
(
&
xuartps
_uart_driver
,
port
);
rc
=
uart_add_one_port
(
&
cdns_uart
_uart_driver
,
port
);
if
(
rc
)
{
if
(
rc
)
{
dev_err
(
&
pdev
->
dev
,
dev_err
(
&
pdev
->
dev
,
"uart_add_one_port() failed; err=%i
\n
"
,
rc
);
"uart_add_one_port() failed; err=%i
\n
"
,
rc
);
...
@@ -1422,103 +1387,89 @@ static int xuartps_probe(struct platform_device *pdev)
...
@@ -1422,103 +1387,89 @@ static int xuartps_probe(struct platform_device *pdev)
err_out_notif_unreg:
err_out_notif_unreg:
#ifdef CONFIG_COMMON_CLK
#ifdef CONFIG_COMMON_CLK
clk_notifier_unregister
(
xuartps_data
->
ref
clk
,
clk_notifier_unregister
(
cdns_uart_data
->
uart
clk
,
&
xuartps
_data
->
clk_rate_change_nb
);
&
cdns_uart
_data
->
clk_rate_change_nb
);
#endif
#endif
err_out_clk_disable:
err_out_clk_disable:
clk_disable_unprepare
(
xuartps_data
->
ref
clk
);
clk_disable_unprepare
(
cdns_uart_data
->
uart
clk
);
err_out_clk_dis_
aper
:
err_out_clk_dis_
pclk
:
clk_disable_unprepare
(
xuartps_data
->
aper
clk
);
clk_disable_unprepare
(
cdns_uart_data
->
p
clk
);
return
rc
;
return
rc
;
}
}
/**
/**
*
xuartps
_remove - called when the platform driver is unregistered
*
cdns_uart
_remove - called when the platform driver is unregistered
* @pdev: Pointer to the platform device structure
* @pdev: Pointer to the platform device structure
*
*
* Return
s 0 on success, negative error
otherwise
* Return
: 0 on success, negative errno
otherwise
*
*
/
*/
static
int
xuartps
_remove
(
struct
platform_device
*
pdev
)
static
int
cdns_uart
_remove
(
struct
platform_device
*
pdev
)
{
{
struct
uart_port
*
port
=
platform_get_drvdata
(
pdev
);
struct
uart_port
*
port
=
platform_get_drvdata
(
pdev
);
struct
xuartps
*
xuartps
_data
=
port
->
private_data
;
struct
cdns_uart
*
cdns_uart
_data
=
port
->
private_data
;
int
rc
;
int
rc
;
/* Remove the
xuartps
port from the serial core */
/* Remove the
cdns_uart
port from the serial core */
#ifdef CONFIG_COMMON_CLK
#ifdef CONFIG_COMMON_CLK
clk_notifier_unregister
(
xuartps_data
->
ref
clk
,
clk_notifier_unregister
(
cdns_uart_data
->
uart
clk
,
&
xuartps
_data
->
clk_rate_change_nb
);
&
cdns_uart
_data
->
clk_rate_change_nb
);
#endif
#endif
rc
=
uart_remove_one_port
(
&
xuartps
_uart_driver
,
port
);
rc
=
uart_remove_one_port
(
&
cdns_uart
_uart_driver
,
port
);
port
->
mapbase
=
0
;
port
->
mapbase
=
0
;
clk_disable_unprepare
(
xuartps_data
->
ref
clk
);
clk_disable_unprepare
(
cdns_uart_data
->
uart
clk
);
clk_disable_unprepare
(
xuartps_data
->
aper
clk
);
clk_disable_unprepare
(
cdns_uart_data
->
p
clk
);
return
rc
;
return
rc
;
}
}
/* Match table for of_platform binding */
/* Match table for of_platform binding */
static
struct
of_device_id
xuartps
_of_match
[]
=
{
static
struct
of_device_id
cdns_uart
_of_match
[]
=
{
{
.
compatible
=
"xlnx,xuartps"
,
},
{
.
compatible
=
"xlnx,xuartps"
,
},
{
.
compatible
=
"cdns,uart-r1p8"
,
},
{}
{}
};
};
MODULE_DEVICE_TABLE
(
of
,
xuartps
_of_match
);
MODULE_DEVICE_TABLE
(
of
,
cdns_uart
_of_match
);
static
struct
platform_driver
xuartps
_platform_driver
=
{
static
struct
platform_driver
cdns_uart
_platform_driver
=
{
.
probe
=
xuartps_probe
,
/* Probe method */
.
probe
=
cdns_uart_probe
,
.
remove
=
xuartps_remove
,
/* Detach method */
.
remove
=
cdns_uart_remove
,
.
driver
=
{
.
driver
=
{
.
owner
=
THIS_MODULE
,
.
owner
=
THIS_MODULE
,
.
name
=
XUARTPS_NAME
,
/* Driver name */
.
name
=
CDNS_UART_NAME
,
.
of_match_table
=
xuartps
_of_match
,
.
of_match_table
=
cdns_uart
_of_match
,
.
pm
=
&
xuartps
_dev_pm_ops
,
.
pm
=
&
cdns_uart
_dev_pm_ops
,
},
},
};
};
/* ---------------------------------------------------------------------
static
int
__init
cdns_uart_init
(
void
)
* Module Init and Exit
*/
/**
* xuartps_init - Initial driver registration call
*
* Returns whether the registration was successful or not
**/
static
int
__init
xuartps_init
(
void
)
{
{
int
retval
=
0
;
int
retval
=
0
;
/* Register the
xuartps
driver with the serial core */
/* Register the
cdns_uart
driver with the serial core */
retval
=
uart_register_driver
(
&
xuartps
_uart_driver
);
retval
=
uart_register_driver
(
&
cdns_uart
_uart_driver
);
if
(
retval
)
if
(
retval
)
return
retval
;
return
retval
;
/* Register the platform driver */
/* Register the platform driver */
retval
=
platform_driver_register
(
&
xuartps
_platform_driver
);
retval
=
platform_driver_register
(
&
cdns_uart
_platform_driver
);
if
(
retval
)
if
(
retval
)
uart_unregister_driver
(
&
xuartps
_uart_driver
);
uart_unregister_driver
(
&
cdns_uart
_uart_driver
);
return
retval
;
return
retval
;
}
}
/**
static
void
__exit
cdns_uart_exit
(
void
)
* xuartps_exit - Driver unregistration call
**/
static
void
__exit
xuartps_exit
(
void
)
{
{
/* The order of unregistration is important. Unregister the
* UART driver before the platform driver crashes the system.
*/
/* Unregister the platform driver */
/* Unregister the platform driver */
platform_driver_unregister
(
&
xuartps
_platform_driver
);
platform_driver_unregister
(
&
cdns_uart
_platform_driver
);
/* Unregister the
xuartps
driver */
/* Unregister the
cdns_uart
driver */
uart_unregister_driver
(
&
xuartps
_uart_driver
);
uart_unregister_driver
(
&
cdns_uart
_uart_driver
);
}
}
module_init
(
xuartps
_init
);
module_init
(
cdns_uart
_init
);
module_exit
(
xuartps
_exit
);
module_exit
(
cdns_uart
_exit
);
MODULE_DESCRIPTION
(
"Driver for
PS
UART"
);
MODULE_DESCRIPTION
(
"Driver for
Cadence
UART"
);
MODULE_AUTHOR
(
"Xilinx Inc."
);
MODULE_AUTHOR
(
"Xilinx Inc."
);
MODULE_LICENSE
(
"GPL"
);
MODULE_LICENSE
(
"GPL"
);
include/asm-generic/vmlinux.lds.h
View file @
728dd198
...
@@ -139,52 +139,23 @@
...
@@ -139,52 +139,23 @@
#define TRACE_SYSCALLS()
#define TRACE_SYSCALLS()
#endif
#endif
#ifdef CONFIG_CLKSRC_OF
#define CLKSRC_OF_TABLES() . = ALIGN(8); \
VMLINUX_SYMBOL(__clksrc_of_table) = .; \
*(__clksrc_of_table) \
*(__clksrc_of_table_end)
#else
#define CLKSRC_OF_TABLES()
#endif
#ifdef CONFIG_IRQCHIP
#define ___OF_TABLE(cfg, name) _OF_TABLE_##cfg(name)
#define IRQCHIP_OF_MATCH_TABLE() \
#define __OF_TABLE(cfg, name) ___OF_TABLE(cfg, name)
#define OF_TABLE(cfg, name) __OF_TABLE(config_enabled(cfg), name)
#define _OF_TABLE_0(name)
#define _OF_TABLE_1(name) \
. = ALIGN(8); \
. = ALIGN(8); \
VMLINUX_SYMBOL(__irqchip_begin) = .; \
VMLINUX_SYMBOL(__##name##_of_table) = .; \
*(__irqchip_of_table) \
*(__##name##_of_table) \
*(__irqchip_of_end)
*(__##name##_of_table_end)
#else
#define IRQCHIP_OF_MATCH_TABLE()
#endif
#ifdef CONFIG_COMMON_CLK
#define CLK_OF_TABLES() . = ALIGN(8); \
VMLINUX_SYMBOL(__clk_of_table) = .; \
*(__clk_of_table) \
*(__clk_of_table_end)
#else
#define CLK_OF_TABLES()
#endif
#ifdef CONFIG_OF_RESERVED_MEM
#define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc)
#define RESERVEDMEM_OF_TABLES() \
#define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip)
. = ALIGN(8); \
#define CLK_OF_TABLES() OF_TABLE(CONFIG_COMMON_CLK, clk)
VMLINUX_SYMBOL(__reservedmem_of_table) = .; \
#define RESERVEDMEM_OF_TABLES() OF_TABLE(CONFIG_OF_RESERVED_MEM, reservedmem)
*(__reservedmem_of_table) \
#define CPU_METHOD_OF_TABLES() OF_TABLE(CONFIG_SMP, cpu_method)
*(__reservedmem_of_table_end)
#define EARLYCON_OF_TABLES() OF_TABLE(CONFIG_SERIAL_EARLYCON, earlycon)
#else
#define RESERVEDMEM_OF_TABLES()
#endif
#ifdef CONFIG_SMP
#define CPU_METHOD_OF_TABLES() . = ALIGN(8); \
VMLINUX_SYMBOL(__cpu_method_of_table_begin) = .; \
*(__cpu_method_of_table) \
VMLINUX_SYMBOL(__cpu_method_of_table_end) = .;
#else
#define CPU_METHOD_OF_TABLES()
#endif
#define KERNEL_DTB() \
#define KERNEL_DTB() \
STRUCT_ALIGN(); \
STRUCT_ALIGN(); \
...
@@ -513,7 +484,8 @@
...
@@ -513,7 +484,8 @@
CLKSRC_OF_TABLES() \
CLKSRC_OF_TABLES() \
CPU_METHOD_OF_TABLES() \
CPU_METHOD_OF_TABLES() \
KERNEL_DTB() \
KERNEL_DTB() \
IRQCHIP_OF_MATCH_TABLE()
IRQCHIP_OF_MATCH_TABLE() \
EARLYCON_OF_TABLES()
#define INIT_TEXT \
#define INIT_TEXT \
*(.init.text) \
*(.init.text) \
...
...
include/linux/clk-provider.h
View file @
728dd198
...
@@ -498,10 +498,7 @@ struct clk_onecell_data {
...
@@ -498,10 +498,7 @@ struct clk_onecell_data {
extern
struct
of_device_id
__clk_of_table
;
extern
struct
of_device_id
__clk_of_table
;
#define CLK_OF_DECLARE(name, compat, fn) \
#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
static const struct of_device_id __clk_of_table_##name \
__used __section(__clk_of_table) \
= { .compatible = compat, .data = fn };
#ifdef CONFIG_OF
#ifdef CONFIG_OF
int
of_clk_add_provider
(
struct
device_node
*
np
,
int
of_clk_add_provider
(
struct
device_node
*
np
,
...
...
include/linux/clocksource.h
View file @
728dd198
...
@@ -339,23 +339,13 @@ extern int clocksource_mmio_init(void __iomem *, const char *,
...
@@ -339,23 +339,13 @@ extern int clocksource_mmio_init(void __iomem *, const char *,
extern
int
clocksource_i8253_init
(
void
);
extern
int
clocksource_i8253_init
(
void
);
struct
device_node
;
#define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \
typedef
void
(
*
clocksource_of_init_fn
)(
struct
device_node
*
);
OF_DECLARE_1(clksrc, name, compat, fn)
#ifdef CONFIG_CLKSRC_OF
#ifdef CONFIG_CLKSRC_OF
extern
void
clocksource_of_init
(
void
);
extern
void
clocksource_of_init
(
void
);
#define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \
static const struct of_device_id __clksrc_of_table_##name \
__used __section(__clksrc_of_table) \
= { .compatible = compat, \
.data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn }
#else
#else
static
inline
void
clocksource_of_init
(
void
)
{}
static
inline
void
clocksource_of_init
(
void
)
{}
#define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \
static const struct of_device_id __clksrc_of_table_##name \
__attribute__((unused)) \
= { .compatible = compat, \
.data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn }
#endif
#endif
#endif
/* _LINUX_CLOCKSOURCE_H */
#endif
/* _LINUX_CLOCKSOURCE_H */
include/linux/of.h
View file @
728dd198
...
@@ -757,4 +757,26 @@ static inline int of_get_available_child_count(const struct device_node *np)
...
@@ -757,4 +757,26 @@ static inline int of_get_available_child_count(const struct device_node *np)
return
num
;
return
num
;
}
}
#ifdef CONFIG_OF
#define _OF_DECLARE(table, name, compat, fn, fn_type) \
static const struct of_device_id __of_table_##name \
__used __section(__##table##_of_table) \
= { .compatible = compat, \
.data = (fn == (fn_type)NULL) ? fn : fn }
#else
#define _OF_DECLARE(table, name, compat, fn, fn_type) \
static const struct of_device_id __of_table_##name \
__attribute__((unused)) \
= { .compatible = compat, \
.data = (fn == (fn_type)NULL) ? fn : fn }
#endif
typedef
int
(
*
of_init_fn_2
)(
struct
device_node
*
,
struct
device_node
*
);
typedef
void
(
*
of_init_fn_1
)(
struct
device_node
*
);
#define OF_DECLARE_1(table, name, compat, fn) \
_OF_DECLARE(table, name, compat, fn, of_init_fn_1)
#define OF_DECLARE_2(table, name, compat, fn) \
_OF_DECLARE(table, name, compat, fn, of_init_fn_2)
#endif
/* _LINUX_OF_H */
#endif
/* _LINUX_OF_H */
include/linux/of_fdt.h
View file @
728dd198
...
@@ -83,6 +83,7 @@ extern void unflatten_device_tree(void);
...
@@ -83,6 +83,7 @@ extern void unflatten_device_tree(void);
extern
void
unflatten_and_copy_device_tree
(
void
);
extern
void
unflatten_and_copy_device_tree
(
void
);
extern
void
early_init_devtree
(
void
*
);
extern
void
early_init_devtree
(
void
*
);
extern
void
early_get_first_memblock_info
(
void
*
,
phys_addr_t
*
);
extern
void
early_get_first_memblock_info
(
void
*
,
phys_addr_t
*
);
extern
u64
fdt_translate_address
(
const
void
*
blob
,
int
node_offset
);
#else
/* CONFIG_OF_FLATTREE */
#else
/* CONFIG_OF_FLATTREE */
static
inline
void
early_init_fdt_scan_reserved_mem
(
void
)
{}
static
inline
void
early_init_fdt_scan_reserved_mem
(
void
)
{}
static
inline
const
char
*
of_flat_dt_get_machine_name
(
void
)
{
return
NULL
;
}
static
inline
const
char
*
of_flat_dt_get_machine_name
(
void
)
{
return
NULL
;
}
...
...
include/linux/of_reserved_mem.h
View file @
728dd198
...
@@ -21,33 +21,19 @@ struct reserved_mem_ops {
...
@@ -21,33 +21,19 @@ struct reserved_mem_ops {
struct
device
*
dev
);
struct
device
*
dev
);
};
};
typedef
int
(
*
reservedmem_of_init_fn
)(
struct
reserved_mem
*
rmem
,
typedef
int
(
*
reservedmem_of_init_fn
)(
struct
reserved_mem
*
rmem
);
unsigned
long
node
,
const
char
*
uname
);
#define RESERVEDMEM_OF_DECLARE(name, compat, init) \
_OF_DECLARE(reservedmem, name, compat, init, reservedmem_of_init_fn)
#ifdef CONFIG_OF_RESERVED_MEM
#ifdef CONFIG_OF_RESERVED_MEM
void
fdt_init_reserved_mem
(
void
);
void
fdt_init_reserved_mem
(
void
);
void
fdt_reserved_mem_save_node
(
unsigned
long
node
,
const
char
*
uname
,
void
fdt_reserved_mem_save_node
(
unsigned
long
node
,
const
char
*
uname
,
phys_addr_t
base
,
phys_addr_t
size
);
phys_addr_t
base
,
phys_addr_t
size
);
#define RESERVEDMEM_OF_DECLARE(name, compat, init) \
static const struct of_device_id __reservedmem_of_table_##name \
__used __section(__reservedmem_of_table) \
= { .compatible = compat, \
.data = (init == (reservedmem_of_init_fn)NULL) ? \
init : init }
#else
#else
static
inline
void
fdt_init_reserved_mem
(
void
)
{
}
static
inline
void
fdt_init_reserved_mem
(
void
)
{
}
static
inline
void
fdt_reserved_mem_save_node
(
unsigned
long
node
,
static
inline
void
fdt_reserved_mem_save_node
(
unsigned
long
node
,
const
char
*
uname
,
phys_addr_t
base
,
phys_addr_t
size
)
{
}
const
char
*
uname
,
phys_addr_t
base
,
phys_addr_t
size
)
{
}
#define RESERVEDMEM_OF_DECLARE(name, compat, init) \
static const struct of_device_id __reservedmem_of_table_##name \
__attribute__((unused)) \
= { .compatible = compat, \
.data = (init == (reservedmem_of_init_fn)NULL) ? \
init : init }
#endif
#endif
#endif
/* __OF_RESERVED_MEM_H */
#endif
/* __OF_RESERVED_MEM_H */
include/linux/serial_core.h
View file @
728dd198
...
@@ -285,6 +285,28 @@ static inline int uart_poll_timeout(struct uart_port *port)
...
@@ -285,6 +285,28 @@ static inline int uart_poll_timeout(struct uart_port *port)
/*
/*
* Console helpers.
* Console helpers.
*/
*/
struct
earlycon_device
{
struct
console
*
con
;
struct
uart_port
port
;
char
options
[
16
];
/* e.g., 115200n8 */
unsigned
int
baud
;
};
int
setup_earlycon
(
char
*
buf
,
const
char
*
match
,
int
(
*
setup
)(
struct
earlycon_device
*
,
const
char
*
));
extern
int
of_setup_earlycon
(
unsigned
long
addr
,
int
(
*
setup
)(
struct
earlycon_device
*
,
const
char
*
));
#define EARLYCON_DECLARE(name, func) \
static int __init name ## _setup_earlycon(char *buf) \
{ \
return setup_earlycon(buf, __stringify(name), func); \
} \
early_param("earlycon", name ## _setup_earlycon);
#define OF_EARLYCON_DECLARE(name, compat, fn) \
_OF_DECLARE(earlycon, name, compat, fn, void *)
struct
uart_port
*
uart_get_console
(
struct
uart_port
*
ports
,
int
nr
,
struct
uart_port
*
uart_get_console
(
struct
uart_port
*
ports
,
int
nr
,
struct
console
*
c
);
struct
console
*
c
);
void
uart_parse_options
(
char
*
options
,
int
*
baud
,
int
*
parity
,
int
*
bits
,
void
uart_parse_options
(
char
*
options
,
int
*
baud
,
int
*
parity
,
int
*
bits
,
...
...
include/linux/tty_ldisc.h
View file @
728dd198
...
@@ -92,7 +92,10 @@
...
@@ -92,7 +92,10 @@
* This function is called by the low-level tty driver to signal
* This function is called by the low-level tty driver to signal
* that line discpline should try to send more characters to the
* that line discpline should try to send more characters to the
* low-level driver for transmission. If the line discpline does
* low-level driver for transmission. If the line discpline does
* not have any more data to send, it can just return.
* not have any more data to send, it can just return. If the line
* discipline does have some data to send, please arise a tasklet
* or workqueue to do the real data transfer. Do not send data in
* this hook, it may leads to a deadlock.
*
*
* int (*hangup)(struct tty_struct *)
* int (*hangup)(struct tty_struct *)
*
*
...
...
include/uapi/linux/serial_core.h
View file @
728dd198
...
@@ -211,7 +211,7 @@
...
@@ -211,7 +211,7 @@
/* VIA VT8500 SoC */
/* VIA VT8500 SoC */
#define PORT_VT8500 97
#define PORT_VT8500 97
/*
Xilinx PSS
UART */
/*
Cadence (Xilinx Zynq)
UART */
#define PORT_XUARTPS 98
#define PORT_XUARTPS 98
/* Atheros AR933X SoC */
/* Atheros AR933X SoC */
...
@@ -238,4 +238,10 @@
...
@@ -238,4 +238,10 @@
/* Tilera TILE-Gx UART */
/* Tilera TILE-Gx UART */
#define PORT_TILEGX 106
#define PORT_TILEGX 106
/* MEN 16z135 UART */
#define PORT_MEN_Z135 107
/* SC16IS74xx */
#define PORT_SC16IS7XX 108
#endif
/* _UAPILINUX_SERIAL_CORE_H */
#endif
/* _UAPILINUX_SERIAL_CORE_H */
include/uapi/linux/serial_reg.h
View file @
728dd198
...
@@ -32,7 +32,7 @@
...
@@ -32,7 +32,7 @@
#define UART_IIR 2
/* In: Interrupt ID Register */
#define UART_IIR 2
/* In: Interrupt ID Register */
#define UART_IIR_NO_INT 0x01
/* No interrupts pending */
#define UART_IIR_NO_INT 0x01
/* No interrupts pending */
#define UART_IIR_ID 0x0
6
/* Mask for the interrupt ID */
#define UART_IIR_ID 0x0
e
/* Mask for the interrupt ID */
#define UART_IIR_MSI 0x00
/* Modem status interrupt */
#define UART_IIR_MSI 0x00
/* Modem status interrupt */
#define UART_IIR_THRI 0x02
/* Transmitter holding register empty */
#define UART_IIR_THRI 0x02
/* Transmitter holding register empty */
#define UART_IIR_RDI 0x04
/* Receiver data interrupt */
#define UART_IIR_RDI 0x04
/* Receiver data interrupt */
...
...
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