Commit 74cc274e authored by Tony Lindgren's avatar Tony Lindgren Committed by Russell King

[ARM PATCH] 1884/1: OMAP update 1/2: arch files

Patch from Tony Lindgren

This patch syncs the mainline kernel with the linux-omap tree.
The highlights of the patch are:
- Changed the BOOT_MEM() to use the new IO address (Tony Lindgren)
- Cleaned up interrupt handler (Juha Yrjölä)
- DMA channel linking for 1610 (Samuel Ortiz)
- GPIO fixes (Juha Yrjölä)
- IRQ fix for OMAP-730 (Kevin Hilman)
- OMAP-1510 FPGA interrupt fix (Dirk Behme)
- OMAP-1610 voltage change settings (Todd Poynor)
- Uncompress kernel serial output fixes (Tony Lindgren)
parent f4b8b484
......@@ -66,7 +66,7 @@ static void __init omap_generic_map_io(void)
MACHINE_START(OMAP_GENERIC, "Generic OMAP-1510/1610")
MAINTAINER("Tony Lindgren <tony@atomide.com>")
BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
BOOT_MEM(0x10000000, 0xfff00000, 0xfef00000)
BOOT_PARAMS(0x10000100)
MAPIO(omap_generic_map_io)
INITIRQ(omap_generic_init_irq)
......
......@@ -149,7 +149,7 @@ static void __init innovator_map_io(void)
MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
MAINTAINER("MontaVista Software, Inc.")
BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
BOOT_MEM(0x10000000, 0xfff00000, 0xfef00000)
BOOT_PARAMS(0x10000100)
MAPIO(innovator_map_io)
INITIRQ(innovator_init_irq)
......
......@@ -89,7 +89,7 @@ static void __init osk_map_io(void)
MACHINE_START(OMAP_OSK, "TI-OSK")
MAINTAINER("Dirk Behme <dirk.behme@de.bosch.com>")
BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
BOOT_MEM(0x10000000, 0xfff00000, 0xfef00000)
BOOT_PARAMS(0x10000100)
MAPIO(osk_map_io)
INITIRQ(osk_init_irq)
......
......@@ -103,7 +103,7 @@ static void __init omap_perseus2_map_io(void)
MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
MAINTAINER("Kevin Hilman <k-hilman@ti.com>")
BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
BOOT_MEM(0x10000000, 0xfff00000, 0xfef00000)
BOOT_PARAMS(0x10000100)
MAPIO(omap_perseus2_map_io)
INITIRQ(omap_perseus2_init_irq)
......
......@@ -3,6 +3,7 @@
*
* Copyright (C) 2003 Nokia Corporation
* Author: Juha Yrjl <juha.yrjola@nokia.com>
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
*
* Support functions for the OMAP internal DMA channels.
*
......@@ -34,6 +35,7 @@
static int enable_1510_mode = 0;
struct omap_dma_lch {
int next_lch;
int dev_id;
u16 saved_csr;
u16 enabled_irqs;
......@@ -154,6 +156,38 @@ void omap_start_dma(int lch)
{
u16 w;
if (!omap_dma_in_1510_mode()) {
int next_lch;
next_lch = dma_chan[lch].next_lch;
/* Enable the queue, if needed so. */
if (next_lch != -1) {
/* Clear the STOP_LNK bits */
w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(lch));
w &= ~(1 << 14);
omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(lch));
w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(next_lch));
w &= ~(1 << 14);
omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(next_lch));
/* And set the ENABLE_LNK bits */
omap_writew(next_lch | (1 << 15),
OMAP_DMA_CLNK_CTRL_REG(lch));
/* The loop case */
if (dma_chan[next_lch].next_lch == lch)
omap_writew(lch | (1 << 15),
OMAP_DMA_CLNK_CTRL_REG(next_lch));
/* Read CSR to make sure it's cleared. */
w = omap_readw(OMAP_DMA_CSR_REG(next_lch));
/* Enable some nice interrupts. */
omap_writew(dma_chan[next_lch].enabled_irqs,
OMAP_DMA_CICR_REG(next_lch));
dma_chan[next_lch].flags |= OMAP_DMA_ACTIVE;
}
}
/* Read CSR to make sure it's cleared. */
w = omap_readw(OMAP_DMA_CSR_REG(lch));
/* Enable some nice interrupts. */
......@@ -168,14 +202,37 @@ void omap_start_dma(int lch)
void omap_stop_dma(int lch)
{
u16 w;
int next_lch;
/* Disable all interrupts on the channel */
omap_writew(0, OMAP_DMA_CICR_REG(lch));
if (omap_dma_in_1510_mode()) {
w = omap_readw(OMAP_DMA_CCR_REG(lch));
w &= ~OMAP_DMA_CCR_EN;
omap_writew(w, OMAP_DMA_CCR_REG(lch));
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
return;
}
next_lch = dma_chan[lch].next_lch;
/*
* According to thw HW spec, enabling the STOP_LNK bit
* resets the CCR_EN bit at the same time.
*/
w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(lch));
w |= (1 << 14);
w = omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(lch));
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
if (next_lch != -1) {
omap_writew(0, OMAP_DMA_CICR_REG(next_lch));
w = omap_readw(OMAP_DMA_CLNK_CTRL_REG(next_lch));
w |= (1 << 14);
w = omap_writew(w, OMAP_DMA_CLNK_CTRL_REG(next_lch));
dma_chan[next_lch].flags &= ~OMAP_DMA_ACTIVE;
}
}
void omap_enable_dma_irq(int lch, u16 bits)
......@@ -315,6 +372,56 @@ int omap_dma_in_1510_mode(void)
return enable_1510_mode;
}
/*
* lch_queue DMA will start right after lch_head one is finished.
* For this DMA link to start, you still need to start (see omap_start_dma)
* the first one. That will fire up the entire queue.
*/
void omap_dma_link_lch (int lch_head, int lch_queue)
{
if (omap_dma_in_1510_mode()) {
printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
BUG();
return;
}
if ((dma_chan[lch_head].dev_id == -1) ||
(dma_chan[lch_queue].dev_id == -1)) {
printk(KERN_ERR "omap_dma: trying to link non requested channels\n");
dump_stack();
}
dma_chan[lch_head].next_lch = lch_queue;
}
/*
* Once the DMA queue is stopped, we can destroy it.
*/
void omap_dma_unlink_lch (int lch_head, int lch_queue)
{
if (omap_dma_in_1510_mode()) {
printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
BUG();
return;
}
if (dma_chan[lch_head].next_lch != lch_queue ||
dma_chan[lch_head].next_lch == -1) {
printk(KERN_ERR "omap_dma: trying to unlink non linked channels\n");
dump_stack();
}
if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
(dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
printk(KERN_ERR "omap_dma: You need to stop the DMA channels before unlinking\n");
dump_stack();
}
dma_chan[lch_head].next_lch = -1;
dma_chan[lch_queue].next_lch = -1;
}
static struct lcd_dma_info {
spinlock_t lock;
......@@ -522,6 +629,8 @@ static int __init omap_init_dma(void)
for (ch = 0; ch < dma_chan_count; ch++) {
dma_chan[ch].dev_id = -1;
dma_chan[ch].next_lch = -1;
if (ch >= 6 && enable_1510_mode)
continue;
......@@ -551,6 +660,8 @@ EXPORT_SYMBOL(omap_stop_dma);
EXPORT_SYMBOL(omap_set_dma_transfer_params);
EXPORT_SYMBOL(omap_set_dma_src_params);
EXPORT_SYMBOL(omap_set_dma_dest_params);
EXPORT_SYMBOL(omap_dma_link_lch);
EXPORT_SYMBOL(omap_dma_unlink_lch);
EXPORT_SYMBOL(omap_request_lcd_dma);
EXPORT_SYMBOL(omap_free_lcd_dma);
......
......@@ -587,15 +587,15 @@ static void gpio_ack_irq(unsigned int irq)
#ifdef CONFIG_ARCH_OMAP1510
if (bank->method == METHOD_GPIO_1510)
omap_writew(1 << gpio, bank->base + OMAP1510_GPIO_INT_STATUS);
omap_writew(1 << (gpio & 0x0f), bank->base + OMAP1510_GPIO_INT_STATUS);
#endif
#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
if (bank->method == METHOD_GPIO_1610)
omap_writew(1 << gpio, bank->base + OMAP1610_GPIO_IRQSTATUS1);
omap_writew(1 << (gpio & 0x0f), bank->base + OMAP1610_GPIO_IRQSTATUS1);
#endif
#ifdef CONFIG_ARCH_OMAP730
if (bank->method == METHOD_GPIO_730)
omap_writel(1 << gpio, bank->base + OMAP730_GPIO_INT_STATUS);
omap_writel(1 << (gpio & 0x1f), bank->base + OMAP730_GPIO_INT_STATUS);
#endif
}
......
......@@ -5,6 +5,7 @@
*
* Copyright (C) 2004 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
* Major cleanups by Juha Yrjl <juha.yrjola@nokia.com>
*
* Completely re-written to support various OMAP chips with bank specific
* interrupt handlers.
......@@ -49,10 +50,16 @@
#include <asm/io.h>
#include "irq.h"
#define IRQ_BANK(irq) ((irq) >> 5)
#define IRQ_BIT(irq) ((irq) & 0x1f)
static unsigned int banks = 0;
static struct omap_irq_bank irq_banks[MAX_NR_IRQ_BANKS];
struct omap_irq_bank {
unsigned long base_reg;
unsigned long trigger_map;
};
static unsigned int irq_bank_count = 0;
static struct omap_irq_bank *irq_banks;
static inline unsigned int irq_bank_readl(int bank, int offset)
{
......@@ -64,10 +71,7 @@ static inline void irq_bank_writel(unsigned long value, int bank, int offset)
omap_writel(value, irq_banks[bank].base_reg + offset);
}
/*
* Ack routine for chips with register offsets of 0x100
*/
static void omap_offset_ack_irq(unsigned int irq)
static void omap_ack_irq(unsigned int irq)
{
if (irq > 31)
omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG);
......@@ -75,83 +79,30 @@ static void omap_offset_ack_irq(unsigned int irq)
omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG);
}
/*
* Mask routine for chips with register offsets of 0x100
*/
static void omap_offset_mask_irq(unsigned int irq)
static void omap_mask_irq(unsigned int irq)
{
int bank = IRQ_TO_BANK(irq);
int bank = IRQ_BANK(irq);
u32 l;
if (bank) {
omap_writel(
omap_readl(OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR)
| (1 << IRQ_BIT(irq)),
OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR);
} else {
omap_writel(
omap_readl(OMAP_IH1_BASE + IRQ_MIR)
| (1 << IRQ_BIT(irq)),
OMAP_IH1_BASE + IRQ_MIR);
}
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR);
l |= 1 << IRQ_BIT(irq);
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR);
}
/*
* Unmask routine for chips with register offsets of 0x100
*/
static void omap_offset_unmask_irq(unsigned int irq)
static void omap_unmask_irq(unsigned int irq)
{
int bank = IRQ_TO_BANK(irq);
if (bank) {
omap_writel(
omap_readl(OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR)
& ~(1 << IRQ_BIT(irq)),
OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR);
} else {
omap_writel(
omap_readl(OMAP_IH1_BASE + IRQ_MIR)
& ~(1 << IRQ_BIT(irq)),
OMAP_IH1_BASE + IRQ_MIR);
}
}
int bank = IRQ_BANK(irq);
u32 l;
static void omap_offset_mask_ack_irq(unsigned int irq)
{
omap_offset_mask_irq(irq);
omap_offset_ack_irq(irq);
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR);
l &= ~(1 << IRQ_BIT(irq));
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR);
}
/*
* Given the irq number returns the bank number
*/
signed int irq_get_bank(unsigned int irq)
{
int i;
for (i = 0; i < banks; i++) {
if (irq >= irq_banks[i].start_irq
&& irq <= irq_banks[i].start_irq + BANK_NR_IRQS) {
return i;
}
}
printk(KERN_ERR "No irq handler found for irq %i\n", irq);
return -ENODEV;
}
/*
* Given the bank and irq number returns the irq bit at the bank register
*/
signed int irq_bank_get_bit(int bank, unsigned int irq)
static void omap_mask_ack_irq(unsigned int irq)
{
if (irq_banks[bank].start_irq > irq) {
printk(KERN_ERR "Incorrect irq %i: bank %i offset %i\n",
irq, bank, irq_banks[bank].start_irq);
return -ENODEV;
}
return irq - irq_banks[bank].start_irq;
omap_mask_irq(irq);
omap_ack_irq(irq);
}
/*
......@@ -161,114 +112,98 @@ signed int irq_bank_get_bit(int bank, unsigned int irq)
* mailing list threads on FIQ handlers if you are planning to
* add a FIQ handler for OMAP.
*/
void omap_irq_set_cfg(int irq, int fiq, int priority, int irq_level)
static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
{
signed int bank;
unsigned int irq_bit;
unsigned long val, offset;
bank = irq_get_bank(irq);
if (bank < 0)
return;
irq_bit = irq_bank_get_bit(bank, irq);
if (irq_bit < 0)
return;
/* FIQ is only availabe on bank 0 interrupts */
bank = IRQ_BANK(irq);
/* FIQ is only available on bank 0 interrupts */
fiq = bank ? 0 : (fiq & 0x1);
val = fiq | ((priority & 0x1f) << 2) | ((irq_level & 0x1) << 1);
offset = IRQ_ILR0 + irq_bit * 0x4;
val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
offset = IRQ_ILR0 + IRQ_BIT(irq) * 0x4;
irq_bank_writel(val, bank, offset);
}
static struct omap_irq_desc *irq_bank_desc[] __initdata = {
&omap730_bank0_irqs,
&omap730_bank1_irqs,
&omap730_bank2_irqs,
&omap1510_bank0_irqs,
&omap1510_bank1_irqs,
&omap1610_bank0_irqs,
&omap1610_bank1_irqs,
&omap1610_bank2_irqs,
&omap1610_bank3_irqs,
NULL,
#ifdef CONFIG_ARCH_OMAP730
static struct omap_irq_bank omap730_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
};
#endif
#ifdef CONFIG_ARCH_OMAP1510
static struct omap_irq_bank omap1510_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
};
#endif
#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
static struct omap_irq_bank omap1610_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfffff7ff },
{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xfffff7ff },
{ .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
};
#endif
static struct irqchip omap_irq_chip = {
.ack = omap_mask_ack_irq,
.mask = omap_mask_irq,
.unmask = omap_unmask_irq,
};
void __init omap_init_irq(void)
{
int i,j, board_irq_type = 0, interrupts = 0;
struct omap_irq_desc *entry;
int i, j;
#ifdef CONFIG_ARCH_OMAP730
if (cpu_is_omap730()) {
board_irq_type = OMAP_IRQ_TYPE730;
} else if (cpu_is_omap1510()) {
board_irq_type = OMAP_IRQ_TYPE1510;
} else if (cpu_is_omap1610() || cpu_is_omap5912()) {
board_irq_type = OMAP_IRQ_TYPE1610;
}
if (board_irq_type == 0) {
printk("Could not detect OMAP type\n");
return;
irq_banks = omap730_irq_banks;
irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
}
/* Scan through the interrupt bank maps and copy the right data */
for (i = 0; (entry = irq_bank_desc[i]) != NULL; i++) {
if (entry->cpu_type == board_irq_type) {
printk("Type %i IRQs from %3i to %3i base at 0x%lx\n",
board_irq_type, entry->start_irq,
entry->start_irq + BANK_NR_IRQS, entry->base_reg);
irq_banks[banks].start_irq = entry->start_irq;
irq_banks[banks].level_map = entry->level_map;
irq_banks[banks].base_reg = entry->base_reg;
irq_banks[banks].mask_reg = entry->mask_reg;
irq_banks[banks].ack_reg = entry->ack_reg;
irq_banks[banks].handler = entry->handler;
interrupts += BANK_NR_IRQS;
banks++;
#endif
#ifdef CONFIG_ARCH_OMAP1510
if (cpu_is_omap1510()) {
irq_banks = omap1510_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
}
#endif
#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
if (cpu_is_omap1610() || cpu_is_omap5912()) {
irq_banks = omap1610_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
}
printk("Found total of %i interrupts in %i interrupt banks\n",
interrupts, banks);
#endif
printk("Total of %i interrupts in %i interrupt banks\n",
irq_bank_count * 32, irq_bank_count);
/* Mask and clear all interrupts */
for (i = 0; i < banks; i++) {
for (i = 0; i < irq_bank_count; i++) {
irq_bank_writel(~0x0, i, IRQ_MIR);
irq_bank_writel(0x0, i, IRQ_ITR);
}
/*
* Clear any pending interrupts
*/
irq_bank_writel(3, 0, IRQ_CONTROL_REG);
irq_bank_writel(3, 1, IRQ_CONTROL_REG);
/* Clear any pending interrupts */
irq_bank_writel(0x03, 0, IRQ_CONTROL_REG);
irq_bank_writel(0x03, 1, IRQ_CONTROL_REG);
/* Install the interrupt handlers for each bank */
for (i = 0; i < banks; i++) {
for (j = irq_banks[i].start_irq;
j <= irq_banks[i].start_irq + BANK_NR_IRQS; j++) {
int irq_level;
set_irq_chip(j, irq_banks[i].handler);
for (i = 0; i < irq_bank_count; i++) {
for (j = i * 32; j < (i + 1) * 32; j++) {
int irq_trigger;
irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
omap_irq_set_cfg(j, 0, 0, irq_trigger);
set_irq_chip(j, &omap_irq_chip);
set_irq_handler(j, do_level_IRQ);
set_irq_flags(j, IRQF_VALID);
irq_level = irq_banks[i].level_map
>> (j - irq_banks[i].start_irq) & 1;
omap_irq_set_cfg(j, 0, 0, irq_level);
}
}
/* Unmask level 2 handler */
omap_writel(0, irq_banks[0].mask_reg);
omap_unmask_irq(INT_IH2_IRQ);
}
EXPORT_SYMBOL(omap_irq_set_cfg);
/*
* linux/arch/arm/mach-omap/irq.h
*
* OMAP specific interrupt bank definitions
*
* Copyright (C) 2004 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#define OMAP_IRQ_TYPE710 1
#define OMAP_IRQ_TYPE730 2
#define OMAP_IRQ_TYPE1510 3
#define OMAP_IRQ_TYPE1610 4
#define OMAP_IRQ_TYPE1710 5
#define MAX_NR_IRQ_BANKS 4
#define BANK_NR_IRQS 32
struct omap_irq_desc {
unsigned int cpu_type;
unsigned int start_irq;
unsigned long level_map;
unsigned long base_reg;
unsigned long mask_reg;
unsigned long ack_reg;
struct irqchip *handler;
};
struct omap_irq_bank {
unsigned int start_irq;
unsigned long level_map;
unsigned long base_reg;
unsigned long mask_reg;
unsigned long ack_reg;
struct irqchip *handler;
};
static void omap_offset_ack_irq(unsigned int irq);
static void omap_offset_mask_irq(unsigned int irq);
static void omap_offset_unmask_irq(unsigned int irq);
static void omap_offset_mask_ack_irq(unsigned int irq);
/* NOTE: These will not work if irq bank offset != 0x100 */
#define IRQ_TO_BANK(irq) (irq >> 5)
#define IRQ_BIT(irq) (irq & 0x1f)
#define BANK_OFFSET(bank) ((bank - 1) * 0x100)
static struct irqchip omap_offset_irq = {
.ack = omap_offset_mask_ack_irq,
.mask = omap_offset_mask_irq,
.unmask = omap_offset_unmask_irq,
};
/*
* OMAP-730 interrupt banks
*/
static struct omap_irq_desc omap730_bank0_irqs __initdata = {
.cpu_type = OMAP_IRQ_TYPE730,
.start_irq = 0,
.level_map = 0xb3f8e22f,
.base_reg = OMAP_IH1_BASE,
.mask_reg = OMAP_IH1_BASE + IRQ_MIR,
.ack_reg = OMAP_IH1_BASE + IRQ_CONTROL_REG,
.handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */
};
static struct omap_irq_desc omap730_bank1_irqs __initdata = {
.cpu_type = OMAP_IRQ_TYPE730,
.start_irq = 32,
.level_map = 0xfdb9c1f2,
.base_reg = OMAP_IH2_BASE,
.mask_reg = OMAP_IH2_BASE + IRQ_MIR,
.ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG,
.handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */
};
static struct omap_irq_desc omap730_bank2_irqs __initdata = {
.cpu_type = OMAP_IRQ_TYPE730,
.start_irq = 64,
.level_map = 0x800040f3,
.base_reg = OMAP_IH2_BASE + 0x100,
.mask_reg = OMAP_IH2_BASE + 0x100 + IRQ_MIR,
.ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG, /* Not replicated */
.handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */
};
/*
* OMAP-1510 interrupt banks
*/
static struct omap_irq_desc omap1510_bank0_irqs __initdata = {
.cpu_type = OMAP_IRQ_TYPE1510,
.start_irq = 0,
.level_map = 0xb3febfff,
.base_reg = OMAP_IH1_BASE,
.mask_reg = OMAP_IH1_BASE + IRQ_MIR,
.ack_reg = OMAP_IH1_BASE + IRQ_CONTROL_REG,
.handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */
};
static struct omap_irq_desc omap1510_bank1_irqs __initdata = {
.cpu_type = OMAP_IRQ_TYPE1510,
.start_irq = 32,
.level_map = 0xffbfffed,
.base_reg = OMAP_IH2_BASE,
.mask_reg = OMAP_IH2_BASE + IRQ_MIR,
.ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG,
.handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */
};
/*
* OMAP-1610 interrupt banks
*/
static struct omap_irq_desc omap1610_bank0_irqs __initdata = {
.cpu_type = OMAP_IRQ_TYPE1610,
.start_irq = 0,
.level_map = 0xb3fefe8f,
.base_reg = OMAP_IH1_BASE,
.mask_reg = OMAP_IH1_BASE + IRQ_MIR,
.ack_reg = OMAP_IH1_BASE + IRQ_CONTROL_REG,
.handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */
};
static struct omap_irq_desc omap1610_bank1_irqs __initdata = {
.cpu_type = OMAP_IRQ_TYPE1610,
.start_irq = 32,
.level_map = 0xfffff7ff,
.base_reg = OMAP_IH2_BASE,
.mask_reg = OMAP_IH2_BASE + IRQ_MIR,
.ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG,
.handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */
};
static struct omap_irq_desc omap1610_bank2_irqs __initdata = {
.cpu_type = OMAP_IRQ_TYPE1610,
.start_irq = 64,
.level_map = 0xffffffff,
.base_reg = OMAP_IH2_BASE + 0x100,
.mask_reg = OMAP_IH2_BASE + 0x100 + IRQ_MIR,
.ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG, /* Not replicated */
.handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */
};
static struct omap_irq_desc omap1610_bank3_irqs __initdata = {
.cpu_type = OMAP_IRQ_TYPE1610,
.start_irq = 96,
.level_map = 0xffffffff,
.base_reg = OMAP_IH2_BASE + 0x200,
.mask_reg = OMAP_IH2_BASE + 0x200 + IRQ_MIR,
.ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG, /* Not replicated */
.handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */
};
......@@ -96,7 +96,7 @@ void perseus2_leds_event(led_event_t evt)
/*
* Actually burn the LEDs
*/
omap_writew(~hw_led_state & 0xffff, OMAP730_FPGA_LEDS);
__raw_writew(~hw_led_state & 0xffff, OMAP730_FPGA_LEDS);
local_irq_restore(flags);
}
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