MIPS: tlbex: Remove cpu_has_local_ebase

The cpu_has_local_ebase macro is, confusingly, not used to indicate
whether the EBase register is local to a CPU or not. Instead it
indicates whether we want to generate the TLB refill exception vector
each time a CPU is brought online. Doing this makes little sense on any
system, since we always use the same value for EBase & thus we cannot
have different TLB refill exception handlers per CPU.

Regenerating the code is not only pointless but also can be actively
harmful, as commit 8759934e ("MIPS: Build uasm-generated code only
once to avoid CPU Hotplug problem") described. That commit introduced
cpu_has_local_ebase to disable the handler regeneration for Loongson
machines, but this is by no means a Loongson-specific problem.

Remove cpu_has_local_ebase & simply generate the TLB refill handler once
during boot, just like the rest of the TLB exception handlers.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: linux-mips@vger.kernel.org

arch/mips/include/asm/cpu-features.h

@@ -243,9 +243,6 @@
 #ifndef cpu_has_pindexed_dcache
 #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
 #endif
-#ifndef cpu_has_local_ebase
-#define cpu_has_local_ebase	1
-#endif
 
 /*
  * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors

arch/mips/include/asm/mach-dec/cpu-feature-overrides.h

@@ -32,7 +32,6 @@
 #define cpu_has_vtag_icache		0
 #define cpu_has_ic_fills_f_dc		0
 #define cpu_has_pindexed_dcache		0
-#define cpu_has_local_ebase		0
 #define cpu_icache_snoops_remote_store	1
 #define cpu_has_mips_4			0
 #define cpu_has_mips_5			0

arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h

@@ -43,7 +43,6 @@
 #define cpu_has_vint		0
 #define cpu_has_vtag_icache	0
 #define cpu_has_watch		1
-#define cpu_has_local_ebase	0
 
 #ifdef CONFIG_CPU_LOONGSON3
 #define cpu_has_wsbh		1

arch/mips/mm/tlbex.c

@@ -2609,12 +2609,9 @@ void build_tlb_refill_handler(void)
 
 	if (cpu_has_3kex) {
 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
-		if (cpu_has_local_ebase)
-			build_r3000_tlb_refill_handler();
 		if (!run_once) {
-			if (!cpu_has_local_ebase)
-				build_r3000_tlb_refill_handler();
 			build_setup_pgd();
+			build_r3000_tlb_refill_handler();
 			build_r3000_tlb_load_handler();
 			build_r3000_tlb_store_handler();
 			build_r3000_tlb_modify_handler();
@@ -2638,13 +2635,11 @@ void build_tlb_refill_handler(void)
 		build_r4000_tlb_modify_handler();
 		if (cpu_has_ldpte)
 			build_loongson3_tlb_refill_handler();
-		else if (!cpu_has_local_ebase)
+		else
 			build_r4000_tlb_refill_handler();
 		flush_tlb_handlers();
 		run_once++;
 	}
-	if (cpu_has_local_ebase)
-		build_r4000_tlb_refill_handler();
 	if (cpu_has_xpa)
 		config_xpa_params();
 	if (cpu_has_htw)