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Commit 777d466d authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'omap-for-v3.11/cleanup-signed' of... 

Merge tag 'omap-for-v3.11/cleanup-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup

From Tony Lindgren:
Move omap4 over to device tree based booting. This allows us to get rid
a big pile of platform init code for things that are already handled by
device tree related code. As am33xx is already device tree based, we
can also remove the same data for am33xx.

* tag 'omap-for-v3.11/cleanup-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP4: hwmod data: Remove irq entries from mcspi, mmc hwmods
  ARM: OMAP4: hwmod data: add DSS data back
  ARM: OMAP4: hwmod data: Clean up the data file
  ARM: AM33XX: hwmod data: irq, dma and addr info clean up
  ARM: OMAP2+: Remove omap4 ocp2scp pdata
  ARM: OMAP2+: Remove omap4 pdata for USB
  ARM: OMAP2+: Remove omap4 pdata from hsmmc.c
  ARM: OMAP2+: Remove legacy mux data for omap4
  ARM: OMAP2+: Remove board-omap4panda.c
  ARM: OMAP2+: Remove board-4430sdp.c
  ARM: OMAP2+: Legacy support for wl12xx when booted with devicetree

Resolved merge conflict due to a fix for 3.10 (the fix is removed since
the code is no longer used -- data comes from device tree).
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 214099b0 09182ab1
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arch/arm/mach-omap2/Kconfig
View file @ 777d466d
......@@ -167,12 +167,6 @@ config OMAP_PACKAGE_CUS
config OMAP_PACKAGE_CBP
bool
config OMAP_PACKAGE_CBL
bool
config OMAP_PACKAGE_CBS
bool
comment "OMAP Board Type"
depends on ARCH_OMAP2PLUS
......@@ -378,22 +372,6 @@ config MACH_TI8148EVM
depends on SOC_TI81XX
default y
config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"
default y
depends on ARCH_OMAP4
select OMAP_PACKAGE_CBL
select OMAP_PACKAGE_CBS
select REGULATOR_FIXED_VOLTAGE if REGULATOR
config MACH_OMAP4_PANDA
bool "OMAP4 Panda Board"
default y
depends on ARCH_OMAP4
select OMAP_PACKAGE_CBL
select OMAP_PACKAGE_CBS
select REGULATOR_FIXED_VOLTAGE if REGULATOR
config OMAP3_EMU
bool "OMAP3 debugging peripherals"
depends on ARCH_OMAP3
......
arch/arm/mach-omap2/Makefile
View file @ 777d466d
......@@ -63,7 +63,6 @@ obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
obj-$(CONFIG_SOC_OMAP2430) += mux2430.o
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
# SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
......@@ -251,8 +250,6 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o
obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o
obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o
obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o
obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
......
arch/arm/mach-omap2/board-4430sdp.c deleted 100644 → 0
View file @ 214099b0
/*
* Board support file for OMAP4430 SDP.
*
* Copyright (C) 2009 Texas Instruments
*
* Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Based on mach-omap2/board-3430sdp.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/usb/otg.h>
#include <linux/spi/spi.h>
#include <linux/i2c/twl.h>
#include <linux/mfd/twl6040.h>
#include <linux/gpio_keys.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/pwm.h>
#include <linux/leds.h>
#include <linux/leds_pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/platform_data/omap4-keypad.h>
#include <linux/usb/musb.h>
#include <linux/usb/phy.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
#include "omap4-keypad.h"
#include <linux/wl12xx.h>
#include <linux/platform_data/omap-abe-twl6040.h>
#include "soc.h"
#include "mux.h"
#include "mmc.h"
#include "hsmmc.h"
#include "control.h"
#include "common-board-devices.h"
#include "dss-common.h"
#define ETH_KS8851_IRQ 34
#define ETH_KS8851_POWER_ON 48
#define ETH_KS8851_QUART 138
#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
#define OMAP4_SFH7741_ENABLE_GPIO 188
#define GPIO_WIFI_PMENA 54
#define GPIO_WIFI_IRQ 53
static const int sdp4430_keymap[] = {
KEY(0, 0, KEY_E),
KEY(0, 1, KEY_R),
KEY(0, 2, KEY_T),
KEY(0, 3, KEY_HOME),
KEY(0, 4, KEY_F5),
KEY(0, 5, KEY_UNKNOWN),
KEY(0, 6, KEY_I),
KEY(0, 7, KEY_LEFTSHIFT),
KEY(1, 0, KEY_D),
KEY(1, 1, KEY_F),
KEY(1, 2, KEY_G),
KEY(1, 3, KEY_SEND),
KEY(1, 4, KEY_F6),
KEY(1, 5, KEY_UNKNOWN),
KEY(1, 6, KEY_K),
KEY(1, 7, KEY_ENTER),
KEY(2, 0, KEY_X),
KEY(2, 1, KEY_C),
KEY(2, 2, KEY_V),
KEY(2, 3, KEY_END),
KEY(2, 4, KEY_F7),
KEY(2, 5, KEY_UNKNOWN),
KEY(2, 6, KEY_DOT),
KEY(2, 7, KEY_CAPSLOCK),
KEY(3, 0, KEY_Z),
KEY(3, 1, KEY_KPPLUS),
KEY(3, 2, KEY_B),
KEY(3, 3, KEY_F1),
KEY(3, 4, KEY_F8),
KEY(3, 5, KEY_UNKNOWN),
KEY(3, 6, KEY_O),
KEY(3, 7, KEY_SPACE),
KEY(4, 0, KEY_W),
KEY(4, 1, KEY_Y),
KEY(4, 2, KEY_U),
KEY(4, 3, KEY_F2),
KEY(4, 4, KEY_VOLUMEUP),
KEY(4, 5, KEY_UNKNOWN),
KEY(4, 6, KEY_L),
KEY(4, 7, KEY_LEFT),
KEY(5, 0, KEY_S),
KEY(5, 1, KEY_H),
KEY(5, 2, KEY_J),
KEY(5, 3, KEY_F3),
KEY(5, 4, KEY_F9),
KEY(5, 5, KEY_VOLUMEDOWN),
KEY(5, 6, KEY_M),
KEY(5, 7, KEY_RIGHT),
KEY(6, 0, KEY_Q),
KEY(6, 1, KEY_A),
KEY(6, 2, KEY_N),
KEY(6, 3, KEY_BACK),
KEY(6, 4, KEY_BACKSPACE),
KEY(6, 5, KEY_UNKNOWN),
KEY(6, 6, KEY_P),
KEY(6, 7, KEY_UP),
KEY(7, 0, KEY_PROG1),
KEY(7, 1, KEY_PROG2),
KEY(7, 2, KEY_PROG3),
KEY(7, 3, KEY_PROG4),
KEY(7, 4, KEY_F4),
KEY(7, 5, KEY_UNKNOWN),
KEY(7, 6, KEY_OK),
KEY(7, 7, KEY_DOWN),
};
static struct omap_device_pad keypad_pads[] = {
{ .name = "kpd_col1.kpd_col1",
.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
},
{ .name = "kpd_col1.kpd_col1",
.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
},
{ .name = "kpd_col2.kpd_col2",
.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
},
{ .name = "kpd_col3.kpd_col3",
.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
},
{ .name = "kpd_col4.kpd_col4",
.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
},
{ .name = "kpd_col5.kpd_col5",
.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
},
{ .name = "gpmc_a23.kpd_col7",
.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
},
{ .name = "gpmc_a22.kpd_col6",
.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
},
{ .name = "kpd_row0.kpd_row0",
.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
OMAP_MUX_MODE1 | OMAP_INPUT_EN,
},
{ .name = "kpd_row1.kpd_row1",
.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
OMAP_MUX_MODE1 | OMAP_INPUT_EN,
},
{ .name = "kpd_row2.kpd_row2",
.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
OMAP_MUX_MODE1 | OMAP_INPUT_EN,
},
{ .name = "kpd_row3.kpd_row3",
.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
OMAP_MUX_MODE1 | OMAP_INPUT_EN,
},
{ .name = "kpd_row4.kpd_row4",
.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
OMAP_MUX_MODE1 | OMAP_INPUT_EN,
},
{ .name = "kpd_row5.kpd_row5",
.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
OMAP_MUX_MODE1 | OMAP_INPUT_EN,
},
{ .name = "gpmc_a18.kpd_row6",
.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
OMAP_MUX_MODE1 | OMAP_INPUT_EN,
},
{ .name = "gpmc_a19.kpd_row7",
.enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
OMAP_MUX_MODE1 | OMAP_INPUT_EN,
},
};
static struct matrix_keymap_data sdp4430_keymap_data = {
.keymap = sdp4430_keymap,
.keymap_size = ARRAY_SIZE(sdp4430_keymap),
};
static struct omap4_keypad_platform_data sdp4430_keypad_data = {
.keymap_data = &sdp4430_keymap_data,
.rows = 8,
.cols = 8,
};
static struct omap_board_data keypad_data = {
.id = 1,
.pads = keypad_pads,
.pads_cnt = ARRAY_SIZE(keypad_pads),
};
static struct gpio_led sdp4430_gpio_leds[] = {
{
.name = "omap4:green:debug0",
.gpio = 61,
},
{
.name = "omap4:green:debug1",
.gpio = 30,
},
{
.name = "omap4:green:debug2",
.gpio = 7,
},
{
.name = "omap4:green:debug3",
.gpio = 8,
},
{
.name = "omap4:green:debug4",
.gpio = 50,
},
{
.name = "omap4:blue:user",
.gpio = 169,
},
{
.name = "omap4:red:user",
.gpio = 170,
},
{
.name = "omap4:green:user",
.gpio = 139,
},
};
static struct gpio_keys_button sdp4430_gpio_keys[] = {
{
.desc = "Proximity Sensor",
.type = EV_SW,
.code = SW_FRONT_PROXIMITY,
.gpio = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO,
.active_low = 0,
}
};
static struct gpio_led_platform_data sdp4430_led_data = {
.leds = sdp4430_gpio_leds,
.num_leds = ARRAY_SIZE(sdp4430_gpio_leds),
};
static struct pwm_lookup sdp4430_pwm_lookup[] = {
PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "omap4::keypad"),
PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", NULL),
PWM_LOOKUP("twl-pwmled", 0, "leds_pwm", "omap4:green:chrg"),
};
static struct led_pwm sdp4430_pwm_leds[] = {
{
.name = "omap4::keypad",
.max_brightness = 127,
.pwm_period_ns = 7812500,
},
{
.name = "omap4:green:chrg",
.max_brightness = 255,
.pwm_period_ns = 7812500,
},
};
static struct led_pwm_platform_data sdp4430_pwm_data = {
.num_leds = ARRAY_SIZE(sdp4430_pwm_leds),
.leds = sdp4430_pwm_leds,
};
static struct platform_device sdp4430_leds_pwm = {
.name = "leds_pwm",
.id = -1,
.dev = {
.platform_data = &sdp4430_pwm_data,
},
};
/* Dummy regulator for pwm-backlight driver */
static struct regulator_consumer_supply backlight_supply =
REGULATOR_SUPPLY("enable", "pwm-backlight");
static struct platform_pwm_backlight_data sdp4430_backlight_data = {
.max_brightness = 127,
.dft_brightness = 127,
.pwm_period_ns = 7812500,
};
static struct platform_device sdp4430_backlight_pwm = {
.name = "pwm-backlight",
.id = -1,
.dev = {
.platform_data = &sdp4430_backlight_data,
},
};
static int omap_prox_activate(struct device *dev)
{
gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
return 0;
}
static void omap_prox_deactivate(struct device *dev)
{
gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0);
}
static struct gpio_keys_platform_data sdp4430_gpio_keys_data = {
.buttons = sdp4430_gpio_keys,
.nbuttons = ARRAY_SIZE(sdp4430_gpio_keys),
.enable = omap_prox_activate,
.disable = omap_prox_deactivate,
};
static struct platform_device sdp4430_gpio_keys_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &sdp4430_gpio_keys_data,
},
};
static struct platform_device sdp4430_leds_gpio = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &sdp4430_led_data,
},
};
static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
{
.modalias = "ks8851",
.bus_num = 1,
.chip_select = 0,
.max_speed_hz = 24000000,
/*
* .irq is set to gpio_to_irq(ETH_KS8851_IRQ)
* in omap_4430sdp_init
*/
},
};
static struct gpio sdp4430_eth_gpios[] __initdata = {
{ ETH_KS8851_POWER_ON, GPIOF_OUT_INIT_HIGH, "eth_power" },
{ ETH_KS8851_QUART, GPIOF_OUT_INIT_HIGH, "quart" },
{ ETH_KS8851_IRQ, GPIOF_IN, "eth_irq" },
};
static int __init omap_ethernet_init(void)
{
int status;
/* Request of GPIO lines */
status = gpio_request_array(sdp4430_eth_gpios,
ARRAY_SIZE(sdp4430_eth_gpios));
if (status)
pr_err("Cannot request ETH GPIOs\n");
return status;
}
static struct regulator_consumer_supply sdp4430_vbat_supply[] = {
REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"),
REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"),
};
static struct regulator_init_data sdp4430_vbat_data = {
.constraints = {
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(sdp4430_vbat_supply),
.consumer_supplies = sdp4430_vbat_supply,
};
static struct fixed_voltage_config sdp4430_vbat_pdata = {
.supply_name = "VBAT",
.microvolts = 3750000,
.init_data = &sdp4430_vbat_data,
.gpio = -EINVAL,
};
static struct platform_device sdp4430_vbat = {
.name = "reg-fixed-voltage",
.id = -1,
.dev = {
.platform_data = &sdp4430_vbat_pdata,
},
};
static struct platform_device sdp4430_dmic_codec = {
.name = "dmic-codec",
.id = -1,
};
static struct platform_device sdp4430_hdmi_audio_codec = {
.name = "hdmi-audio-codec",
.id = -1,
};
static struct omap_abe_twl6040_data sdp4430_abe_audio_data = {
.card_name = "SDP4430",
.has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
.has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
.has_ep = 1,
.has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
.has_vibra = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
.has_dmic = 1,
.has_hsmic = 1,
.has_mainmic = 1,
.has_submic = 1,
.has_afm = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
.jack_detection = 1,
/* MCLK input is 38.4MHz */
.mclk_freq = 38400000,
};
static struct platform_device sdp4430_abe_audio = {
.name = "omap-abe-twl6040",
.id = -1,
.dev = {
.platform_data = &sdp4430_abe_audio_data,
},
};
static struct platform_device *sdp4430_devices[] __initdata = {
&sdp4430_gpio_keys_device,
&sdp4430_leds_gpio,
&sdp4430_leds_pwm,
&sdp4430_backlight_pwm,
&sdp4430_vbat,
&sdp4430_dmic_codec,
&sdp4430_abe_audio,
&sdp4430_hdmi_audio_codec,
};
static struct omap_musb_board_data musb_board_data = {
.interface_type = MUSB_INTERFACE_UTMI,
.mode = MUSB_OTG,
.power = 100,
};
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 2,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.nonremovable = true,
.ocr_mask = MMC_VDD_29_30,
.no_off_init = true,
},
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
},
{
.mmc = 5,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
.pm_caps = MMC_PM_KEEP_POWER,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.ocr_mask = MMC_VDD_165_195,
.nonremovable = true,
},
{} /* Terminator */
};
static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
};
static struct regulator_consumer_supply omap4_sdp4430_vmmc5_supply = {
.supply = "vmmc",
.dev_name = "omap_hsmmc.4",
};
static struct regulator_init_data sdp4430_vmmc5 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap4_sdp4430_vmmc5_supply,
};
static struct fixed_voltage_config sdp4430_vwlan = {
.supply_name = "vwl1271",
.microvolts = 1800000, /* 1.8V */
.gpio = GPIO_WIFI_PMENA,
.startup_delay = 70000, /* 70msec */
.enable_high = 1,
.enabled_at_boot = 0,
.init_data = &sdp4430_vmmc5,
};
static struct platform_device omap_vwlan_device = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &sdp4430_vwlan,
},
};
static struct regulator_init_data sdp4430_vaux1 = {
.constraints = {
.min_uV = 1000000,
.max_uV = 3000000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(sdp4430_vaux_supply),
.consumer_supplies = sdp4430_vaux_supply,
};
static struct regulator_init_data sdp4430_vusim = {
.constraints = {
.min_uV = 1200000,
.max_uV = 2900000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct twl6040_codec_data twl6040_codec = {
/* single-step ramp for headset and handsfree */
.hs_left_step = 0x0f,
.hs_right_step = 0x0f,
.hf_left_step = 0x1d,
.hf_right_step = 0x1d,
};
static struct twl6040_vibra_data twl6040_vibra = {
.vibldrv_res = 8,
.vibrdrv_res = 3,
.viblmotor_res = 10,
.vibrmotor_res = 10,
.vddvibl_uV = 0, /* fixed volt supply - VBAT */
.vddvibr_uV = 0, /* fixed volt supply - VBAT */
};
static struct twl6040_platform_data twl6040_data = {
.codec = &twl6040_codec,
.vibra = &twl6040_vibra,
.audpwron_gpio = 127,
};
static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = {
{
I2C_BOARD_INFO("twl6040", 0x4b),
.irq = 119 + OMAP44XX_IRQ_GIC_START,
.platform_data = &twl6040_data,
},
};
static struct twl4030_platform_data sdp4430_twldata = {
/* Regulators */
.vusim = &sdp4430_vusim,
.vaux1 = &sdp4430_vaux1,
};
static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
{
I2C_BOARD_INFO("tmp105", 0x48),
},
{
I2C_BOARD_INFO("bh1780", 0x29),
},
};
static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
{
I2C_BOARD_INFO("hmc5843", 0x1e),
},
};
static int __init omap4_i2c_init(void)
{
omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
TWL_COMMON_REGULATOR_VDAC |
TWL_COMMON_REGULATOR_VAUX2 |
TWL_COMMON_REGULATOR_VAUX3 |
TWL_COMMON_REGULATOR_VMMC |
TWL_COMMON_REGULATOR_VPP |
TWL_COMMON_REGULATOR_VANA |
TWL_COMMON_REGULATOR_VCXIO |
TWL_COMMON_REGULATOR_VUSB |
TWL_COMMON_REGULATOR_CLK32KG |
TWL_COMMON_REGULATOR_V1V8 |
TWL_COMMON_REGULATOR_V2V1);
omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo,
ARRAY_SIZE(sdp4430_i2c_1_boardinfo));
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo,
ARRAY_SIZE(sdp4430_i2c_4_boardinfo));
return 0;
}
static void __init omap_sfh7741prox_init(void)
{
int error;
error = gpio_request_one(OMAP4_SFH7741_ENABLE_GPIO,
GPIOF_OUT_INIT_LOW, "sfh7741");
if (error < 0)
pr_err("%s:failed to request GPIO %d, error %d\n",
__func__, OMAP4_SFH7741_ENABLE_GPIO, error);
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
/* NIRQ2 for twl6040 */
OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
/* GPIO_127 for twl6040 */
OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
/* McPDM */
OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
/* DMIC */
OMAP4_MUX(ABE_DMIC_CLK1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP4_MUX(ABE_DMIC_DIN1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP4_MUX(ABE_DMIC_DIN2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP4_MUX(ABE_DMIC_DIN3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* McBSP1 */
OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
OMAP_PULL_ENA),
OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* McBSP2 */
OMAP4_MUX(ABE_MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP4_MUX(ABE_MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP4_MUX(ABE_MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
OMAP_PULL_ENA),
OMAP4_MUX(ABE_MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap4_sdp4430_wifi_mux_init(void)
{
omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT |
OMAP_PIN_OFF_WAKEUPENABLE);
omap_mux_init_gpio(GPIO_WIFI_PMENA, OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdmmc5_cmd.sdmmc5_cmd",
OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc5_clk.sdmmc5_clk",
OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc5_dat0.sdmmc5_dat0",
OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc5_dat1.sdmmc5_dat1",
OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc5_dat2.sdmmc5_dat2",
OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc5_dat3.sdmmc5_dat3",
OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
}
static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
.board_ref_clock = WL12XX_REFCLOCK_26,
.board_tcxo_clock = WL12XX_TCXOCLOCK_26,
};
static void __init omap4_sdp4430_wifi_init(void)
{
int ret;
omap4_sdp4430_wifi_mux_init();
omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
if (ret)
pr_err("Error setting wl12xx data: %d\n", ret);
ret = platform_device_register(&omap_vwlan_device);
if (ret)
pr_err("Error registering wl12xx device: %d\n", ret);
}
static void __init omap_4430sdp_init(void)
{
int status;
int package = OMAP_PACKAGE_CBS;
if (omap_rev() == OMAP4430_REV_ES1_0)
package = OMAP_PACKAGE_CBL;
omap4_mux_init(board_mux, NULL, package);
omap4_i2c_init();
omap_sfh7741prox_init();
regulator_register_always_on(0, "backlight-enable",
&backlight_supply, 1, 0);
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap4_sdp4430_wifi_init();
omap4_twl6030_hsmmc_init(mmc);
usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
usb_musb_init(&musb_board_data);
status = omap_ethernet_init();
if (status) {
pr_err("Ethernet initialization failed: %d\n", status);
} else {
sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
spi_register_board_info(sdp4430_spi_board_info,
ARRAY_SIZE(sdp4430_spi_board_info));
}
pwm_add_table(sdp4430_pwm_lookup, ARRAY_SIZE(sdp4430_pwm_lookup));
status = omap4_keyboard_init(&sdp4430_keypad_data, &keypad_data);
if (status)
pr_err("Keypad initialization failed: %d\n", status);
omap_4430sdp_display_init();
}
MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
/* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
.atag_offset = 0x100,
.smp = smp_ops(omap4_smp_ops),
.reserve = omap_reserve,
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
.init_irq = gic_init_irq,
.init_machine = omap_4430sdp_init,
.init_late = omap4430_init_late,
.init_time = omap4_local_timer_init,
.restart = omap44xx_restart,
MACHINE_END
arch/arm/mach-omap2/board-omap4panda.c deleted 100644 → 0
View file @ 214099b0
/*
* Board support file for OMAP4430 based PandaBoard.
*
* Copyright (C) 2010 Texas Instruments
*
* Author: David Anders <x0132446@ti.com>
*
* Based on mach-omap2/board-4430sdp.c
*
* Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Based on mach-omap2/board-3430sdp.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/usb/otg.h>
#include <linux/i2c/twl.h>
#include <linux/mfd/twl6040.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/ti_wilink_st.h>
#include <linux/usb/musb.h>
#include <linux/usb/phy.h>
#include <linux/usb/nop-usb-xceiv.h>
#include <linux/wl12xx.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/platform_data/omap-abe-twl6040.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
#include "soc.h"
#include "mmc.h"
#include "hsmmc.h"
#include "control.h"
#include "mux.h"
#include "common-board-devices.h"
#include "dss-common.h"
#define GPIO_HUB_POWER 1
#define GPIO_HUB_NRESET 62
#define GPIO_WIFI_PMENA 43
#define GPIO_WIFI_IRQ 53
/* wl127x BT, FM, GPS connectivity chip */
static struct ti_st_plat_data wilink_platform_data = {
.nshutdown_gpio = 46,
.dev_name = "/dev/ttyO1",
.flow_cntrl = 1,
.baud_rate = 3000000,
.chip_enable = NULL,
.suspend = NULL,
.resume = NULL,
};
static struct platform_device wl1271_device = {
.name = "kim",
.id = -1,
.dev = {
.platform_data = &wilink_platform_data,
},
};
static struct gpio_led gpio_leds[] = {
{
.name = "pandaboard::status1",
.default_trigger = "heartbeat",
.gpio = 7,
},
{
.name = "pandaboard::status2",
.default_trigger = "mmc0",
.gpio = 8,
},
};
static struct gpio_led_platform_data gpio_led_info = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct platform_device leds_gpio = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &gpio_led_info,
},
};
static struct omap_abe_twl6040_data panda_abe_audio_data = {
/* Audio out */
.has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
/* HandsFree through expansion connector */
.has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
/* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */
.has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
/* PandaBoard: FM RX, PandaBoardES: audio in */
.has_afm = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
/* No jack detection. */
.jack_detection = 0,
/* MCLK input is 38.4MHz */
.mclk_freq = 38400000,
};
static struct platform_device panda_abe_audio = {
.name = "omap-abe-twl6040",
.id = -1,
.dev = {
.platform_data = &panda_abe_audio_data,
},
};
static struct platform_device panda_hdmi_audio_codec = {
.name = "hdmi-audio-codec",
.id = -1,
};
static struct platform_device btwilink_device = {
.name = "btwilink",
.id = -1,
};
/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */
static struct nop_usb_xceiv_platform_data hsusb1_phy_data = {
/* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
.clk_rate = 19200000,
};
static struct usbhs_phy_data phy_data[] __initdata = {
{
.port = 1,
.reset_gpio = GPIO_HUB_NRESET,
.vcc_gpio = GPIO_HUB_POWER,
.vcc_polarity = 1,
.platform_data = &hsusb1_phy_data,
},
};
static struct platform_device *panda_devices[] __initdata = {
&leds_gpio,
&wl1271_device,
&panda_abe_audio,
&panda_hdmi_audio_codec,
&btwilink_device,
};
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
};
static void __init omap4_ehci_init(void)
{
int ret;
/* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
if (ret)
pr_err("Failed to add main_clk alias to auxclk3_ck\n");
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
usbhs_init(&usbhs_bdata);
}
static struct omap_musb_board_data musb_board_data = {
.interface_type = MUSB_INTERFACE_UTMI,
.mode = MUSB_OTG,
.power = 100,
};
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_wp = -EINVAL,
.gpio_cd = -EINVAL,
},
{
.name = "wl1271",
.mmc = 5,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
.gpio_wp = -EINVAL,
.gpio_cd = -EINVAL,
.ocr_mask = MMC_VDD_165_195,
.nonremovable = true,
},
{} /* Terminator */
};
static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
};
static struct regulator_init_data panda_vmmc5 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
.consumer_supplies = omap4_panda_vmmc5_supply,
};
static struct fixed_voltage_config panda_vwlan = {
.supply_name = "vwl1271",
.microvolts = 1800000, /* 1.8V */
.gpio = GPIO_WIFI_PMENA,
.startup_delay = 70000, /* 70msec */
.enable_high = 1,
.enabled_at_boot = 0,
.init_data = &panda_vmmc5,
};
static struct platform_device omap_vwlan_device = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &panda_vwlan,
},
};
static struct wl12xx_platform_data omap_panda_wlan_data __initdata = {
.board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
};
static struct twl6040_codec_data twl6040_codec = {
/* single-step ramp for headset and handsfree */
.hs_left_step = 0x0f,
.hs_right_step = 0x0f,
.hf_left_step = 0x1d,
.hf_right_step = 0x1d,
};
static struct twl6040_platform_data twl6040_data = {
.codec = &twl6040_codec,
.audpwron_gpio = 127,
};
static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
{
I2C_BOARD_INFO("twl6040", 0x4b),
.irq = 119 + OMAP44XX_IRQ_GIC_START,
.platform_data = &twl6040_data,
},
};
/* Panda board uses the common PMIC configuration */
static struct twl4030_platform_data omap4_panda_twldata;
/*
* Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
* is connected as I2C slave device, and can be accessed at address 0x50
*/
static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
{
I2C_BOARD_INFO("eeprom", 0x50),
},
};
static int __init omap4_panda_i2c_init(void)
{
omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
TWL_COMMON_REGULATOR_VDAC |
TWL_COMMON_REGULATOR_VAUX2 |
TWL_COMMON_REGULATOR_VAUX3 |
TWL_COMMON_REGULATOR_VMMC |
TWL_COMMON_REGULATOR_VPP |
TWL_COMMON_REGULATOR_VANA |
TWL_COMMON_REGULATOR_VCXIO |
TWL_COMMON_REGULATOR_VUSB |
TWL_COMMON_REGULATOR_CLK32KG |
TWL_COMMON_REGULATOR_V1V8 |
TWL_COMMON_REGULATOR_V2V1);
omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
ARRAY_SIZE(panda_i2c_1_boardinfo));
omap_register_i2c_bus(2, 400, NULL, 0);
/*
* Bus 3 is attached to the DVI port where devices like the pico DLP
* projector don't work reliably with 400kHz
*/
omap_register_i2c_bus(3, 100, panda_i2c_eeprom,
ARRAY_SIZE(panda_i2c_eeprom));
omap_register_i2c_bus(4, 400, NULL, 0);
return 0;
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* WLAN IRQ - GPIO 53 */
OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
/* WLAN POWER ENABLE - GPIO 43 */
OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
/* WLAN SDIO: MMC5 CMD */
OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
/* WLAN SDIO: MMC5 CLK */
OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
/* WLAN SDIO: MMC5 DAT[0-3] */
OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
/* gpio 0 - TFP410 PD */
OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3),
/* dispc2_data23 */
OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data22 */
OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data21 */
OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data20 */
OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data19 */
OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data18 */
OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data15 */
OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data14 */
OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data13 */
OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data12 */
OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data11 */
OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data10 */
OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data9 */
OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data16 */
OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data17 */
OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_hsync */
OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_pclk */
OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_vsync */
OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_de */
OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data8 */
OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data7 */
OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data6 */
OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data5 */
OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data4 */
OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data3 */
OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data2 */
OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data1 */
OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* dispc2_data0 */
OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
/* NIRQ2 for twl6040 */
OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
/* GPIO_127 for twl6040 */
OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
/* McPDM */
OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
/* McBSP1 */
OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
OMAP_PULL_ENA),
OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* UART2 - BT/FM/GPS shared transport */
OMAP4_MUX(UART2_CTS, OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP4_MUX(UART2_RTS, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP4_MUX(UART2_RX, OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP4_MUX(UART2_TX, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void omap4_panda_init_rev(void)
{
if (cpu_is_omap443x()) {
/* PandaBoard 4430 */
/* ASoC audio configuration */
panda_abe_audio_data.card_name = "PandaBoard";
panda_abe_audio_data.has_hsmic = 1;
} else {
/* PandaBoard ES */
/* ASoC audio configuration */
panda_abe_audio_data.card_name = "PandaBoardES";
}
}
static void __init omap4_panda_init(void)
{
int package = OMAP_PACKAGE_CBS;
int ret;
if (omap_rev() == OMAP4430_REV_ES1_0)
package = OMAP_PACKAGE_CBL;
omap4_mux_init(board_mux, NULL, package);
omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
if (ret)
pr_err("error setting wl12xx data: %d\n", ret);
omap4_panda_init_rev();
omap4_panda_i2c_init();
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
platform_device_register(&omap_vwlan_device);
omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap4_twl6030_hsmmc_init(mmc);
omap4_ehci_init();
usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
usb_musb_init(&musb_board_data);
omap4_panda_display_init();
}
MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
/* Maintainer: David Anders - Texas Instruments Inc */
.atag_offset = 0x100,
.smp = smp_ops(omap4_smp_ops),
.reserve = omap_reserve,
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
.init_irq = gic_init_irq,
.init_machine = omap4_panda_init,
.init_late = omap4430_init_late,
.init_time = omap4_local_timer_init,
.restart = omap44xx_restart,
MACHINE_END
arch/arm/mach-omap2/devices.c
View file @ 777d466d
......@@ -15,12 +15,12 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/omap4-keypad.h>
#include <linux/platform_data/omap_ocp2scp.h>
#include <linux/usb/omap_control_usb.h>
#include <linux/wl12xx.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
......@@ -253,49 +253,6 @@ static inline void omap_init_camera(void)
#endif
}
#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB)
static struct omap_control_usb_platform_data omap4_control_usb_pdata = {
.type = 1,
};
struct resource omap4_control_usb_res[] = {
{
.name = "control_dev_conf",
.start = 0x4a002300,
.end = 0x4a002303,
.flags = IORESOURCE_MEM,
},
{
.name = "otghs_control",
.start = 0x4a00233c,
.end = 0x4a00233f,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap4_control_usb = {
.name = "omap-control-usb",
.id = -1,
.dev = {
.platform_data = &omap4_control_usb_pdata,
},
.num_resources = 2,
.resource = omap4_control_usb_res,
};
static inline void __init omap_init_control_usb(void)
{
if (!cpu_is_omap44xx())
return;
if (platform_device_register(&omap4_control_usb))
pr_err("Error registering omap_control_usb device\n");
}
#else
static inline void omap_init_control_usb(void) { }
#endif /* CONFIG_OMAP_CONTROL_USB */
int __init omap4_keyboard_init(struct omap4_keypad_platform_data
*sdp4430_keypad_data, struct omap_board_data *bdata)
{
......@@ -557,80 +514,38 @@ static void omap_init_vout(void)
static inline void omap_init_vout(void) {}
#endif
#if defined(CONFIG_OMAP_OCP2SCP) || defined(CONFIG_OMAP_OCP2SCP_MODULE)
static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev)
{
int cnt = 0;
#if IS_ENABLED(CONFIG_WL12XX)
while (ocp2scp_dev->drv_name != NULL) {
cnt++;
ocp2scp_dev++;
}
static struct wl12xx_platform_data wl12xx __initdata;
return cnt;
}
static void __init omap_init_ocp2scp(void)
void __init omap_init_wl12xx_of(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
int bus_id = -1, dev_cnt = 0, i;
struct omap_ocp2scp_dev *ocp2scp_dev;
const char *oh_name, *name;
struct omap_ocp2scp_platform_data *pdata;
if (!cpu_is_omap44xx())
return;
oh_name = "ocp2scp_usb_phy";
name = "omap-ocp2scp";
int ret;
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("%s: could not find omap_hwmod for %s\n", __func__,
oh_name);
return;
}
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
if (!pdata) {
pr_err("%s: No memory for ocp2scp pdata\n", __func__);
return;
}
ocp2scp_dev = oh->dev_attr;
dev_cnt = count_ocp2scp_devices(ocp2scp_dev);
if (!dev_cnt) {
pr_err("%s: No devices connected to ocp2scp\n", __func__);
kfree(pdata);
if (!of_have_populated_dt())
return;
}
pdata->devices = kzalloc(sizeof(struct omap_ocp2scp_dev *)
* dev_cnt, GFP_KERNEL);
if (!pdata->devices) {
pr_err("%s: No memory for ocp2scp pdata devices\n", __func__);
kfree(pdata);
if (of_machine_is_compatible("ti,omap4-sdp")) {
wl12xx.board_ref_clock = WL12XX_REFCLOCK_26;
wl12xx.board_tcxo_clock = WL12XX_TCXOCLOCK_26;
wl12xx.irq = gpio_to_irq(53);
} else if (of_machine_is_compatible("ti,omap4-panda")) {
wl12xx.board_ref_clock = WL12XX_REFCLOCK_38;
wl12xx.irq = gpio_to_irq(53);
} else {
return;
}
for (i = 0; i < dev_cnt; i++, ocp2scp_dev++)
pdata->devices[i] = ocp2scp_dev;
pdata->dev_cnt = dev_cnt;
pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata));
if (IS_ERR(pdev)) {
pr_err("Could not build omap_device for %s %s\n",
name, oh_name);
kfree(pdata->devices);
kfree(pdata);
ret = wl12xx_set_platform_data(&wl12xx);
if (ret) {
pr_err("error setting wl12xx data: %d\n", ret);
return;
}
}
#else
static inline void omap_init_ocp2scp(void) { }
static inline void omap_init_wl12xx_of(void)
{
}
#endif
/*-------------------------------------------------------------------------*/
......@@ -651,17 +566,18 @@ static int __init omap2_init_devices(void)
omap_init_mbox();
/* If dtb is there, the devices will be created dynamically */
if (!of_have_populated_dt()) {
omap_init_control_usb();
omap_init_dmic();
omap_init_mcpdm();
omap_init_mcspi();
omap_init_sham();
omap_init_aes();
} else {
/* These can be removed when bindings are done */
omap_init_wl12xx_of();
}
omap_init_sti();
omap_init_rng();
omap_init_vout();
omap_init_ocp2scp();
return 0;
}
......
arch/arm/mach-omap2/hsmmc.c
View file @ 777d466d
......@@ -29,7 +29,6 @@
static u16 control_pbias_offset;
static u16 control_devconf1_offset;
static u16 control_mmc1;
#define HSMMC_NAME_LEN 9
......@@ -121,57 +120,6 @@ static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
}
}
static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
int power_on, int vdd)
{
u32 reg;
/*
* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
* card with Vcc regulator (from twl4030 or whatever). OMAP has both
* 1.8V and 3.0V modes, controlled by the PBIAS register.
*/
reg = omap4_ctrl_pad_readl(control_pbias_offset);
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
OMAP4_MMC1_PWRDNZ_MASK |
OMAP4_MMC1_PBIASLITE_VMODE_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
int power_on, int vdd)
{
u32 reg;
unsigned long timeout;
if (power_on) {
reg = omap4_ctrl_pad_readl(control_pbias_offset);
reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
if ((1 << vdd) <= MMC_VDD_165_195)
reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
else
reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
OMAP4_MMC1_PWRDNZ_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
timeout = jiffies + msecs_to_jiffies(5);
do {
reg = omap4_ctrl_pad_readl(control_pbias_offset);
if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
break;
usleep_range(100, 200);
} while (!time_after(jiffies, timeout));
if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
pr_err("Pbias Voltage is not same as LDO\n");
/* Caution : On VMODE_ERROR Power Down MMC IO */
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
}
}
static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
{
u32 reg;
......@@ -317,11 +265,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
mmc->slots[0].pm_caps = c->pm_caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->max_freq = c->max_freq;
if (cpu_is_omap44xx())
mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
else
mmc->reg_offset = 0;
mmc->reg_offset = 0;
mmc->get_context_loss_count = hsmmc_get_context_loss;
mmc->slots[0].switch_pin = c->gpio_cd;
......@@ -368,24 +312,14 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
if (!soc_is_am35xx())
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
switch (c->mmc) {
case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* on-chip level shifting via PBIAS0/PBIAS1 */
if (cpu_is_omap44xx()) {
mmc->slots[0].before_set_reg =
omap4_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap4_hsmmc1_after_set_reg;
} else {
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
if (soc_is_am35xx())
......@@ -563,34 +497,17 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
u32 reg;
if (omap_hsmmc_done)
return;
omap_hsmmc_done = 1;
if (!cpu_is_omap44xx()) {
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
} else {
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
} else {
control_pbias_offset =
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
for (; controllers->mmc; controllers++)
......
arch/arm/mach-omap2/mux.h
View file @ 777d466d
......@@ -10,7 +10,6 @@
#include "mux2420.h"
#include "mux2430.h"
#include "mux34xx.h"
#include "mux44xx.h"
#define OMAP_MUX_TERMINATOR 0xffff
......@@ -64,8 +63,6 @@
/* Flags for omapX_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
#define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */
#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */
#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
......
arch/arm/mach-omap2/mux44xx.c deleted 100644 → 0
View file @ 214099b0
/*
* OMAP44xx ES1.0 pin mux definition
*
* Copyright (C) 2010 Texas Instruments, Inc.
*
* Benoit Cousson (b-cousson@ti.com)
*
* - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com>
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/init.h>
#include "mux.h"
#ifdef CONFIG_OMAP_MUX
#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
{ \
.reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
.gpio = (g), \
.muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
}
#else
#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
{ \
.reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
.gpio = (g), \
}
#endif
#define _OMAP4_BALLENTRY(M0, bb, bt) \
{ \
.reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
.balls = { bb, bt }, \
}
/*
* Superset of all mux modes for omap4 ES1.0
*/
static struct omap_mux __initdata omap4_core_muxmodes[] = {
_OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
"sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
"sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
"sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
"sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
"gpio_32", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
"gpio_33", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
"gpio_34", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
"gpio_35", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
"gpio_36", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
"gpio_37", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
"gpio_38", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
"gpio_39", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
"gpio_40", "venc_656_data0", NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
"gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
"gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
"gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
"gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
"gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
"gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
"gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
"gpio_48", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
"gpio_49", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
"sys_ndmareq0", NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
"gpio_51", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
"gpio_52", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
"c2c_dataout4", "gpio_53", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
"sys_ndmareq1", NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
"sys_ndmareq2", NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
"gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
"gpio_59", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
"gpio_60", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
"gpio_61", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
"gpio_62", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
"c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
"c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
"c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
"c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
"c2c_dataout1", "gpio_104", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
"gpio_65", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
"gpio_66", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
"gpio_83", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
"hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
NULL, "hw_dbg20", "safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
"hsi1_cadata", "mcbsp4_clkr", "gpio_85",
"usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
"hsi1_caflag", "mcbsp4_fsr", "gpio_86",
"usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
"hsi1_acready", "mcbsp4_fsx", "gpio_87",
"usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
"hsi1_acwake", "mcbsp4_clkx", "gpio_88",
"usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
"hsi1_acdata", "mcbsp4_dx", "gpio_89",
"usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
"hsi1_acflag", "mcbsp4_dr", "gpio_90",
"usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
"hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
"usbb1_mm_txen", "hw_dbg27", "safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
"dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
"usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
"dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
"usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
"dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
"usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
"dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
"usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
"gpio_96", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
"gpio_98", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
"gpio_99", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
"gpio_100", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
"gpio_101", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
"gpio_102", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
"gpio_103", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
"gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
"gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
"gpio_106", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
"gpio_107", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
"gpio_108", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
"gpio_109", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
"abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
"abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
"abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
"abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
"abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
"abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
"abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
"abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
"abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
"abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
NULL, NULL, NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
NULL, NULL, NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
"gpio_119", "usbb2_mm_txse0", NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
"gpio_120", "usbb2_mm_txdat", NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
"abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
"gpio_123", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
"gpio_124", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
"gpio_125", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
"gpio_126", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
"gpio_127", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
NULL, NULL),
_OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
NULL, NULL),
_OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
"gpio_128", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
"gpio_129", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
"gpio_135", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
"gpio_136", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
"gpio_138", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
"slimbus2_clock", "gpio_139", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
"slimbus2_data", "gpio_140", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
"gpio_142", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
"dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
"dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
"usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
"usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
"usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
"usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
"gpio_149", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
"gpio_150", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
"gpio_151", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
"gpio_152", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
"gpio_153", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
"gpio_154", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
"gpio_155", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
"gpio_156", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
"usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
"hsi2_cawake", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
"usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
"hsi2_cadata", "dispc2_data23", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
"usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
"hsi2_caflag", "dispc2_data22", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
"usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
"hsi2_acready", "dispc2_data21", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
"usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
"hsi2_acwake", "dispc2_data20", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
"usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
"hsi2_acdata", "dispc2_data19", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
"usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
"hsi2_acflag", "dispc2_data18", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
"usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
"hsi2_caready", "dispc2_data15", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
"usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
"mcspi3_somi", "dispc2_data14", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
"usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
"mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
"usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
"mcspi3_simo", "dispc2_data12", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
"usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
"mcspi3_clk", "dispc2_data11", NULL, "reserved"),
_OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
"gpio_169", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
"gpio_171", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
"gpio_172", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
"gpio_173", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
"gpio_174", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
"gpio_0", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
"gpio_1", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
"gpi_175", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
"gpi_176", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
"gpi_177", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
"gpi_178", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
"gpi_2", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
"gpi_3", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
"uart2_rx", "gpio_179", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
"uart2_tx", "gpio_180", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
"gpio_181", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
"gpio_182", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
NULL, "hw_dbg0", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
NULL, "hw_dbg1", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
"gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
"gpio_14", NULL, "dispc2_data10", "hw_dbg3",
"reserved"),
_OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
"gpio_15", NULL, "dispc2_data9", "hw_dbg4",
"reserved"),
_OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
"gpio_16", "rfbi_te_vsync0", "dispc2_data16",
"hw_dbg5", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
"uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
"dispc2_data17", "hw_dbg6", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
"uart3_rx_irrx", "gpio_18", "rfbi_cs0",
"dispc2_hsync", "hw_dbg7", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
"uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
"hw_dbg8", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
"uart3_cts_rctx", "gpio_20", "rfbi_we",
"dispc2_vsync", "hw_dbg9", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
"reserved"),
_OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
"hw_dbg11", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
"hw_dbg12", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
"hw_dbg13", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
"uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
"hw_dbg14", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
"hw_dbg15", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
"dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
"hw_dbg16", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
"dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
"hw_dbg17", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
"dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
"hw_dbg18", "reserved"),
_OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
"dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
"hw_dbg19", "reserved"),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
/*
* Balls for 44XX CBL package
* 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
* 0.40mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CBL)
static struct omap_ball __initdata omap4_core_cbl_ball[] = {
_OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
_OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
_OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
_OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
_OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
_OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
_OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
_OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
_OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
_OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
_OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
_OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
_OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
_OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
_OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
_OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
_OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
_OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
_OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
_OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
_OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
_OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
_OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
_OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
_OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
_OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
_OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
_OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
_OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
_OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
_OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
_OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
_OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
_OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
_OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
_OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
_OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
_OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
_OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
_OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
_OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
_OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
_OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
_OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
_OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
_OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
_OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
_OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
_OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
_OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
_OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
_OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
_OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
_OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
_OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
_OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
_OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
_OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
_OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
_OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
_OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
_OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
_OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
_OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
_OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
_OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
_OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
_OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
_OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
_OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
_OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
_OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
_OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
_OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
_OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
_OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
_OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
_OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
_OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
_OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
_OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
_OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
_OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
_OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
_OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
_OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
_OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
_OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
_OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
_OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
_OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
_OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
_OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
_OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
_OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
_OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
_OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
_OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
_OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
_OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
_OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
_OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
_OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
_OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
_OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
_OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
_OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
_OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
_OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
_OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
_OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
_OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
_OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
_OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
_OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
_OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
_OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
_OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
_OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
_OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
_OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
_OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
_OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
_OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
_OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
_OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
_OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
_OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
_OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
_OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
_OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
_OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
_OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
_OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
_OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
_OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
_OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
_OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
_OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
_OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
_OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
_OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
_OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
_OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
_OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
_OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
_OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
_OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
_OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
_OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
_OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
_OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
_OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
_OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
_OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
_OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
_OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
_OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
_OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
_OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
_OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
_OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
_OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap4_core_cbl_ball NULL
#endif
/*
* Signals different on ES2.0 compared to superset
*/
static struct omap_mux __initdata omap4_es2_core_subset[] = {
_OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
"gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
"gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
"gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
"gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
"gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
"gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
"gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
_OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
"gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
_OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
"gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
"gpio_48", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
"c2c_dataout7", "gpio_52", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
"sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
_OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
"gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
_OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
"c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0",
"gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1",
"gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0",
"c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
"c2c_dataout1", "gpio_104", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
"hsi1_acwake", "mcbsp4_clkx", "gpio_88",
"usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
"hsi1_acdata", "mcbsp4_dx", "gpio_89",
"usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25",
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
"hsi1_acflag", "mcbsp4_dr", "gpio_90",
"usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26",
"safe_mode"),
_OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
"hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
"usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
_OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
"gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
"safe_mode"),
_OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
"gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL,
"safe_mode"),
_OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
"abe_mcasp_axr", "gpio_121", NULL,
"dmtimer11_pwm_evt", NULL, "safe_mode"),
_OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
"abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
"usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
"usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd",
NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
"usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0",
NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
"usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1",
NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
"gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
_OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
"gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
_OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk",
"kpd_col6", "gpio_151", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd",
"kpd_col7", "gpio_152", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0",
"kpd_row6", "gpio_153", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3",
"kpd_row7", "gpio_154", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8",
"gpio_155", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
"gpio_156", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
"usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
"hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
"usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
"hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
"usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
"hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
"usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
"hsi2_acwake", "dispc2_data20", "usbb2_mm_txen",
"safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
"usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
"hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat",
"safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
"usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
"hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0",
"safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
"usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
"hsi2_caready", "dispc2_data15", "rfbi_data15",
"safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
"usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
"mcspi3_somi", "dispc2_data14", "rfbi_data14",
"safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
"usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
"mcspi3_cs0", "dispc2_data13", "rfbi_data13",
"safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
"usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
"mcspi3_simo", "dispc2_data12", "rfbi_data12",
"safe_mode"),
_OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
"usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
"mcspi3_clk", "dispc2_data11", "rfbi_data11",
"safe_mode"),
_OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
"gpio_171", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
"gpio_172", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL,
"gpio_173", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL,
"gpio_174", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL,
"gpio_175", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL,
"gpio_176", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL,
"gpio_177", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL,
"gpio_178", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
"uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
"uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
"gpio_13", NULL, "dispc2_fid", "hw_dbg2",
"safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
"gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3",
"safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
"gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4",
"safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
"gpio_16", "rfbi_te_vsync0", "dispc2_data16",
"hw_dbg5", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
"uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
"dispc2_data17", "hw_dbg6", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
"uart3_rx_irrx", "gpio_18", "rfbi_cs0",
"dispc2_hsync", "hw_dbg7", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
"uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
"hw_dbg8", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
"uart3_cts_rctx", "gpio_20", "rfbi_we",
"dispc2_vsync", "hw_dbg9", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
"safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
"hw_dbg11", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
"hw_dbg12", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
"hw_dbg13", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
"uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
"hw_dbg14", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
"hw_dbg15", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
"dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
"hw_dbg16", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
"dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
"hw_dbg17", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
"dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
"hw_dbg18", "safe_mode"),
_OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
"dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
"hw_dbg19", "safe_mode"),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
/*
* Balls for 44XX CBS package
* 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
* 0.40mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CBS)
static struct omap_ball __initdata omap4_core_cbs_ball[] = {
_OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
_OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
_OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
_OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
_OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
_OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
_OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
_OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
_OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
_OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
_OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
_OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
_OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
_OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
_OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
_OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
_OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
_OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
_OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
_OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
_OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
_OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
_OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
_OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
_OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
_OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
_OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
_OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
_OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
_OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
_OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
_OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
_OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
_OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
_OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
_OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
_OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
_OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
_OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
_OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL),
_OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL),
_OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL),
_OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL),
_OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL),
_OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
_OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
_OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
_OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
_OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
_OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
_OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
_OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
_OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
_OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
_OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
_OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
_OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
_OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
_OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
_OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
_OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
_OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
_OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
_OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
_OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
_OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
_OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
_OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
_OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
_OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
_OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
_OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
_OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
_OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
_OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
_OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
_OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
_OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
_OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
_OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
_OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
_OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
_OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
_OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
_OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
_OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
_OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
_OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
_OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
_OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
_OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
_OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
_OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
_OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
_OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
_OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
_OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
_OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
_OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
_OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
_OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
_OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
_OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
_OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
_OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
_OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
_OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
_OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
_OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
_OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
_OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
_OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
_OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
_OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
_OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
_OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
_OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
_OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
_OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
_OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
_OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
_OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
_OMAP4_BALLENTRY(KPD_COL3, "g26", NULL),
_OMAP4_BALLENTRY(KPD_COL4, "g25", NULL),
_OMAP4_BALLENTRY(KPD_COL5, "h26", NULL),
_OMAP4_BALLENTRY(KPD_COL0, "h25", NULL),
_OMAP4_BALLENTRY(KPD_COL1, "j27", NULL),
_OMAP4_BALLENTRY(KPD_COL2, "h27", NULL),
_OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL),
_OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL),
_OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL),
_OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL),
_OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
_OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
_OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
_OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
_OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
_OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
_OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
_OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
_OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
_OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
_OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
_OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
_OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
_OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
_OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
_OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
_OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
_OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
_OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
_OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
_OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
_OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
_OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
_OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
_OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
_OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
_OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
_OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
_OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
_OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
_OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
_OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
_OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
_OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
_OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap4_core_cbs_ball NULL
#endif
/*
* Superset of all mux modes for omap4
*/
static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
_OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
NULL, NULL),
_OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
NULL, NULL),
_OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
"c2c_wakereqin", NULL, NULL, NULL),
_OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
"gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
"sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
"sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
"sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
"gpio_wk8", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
NULL, NULL),
_OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
NULL, NULL, NULL),
_OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
_OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
"gpio_wk9", "c2c_wakereqout", NULL, NULL,
"safe_mode"),
_OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
"gpio_wk10", NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
NULL, NULL, NULL),
_OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
NULL, "safe_mode"),
_OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
NULL, NULL, NULL),
_OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
NULL, NULL),
_OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
NULL, NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
/*
* Balls for 44XX CBL & CBS package - wakeup partition
* 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
* 0.40mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CBL)
static struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = {
_OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
_OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
_OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
_OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
_OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
_OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
_OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
_OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
_OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
_OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
_OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
_OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
_OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
_OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
_OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
_OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
_OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
_OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
_OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
_OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
_OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
_OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
_OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
_OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
_OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
_OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
_OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
_OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap4_wkup_cbl_cbs_ball NULL
#endif
int __init omap4_mux_init(struct omap_board_mux *board_subset,
struct omap_board_mux *board_wkup_subset, int flags)
{
struct omap_ball *package_balls_core;
struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
struct omap_mux *core_muxmodes;
struct omap_mux *core_subset = NULL;
int ret;
switch (flags & OMAP_PACKAGE_MASK) {
case OMAP_PACKAGE_CBL:
pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__);
package_balls_core = omap4_core_cbl_ball;
core_muxmodes = omap4_core_muxmodes;
break;
case OMAP_PACKAGE_CBS:
pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
package_balls_core = omap4_core_cbs_ball;
core_muxmodes = omap4_core_muxmodes;
core_subset = omap4_es2_core_subset;
break;
default:
pr_err("%s: Unknown omap package, mux disabled\n", __func__);
return -EINVAL;
}
ret = omap_mux_init("core",
OMAP_MUX_GPIO_IN_MODE3,
OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
core_muxmodes, core_subset, board_subset,
package_balls_core);
if (ret)
return ret;
ret = omap_mux_init("wkup",
OMAP_MUX_GPIO_IN_MODE3,
OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
omap4_wkup_muxmodes, NULL, board_wkup_subset,
package_balls_wkup);
return ret;
}
arch/arm/mach-omap2/mux44xx.h deleted 100644 → 0
View file @ 214099b0
/*
* OMAP44xx MUX registers and bitfields
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
*
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
#define OMAP4_MUX(M0, mux_value) \
{ \
.reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
.value = (mux_value), \
}
/* ctrl_module_pad_core base address */
#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000
/* ctrl_module_pad_core registers offset */
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c
#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e
#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060
#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062
#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064
#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066
#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068
#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a
#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c
#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e
#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070
#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072
#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074
#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076
#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078
#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a
#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c
#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e
#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080
#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082
#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084
#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086
#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088
#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a
#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c
#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e
#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090
#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092
#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094
#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096
#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098
#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a
#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c
#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e
#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0
#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2
#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4
#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6
#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8
#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa
#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac
#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae
#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0
#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2
#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4
#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6
#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8
#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba
#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc
#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be
#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6
#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8
#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da
#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc
#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de
#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0
#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2
#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4
#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6
#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8
#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea
#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec
#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee
#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0
#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2
#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4
#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6
#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8
#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa
#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc
#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe
#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100
#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102
#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104
#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106
#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108
#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a
#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c
#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e
#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110
#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112
#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114
#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116
#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118
#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a
#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c
#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e
#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120
#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122
#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124
#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126
#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128
#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a
#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c
#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e
#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130
#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132
#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134
#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136
#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138
#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a
#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c
#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e
#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140
#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142
#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144
#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146
#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148
#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a
#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c
#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e
#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150
#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152
#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154
#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156
#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158
#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a
#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c
#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174
#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176
#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178
#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190
#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192
#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194
#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196
#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198
#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a
#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c
#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e
#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0
#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2
#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4
#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6
#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8
#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa
#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2
#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4
/* ES2.0 only */
#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e
#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090
#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092
#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094
#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096
#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c
#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e
#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180
#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182
#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184
#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186
#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188
#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a
#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c
#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e
#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190
#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192
#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \
(OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \
- OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
/* ctrl_module_pad_wkup base address */
#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000
/* ctrl_module_pad_wkup registers offset */
#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040
#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042
#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044
#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046
#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048
#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a
#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c
#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e
#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050
#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052
#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054
#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056
#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058
#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a
#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c
#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e
#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060
#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062
#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064
#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066
#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068
#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a
#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c
#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e
#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070
#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072
#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074
#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076
#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \
(OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \
- OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
#endif
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View file @ 777d466d
......@@ -34,29 +34,6 @@
* IP blocks
*/
/*
* 'emif_fw' class
* instance(s): emif_fw
*/
static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
.name = "emif_fw",
};
/* emif_fw */
static struct omap_hwmod am33xx_emif_fw_hwmod = {
.name = "emif_fw",
.class = &am33xx_emif_fw_hwmod_class,
.clkdm_name = "l4fw_clkdm",
.main_clk = "l4fw_gclk",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'emif' class
* instance(s): emif
......@@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = {
.sysc = &am33xx_emif_sysc,
};
static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
{ .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
{ .irq = -1 },
};
/* emif */
static struct omap_hwmod am33xx_emif_hwmod = {
.name = "emif",
.class = &am33xx_emif_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.mpu_irqs = am33xx_emif_irqs,
.main_clk = "dpll_ddr_m2_div2_ck",
.prcm = {
.omap4 = {
......@@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = {
.name = "l3",
};
/* l3_main (l3_fast) */
static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
{ .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
{ .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_l3_main_hwmod = {
.name = "l3_main",
.class = &am33xx_l3_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.mpu_irqs = am33xx_l3_main_irqs,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
......@@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = {
},
};
/* l4_fw */
static struct omap_hwmod am33xx_l4_fw_hwmod = {
.name = "l4_fw",
.class = &am33xx_l4_hwmod_class,
.clkdm_name = "l4fw_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mpu' class
*/
......@@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
.name = "mpu",
};
/* mpu */
static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
{ .name = "emuint", .irq = 0 + OMAP_INTC_START, },
{ .name = "commtx", .irq = 1 + OMAP_INTC_START, },
{ .name = "commrx", .irq = 2 + OMAP_INTC_START, },
{ .name = "bench", .irq = 3 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_mpu_hwmod = {
.name = "mpu",
.class = &am33xx_mpu_hwmod_class,
.clkdm_name = "mpu_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.mpu_irqs = am33xx_mpu_irqs,
.main_clk = "dpll_mpu_m2_ck",
.prcm = {
.omap4 = {
......@@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
};
static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
{ .name = "txev", .irq = 78 + OMAP_INTC_START, },
{ .irq = -1 },
};
/* wkup_m3 */
static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.name = "wkup_m3",
......@@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.clkdm_name = "l4_wkup_aon_clkdm",
/* Keep hardreset asserted */
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
.mpu_irqs = am33xx_wkup_m3_irqs,
.main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
......@@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
{ .name = "pruss", .rst_shift = 1 },
};
static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
{ .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
{ .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
{ .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
{ .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
{ .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
{ .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
{ .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
{ .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
{ .irq = -1 },
};
/* pru-icss */
/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod am33xx_pruss_hwmod = {
.name = "pruss",
.class = &am33xx_pruss_hwmod_class,
.clkdm_name = "pruss_ocp_clkdm",
.mpu_irqs = am33xx_pruss_irqs,
.main_clk = "pruss_ocp_gclk",
.prcm = {
.omap4 = {
......@@ -332,16 +252,10 @@ static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
{ .name = "gfx", .rst_shift = 0 },
};
static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
{ .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_gfx_hwmod = {
.name = "gfx",
.class = &am33xx_gfx_hwmod_class,
.clkdm_name = "gfx_l3_clkdm",
.mpu_irqs = am33xx_gfx_irqs,
.main_clk = "gfx_fck_div_ck",
.prcm = {
.omap4 = {
......@@ -387,16 +301,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
.sysc = &am33xx_adc_tsc_sysc,
};
static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
{ .irq = 16 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_adc_tsc_hwmod = {
.name = "adc_tsc",
.class = &am33xx_adc_tsc_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = am33xx_adc_tsc_irqs,
.main_clk = "adc_tsc_fck",
.prcm = {
.omap4 = {
......@@ -515,23 +423,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
.sysc = &am33xx_aes0_sysc,
};
static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
{ .irq = 103 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
{ .name = "tx", .dma_req = 6, },
{ .name = "rx", .dma_req = 5, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_aes0_hwmod = {
.name = "aes",
.class = &am33xx_aes0_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_aes0_irqs,
.sdma_reqs = am33xx_aes0_edma_reqs,
.main_clk = "aes0_fck",
.prcm = {
.omap4 = {
......@@ -554,22 +449,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
.sysc = &am33xx_sha0_sysc,
};
static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
{ .irq = 109 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
{ .name = "rx", .dma_req = 36, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_sha0_hwmod = {
.name = "sham",
.class = &am33xx_sha0_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_sha0_irqs,
.sdma_reqs = am33xx_sha0_edma_reqs,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
......@@ -604,16 +487,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
};
/* smartreflex0 */
static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
{ .irq = 120 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_smartreflex0_hwmod = {
.name = "smartreflex0",
.class = &am33xx_smartreflex_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = am33xx_smartreflex0_irqs,
.main_clk = "smartreflex0_fck",
.prcm = {
.omap4 = {
......@@ -624,16 +501,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
};
/* smartreflex1 */
static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
{ .irq = 121 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_smartreflex1_hwmod = {
.name = "smartreflex1",
.class = &am33xx_smartreflex_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = am33xx_smartreflex1_irqs,
.main_clk = "smartreflex1_fck",
.prcm = {
.omap4 = {
......@@ -650,17 +521,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = {
.name = "control",
};
static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
{ .irq = 8 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_control_hwmod = {
.name = "control",
.class = &am33xx_control_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.mpu_irqs = am33xx_control_irqs,
.main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
......@@ -690,20 +555,11 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
.sysc = &am33xx_cpgmac_sysc,
};
static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
{ .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
{ .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
{ .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
{ .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_cpgmac0_hwmod = {
.name = "cpgmac0",
.class = &am33xx_cpgmac0_hwmod_class,
.clkdm_name = "cpsw_125mhz_clkdm",
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.mpu_irqs = am33xx_cpgmac0_irqs,
.main_clk = "cpsw_125mhz_gclk",
.prcm = {
.omap4 = {
......@@ -735,17 +591,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
};
/* dcan0 */
static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
{ .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
{ .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_dcan0_hwmod = {
.name = "d_can0",
.class = &am33xx_dcan_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_dcan0_irqs,
.main_clk = "dcan0_fck",
.prcm = {
.omap4 = {
......@@ -756,16 +605,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = {
};
/* dcan1 */
static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
{ .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
{ .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_dcan1_hwmod = {
.name = "d_can1",
.class = &am33xx_dcan_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_dcan1_irqs,
.main_clk = "dcan1_fck",
.prcm = {
.omap4 = {
......@@ -792,16 +635,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = {
.sysc = &am33xx_elm_sysc,
};
static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
{ .irq = 4 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_elm_hwmod = {
.name = "elm",
.class = &am33xx_elm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_elm_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
......@@ -854,45 +691,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = {
};
/* ecap0 */
static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
{ .irq = 31 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ecap0_hwmod = {
.name = "ecap0",
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap0_irqs,
.main_clk = "l4ls_gclk",
};
/* eqep0 */
static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
{ .irq = 79 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep0_hwmod = {
.name = "eqep0",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep0_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm0 */
static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
{ .name = "int", .irq = 86 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 58 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
.name = "ehrpwm0",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm0_irqs,
.main_clk = "l4ls_gclk",
};
......@@ -911,45 +729,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = {
};
/* ecap1 */
static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
{ .irq = 47 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ecap1_hwmod = {
.name = "ecap1",
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap1_irqs,
.main_clk = "l4ls_gclk",
};
/* eqep1 */
static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
{ .irq = 88 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep1_hwmod = {
.name = "eqep1",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep1_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm1 */
static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
{ .name = "int", .irq = 87 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 59 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
.name = "ehrpwm1",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm1_irqs,
.main_clk = "l4ls_gclk",
};
......@@ -968,45 +767,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = {
};
/* ecap2 */
static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
{ .irq = 61 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ecap2_hwmod = {
.name = "ecap2",
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap2_irqs,
.main_clk = "l4ls_gclk",
};
/* eqep2 */
static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
{ .irq = 89 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep2_hwmod = {
.name = "eqep2",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep2_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm2 */
static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
{ .name = "int", .irq = 39 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 60 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
.name = "ehrpwm2",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm2_irqs,
.main_clk = "l4ls_gclk",
};
......@@ -1041,17 +821,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio0_dbclk" },
};
static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
{ .irq = 96 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_gpio0_hwmod = {
.name = "gpio1",
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = am33xx_gpio0_irqs,
.main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
......@@ -1065,11 +839,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
};
/* gpio1 */
static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
{ .irq = 98 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
};
......@@ -1079,7 +848,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = am33xx_gpio1_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
......@@ -1093,11 +861,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
};
/* gpio2 */
static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
{ .irq = 32 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbclk" },
};
......@@ -1107,7 +870,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = am33xx_gpio2_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
......@@ -1121,11 +883,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
};
/* gpio3 */
static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
{ .irq = 62 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbclk" },
};
......@@ -1135,7 +892,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = {
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = am33xx_gpio3_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
......@@ -1164,17 +920,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
.sysc = &gpmc_sysc,
};
static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
{ .irq = 100 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_gpmc_hwmod = {
.name = "gpmc",
.class = &am33xx_gpmc_hwmod_class,
.clkdm_name = "l3s_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.mpu_irqs = am33xx_gpmc_irqs,
.main_clk = "l3s_gclk",
.prcm = {
.omap4 = {
......@@ -1208,23 +958,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
};
/* i2c1 */
static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
{ .irq = 70 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
{ .name = "tx", .dma_req = 0, },
{ .name = "rx", .dma_req = 0, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_i2c1_hwmod = {
.name = "i2c1",
.class = &i2c_class,
.clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = i2c1_mpu_irqs,
.sdma_reqs = i2c1_edma_reqs,
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "dpll_per_m2_div4_wkupdm_ck",
.prcm = {
......@@ -1237,23 +974,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = {
};
/* i2c1 */
static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
{ .irq = 71 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
{ .name = "tx", .dma_req = 0, },
{ .name = "rx", .dma_req = 0, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_i2c2_hwmod = {
.name = "i2c2",
.class = &i2c_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = i2c2_mpu_irqs,
.sdma_reqs = i2c2_edma_reqs,
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
......@@ -1266,23 +990,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = {
};
/* i2c3 */
static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
{ .name = "tx", .dma_req = 0, },
{ .name = "rx", .dma_req = 0, },
{ .dma_req = -1 }
};
static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
{ .irq = 30 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_i2c3_hwmod = {
.name = "i2c3",
.class = &i2c_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = i2c3_mpu_irqs,
.sdma_reqs = i2c3_edma_reqs,
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
......@@ -1309,16 +1020,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
.sysc = &lcdc_sysc,
};
static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
{ .irq = 36 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_lcdc_hwmod = {
.name = "lcdc",
.class = &am33xx_lcdc_hwmod_class,
.clkdm_name = "lcdc_clkdm",
.mpu_irqs = am33xx_lcdc_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "lcd_gclk",
.prcm = {
......@@ -1348,16 +1053,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
.sysc = &am33xx_mailbox_sysc,
};
static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
{ .irq = 77 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_mailbox_hwmod = {
.name = "mailbox",
.class = &am33xx_mailbox_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_mailbox_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
......@@ -1384,24 +1083,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
};
/* mcasp0 */
static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
{ .name = "ax", .irq = 80 + OMAP_INTC_START, },
{ .name = "ar", .irq = 81 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
{ .name = "tx", .dma_req = 8, },
{ .name = "rx", .dma_req = 9, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_mcasp0_hwmod = {
.name = "mcasp0",
.class = &am33xx_mcasp_hwmod_class,
.clkdm_name = "l3s_clkdm",
.mpu_irqs = am33xx_mcasp0_irqs,
.sdma_reqs = am33xx_mcasp0_edma_reqs,
.main_clk = "mcasp0_fck",
.prcm = {
.omap4 = {
......@@ -1412,24 +1097,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = {
};
/* mcasp1 */
static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
{ .name = "ax", .irq = 82 + OMAP_INTC_START, },
{ .name = "ar", .irq = 83 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
{ .name = "tx", .dma_req = 10, },
{ .name = "rx", .dma_req = 11, },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_mcasp1_hwmod = {
.name = "mcasp1",
.class = &am33xx_mcasp_hwmod_class,
.clkdm_name = "l3s_clkdm",
.mpu_irqs = am33xx_mcasp1_irqs,
.sdma_reqs = am33xx_mcasp1_edma_reqs,
.main_clk = "mcasp1_fck",
.prcm = {
.omap4 = {
......@@ -1457,17 +1128,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
};
/* mmc0 */
static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
{ .irq = 64 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
{ .name = "tx", .dma_req = 24, },
{ .name = "rx", .dma_req = 25, },
{ .dma_req = -1 }
};
static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};
......@@ -1476,8 +1136,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
.name = "mmc1",
.class = &am33xx_mmc_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_mmc0_irqs,
.sdma_reqs = am33xx_mmc0_edma_reqs,
.main_clk = "mmc_clk",
.prcm = {
.omap4 = {
......@@ -1489,17 +1147,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
};
/* mmc1 */
static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
{ .irq = 28 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
{ .name = "tx", .dma_req = 2, },
{ .name = "rx", .dma_req = 3, },
{ .dma_req = -1 }
};
static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};
......@@ -1508,8 +1155,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
.name = "mmc2",
.class = &am33xx_mmc_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_mmc1_irqs,
.sdma_reqs = am33xx_mmc1_edma_reqs,
.main_clk = "mmc_clk",
.prcm = {
.omap4 = {
......@@ -1521,17 +1166,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
};
/* mmc2 */
static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
{ .irq = 29 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
{ .name = "tx", .dma_req = 64, },
{ .name = "rx", .dma_req = 65, },
{ .dma_req = -1 }
};
static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};
......@@ -1539,8 +1173,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = {
.name = "mmc3",
.class = &am33xx_mmc_hwmod_class,
.clkdm_name = "l3s_clkdm",
.mpu_irqs = am33xx_mmc2_irqs,
.sdma_reqs = am33xx_mmc2_edma_reqs,
.main_clk = "mmc_clk",
.prcm = {
.omap4 = {
......@@ -1569,17 +1201,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
.sysc = &am33xx_rtc_sysc,
};
static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
{ .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
{ .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_rtc_hwmod = {
.name = "rtc",
.class = &am33xx_rtc_hwmod_class,
.clkdm_name = "l4_rtc_clkdm",
.mpu_irqs = am33xx_rtc_irqs,
.main_clk = "clk_32768_ck",
.prcm = {
.omap4 = {
......@@ -1608,19 +1233,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = {
};
/* spi0 */
static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
{ .irq = 65 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
{ .name = "rx0", .dma_req = 17 },
{ .name = "tx0", .dma_req = 16 },
{ .name = "rx1", .dma_req = 19 },
{ .name = "tx1", .dma_req = 18 },
{ .dma_req = -1 }
};
static struct omap2_mcspi_dev_attr mcspi_attrib = {
.num_chipselect = 2,
};
......@@ -1628,8 +1240,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
.name = "spi0",
.class = &am33xx_spi_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_spi0_irqs,
.sdma_reqs = am33xx_mcspi0_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
......@@ -1641,25 +1251,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
};
/* spi1 */
static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
{ .irq = 125 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
{ .name = "rx0", .dma_req = 43 },
{ .name = "tx0", .dma_req = 42 },
{ .name = "rx1", .dma_req = 45 },
{ .name = "tx1", .dma_req = 44 },
{ .dma_req = -1 }
};
static struct omap_hwmod am33xx_spi1_hwmod = {
.name = "spi1",
.class = &am33xx_spi_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_spi1_irqs,
.sdma_reqs = am33xx_mcspi1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
......@@ -1725,16 +1320,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
.sysc = &am33xx_timer1ms_sysc,
};
static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
{ .irq = 67 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer1_hwmod = {
.name = "timer1",
.class = &am33xx_timer1ms_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = am33xx_timer1_irqs,
.main_clk = "timer1_fck",
.prcm = {
.omap4 = {
......@@ -1744,16 +1333,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = {
},
};
static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
{ .irq = 68 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer2_hwmod = {
.name = "timer2",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer2_irqs,
.main_clk = "timer2_fck",
.prcm = {
.omap4 = {
......@@ -1763,16 +1346,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = {
},
};
static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
{ .irq = 69 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer3_hwmod = {
.name = "timer3",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer3_irqs,
.main_clk = "timer3_fck",
.prcm = {
.omap4 = {
......@@ -1782,16 +1359,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = {
},
};
static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
{ .irq = 92 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer4_hwmod = {
.name = "timer4",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer4_irqs,
.main_clk = "timer4_fck",
.prcm = {
.omap4 = {
......@@ -1801,16 +1372,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = {
},
};
static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
{ .irq = 93 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer5_hwmod = {
.name = "timer5",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer5_irqs,
.main_clk = "timer5_fck",
.prcm = {
.omap4 = {
......@@ -1820,16 +1385,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = {
},
};
static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
{ .irq = 94 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer6_hwmod = {
.name = "timer6",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer6_irqs,
.main_clk = "timer6_fck",
.prcm = {
.omap4 = {
......@@ -1839,16 +1398,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = {
},
};
static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
{ .irq = 95 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_timer7_hwmod = {
.name = "timer7",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_timer7_irqs,
.main_clk = "timer7_fck",
.prcm = {
.omap4 = {
......@@ -1863,18 +1416,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
.name = "tpcc",
};
static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
{ .name = "edma0", .irq = 12 + OMAP_INTC_START, },
{ .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
{ .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_tpcc_hwmod = {
.name = "tpcc",
.class = &am33xx_tpcc_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tpcc_irqs,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
......@@ -1900,16 +1445,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
};
/* tptc0 */
static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
{ .irq = 112 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_tptc0_hwmod = {
.name = "tptc0",
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tptc0_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "l3_gclk",
.prcm = {
......@@ -1921,16 +1460,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
};
/* tptc1 */
static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
{ .irq = 113 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_tptc1_hwmod = {
.name = "tptc1",
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tptc1_irqs,
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "l3_gclk",
.prcm = {
......@@ -1942,16 +1475,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = {
};
/* tptc2 */
static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
{ .irq = 114 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_tptc2_hwmod = {
.name = "tptc2",
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tptc2_irqs,
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "l3_gclk",
.prcm = {
......@@ -1980,24 +1507,11 @@ static struct omap_hwmod_class uart_class = {
};
/* uart1 */
static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
{ .name = "tx", .dma_req = 26, },
{ .name = "rx", .dma_req = 27, },
{ .dma_req = -1 }
};
static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
{ .irq = 72 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart1_hwmod = {
.name = "uart1",
.class = &uart_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart1_irqs,
.sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_wkupdm_ck",
.prcm = {
.omap4 = {
......@@ -2007,25 +1521,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
},
};
/* uart2 */
static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
{ .name = "tx", .dma_req = 28, },
{ .name = "rx", .dma_req = 29, },
{ .dma_req = -1 }
};
static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
{ .irq = 73 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart2_hwmod = {
.name = "uart2",
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart2_irqs,
.sdma_reqs = uart2_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
......@@ -2036,24 +1536,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
};
/* uart3 */
static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
{ .name = "tx", .dma_req = 30, },
{ .name = "rx", .dma_req = 31, },
{ .dma_req = -1 }
};
static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
{ .irq = 74 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart3_hwmod = {
.name = "uart3",
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart3_irqs,
.sdma_reqs = uart3_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
......@@ -2063,18 +1550,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
},
};
static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
{ .irq = 44 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart4_hwmod = {
.name = "uart4",
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart4_irqs,
.sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
......@@ -2084,18 +1564,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
},
};
static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
{ .irq = 45 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart5_hwmod = {
.name = "uart5",
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart5_irqs,
.sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
......@@ -2105,18 +1578,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
},
};
static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
{ .irq = 46 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_uart6_hwmod = {
.name = "uart6",
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = am33xx_uart6_irqs,
.sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
......@@ -2180,18 +1646,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = {
.sysc = &am33xx_usbhsotg_sysc,
};
static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
{ .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
{ .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
{ .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
{ .irq = -1, },
};
static struct omap_hwmod am33xx_usbss_hwmod = {
.name = "usb_otg_hs",
.class = &am33xx_usbotg_class,
.clkdm_name = "l3s_clkdm",
.mpu_irqs = am33xx_usbss_mpu_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "usbotg_fck",
.prcm = {
......@@ -2207,14 +1665,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
* Interfaces
*/
/* l4 fw -> emif fw */
static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
.master = &am33xx_l4_fw_hwmod,
.slave = &am33xx_emif_fw_hwmod,
.clk = "l4fw_gclk",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
{
.pa_start = 0x4c000000,
......@@ -2272,14 +1722,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 s -> l4 fw */
static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_l4_fw_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 main -> l3 instr */
static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
.master = &am33xx_l3_main_hwmod,
......@@ -2329,261 +1771,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
};
/* l4 wkup -> wkup m3 */
static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
{
.name = "umem",
.pa_start = 0x44d00000,
.pa_end = 0x44d00000 + SZ_16K - 1,
.flags = ADDR_TYPE_RT
},
{
.name = "dmem",
.pa_start = 0x44d80000,
.pa_end = 0x44d80000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wkup_m3_hwmod,
.clk = "dpll_core_m4_div2_ck",
.addr = am33xx_wkup_m3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 hs -> pru-icss */
static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
{
.pa_start = 0x4a300000,
.pa_end = 0x4a300000 + SZ_512K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
.master = &am33xx_l4_hs_hwmod,
.slave = &am33xx_pruss_hwmod,
.clk = "dpll_core_m4_ck",
.addr = am33xx_pruss_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 main -> gfx */
static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
{
.pa_start = 0x56000000,
.pa_end = 0x56000000 + SZ_16M - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_gfx_hwmod,
.clk = "dpll_core_m4_ck",
.addr = am33xx_gfx_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 wkup -> smartreflex0 */
static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
{
.pa_start = 0x44e37000,
.pa_end = 0x44e37000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex0_hwmod,
.clk = "dpll_core_m4_div2_ck",
.addr = am33xx_smartreflex0_addrs,
.user = OCP_USER_MPU,
};
/* l4 wkup -> smartreflex1 */
static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
{
.pa_start = 0x44e39000,
.pa_end = 0x44e39000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex1_hwmod,
.clk = "dpll_core_m4_div2_ck",
.addr = am33xx_smartreflex1_addrs,
.user = OCP_USER_MPU,
};
/* l4 wkup -> control */
static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
{
.pa_start = 0x44e10000,
.pa_end = 0x44e10000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_control_hwmod,
.clk = "dpll_core_m4_div2_ck",
.addr = am33xx_control_addrs,
.user = OCP_USER_MPU,
};
/* l4 wkup -> rtc */
static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
{
.pa_start = 0x44e3e000,
.pa_end = 0x44e3e000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_rtc_hwmod,
.clk = "clkdiv32k_ick",
.addr = am33xx_rtc_addrs,
.user = OCP_USER_MPU,
};
/* l4 per/ls -> DCAN0 */
static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
{
.pa_start = 0x481CC000,
.pa_end = 0x481CC000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_dcan0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_dcan0_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per/ls -> DCAN1 */
static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
{
.pa_start = 0x481D0000,
.pa_end = 0x481D0000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_dcan1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_dcan1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per/ls -> GPIO2 */
static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
{
.pa_start = 0x4804C000,
.pa_end = 0x4804C000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_gpio1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_gpio1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per/ls -> gpio3 */
static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
{
.pa_start = 0x481AC000,
.pa_end = 0x481AC000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_gpio2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_gpio2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per/ls -> gpio4 */
static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
{
.pa_start = 0x481AE000,
.pa_end = 0x481AE000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_gpio3_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_gpio3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4 WKUP -> I2C1 */
static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
{
.pa_start = 0x44E0B000,
.pa_end = 0x44E0B000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_i2c1_hwmod,
.clk = "dpll_core_m4_div2_ck",
.addr = am33xx_i2c1_addr_space,
.user = OCP_USER_MPU,
};
/* L4 WKUP -> GPIO1 */
static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
{
.pa_start = 0x44E07000,
.pa_end = 0x44E07000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_gpio0_hwmod,
.clk = "dpll_core_m4_div2_ck",
.addr = am33xx_gpio0_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -2605,41 +1900,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
/* cpsw ss */
{
.pa_start = 0x4a100000,
.pa_end = 0x4a100000 + SZ_2K - 1,
},
/* cpsw wr */
{
.pa_start = 0x4a101200,
.pa_end = 0x4a101200 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
.master = &am33xx_l4_hs_hwmod,
.slave = &am33xx_cpgmac0_hwmod,
.clk = "cpsw_125mhz_gclk",
.addr = am33xx_cpgmac0_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
{
.pa_start = 0x4A101000,
.pa_end = 0x4A101000 + SZ_256 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
.master = &am33xx_cpgmac0_hwmod,
.slave = &am33xx_mdio_hwmod,
.addr = am33xx_mdio_addr_space,
.user = OCP_USER_MPU,
};
......@@ -2677,51 +1947,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
{
.pa_start = 0x48300100,
.pa_end = 0x48300100 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_ecap0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ecap0_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
{
.pa_start = 0x48300180,
.pa_end = 0x48300180 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_eqep0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_eqep0_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
{
.pa_start = 0x48300200,
.pa_end = 0x48300200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_ehrpwm0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm0_addr_space,
.user = OCP_USER_MPU,
};
......@@ -2743,51 +1986,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
{
.pa_start = 0x48302100,
.pa_end = 0x48302100 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_ecap1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ecap1_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
{
.pa_start = 0x48302180,
.pa_end = 0x48302180 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_eqep1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_eqep1_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
{
.pa_start = 0x48302200,
.pa_end = 0x48302200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_ehrpwm1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm1_addr_space,
.user = OCP_USER_MPU,
};
......@@ -2808,51 +2024,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
{
.pa_start = 0x48304100,
.pa_end = 0x48304100 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_ecap2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ecap2_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
{
.pa_start = 0x48304180,
.pa_end = 0x48304180 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_eqep2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_eqep2_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
{
.pa_start = 0x48304200,
.pa_end = 0x48304200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_ehrpwm2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm2_addr_space,
.user = OCP_USER_MPU,
};
......@@ -2875,37 +2064,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
};
/* i2c2 */
static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
{
.pa_start = 0x4802A000,
.pa_end = 0x4802A000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_i2c2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_i2c2_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
{
.pa_start = 0x4819C000,
.pa_end = 0x4819C000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_i2c3_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_i2c3_addr_space,
.user = OCP_USER_MPU,
};
......@@ -2945,20 +2114,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
};
/* l4 ls -> spinlock */
static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
{
.pa_start = 0x480Ca000,
.pa_end = 0x480Ca000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spinlock_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_spinlock_addrs,
.user = OCP_USER_MPU,
};
......@@ -2980,24 +2139,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
.user = OCP_USER_MPU,
};
/* l3 s -> mcasp0 data */
static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
{
.pa_start = 0x46000000,
.pa_end = 0x46000000 + SZ_4M - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_mcasp0_hwmod,
.clk = "l3s_gclk",
.addr = am33xx_mcasp0_data_addr_space,
.user = OCP_USER_SDMA,
};
/* l4 ls -> mcasp1 */
static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
{
......@@ -3016,24 +2157,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
.user = OCP_USER_MPU,
};
/* l3 s -> mcasp1 data */
static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
{
.pa_start = 0x46400000,
.pa_end = 0x46400000 + SZ_4M - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_mcasp1_hwmod,
.clk = "l3s_gclk",
.addr = am33xx_mcasp1_data_addr_space,
.user = OCP_USER_SDMA,
};
/* l4 ls -> mmc0 */
static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
{
......@@ -3089,182 +2212,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
};
/* l4 ls -> mcspi0 */
static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
{
.pa_start = 0x48030000,
.pa_end = 0x48030000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spi0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_mcspi0_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> mcspi1 */
static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
{
.pa_start = 0x481A0000,
.pa_end = 0x481A0000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spi1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_mcspi1_addr_space,
.user = OCP_USER_MPU,
};
/* l4 wkup -> timer1 */
static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
{
.pa_start = 0x44E31000,
.pa_end = 0x44E31000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_timer1_hwmod,
.clk = "dpll_core_m4_div2_ck",
.addr = am33xx_timer1_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer2 */
static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
{
.pa_start = 0x48040000,
.pa_end = 0x48040000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_timer2_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer3 */
static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
{
.pa_start = 0x48042000,
.pa_end = 0x48042000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer3_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_timer3_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer4 */
static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
{
.pa_start = 0x48044000,
.pa_end = 0x48044000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer4_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_timer4_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer5 */
static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
{
.pa_start = 0x48046000,
.pa_end = 0x48046000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer5_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_timer5_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer6 */
static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
{
.pa_start = 0x48048000,
.pa_end = 0x48048000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer6_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_timer6_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer7 */
static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
{
.pa_start = 0x4804A000,
.pa_end = 0x4804A000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer7_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_timer7_addr_space,
.user = OCP_USER_MPU,
};
/* l3 main -> tpcc */
static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
{
.pa_start = 0x49000000,
.pa_end = 0x49000000 + SZ_32K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_tpcc_hwmod,
.clk = "l3_gclk",
.addr = am33xx_tpcc_addr_space,
.user = OCP_USER_MPU,
};
......@@ -3323,160 +2346,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
};
/* l4 wkup -> uart1 */
static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
{
.pa_start = 0x44E09000,
.pa_end = 0x44E09000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_uart1_hwmod,
.clk = "dpll_core_m4_div2_ck",
.addr = am33xx_uart1_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> uart2 */
static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
{
.pa_start = 0x48022000,
.pa_end = 0x48022000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_uart2_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> uart3 */
static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
{
.pa_start = 0x48024000,
.pa_end = 0x48024000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart3_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_uart3_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> uart4 */
static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
{
.pa_start = 0x481A6000,
.pa_end = 0x481A6000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart4_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_uart4_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> uart5 */
static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
{
.pa_start = 0x481A8000,
.pa_end = 0x481A8000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart5_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_uart5_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> uart6 */
static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
{
.pa_start = 0x481aa000,
.pa_end = 0x481aa000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart6_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_uart6_addr_space,
.user = OCP_USER_MPU,
};
/* l4 wkup -> wd_timer1 */
static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
{
.pa_start = 0x44e35000,
.pa_end = 0x44e35000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wd_timer1_hwmod,
.clk = "dpll_core_m4_div2_ck",
.addr = am33xx_wd_timer1_addrs,
.user = OCP_USER_MPU,
};
/* usbss */
/* l3 s -> USBSS interface */
static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
{
.name = "usbss",
.pa_start = 0x47400000,
.pa_end = 0x47400000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{
.name = "musb0",
.pa_start = 0x47401000,
.pa_end = 0x47401000 + SZ_2K - 1,
.flags = ADDR_TYPE_RT
},
{
.name = "musb1",
.pa_start = 0x47401800,
.pa_end = 0x47401800 + SZ_2K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_usbss_hwmod,
.clk = "l3s_gclk",
.addr = am33xx_usbss_addr_space,
.user = OCP_USER_MPU,
.flags = OCPIF_SWSUP_IDLE,
};
......@@ -3525,13 +2455,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
};
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_fw__emif_fw,
&am33xx_l3_main__emif,
&am33xx_mpu__l3_main,
&am33xx_mpu__prcm,
&am33xx_l3_s__l4_ls,
&am33xx_l3_s__l4_wkup,
&am33xx_l3_s__l4_fw,
&am33xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
......@@ -3561,9 +2489,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_per__i2c3,
&am33xx_l4_per__mailbox,
&am33xx_l4_ls__mcasp0,
&am33xx_l3_s__mcasp0_data,
&am33xx_l4_ls__mcasp1,
&am33xx_l3_s__mcasp1_data,
&am33xx_l4_ls__mmc0,
&am33xx_l4_ls__mmc1,
&am33xx_l3_s__mmc2,
......
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file @ 777d466d
......@@ -12,6 +12,8 @@
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
* Note that this file is currently not in sync with autogeneration scripts.
* The above note to be removed, once it is synced up.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -21,7 +23,6 @@
#include <linux/io.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/power/smartreflex.h>
#include <linux/platform_data/omap_ocp2scp.h>
#include <linux/i2c-omap.h>
#include <linux/omap-dma.h>
......@@ -51,27 +52,6 @@
* IP blocks
*/
/*
* 'c2c_target_fw' class
* instance(s): c2c_target_fw
*/
static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
.name = "c2c_target_fw",
};
/* c2c_target_fw */
static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
.name = "c2c_target_fw",
.class = &omap44xx_c2c_target_fw_hwmod_class,
.clkdm_name = "d2d_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
},
},
};
/*
* 'dmm' class
* instance(s): dmm
......@@ -81,16 +61,10 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
};
/* dmm */
static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_dmm_hwmod = {
.name = "dmm",
.class = &omap44xx_dmm_hwmod_class,
.clkdm_name = "l3_emif_clkdm",
.mpu_irqs = omap44xx_dmm_irqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
......@@ -99,27 +73,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
},
};
/*
* 'emif_fw' class
* instance(s): emif_fw
*/
static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
.name = "emif_fw",
};
/* emif_fw */
static struct omap_hwmod omap44xx_emif_fw_hwmod = {
.name = "emif_fw",
.class = &omap44xx_emif_fw_hwmod_class,
.clkdm_name = "l3_emif_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
},
},
};
/*
* 'l3' class
* instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
......@@ -143,17 +96,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
};
/* l3_main_1 */
static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
{ .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
{ .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
.name = "l3_main_1",
.class = &omap44xx_l3_hwmod_class,
.clkdm_name = "l3_1_clkdm",
.mpu_irqs = omap44xx_l3_main_1_irqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
......@@ -326,29 +272,10 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
};
/* aess */
static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
{ .irq = 99 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
{ .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_aess_hwmod = {
.name = "aess",
.class = &omap44xx_aess_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_aess_irqs,
.sdma_reqs = omap44xx_aess_sdma_reqs,
.main_clk = "aess_fclk",
.prcm = {
.omap4 = {
......@@ -371,22 +298,10 @@ static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
};
/* c2c */
static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
{ .irq = 88 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
{ .dma_req = 68 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_c2c_hwmod = {
.name = "c2c",
.class = &omap44xx_c2c_hwmod_class,
.clkdm_name = "d2d_clkdm",
.mpu_irqs = omap44xx_c2c_irqs,
.sdma_reqs = omap44xx_c2c_sdma_reqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
......@@ -449,16 +364,10 @@ static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
};
/* ctrl_module_core */
static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
{ .irq = 8 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
.name = "ctrl_module_core",
.class = &omap44xx_ctrl_module_hwmod_class,
.clkdm_name = "l4_cfg_clkdm",
.mpu_irqs = omap44xx_ctrl_module_core_irqs,
.prcm = {
.omap4 = {
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
......@@ -601,22 +510,10 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
};
/* dmic */
static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
{ .irq = 114 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
{ .dma_req = 66 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_dmic_hwmod = {
.name = "dmic",
.class = &omap44xx_dmic_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_dmic_irqs,
.sdma_reqs = omap44xx_dmic_sdma_reqs,
.main_clk = "func_dmic_abe_gfclk",
.prcm = {
.omap4 = {
......@@ -637,11 +534,6 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
};
/* dsp */
static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
{ .name = "dsp", .rst_shift = 0 },
};
......@@ -650,7 +542,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
.name = "dsp",
.class = &omap44xx_dsp_hwmod_class,
.clkdm_name = "tesla_clkdm",
.mpu_irqs = omap44xx_dsp_irqs,
.rst_lines = omap44xx_dsp_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
.main_clk = "dpll_iva_m4x2_ck",
......@@ -992,16 +883,10 @@ static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
};
/* elm */
static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
{ .irq = 4 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_elm_hwmod = {
.name = "elm",
.class = &omap44xx_elm_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_elm_irqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
......@@ -1025,17 +910,11 @@ static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
};
/* emif1 */
static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
{ .irq = 110 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_emif1_hwmod = {
.name = "emif1",
.class = &omap44xx_emif_hwmod_class,
.clkdm_name = "l3_emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_emif1_irqs,
.main_clk = "ddrphy_ck",
.prcm = {
.omap4 = {
......@@ -1047,17 +926,11 @@ static struct omap_hwmod omap44xx_emif1_hwmod = {
};
/* emif2 */
static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
{ .irq = 111 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_emif2_hwmod = {
.name = "emif2",
.class = &omap44xx_emif_hwmod_class,
.clkdm_name = "l3_emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_emif2_irqs,
.main_clk = "ddrphy_ck",
.prcm = {
.omap4 = {
......@@ -1098,16 +971,10 @@ static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
};
/* fdif */
static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
{ .irq = 69 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_fdif_hwmod = {
.name = "fdif",
.class = &omap44xx_fdif_hwmod_class,
.clkdm_name = "iss_clkdm",
.mpu_irqs = omap44xx_fdif_irqs,
.main_clk = "fdif_fck",
.prcm = {
.omap4 = {
......@@ -1148,11 +1015,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
};
/* gpio1 */
static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
};
......@@ -1161,7 +1023,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
.name = "gpio1",
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = omap44xx_gpio1_irqs,
.main_clk = "l4_wkup_clk_mux_ck",
.prcm = {
.omap4 = {
......@@ -1176,11 +1037,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
};
/* gpio2 */
static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbclk" },
};
......@@ -1190,7 +1046,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio2_irqs,
.main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
......@@ -1205,11 +1060,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
};
/* gpio3 */
static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbclk" },
};
......@@ -1219,7 +1069,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio3_irqs,
.main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
......@@ -1234,11 +1083,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
};
/* gpio4 */
static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio4_dbclk" },
};
......@@ -1248,7 +1092,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio4_irqs,
.main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
......@@ -1263,11 +1106,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
};
/* gpio5 */
static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio5_dbclk" },
};
......@@ -1277,7 +1115,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio5_irqs,
.main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
......@@ -1292,11 +1129,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
};
/* gpio6 */
static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio6_dbclk" },
};
......@@ -1306,7 +1138,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio6_irqs,
.main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
......@@ -1341,16 +1172,6 @@ static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
};
/* gpmc */
static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
{ .irq = 20 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
{ .dma_req = 3 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_gpmc_hwmod = {
.name = "gpmc",
.class = &omap44xx_gpmc_hwmod_class,
......@@ -1364,8 +1185,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
* HWMOD_INIT_NO_RESET should be removed ASAP.
*/
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_gpmc_irqs,
.sdma_reqs = omap44xx_gpmc_sdma_reqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
......@@ -1396,16 +1215,10 @@ static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
};
/* gpu */
static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
{ .irq = 21 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_gpu_hwmod = {
.name = "gpu",
.class = &omap44xx_gpu_hwmod_class,
.clkdm_name = "l3_gfx_clkdm",
.mpu_irqs = omap44xx_gpu_irqs,
.main_clk = "sgx_clk_mux",
.prcm = {
.omap4 = {
......@@ -1436,17 +1249,11 @@ static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
};
/* hdq1w */
static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
{ .irq = 58 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_hdq1w_hwmod = {
.name = "hdq1w",
.class = &omap44xx_hdq1w_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
.mpu_irqs = omap44xx_hdq1w_irqs,
.main_clk = "func_12m_fclk",
.prcm = {
.omap4 = {
......@@ -1482,18 +1289,10 @@ static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
};
/* hsi */
static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
{ .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
{ .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
{ .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_hsi_hwmod = {
.name = "hsi",
.class = &omap44xx_hsi_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.mpu_irqs = omap44xx_hsi_irqs,
.main_clk = "hsi_fck",
.prcm = {
.omap4 = {
......@@ -1533,24 +1332,11 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
};
/* i2c1 */
static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_i2c1_hwmod = {
.name = "i2c1",
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap44xx_i2c1_irqs,
.sdma_reqs = omap44xx_i2c1_sdma_reqs,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
......@@ -1563,24 +1349,11 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
};
/* i2c2 */
static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_i2c2_hwmod = {
.name = "i2c2",
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap44xx_i2c2_irqs,
.sdma_reqs = omap44xx_i2c2_sdma_reqs,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
......@@ -1593,24 +1366,11 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
};
/* i2c3 */
static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_i2c3_hwmod = {
.name = "i2c3",
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap44xx_i2c3_irqs,
.sdma_reqs = omap44xx_i2c3_sdma_reqs,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
......@@ -1623,24 +1383,11 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
};
/* i2c4 */
static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_i2c4_hwmod = {
.name = "i2c4",
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap44xx_i2c4_irqs,
.sdma_reqs = omap44xx_i2c4_sdma_reqs,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
......@@ -1662,11 +1409,6 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
};
/* ipu */
static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
{ .irq = 100 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
{ .name = "cpu0", .rst_shift = 0 },
{ .name = "cpu1", .rst_shift = 1 },
......@@ -1676,7 +1418,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
.name = "ipu",
.class = &omap44xx_ipu_hwmod_class,
.clkdm_name = "ducati_clkdm",
.mpu_irqs = omap44xx_ipu_irqs,
.rst_lines = omap44xx_ipu_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
.main_clk = "ducati_clk_mux_ck",
......@@ -1721,19 +1462,6 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
};
/* iss */
static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
{ .irq = 24 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
{ .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
{ .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
{ .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
{ .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod_opt_clk iss_opt_clks[] = {
{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
};
......@@ -1742,8 +1470,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
.name = "iss",
.class = &omap44xx_iss_hwmod_class,
.clkdm_name = "iss_clkdm",
.mpu_irqs = omap44xx_iss_irqs,
.sdma_reqs = omap44xx_iss_sdma_reqs,
.main_clk = "ducati_clk_mux_ck",
.prcm = {
.omap4 = {
......@@ -1766,13 +1492,6 @@ static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
};
/* iva */
static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
{ .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
{ .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
{ .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
{ .name = "seq0", .rst_shift = 0 },
{ .name = "seq1", .rst_shift = 1 },
......@@ -1783,7 +1502,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
.name = "iva",
.class = &omap44xx_iva_hwmod_class,
.clkdm_name = "ivahd_clkdm",
.mpu_irqs = omap44xx_iva_irqs,
.rst_lines = omap44xx_iva_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
.main_clk = "dpll_iva_m5x2_ck",
......@@ -1820,16 +1538,10 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
};
/* kbd */
static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
{ .irq = 120 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_kbd_hwmod = {
.name = "kbd",
.class = &omap44xx_kbd_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = omap44xx_kbd_irqs,
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
......@@ -1861,16 +1573,10 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
};
/* mailbox */
static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
{ .irq = 26 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_mailbox_hwmod = {
.name = "mailbox",
.class = &omap44xx_mailbox_hwmod_class,
.clkdm_name = "l4_cfg_clkdm",
.mpu_irqs = omap44xx_mailbox_irqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
......@@ -1903,24 +1609,10 @@ static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
};
/* mcasp */
static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
{ .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
{ .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
{ .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
{ .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_mcasp_hwmod = {
.name = "mcasp",
.class = &omap44xx_mcasp_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_mcasp_irqs,
.sdma_reqs = omap44xx_mcasp_sdma_reqs,
.main_clk = "func_mcasp_abe_gfclk",
.prcm = {
.omap4 = {
......@@ -1951,17 +1643,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
};
/* mcbsp1 */
static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
{ .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
......@@ -1971,8 +1652,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_mcbsp1_irqs,
.sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
.main_clk = "func_mcbsp1_gfclk",
.prcm = {
.omap4 = {
......@@ -1986,17 +1665,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
};
/* mcbsp2 */
static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
{ .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
......@@ -2006,8 +1674,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_mcbsp2_irqs,
.sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
.main_clk = "func_mcbsp2_gfclk",
.prcm = {
.omap4 = {
......@@ -2021,17 +1687,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
};
/* mcbsp3 */
static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
{ .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
......@@ -2041,8 +1696,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_mcbsp3_irqs,
.sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
.main_clk = "func_mcbsp3_gfclk",
.prcm = {
.omap4 = {
......@@ -2056,17 +1709,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
};
/* mcbsp4 */
static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
{ .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
......@@ -2076,8 +1718,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
.name = "mcbsp4",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mcbsp4_irqs,
.sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
.main_clk = "per_mcbsp4_gfclk",
.prcm = {
.omap4 = {
......@@ -2112,17 +1752,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
};
/* mcpdm */
static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
{ .irq = 112 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
{ .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
{ .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_mcpdm_hwmod = {
.name = "mcpdm",
.class = &omap44xx_mcpdm_hwmod_class,
......@@ -2139,8 +1768,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
* results 'slow motion' audio playback.
*/
.flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
.mpu_irqs = omap44xx_mcpdm_irqs,
.sdma_reqs = omap44xx_mcpdm_sdma_reqs,
.main_clk = "pad_clks_ck",
.prcm = {
.omap4 = {
......@@ -2174,11 +1801,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
};
/* mcspi1 */
static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
......@@ -2200,7 +1822,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mcspi1_irqs,
.sdma_reqs = omap44xx_mcspi1_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
......@@ -2214,11 +1835,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
};
/* mcspi2 */
static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
......@@ -2236,7 +1852,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mcspi2_irqs,
.sdma_reqs = omap44xx_mcspi2_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
......@@ -2250,11 +1865,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
};
/* mcspi3 */
static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
......@@ -2272,7 +1882,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mcspi3_irqs,
.sdma_reqs = omap44xx_mcspi3_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
......@@ -2286,11 +1895,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
};
/* mcspi4 */
static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
......@@ -2306,7 +1910,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mcspi4_irqs,
.sdma_reqs = omap44xx_mcspi4_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
......@@ -2342,11 +1945,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
};
/* mmc1 */
static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
{ .irq = 83 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
......@@ -2362,7 +1960,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
.name = "mmc1",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.mpu_irqs = omap44xx_mmc1_irqs,
.sdma_reqs = omap44xx_mmc1_sdma_reqs,
.main_clk = "hsmmc1_fclk",
.prcm = {
......@@ -2376,11 +1973,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
};
/* mmc2 */
static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
{ .irq = 86 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
......@@ -2391,7 +1983,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
.name = "mmc2",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.mpu_irqs = omap44xx_mmc2_irqs,
.sdma_reqs = omap44xx_mmc2_sdma_reqs,
.main_clk = "hsmmc2_fclk",
.prcm = {
......@@ -2404,11 +1995,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
};
/* mmc3 */
static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
{ .irq = 94 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
......@@ -2419,7 +2005,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
.name = "mmc3",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mmc3_irqs,
.sdma_reqs = omap44xx_mmc3_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
......@@ -2432,11 +2017,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
};
/* mmc4 */
static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
{ .irq = 96 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
......@@ -2447,7 +2027,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
.name = "mmc4",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mmc4_irqs,
.sdma_reqs = omap44xx_mmc4_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
......@@ -2460,11 +2039,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
};
/* mmc5 */
static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
{ .irq = 59 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
{ .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
......@@ -2475,7 +2049,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
.name = "mmc5",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mmc5_irqs,
.sdma_reqs = omap44xx_mmc5_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
......@@ -2517,11 +2090,6 @@ static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
};
static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
{ .irq = 100 + OMAP44XX_IRQ_GIC_START, },
{ .irq = -1 }
};
static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
{ .name = "mmu_cache", .rst_shift = 2 },
};
......@@ -2548,7 +2116,6 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
.name = "mmu_ipu",
.class = &omap44xx_mmu_hwmod_class,
.clkdm_name = "ducati_clkdm",
.mpu_irqs = omap44xx_mmu_ipu_irqs,
.rst_lines = omap44xx_mmu_ipu_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
.main_clk = "ducati_clk_mux_ck",
......@@ -2572,11 +2139,6 @@ static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
};
static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
{ .name = "mmu_cache", .rst_shift = 1 },
};
......@@ -2603,7 +2165,6 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
.name = "mmu_dsp",
.class = &omap44xx_mmu_hwmod_class,
.clkdm_name = "tesla_clkdm",
.mpu_irqs = omap44xx_mmu_dsp_irqs,
.rst_lines = omap44xx_mmu_dsp_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
.main_clk = "dpll_iva_m4x2_ck",
......@@ -2628,21 +2189,11 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
};
/* mpu */
static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
{ .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
{ .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_mpu_hwmod = {
.name = "mpu",
.class = &omap44xx_mpu_hwmod_class,
.clkdm_name = "mpuss_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_mpu_irqs,
.main_clk = "dpll_mpu_m2_ck",
.prcm = {
.omap4 = {
......@@ -2695,25 +2246,6 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
.sysc = &omap44xx_ocp2scp_sysc,
};
/* ocp2scp dev_attr */
static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
{
.name = "usb_phy",
.start = 0x4a0ad080,
.end = 0x4a0ae000,
.flags = IORESOURCE_MEM,
},
{ }
};
static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
{
.drv_name = "omap-usb2",
.res = omap44xx_usb_phy_and_pll_addrs,
},
{ }
};
/* ocp2scp_usb_phy */
static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
.name = "ocp2scp_usb_phy",
......@@ -2737,7 +2269,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
.modulemode = MODULEMODE_HWCTRL,
},
},
.dev_attr = ocp2scp_dev_attr,
};
/*
......@@ -2788,11 +2319,6 @@ static struct omap_hwmod omap44xx_cm_core_hwmod = {
};
/* prm */
static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
{ .irq = 11 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
{ .name = "rst_global_warm_sw", .rst_shift = 0 },
{ .name = "rst_global_cold_sw", .rst_shift = 1 },
......@@ -2801,7 +2327,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
static struct omap_hwmod omap44xx_prm_hwmod = {
.name = "prm",
.class = &omap44xx_prcm_hwmod_class,
.mpu_irqs = omap44xx_prm_irqs,
.rst_lines = omap44xx_prm_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
};
......@@ -2872,23 +2397,6 @@ static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
};
/* slimbus1 */
static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
{ .irq = 97 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
{ .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
{ .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
{ .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
{ .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
{ .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
{ .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
{ .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
{ .role = "fclk_1", .clk = "slimbus1_fclk_1" },
{ .role = "fclk_0", .clk = "slimbus1_fclk_0" },
......@@ -2900,8 +2408,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
.name = "slimbus1",
.class = &omap44xx_slimbus_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_slimbus1_irqs,
.sdma_reqs = omap44xx_slimbus1_sdma_reqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
......@@ -2914,23 +2420,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
};
/* slimbus2 */
static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
{ .irq = 98 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
{ .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
{ .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
{ .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
{ .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
{ .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
{ .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
{ .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
{ .role = "fclk_1", .clk = "slimbus2_fclk_1" },
{ .role = "fclk_0", .clk = "slimbus2_fclk_0" },
......@@ -2941,8 +2430,6 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = {
.name = "slimbus2",
.class = &omap44xx_slimbus_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_slimbus2_irqs,
.sdma_reqs = omap44xx_slimbus2_sdma_reqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
......@@ -2985,16 +2472,10 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
.sensor_voltdm_name = "core",
};
static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
.name = "smartreflex_core",
.class = &omap44xx_smartreflex_hwmod_class,
.clkdm_name = "l4_ao_clkdm",
.mpu_irqs = omap44xx_smartreflex_core_irqs,
.main_clk = "smartreflex_core_fck",
.prcm = {
......@@ -3012,16 +2493,10 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
.sensor_voltdm_name = "iva",
};
static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
.name = "smartreflex_iva",
.class = &omap44xx_smartreflex_hwmod_class,
.clkdm_name = "l4_ao_clkdm",
.mpu_irqs = omap44xx_smartreflex_iva_irqs,
.main_clk = "smartreflex_iva_fck",
.prcm = {
.omap4 = {
......@@ -3038,16 +2513,10 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
.sensor_voltdm_name = "mpu",
};
static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
.name = "smartreflex_mpu",
.class = &omap44xx_smartreflex_hwmod_class,
.clkdm_name = "l4_ao_clkdm",
.mpu_irqs = omap44xx_smartreflex_mpu_irqs,
.main_clk = "smartreflex_mpu_fck",
.prcm = {
.omap4 = {
......@@ -3155,17 +2624,11 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
};
/* timer1 */
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer1_hwmod = {
.name = "timer1",
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap44xx_timer1_irqs,
.main_clk = "dmt1_clk_mux",
.prcm = {
.omap4 = {
......@@ -3178,17 +2641,11 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
};
/* timer2 */
static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
{ .irq = 38 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer2_hwmod = {
.name = "timer2",
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap44xx_timer2_irqs,
.main_clk = "cm2_dm2_mux",
.prcm = {
.omap4 = {
......@@ -3200,16 +2657,10 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
};
/* timer3 */
static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
{ .irq = 39 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer3_hwmod = {
.name = "timer3",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_timer3_irqs,
.main_clk = "cm2_dm3_mux",
.prcm = {
.omap4 = {
......@@ -3221,16 +2672,10 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
};
/* timer4 */
static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
{ .irq = 40 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer4_hwmod = {
.name = "timer4",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_timer4_irqs,
.main_clk = "cm2_dm4_mux",
.prcm = {
.omap4 = {
......@@ -3242,16 +2687,10 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
};
/* timer5 */
static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
{ .irq = 41 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer5_hwmod = {
.name = "timer5",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_timer5_irqs,
.main_clk = "timer5_sync_mux",
.prcm = {
.omap4 = {
......@@ -3264,16 +2703,10 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
};
/* timer6 */
static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
{ .irq = 42 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer6_hwmod = {
.name = "timer6",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_timer6_irqs,
.main_clk = "timer6_sync_mux",
.prcm = {
.omap4 = {
......@@ -3286,16 +2719,10 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
};
/* timer7 */
static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
{ .irq = 43 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer7_hwmod = {
.name = "timer7",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_timer7_irqs,
.main_clk = "timer7_sync_mux",
.prcm = {
.omap4 = {
......@@ -3308,16 +2735,10 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
};
/* timer8 */
static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
{ .irq = 44 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer8_hwmod = {
.name = "timer8",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_timer8_irqs,
.main_clk = "timer8_sync_mux",
.prcm = {
.omap4 = {
......@@ -3330,16 +2751,10 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
};
/* timer9 */
static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
{ .irq = 45 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer9_hwmod = {
.name = "timer9",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_timer9_irqs,
.main_clk = "cm2_dm9_mux",
.prcm = {
.omap4 = {
......@@ -3352,17 +2767,11 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
};
/* timer10 */
static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
{ .irq = 46 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer10_hwmod = {
.name = "timer10",
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap44xx_timer10_irqs,
.main_clk = "cm2_dm10_mux",
.prcm = {
.omap4 = {
......@@ -3375,16 +2784,10 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
};
/* timer11 */
static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
{ .irq = 47 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_timer11_hwmod = {
.name = "timer11",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_timer11_irqs,
.main_clk = "cm2_dm11_mux",
.prcm = {
.omap4 = {
......@@ -3419,24 +2822,11 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
};
/* uart1 */
static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
{ .irq = 72 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_uart1_hwmod = {
.name = "uart1",
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = omap44xx_uart1_irqs,
.sdma_reqs = omap44xx_uart1_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
......@@ -3448,24 +2838,11 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
};
/* uart2 */
static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
{ .irq = 73 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_uart2_hwmod = {
.name = "uart2",
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = omap44xx_uart2_irqs,
.sdma_reqs = omap44xx_uart2_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
......@@ -3477,25 +2854,12 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
};
/* uart3 */
static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
{ .irq = 74 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_uart3_hwmod = {
.name = "uart3",
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = omap44xx_uart3_irqs,
.sdma_reqs = omap44xx_uart3_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
......@@ -3507,24 +2871,11 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
};
/* uart4 */
static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
{ .irq = 70 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
{ .dma_req = -1 }
};
static struct omap_hwmod omap44xx_uart4_hwmod = {
.name = "uart4",
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.mpu_irqs = omap44xx_uart4_irqs,
.sdma_reqs = omap44xx_uart4_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
......@@ -3563,17 +2914,10 @@ static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
};
/* usb_host_fs */
static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
{ .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
{ .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
.name = "usb_host_fs",
.class = &omap44xx_usb_host_fs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.mpu_irqs = omap44xx_usb_host_fs_irqs,
.main_clk = "usb_host_fs_fck",
.prcm = {
.omap4 = {
......@@ -3607,12 +2951,6 @@ static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
};
/* usb_host_hs */
static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
{ .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
{ .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
.name = "usb_host_hs",
.class = &omap44xx_usb_host_hs_hwmod_class,
......@@ -3625,7 +2963,6 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
.mpu_irqs = omap44xx_usb_host_hs_irqs,
/*
* Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
......@@ -3700,12 +3037,6 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
};
/* usb_otg_hs */
static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
{ .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
{ .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
};
......@@ -3715,7 +3046,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
.class = &omap44xx_usb_otg_hs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.mpu_irqs = omap44xx_usb_otg_hs_irqs,
.main_clk = "usb_otg_hs_ick",
.prcm = {
.omap4 = {
......@@ -3749,16 +3079,10 @@ static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
.sysc = &omap44xx_usb_tll_hs_sysc,
};
static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
{ .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
.name = "usb_tll_hs",
.class = &omap44xx_usb_tll_hs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.mpu_irqs = omap44xx_usb_tll_hs_irqs,
.main_clk = "usb_tll_hs_ick",
.prcm = {
.omap4 = {
......@@ -3794,16 +3118,10 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
};
/* wd_timer2 */
static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
{ .irq = 80 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &omap44xx_wd_timer_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = omap44xx_wd_timer2_irqs,
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
......@@ -3815,16 +3133,10 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
};
/* wd_timer3 */
static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
{ .irq = -1 }
};
static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.name = "wd_timer3",
.class = &omap44xx_wd_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_wd_timer3_irqs,
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
......@@ -3840,32 +3152,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
* interfaces
*/
static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
{
.pa_start = 0x4a204000,
.pa_end = 0x4a2040ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* c2c -> c2c_target_fw */
static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
.master = &omap44xx_c2c_hwmod,
.slave = &omap44xx_c2c_target_fw_hwmod,
.clk = "div_core_ck",
.addr = omap44xx_c2c_target_fw_addrs,
.user = OCP_USER_MPU,
};
/* l4_cfg -> c2c_target_fw */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_c2c_target_fw_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> dmm */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
.master = &omap44xx_l3_main_1_hwmod,
......@@ -3874,55 +3160,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
.user = OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
{
.pa_start = 0x4e000000,
.pa_end = 0x4e0007ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* mpu -> dmm */
static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
.master = &omap44xx_mpu_hwmod,
.slave = &omap44xx_dmm_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_dmm_addrs,
.user = OCP_USER_MPU,
};
/* c2c -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
.master = &omap44xx_c2c_hwmod,
.slave = &omap44xx_emif_fw_hwmod,
.clk = "div_core_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dmm -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
.master = &omap44xx_dmm_hwmod,
.slave = &omap44xx_emif_fw_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
{
.pa_start = 0x4a20c000,
.pa_end = 0x4a20c0ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_emif_fw_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_emif_fw_addrs,
.user = OCP_USER_MPU,
};
......@@ -3998,32 +3240,14 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
{
.pa_start = 0x44000000,
.pa_end = 0x44000fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* mpu -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
.master = &omap44xx_mpu_hwmod,
.slave = &omap44xx_l3_main_1_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_l3_main_1_addrs,
.user = OCP_USER_MPU,
};
/* c2c_target_fw -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
.master = &omap44xx_c2c_target_fw_hwmod,
.slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* debugss -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
.master = &omap44xx_debugss_hwmod,
......@@ -4088,21 +3312,11 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
{
.pa_start = 0x44800000,
.pa_end = 0x44801fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l3_main_1 -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
.master = &omap44xx_l3_main_1_hwmod,
.slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_l3_main_2_addrs,
.user = OCP_USER_MPU,
};
......@@ -4138,21 +3352,11 @@ static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
{
.pa_start = 0x45000000,
.pa_end = 0x45000fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
.master = &omap44xx_l3_main_1_hwmod,
.slave = &omap44xx_l3_main_3_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_l3_main_3_addrs,
.user = OCP_USER_MPU,
};
......@@ -4236,21 +3440,11 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
{
.pa_start = 0x4a102000,
.pa_end = 0x4a10207f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> ocp_wp_noc */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_ocp_wp_noc_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_ocp_wp_noc_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -4340,21 +3534,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
{
.pa_start = 0x4a304000,
.pa_end = 0x4a30401f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_counter_32k_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_counter_32k_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -4430,21 +3614,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
{
.pa_start = 0x54160000,
.pa_end = 0x54167fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l3_instr -> debugss */
static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
.master = &omap44xx_l3_instr_hwmod,
.slave = &omap44xx_debugss_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_debugss_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -4466,41 +3640,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
{
.name = "mpu",
.pa_start = 0x4012e000,
.pa_end = 0x4012e07f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> dmic */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_dmic_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_dmic_addrs,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
{
.name = "dma",
.pa_start = 0x4902e000,
.pa_end = 0x4902e07f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> dmic (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_dmic_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_dmic_dma_addrs,
.user = OCP_USER_SDMA,
};
......@@ -4798,42 +3950,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
{
.pa_start = 0x4c000000,
.pa_end = 0x4c0000ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* emif_fw -> emif1 */
static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
.master = &omap44xx_emif_fw_hwmod,
.slave = &omap44xx_emif1_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_emif1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
{
.pa_start = 0x4d000000,
.pa_end = 0x4d0000ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* emif_fw -> emif2 */
static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
.master = &omap44xx_emif_fw_hwmod,
.slave = &omap44xx_emif2_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_emif2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
{
.pa_start = 0x4a10a000,
......@@ -4852,129 +3968,59 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
{
.pa_start = 0x4a310000,
.pa_end = 0x4a3101ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_wkup -> gpio1 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_gpio1_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_gpio1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
{
.pa_start = 0x48055000,
.pa_end = 0x480551ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> gpio2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_gpio2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
{
.pa_start = 0x48057000,
.pa_end = 0x480571ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> gpio3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_gpio3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
{
.pa_start = 0x48059000,
.pa_end = 0x480591ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> gpio4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_gpio4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
{
.pa_start = 0x4805b000,
.pa_end = 0x4805b1ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> gpio5 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio5_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_gpio5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
{
.pa_start = 0x4805d000,
.pa_end = 0x4805d1ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> gpio6 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio6_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_gpio6_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
{
.pa_start = 0x50000000,
.pa_end = 0x500003ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l3_main_2 -> gpmc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_gpmc_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_gpmc_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -5032,75 +4078,35 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
{
.pa_start = 0x48070000,
.pa_end = 0x480700ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> i2c1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_i2c1_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_i2c1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
{
.pa_start = 0x48072000,
.pa_end = 0x480720ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> i2c2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_i2c2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_i2c2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
{
.pa_start = 0x48060000,
.pa_end = 0x480600ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> i2c3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_i2c3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_i2c3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
{
.pa_start = 0x48350000,
.pa_end = 0x483500ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> i2c4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_i2c4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_i2c4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -5138,39 +4144,19 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
.user = OCP_USER_IVA,
};
static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
{
.pa_start = 0x5a000000,
.pa_end = 0x5a07ffff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l3_main_2 -> iva */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_iva_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_iva_addrs,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
{
.pa_start = 0x4a31c000,
.pa_end = 0x4a31c07f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_wkup -> kbd */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_kbd_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_kbd_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -5228,335 +4214,147 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
.user = OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
{
.name = "mpu",
.pa_start = 0x40122000,
.pa_end = 0x401220ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> mcbsp1 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp1_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp1_addrs,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
{
.name = "dma",
.pa_start = 0x49022000,
.pa_end = 0x490220ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> mcbsp1 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp1_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp1_dma_addrs,
.user = OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
{
.name = "mpu",
.pa_start = 0x40124000,
.pa_end = 0x401240ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> mcbsp2 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp2_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp2_addrs,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
{
.name = "dma",
.pa_start = 0x49024000,
.pa_end = 0x490240ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> mcbsp2 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp2_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp2_dma_addrs,
.user = OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
{
.name = "mpu",
.pa_start = 0x40126000,
.pa_end = 0x401260ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> mcbsp3 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp3_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp3_addrs,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
{
.name = "dma",
.pa_start = 0x49026000,
.pa_end = 0x490260ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> mcbsp3 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp3_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp3_dma_addrs,
.user = OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
{
.pa_start = 0x48096000,
.pa_end = 0x480960ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mcbsp4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcbsp4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mcbsp4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
{
.name = "mpu",
.pa_start = 0x40132000,
.pa_end = 0x4013207f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> mcpdm */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcpdm_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcpdm_addrs,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
{
.name = "dma",
.pa_start = 0x49032000,
.pa_end = 0x4903207f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> mcpdm (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcpdm_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcpdm_dma_addrs,
.user = OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x480981ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mcspi1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcspi1_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mcspi1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a1ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mcspi2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcspi2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mcspi2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
{
.pa_start = 0x480b8000,
.pa_end = 0x480b81ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mcspi3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcspi3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mcspi3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
{
.pa_start = 0x480ba000,
.pa_end = 0x480ba1ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mcspi4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcspi4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mcspi4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
{
.pa_start = 0x4809c000,
.pa_end = 0x4809c3ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mmc1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mmc1_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mmc1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
{
.pa_start = 0x480b4000,
.pa_end = 0x480b43ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mmc2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mmc2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mmc2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
{
.pa_start = 0x480ad000,
.pa_end = 0x480ad3ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mmc3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mmc3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mmc3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
{
.pa_start = 0x480d1000,
.pa_end = 0x480d13ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mmc4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mmc4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mmc4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
{
.pa_start = 0x480d5000,
.pa_end = 0x480d53ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> mmc5 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mmc5_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mmc5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -5568,111 +4366,51 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
{
.pa_start = 0x4a0ad000,
.pa_end = 0x4a0ad01f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> ocp2scp_usb_phy */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_ocp2scp_usb_phy_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_ocp2scp_usb_phy_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
{
.pa_start = 0x48243000,
.pa_end = 0x48243fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* mpu_private -> prcm_mpu */
static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
.master = &omap44xx_mpu_private_hwmod,
.slave = &omap44xx_prcm_mpu_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_prcm_mpu_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
{
.pa_start = 0x4a004000,
.pa_end = 0x4a004fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_wkup -> cm_core_aon */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_cm_core_aon_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_cm_core_aon_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
{
.pa_start = 0x4a008000,
.pa_end = 0x4a009fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> cm_core */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_cm_core_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_cm_core_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
{
.pa_start = 0x4a306000,
.pa_end = 0x4a307fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_wkup -> prm */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_prm_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_prm_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
{
.pa_start = 0x4a30a000,
.pa_end = 0x4a30a7ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_wkup -> scrm */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_scrm_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_scrm_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -5810,447 +4548,195 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
{
.pa_start = 0x4a318000,
.pa_end = 0x4a31807f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_timer1_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_timer1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
{
.pa_start = 0x48032000,
.pa_end = 0x4803207f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
{
.pa_start = 0x48034000,
.pa_end = 0x4803407f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
{
.pa_start = 0x48036000,
.pa_end = 0x4803607f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
{
.pa_start = 0x40138000,
.pa_end = 0x4013807f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> timer5 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer5_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer5_addrs,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
{
.pa_start = 0x49038000,
.pa_end = 0x4903807f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> timer5 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer5_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer5_dma_addrs,
.user = OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
{
.pa_start = 0x4013a000,
.pa_end = 0x4013a07f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> timer6 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer6_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer6_addrs,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
{
.pa_start = 0x4903a000,
.pa_end = 0x4903a07f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> timer6 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer6_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer6_dma_addrs,
.user = OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
{
.pa_start = 0x4013c000,
.pa_end = 0x4013c07f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> timer7 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer7_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer7_addrs,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
{
.pa_start = 0x4903c000,
.pa_end = 0x4903c07f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> timer7 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer7_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer7_dma_addrs,
.user = OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
{
.pa_start = 0x4013e000,
.pa_end = 0x4013e07f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> timer8 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer8_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer8_addrs,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
{
.pa_start = 0x4903e000,
.pa_end = 0x4903e07f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_abe -> timer8 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer8_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer8_dma_addrs,
.user = OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
{
.pa_start = 0x4803e000,
.pa_end = 0x4803e07f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer9 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer9_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer9_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
{
.pa_start = 0x48086000,
.pa_end = 0x4808607f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer10 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer10_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer10_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
{
.pa_start = 0x48088000,
.pa_end = 0x4808807f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> timer11 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer11_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer11_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
{
.pa_start = 0x4806a000,
.pa_end = 0x4806a0ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> uart1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_uart1_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_uart1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
{
.pa_start = 0x4806c000,
.pa_end = 0x4806c0ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> uart2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_uart2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_uart2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
{
.pa_start = 0x48020000,
.pa_end = 0x480200ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> uart3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_uart3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_uart3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
{
.pa_start = 0x4806e000,
.pa_end = 0x4806e0ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per -> uart4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_uart4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_uart4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
{
.pa_start = 0x4a0a9000,
.pa_end = 0x4a0a93ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> usb_host_fs */
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_usb_host_fs_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_usb_host_fs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
{
.name = "uhh",
.pa_start = 0x4a064000,
.pa_end = 0x4a0647ff,
.flags = ADDR_TYPE_RT
},
{
.name = "ohci",
.pa_start = 0x4a064800,
.pa_end = 0x4a064bff,
},
{
.name = "ehci",
.pa_start = 0x4a064c00,
.pa_end = 0x4a064fff,
},
{}
};
/* l4_cfg -> usb_host_hs */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_usb_host_hs_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_usb_host_hs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
{
.pa_start = 0x4a0ab000,
.pa_end = 0x4a0ab7ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> usb_otg_hs */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_usb_otg_hs_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_usb_otg_hs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
{
.name = "tll",
.pa_start = 0x4a062000,
.pa_end = 0x4a063fff,
.flags = ADDR_TYPE_RT
},
{}
};
/* l4_cfg -> usb_tll_hs */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_usb_tll_hs_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_usb_tll_hs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
{
.pa_start = 0x4a314000,
.pa_end = 0x4a31407f,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_wd_timer2_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_wd_timer2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -6290,14 +4776,25 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
.user = OCP_USER_SDMA,
};
/* mpu -> emif1 */
static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
.master = &omap44xx_mpu_hwmod,
.slave = &omap44xx_emif1_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> emif2 */
static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
.master = &omap44xx_mpu_hwmod,
.slave = &omap44xx_emif2_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_c2c__c2c_target_fw,
&omap44xx_l4_cfg__c2c_target_fw,
&omap44xx_l3_main_1__dmm,
&omap44xx_mpu__dmm,
&omap44xx_c2c__emif_fw,
&omap44xx_dmm__emif_fw,
&omap44xx_l4_cfg__emif_fw,
&omap44xx_iva__l3_instr,
&omap44xx_l3_main_3__l3_instr,
&omap44xx_ocp_wp_noc__l3_instr,
......@@ -6308,7 +4805,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_mmc1__l3_main_1,
&omap44xx_mmc2__l3_main_1,
&omap44xx_mpu__l3_main_1,
&omap44xx_c2c_target_fw__l3_main_2,
&omap44xx_debugss__l3_main_2,
&omap44xx_dma_system__l3_main_2,
&omap44xx_fdif__l3_main_2,
......@@ -6364,8 +4860,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l3_main_2__dss_venc,
&omap44xx_l4_per__dss_venc,
&omap44xx_l4_per__elm,
&omap44xx_emif_fw__emif1,
&omap44xx_emif_fw__emif2,
&omap44xx_l4_cfg__fdif,
&omap44xx_l4_wkup__gpio1,
&omap44xx_l4_per__gpio2,
......@@ -6450,6 +4944,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_wkup__wd_timer2,
&omap44xx_l4_abe__wd_timer3,
&omap44xx_l4_abe__wd_timer3_dma,
&omap44xx_mpu__emif1,
&omap44xx_mpu__emif2,
NULL,
};
......
arch/arm/mach-omap2/usb-host.c
View file @ 777d466d
......@@ -188,125 +188,6 @@ static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
return;
}
static
void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
{
switch (port_mode[0]) {
case OMAP_EHCI_PORT_MODE_PHY:
omap_mux_init_signal("usbb1_ulpiphy_stp",
OMAP_PIN_OUTPUT);
omap_mux_init_signal("usbb1_ulpiphy_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpiphy_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpiphy_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpiphy_dat0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpiphy_dat1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpiphy_dat2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpiphy_dat3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpiphy_dat4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpiphy_dat5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpiphy_dat6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpiphy_dat7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_EHCI_PORT_MODE_TLL:
omap_mux_init_signal("usbb1_ulpitll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("usbb1_ulpitll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpitll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpitll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpitll_dat0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpitll_dat1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpitll_dat2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpitll_dat3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpitll_dat4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpitll_dat5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpitll_dat6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_ulpitll_dat7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
default:
break;
}
switch (port_mode[1]) {
case OMAP_EHCI_PORT_MODE_PHY:
omap_mux_init_signal("usbb2_ulpiphy_stp",
OMAP_PIN_OUTPUT);
omap_mux_init_signal("usbb2_ulpiphy_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpiphy_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpiphy_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpiphy_dat0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpiphy_dat1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpiphy_dat2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpiphy_dat3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpiphy_dat4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpiphy_dat5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpiphy_dat6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpiphy_dat7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_EHCI_PORT_MODE_TLL:
omap_mux_init_signal("usbb2_ulpitll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("usbb2_ulpitll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpitll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpitll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpitll_dat0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpitll_dat1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpitll_dat2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpitll_dat3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpitll_dat4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpitll_dat5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpitll_dat6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_ulpitll_dat7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
default:
break;
}
}
static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
{
switch (port_mode[0]) {
......@@ -404,78 +285,6 @@ static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
}
}
static
void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
{
switch (port_mode[0]) {
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
omap_mux_init_signal("usbb1_mm_rxdp",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_mm_rxdm",
OMAP_PIN_INPUT_PULLDOWN);
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
omap_mux_init_signal("usbb1_mm_rxrcv",
OMAP_PIN_INPUT_PULLDOWN);
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
omap_mux_init_signal("usbb1_mm_txen",
OMAP_PIN_INPUT_PULLDOWN);
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
omap_mux_init_signal("usbb1_mm_txdat",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb1_mm_txse0",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
default:
break;
}
switch (port_mode[1]) {
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
omap_mux_init_signal("usbb2_mm_rxdp",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_mm_rxdm",
OMAP_PIN_INPUT_PULLDOWN);
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
omap_mux_init_signal("usbb2_mm_rxrcv",
OMAP_PIN_INPUT_PULLDOWN);
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
omap_mux_init_signal("usbb2_mm_txen",
OMAP_PIN_INPUT_PULLDOWN);
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
omap_mux_init_signal("usbb2_mm_txdat",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("usbb2_mm_txse0",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
default:
break;
}
}
void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
{
struct omap_hwmod *uhh_hwm, *tll_hwm;
......@@ -489,9 +298,6 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
if (omap_rev() <= OMAP3430_REV_ES2_1)
pdata->single_ulpi_bypass = true;
} else if (cpu_is_omap44xx()) {
setup_4430ehci_io_mux(pdata->port_mode);
setup_4430ohci_io_mux(pdata->port_mode);
}
uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
......
arch/arm/mach-omap2/usb-musb.c
View file @ 777d466d
......@@ -85,9 +85,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
musb_plat.mode = board_data->mode;
musb_plat.extvbus = board_data->extvbus;
if (cpu_is_omap44xx())
musb_plat.has_mailbox = true;
if (soc_is_am35xx()) {
oh_name = "am35x_otg_hs";
name = "musb-am35x";
......
drivers/bus/omap-ocp2scp.c
View file @ 777d466d
......@@ -22,26 +22,6 @@
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_data/omap_ocp2scp.h>
/**
* _count_resources - count for the number of resources
* @res: struct resource *
*
* Count and return the number of resources populated for the device that is
* connected to ocp2scp.
*/
static unsigned _count_resources(struct resource *res)
{
int cnt = 0;
while (res->start != res->end) {
cnt++;
res++;
}
return cnt;
}
static int ocp2scp_remove_devices(struct device *dev, void *c)
{
......@@ -55,11 +35,7 @@ static int ocp2scp_remove_devices(struct device *dev, void *c)
static int omap_ocp2scp_probe(struct platform_device *pdev)
{
int ret;
unsigned res_cnt, i;
struct device_node *np = pdev->dev.of_node;
struct platform_device *pdev_child;
struct omap_ocp2scp_platform_data *pdata = pdev->dev.platform_data;
struct omap_ocp2scp_dev *dev;
if (np) {
ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
......@@ -68,48 +44,12 @@ static int omap_ocp2scp_probe(struct platform_device *pdev)
"failed to add resources for ocp2scp child\n");
goto err0;
}
} else if (pdata) {
for (i = 0, dev = *pdata->devices; i < pdata->dev_cnt; i++,
dev++) {
res_cnt = _count_resources(dev->res);
pdev_child = platform_device_alloc(dev->drv_name,
PLATFORM_DEVID_AUTO);
if (!pdev_child) {
dev_err(&pdev->dev,
"failed to allocate mem for ocp2scp child\n");
goto err0;
}
ret = platform_device_add_resources(pdev_child,
dev->res, res_cnt);
if (ret) {
dev_err(&pdev->dev,
"failed to add resources for ocp2scp child\n");
goto err1;
}
pdev_child->dev.parent = &pdev->dev;
ret = platform_device_add(pdev_child);
if (ret) {
dev_err(&pdev->dev,
"failed to register ocp2scp child device\n");
goto err1;
}
}
} else {
dev_err(&pdev->dev, "OCP2SCP initialized without plat data\n");
return -EINVAL;
}
pm_runtime_enable(&pdev->dev);
return 0;
err1:
platform_device_put(pdev_child);
err0:
device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
......
include/linux/platform_data/omap_ocp2scp.h deleted 100644 → 0
View file @ 214099b0
/*
* omap_ocp2scp.h -- ocp2scp header file
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Author: Kishon Vijay Abraham I <kishon@ti.com>
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __DRIVERS_OMAP_OCP2SCP_H
#define __DRIVERS_OMAP_OCP2SCP_H
struct omap_ocp2scp_dev {
const char *drv_name;
struct resource *res;
};
struct omap_ocp2scp_platform_data {
int dev_cnt;
struct omap_ocp2scp_dev **devices;
};
#endif /* __DRIVERS_OMAP_OCP2SCP_H */
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