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Commit 77a80e23 authored by Hariprasad Shenai's avatar Hariprasad Shenai Committed by David S. Miller
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RDMA/cxgb4: Cleanup Filter related macros/register defines 

This patch cleanups all filter related macros/register defines that are defined
in t4fw_api.h and the affected files.
Signed-off-by: default avatarHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2f90ade6
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Inline Side-by-side
Showing with 337 additions and 337 deletions
drivers/infiniband/hw/cxgb4/cm.c
View file @ 77a80e23
......@@ -1762,10 +1762,10 @@ static void send_fw_act_open_req(struct c4iw_ep *ep, unsigned int atid)
req->le.pport = sin->sin_port;
req->le.u.ipv4.pip = sin->sin_addr.s_addr;
req->tcb.t_state_to_astid =
htonl(V_FW_OFLD_CONNECTION_WR_T_STATE(TCP_SYN_SENT) |
V_FW_OFLD_CONNECTION_WR_ASTID(atid));
htonl(FW_OFLD_CONNECTION_WR_T_STATE_V(TCP_SYN_SENT) |
FW_OFLD_CONNECTION_WR_ASTID_V(atid));
req->tcb.cplrxdataack_cplpassacceptrpl =
htons(F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK);
htons(FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F);
req->tcb.tx_max = (__force __be32) jiffies;
req->tcb.rcv_adv = htons(1);
best_mtu(ep->com.dev->rdev.lldi.mtus, ep->mtu, &mtu_idx,
......@@ -3539,7 +3539,7 @@ static void send_fw_pass_open_req(struct c4iw_dev *dev, struct sk_buff *skb,
memset(req, 0, sizeof(*req));
req->op_compl = htonl(V_WR_OP(FW_OFLD_CONNECTION_WR) | FW_WR_COMPL_F);
req->len16_pkd = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*req), 16)));
req->le.version_cpl = htonl(F_FW_OFLD_CONNECTION_WR_CPL);
req->le.version_cpl = htonl(FW_OFLD_CONNECTION_WR_CPL_F);
req->le.filter = (__force __be32) filter;
req->le.lport = lport;
req->le.pport = rport;
......@@ -3548,9 +3548,9 @@ static void send_fw_pass_open_req(struct c4iw_dev *dev, struct sk_buff *skb,
req->tcb.rcv_nxt = htonl(rcv_isn + 1);
req->tcb.rcv_adv = htons(window);
req->tcb.t_state_to_astid =
htonl(V_FW_OFLD_CONNECTION_WR_T_STATE(TCP_SYN_RECV) |
V_FW_OFLD_CONNECTION_WR_RCV_SCALE(cpl->tcpopt.wsf) |
V_FW_OFLD_CONNECTION_WR_ASTID(
htonl(FW_OFLD_CONNECTION_WR_T_STATE_V(TCP_SYN_RECV) |
FW_OFLD_CONNECTION_WR_RCV_SCALE_V(cpl->tcpopt.wsf) |
FW_OFLD_CONNECTION_WR_ASTID_V(
GET_PASS_OPEN_TID(ntohl(cpl->tos_stid))));
/*
......
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
View file @ 77a80e23
......@@ -1342,49 +1342,49 @@ static int set_filter_wr(struct adapter *adapter, int fidx)
fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
fwr->tid_to_iq =
htonl(V_FW_FILTER_WR_TID(ftid) |
V_FW_FILTER_WR_RQTYPE(f->fs.type) |
V_FW_FILTER_WR_NOREPLY(0) |
V_FW_FILTER_WR_IQ(f->fs.iq));
htonl(FW_FILTER_WR_TID_V(ftid) |
FW_FILTER_WR_RQTYPE_V(f->fs.type) |
FW_FILTER_WR_NOREPLY_V(0) |
FW_FILTER_WR_IQ_V(f->fs.iq));
fwr->del_filter_to_l2tix =
htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
f->fs.newvlan == VLAN_REWRITE) |
V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
f->fs.newvlan == VLAN_REWRITE) |
V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
V_FW_FILTER_WR_PRIO(f->fs.prio) |
V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
FW_FILTER_WR_PRIO_V(f->fs.prio) |
FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
fwr->ethtype = htons(f->fs.val.ethtype);
fwr->ethtypem = htons(f->fs.mask.ethtype);
fwr->frag_to_ovlan_vldm =
(V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
(FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
fwr->smac_sel = 0;
fwr->rx_chan_rx_rpl_iq =
htons(V_FW_FILTER_WR_RX_CHAN(0) |
V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
htons(FW_FILTER_WR_RX_CHAN_V(0) |
FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
fwr->maci_to_matchtypem =
htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
V_FW_FILTER_WR_PORT(f->fs.val.iport) |
V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
FW_FILTER_WR_PORT_V(f->fs.val.iport) |
FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
fwr->ptcl = f->fs.val.proto;
fwr->ptclm = f->fs.mask.proto;
fwr->ttyp = f->fs.val.tos;
......
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
View file @ 77a80e23
......@@ -2556,11 +2556,11 @@ void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
memset(wr, 0, sizeof(*wr));
wr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
wr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*wr) / 16));
wr->tid_to_iq = htonl(V_FW_FILTER_WR_TID(ftid) |
V_FW_FILTER_WR_NOREPLY(qid < 0));
wr->del_filter_to_l2tix = htonl(F_FW_FILTER_WR_DEL_FILTER);
wr->tid_to_iq = htonl(FW_FILTER_WR_TID_V(ftid) |
FW_FILTER_WR_NOREPLY_V(qid < 0));
wr->del_filter_to_l2tix = htonl(FW_FILTER_WR_DEL_FILTER_F);
if (qid >= 0)
wr->rx_chan_rx_rpl_iq = htons(V_FW_FILTER_WR_RX_RPL_IQ(qid));
wr->rx_chan_rx_rpl_iq = htons(FW_FILTER_WR_RX_RPL_IQ_V(qid));
}
#define INIT_CMD(var, cmd, rd_wr) do { \
......
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
View file @ 77a80e23
......@@ -197,239 +197,239 @@ struct fw_filter_wr {
__u8 sma[6];
};
#define S_FW_FILTER_WR_TID 12
#define M_FW_FILTER_WR_TID 0xfffff
#define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
#define G_FW_FILTER_WR_TID(x) \
(((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
#define S_FW_FILTER_WR_RQTYPE 11
#define M_FW_FILTER_WR_RQTYPE 0x1
#define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
#define G_FW_FILTER_WR_RQTYPE(x) \
(((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
#define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U)
#define S_FW_FILTER_WR_NOREPLY 10
#define M_FW_FILTER_WR_NOREPLY 0x1
#define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
#define G_FW_FILTER_WR_NOREPLY(x) \
(((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
#define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U)
#define S_FW_FILTER_WR_IQ 0
#define M_FW_FILTER_WR_IQ 0x3ff
#define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
#define G_FW_FILTER_WR_IQ(x) \
(((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
#define S_FW_FILTER_WR_DEL_FILTER 31
#define M_FW_FILTER_WR_DEL_FILTER 0x1
#define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
#define G_FW_FILTER_WR_DEL_FILTER(x) \
(((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
#define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
#define S_FW_FILTER_WR_RPTTID 25
#define M_FW_FILTER_WR_RPTTID 0x1
#define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
#define G_FW_FILTER_WR_RPTTID(x) \
(((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
#define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U)
#define S_FW_FILTER_WR_DROP 24
#define M_FW_FILTER_WR_DROP 0x1
#define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
#define G_FW_FILTER_WR_DROP(x) \
(((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
#define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U)
#define S_FW_FILTER_WR_DIRSTEER 23
#define M_FW_FILTER_WR_DIRSTEER 0x1
#define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
#define G_FW_FILTER_WR_DIRSTEER(x) \
(((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
#define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U)
#define S_FW_FILTER_WR_MASKHASH 22
#define M_FW_FILTER_WR_MASKHASH 0x1
#define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
#define G_FW_FILTER_WR_MASKHASH(x) \
(((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
#define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U)
#define S_FW_FILTER_WR_DIRSTEERHASH 21
#define M_FW_FILTER_WR_DIRSTEERHASH 0x1
#define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
#define G_FW_FILTER_WR_DIRSTEERHASH(x) \
(((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
#define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U)
#define S_FW_FILTER_WR_LPBK 20
#define M_FW_FILTER_WR_LPBK 0x1
#define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
#define G_FW_FILTER_WR_LPBK(x) \
(((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
#define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U)
#define S_FW_FILTER_WR_DMAC 19
#define M_FW_FILTER_WR_DMAC 0x1
#define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
#define G_FW_FILTER_WR_DMAC(x) \
(((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
#define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U)
#define S_FW_FILTER_WR_SMAC 18
#define M_FW_FILTER_WR_SMAC 0x1
#define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC)
#define G_FW_FILTER_WR_SMAC(x) \
(((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
#define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U)
#define S_FW_FILTER_WR_INSVLAN 17
#define M_FW_FILTER_WR_INSVLAN 0x1
#define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
#define G_FW_FILTER_WR_INSVLAN(x) \
(((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
#define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U)
#define S_FW_FILTER_WR_RMVLAN 16
#define M_FW_FILTER_WR_RMVLAN 0x1
#define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
#define G_FW_FILTER_WR_RMVLAN(x) \
(((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
#define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U)
#define S_FW_FILTER_WR_HITCNTS 15
#define M_FW_FILTER_WR_HITCNTS 0x1
#define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
#define G_FW_FILTER_WR_HITCNTS(x) \
(((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
#define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U)
#define S_FW_FILTER_WR_TXCHAN 13
#define M_FW_FILTER_WR_TXCHAN 0x3
#define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
#define G_FW_FILTER_WR_TXCHAN(x) \
(((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
#define S_FW_FILTER_WR_PRIO 12
#define M_FW_FILTER_WR_PRIO 0x1
#define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
#define G_FW_FILTER_WR_PRIO(x) \
(((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
#define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U)
#define S_FW_FILTER_WR_L2TIX 0
#define M_FW_FILTER_WR_L2TIX 0xfff
#define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
#define G_FW_FILTER_WR_L2TIX(x) \
(((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
#define S_FW_FILTER_WR_FRAG 7
#define M_FW_FILTER_WR_FRAG 0x1
#define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
#define G_FW_FILTER_WR_FRAG(x) \
(((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
#define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U)
#define S_FW_FILTER_WR_FRAGM 6
#define M_FW_FILTER_WR_FRAGM 0x1
#define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
#define G_FW_FILTER_WR_FRAGM(x) \
(((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
#define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U)
#define S_FW_FILTER_WR_IVLAN_VLD 5
#define M_FW_FILTER_WR_IVLAN_VLD 0x1
#define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
#define G_FW_FILTER_WR_IVLAN_VLD(x) \
(((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
#define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U)
#define S_FW_FILTER_WR_OVLAN_VLD 4
#define M_FW_FILTER_WR_OVLAN_VLD 0x1
#define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
#define G_FW_FILTER_WR_OVLAN_VLD(x) \
(((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
#define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U)
#define S_FW_FILTER_WR_IVLAN_VLDM 3
#define M_FW_FILTER_WR_IVLAN_VLDM 0x1
#define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
#define G_FW_FILTER_WR_IVLAN_VLDM(x) \
(((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
#define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U)
#define S_FW_FILTER_WR_OVLAN_VLDM 2
#define M_FW_FILTER_WR_OVLAN_VLDM 0x1
#define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
#define G_FW_FILTER_WR_OVLAN_VLDM(x) \
(((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
#define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U)
#define S_FW_FILTER_WR_RX_CHAN 15
#define M_FW_FILTER_WR_RX_CHAN 0x1
#define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
#define G_FW_FILTER_WR_RX_CHAN(x) \
(((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
#define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U)
#define S_FW_FILTER_WR_RX_RPL_IQ 0
#define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff
#define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
#define G_FW_FILTER_WR_RX_RPL_IQ(x) \
(((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
#define S_FW_FILTER_WR_MACI 23
#define M_FW_FILTER_WR_MACI 0x1ff
#define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
#define G_FW_FILTER_WR_MACI(x) \
(((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
#define S_FW_FILTER_WR_MACIM 14
#define M_FW_FILTER_WR_MACIM 0x1ff
#define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
#define G_FW_FILTER_WR_MACIM(x) \
(((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
#define S_FW_FILTER_WR_FCOE 13
#define M_FW_FILTER_WR_FCOE 0x1
#define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
#define G_FW_FILTER_WR_FCOE(x) \
(((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
#define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U)
#define S_FW_FILTER_WR_FCOEM 12
#define M_FW_FILTER_WR_FCOEM 0x1
#define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
#define G_FW_FILTER_WR_FCOEM(x) \
(((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
#define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U)
#define S_FW_FILTER_WR_PORT 9
#define M_FW_FILTER_WR_PORT 0x7
#define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
#define G_FW_FILTER_WR_PORT(x) \
(((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
#define S_FW_FILTER_WR_PORTM 6
#define M_FW_FILTER_WR_PORTM 0x7
#define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
#define G_FW_FILTER_WR_PORTM(x) \
(((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
#define S_FW_FILTER_WR_MATCHTYPE 3
#define M_FW_FILTER_WR_MATCHTYPE 0x7
#define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
#define G_FW_FILTER_WR_MATCHTYPE(x) \
(((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
#define S_FW_FILTER_WR_MATCHTYPEM 0
#define M_FW_FILTER_WR_MATCHTYPEM 0x7
#define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
#define G_FW_FILTER_WR_MATCHTYPEM(x) \
(((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
#define FW_FILTER_WR_TID_S 12
#define FW_FILTER_WR_TID_M 0xfffff
#define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S)
#define FW_FILTER_WR_TID_G(x) \
(((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
#define FW_FILTER_WR_RQTYPE_S 11
#define FW_FILTER_WR_RQTYPE_M 0x1
#define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S)
#define FW_FILTER_WR_RQTYPE_G(x) \
(((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
#define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U)
#define FW_FILTER_WR_NOREPLY_S 10
#define FW_FILTER_WR_NOREPLY_M 0x1
#define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S)
#define FW_FILTER_WR_NOREPLY_G(x) \
(((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
#define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U)
#define FW_FILTER_WR_IQ_S 0
#define FW_FILTER_WR_IQ_M 0x3ff
#define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S)
#define FW_FILTER_WR_IQ_G(x) \
(((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
#define FW_FILTER_WR_DEL_FILTER_S 31
#define FW_FILTER_WR_DEL_FILTER_M 0x1
#define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S)
#define FW_FILTER_WR_DEL_FILTER_G(x) \
(((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
#define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U)
#define FW_FILTER_WR_RPTTID_S 25
#define FW_FILTER_WR_RPTTID_M 0x1
#define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S)
#define FW_FILTER_WR_RPTTID_G(x) \
(((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
#define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U)
#define FW_FILTER_WR_DROP_S 24
#define FW_FILTER_WR_DROP_M 0x1
#define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S)
#define FW_FILTER_WR_DROP_G(x) \
(((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
#define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U)
#define FW_FILTER_WR_DIRSTEER_S 23
#define FW_FILTER_WR_DIRSTEER_M 0x1
#define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S)
#define FW_FILTER_WR_DIRSTEER_G(x) \
(((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
#define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
#define FW_FILTER_WR_MASKHASH_S 22
#define FW_FILTER_WR_MASKHASH_M 0x1
#define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S)
#define FW_FILTER_WR_MASKHASH_G(x) \
(((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
#define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
#define FW_FILTER_WR_DIRSTEERHASH_S 21
#define FW_FILTER_WR_DIRSTEERHASH_M 0x1
#define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
#define FW_FILTER_WR_DIRSTEERHASH_G(x) \
(((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
#define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U)
#define FW_FILTER_WR_LPBK_S 20
#define FW_FILTER_WR_LPBK_M 0x1
#define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S)
#define FW_FILTER_WR_LPBK_G(x) \
(((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
#define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U)
#define FW_FILTER_WR_DMAC_S 19
#define FW_FILTER_WR_DMAC_M 0x1
#define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S)
#define FW_FILTER_WR_DMAC_G(x) \
(((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
#define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U)
#define FW_FILTER_WR_SMAC_S 18
#define FW_FILTER_WR_SMAC_M 0x1
#define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S)
#define FW_FILTER_WR_SMAC_G(x) \
(((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
#define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U)
#define FW_FILTER_WR_INSVLAN_S 17
#define FW_FILTER_WR_INSVLAN_M 0x1
#define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S)
#define FW_FILTER_WR_INSVLAN_G(x) \
(((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
#define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U)
#define FW_FILTER_WR_RMVLAN_S 16
#define FW_FILTER_WR_RMVLAN_M 0x1
#define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S)
#define FW_FILTER_WR_RMVLAN_G(x) \
(((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
#define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U)
#define FW_FILTER_WR_HITCNTS_S 15
#define FW_FILTER_WR_HITCNTS_M 0x1
#define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S)
#define FW_FILTER_WR_HITCNTS_G(x) \
(((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
#define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U)
#define FW_FILTER_WR_TXCHAN_S 13
#define FW_FILTER_WR_TXCHAN_M 0x3
#define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S)
#define FW_FILTER_WR_TXCHAN_G(x) \
(((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
#define FW_FILTER_WR_PRIO_S 12
#define FW_FILTER_WR_PRIO_M 0x1
#define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S)
#define FW_FILTER_WR_PRIO_G(x) \
(((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
#define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U)
#define FW_FILTER_WR_L2TIX_S 0
#define FW_FILTER_WR_L2TIX_M 0xfff
#define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
#define FW_FILTER_WR_L2TIX_G(x) \
(((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
#define FW_FILTER_WR_FRAG_S 7
#define FW_FILTER_WR_FRAG_M 0x1
#define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S)
#define FW_FILTER_WR_FRAG_G(x) \
(((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
#define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U)
#define FW_FILTER_WR_FRAGM_S 6
#define FW_FILTER_WR_FRAGM_M 0x1
#define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
#define FW_FILTER_WR_FRAGM_G(x) \
(((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
#define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U)
#define FW_FILTER_WR_IVLAN_VLD_S 5
#define FW_FILTER_WR_IVLAN_VLD_M 0x1
#define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S)
#define FW_FILTER_WR_IVLAN_VLD_G(x) \
(((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
#define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U)
#define FW_FILTER_WR_OVLAN_VLD_S 4
#define FW_FILTER_WR_OVLAN_VLD_M 0x1
#define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S)
#define FW_FILTER_WR_OVLAN_VLD_G(x) \
(((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
#define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U)
#define FW_FILTER_WR_IVLAN_VLDM_S 3
#define FW_FILTER_WR_IVLAN_VLDM_M 0x1
#define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
#define FW_FILTER_WR_IVLAN_VLDM_G(x) \
(((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
#define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U)
#define FW_FILTER_WR_OVLAN_VLDM_S 2
#define FW_FILTER_WR_OVLAN_VLDM_M 0x1
#define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
#define FW_FILTER_WR_OVLAN_VLDM_G(x) \
(((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
#define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U)
#define FW_FILTER_WR_RX_CHAN_S 15
#define FW_FILTER_WR_RX_CHAN_M 0x1
#define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S)
#define FW_FILTER_WR_RX_CHAN_G(x) \
(((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
#define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U)
#define FW_FILTER_WR_RX_RPL_IQ_S 0
#define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff
#define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
#define FW_FILTER_WR_RX_RPL_IQ_G(x) \
(((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
#define FW_FILTER_WR_MACI_S 23
#define FW_FILTER_WR_MACI_M 0x1ff
#define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)
#define FW_FILTER_WR_MACI_G(x) \
(((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
#define FW_FILTER_WR_MACIM_S 14
#define FW_FILTER_WR_MACIM_M 0x1ff
#define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
#define FW_FILTER_WR_MACIM_G(x) \
(((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
#define FW_FILTER_WR_FCOE_S 13
#define FW_FILTER_WR_FCOE_M 0x1
#define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S)
#define FW_FILTER_WR_FCOE_G(x) \
(((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
#define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U)
#define FW_FILTER_WR_FCOEM_S 12
#define FW_FILTER_WR_FCOEM_M 0x1
#define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
#define FW_FILTER_WR_FCOEM_G(x) \
(((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
#define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U)
#define FW_FILTER_WR_PORT_S 9
#define FW_FILTER_WR_PORT_M 0x7
#define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S)
#define FW_FILTER_WR_PORT_G(x) \
(((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
#define FW_FILTER_WR_PORTM_S 6
#define FW_FILTER_WR_PORTM_M 0x7
#define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
#define FW_FILTER_WR_PORTM_G(x) \
(((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
#define FW_FILTER_WR_MATCHTYPE_S 3
#define FW_FILTER_WR_MATCHTYPE_M 0x7
#define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S)
#define FW_FILTER_WR_MATCHTYPE_G(x) \
(((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
#define FW_FILTER_WR_MATCHTYPEM_S 0
#define FW_FILTER_WR_MATCHTYPEM_M 0x7
#define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S)
#define FW_FILTER_WR_MATCHTYPEM_G(x) \
(((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
struct fw_ulptx_wr {
__be32 op_to_compl;
......@@ -491,65 +491,65 @@ struct fw_ofld_connection_wr {
} tcb;
};
#define S_FW_OFLD_CONNECTION_WR_VERSION 31
#define M_FW_OFLD_CONNECTION_WR_VERSION 0x1
#define V_FW_OFLD_CONNECTION_WR_VERSION(x) \
((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
#define G_FW_OFLD_CONNECTION_WR_VERSION(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
M_FW_OFLD_CONNECTION_WR_VERSION)
#define F_FW_OFLD_CONNECTION_WR_VERSION \
V_FW_OFLD_CONNECTION_WR_VERSION(1U)
#define S_FW_OFLD_CONNECTION_WR_CPL 30
#define M_FW_OFLD_CONNECTION_WR_CPL 0x1
#define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL)
#define G_FW_OFLD_CONNECTION_WR_CPL(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
#define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U)
#define S_FW_OFLD_CONNECTION_WR_T_STATE 28
#define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf
#define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \
((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
#define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
M_FW_OFLD_CONNECTION_WR_T_STATE)
#define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24
#define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf
#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
#define S_FW_OFLD_CONNECTION_WR_ASTID 0
#define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff
#define V_FW_OFLD_CONNECTION_WR_ASTID(x) \
((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
#define G_FW_OFLD_CONNECTION_WR_ASTID(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
#define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15
#define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1
#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \
V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
#define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14
#define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1
#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \
V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
#define FW_OFLD_CONNECTION_WR_VERSION_S 31
#define FW_OFLD_CONNECTION_WR_VERSION_M 0x1
#define FW_OFLD_CONNECTION_WR_VERSION_V(x) \
((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
#define FW_OFLD_CONNECTION_WR_VERSION_G(x) \
(((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
FW_OFLD_CONNECTION_WR_VERSION_M)
#define FW_OFLD_CONNECTION_WR_VERSION_F \
FW_OFLD_CONNECTION_WR_VERSION_V(1U)
#define FW_OFLD_CONNECTION_WR_CPL_S 30
#define FW_OFLD_CONNECTION_WR_CPL_M 0x1
#define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
#define FW_OFLD_CONNECTION_WR_CPL_G(x) \
(((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
#define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U)
#define FW_OFLD_CONNECTION_WR_T_STATE_S 28
#define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf
#define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \
((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
#define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \
(((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
FW_OFLD_CONNECTION_WR_T_STATE_M)
#define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24
#define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf
#define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \
((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
#define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \
(((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
#define FW_OFLD_CONNECTION_WR_ASTID_S 0
#define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff
#define FW_OFLD_CONNECTION_WR_ASTID_V(x) \
((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
#define FW_OFLD_CONNECTION_WR_ASTID_G(x) \
(((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15
#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1
#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \
((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \
(((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \
FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14
#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1
#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \
((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \
(((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \
FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
enum fw_flowc_mnem {
FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
......
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