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Commit 7825e0c4 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Olof Johansson:
 "A handful of fixes before final release:

  Marvell Armada:
   - One to fix a typo in the devicetree specifying memory ranges for
     the crypto engine
   - Two to deal with marking PCI and device-memory as strongly ordered
     to avoid hardware deadlocks, in particular when enabling above
     crypto driver.
   - Compile fix for PM

  Allwinner:
   - DT clock fixes to deal with u-boot-enabled framebuffer (simplefb).
   - Make R8 (C.H.I.P. SoC) inherit system compatibility from A13 to
     make clocks register proper.

  Tegra:
   - Fix SD card voltage setting on the Tegra3 Beaver dev board

  Misc:
   - Two maintainers updates for STM32 and STi platforms"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: tegra: beaver: Allow SD card voltage to be changed
  MAINTAINERS: update STi maintainer list
  MAINTAINERS: update STM32 maintainers list
  ARM: mvebu: compile pm code conditionally
  ARM: dts: sun7i: Fix pll3x2 and pll7x2 not having a parent clock
  ARM: dts: sunxi: Add pll3 to simplefb nodes clocks lists
  ARM: dts: armada-38x: fix MBUS_ID for crypto SRAM on Armada 385 Linksys
  ARM: mvebu: map PCI I/O regions strongly ordered
  ARM: mvebu: fix HW I/O coherency related deadlocks
  ARM: sunxi/dt: make the CHIP inherit from allwinner,sun5i-a13
parents 48d4ca56 5eb49534
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MAINTAINERS
View file @ 7825e0c4
...@@ -1694,8 +1694,6 @@ S: Maintained ...@@ -1694,8 +1694,6 @@ S: Maintained
F: drivers/edac/altera_edac. F: drivers/edac/altera_edac.
ARM/STI ARCHITECTURE ARM/STI ARCHITECTURE
M: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>
M: Maxime Coquelin <maxime.coquelin@st.com>
M: Patrice Chotard <patrice.chotard@st.com> M: Patrice Chotard <patrice.chotard@st.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: kernel@stlinux.com L: kernel@stlinux.com
...@@ -1728,6 +1726,7 @@ F: drivers/ata/ahci_st.c ...@@ -1728,6 +1726,7 @@ F: drivers/ata/ahci_st.c
ARM/STM32 ARCHITECTURE ARM/STM32 ARCHITECTURE
M: Maxime Coquelin <mcoquelin.stm32@gmail.com> M: Maxime Coquelin <mcoquelin.stm32@gmail.com>
M: Alexandre Torgue <alexandre.torgue@st.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32.git
......
arch/arm/boot/dts/armada-385-linksys.dtsi
View file @ 7825e0c4
...@@ -58,8 +58,8 @@ memory { ...@@ -58,8 +58,8 @@ memory {
soc { soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs { internal-regs {
......
arch/arm/boot/dts/sun4i-a10.dtsi
View file @ 7825e0c4
...@@ -65,8 +65,9 @@ framebuffer@0 { ...@@ -65,8 +65,9 @@ framebuffer@0 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi"; allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
<&ahb_gates 44>, <&dram_gates 26>; <&ahb_gates 43>, <&ahb_gates 44>,
<&dram_gates 26>;
status = "disabled"; status = "disabled";
}; };
...@@ -74,8 +75,9 @@ framebuffer@1 { ...@@ -74,8 +75,9 @@ framebuffer@1 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
<&ahb_gates 44>, <&ahb_gates 46>, <&ahb_gates 43>, <&ahb_gates 44>,
<&ahb_gates 46>,
<&dram_gates 25>, <&dram_gates 26>; <&dram_gates 25>, <&dram_gates 26>;
status = "disabled"; status = "disabled";
}; };
...@@ -84,9 +86,9 @@ framebuffer@2 { ...@@ -84,9 +86,9 @@ framebuffer@2 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0"; allwinner,pipeline = "de_fe0-de_be0-lcd0";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
<&ahb_gates 46>, <&dram_gates 25>, <&ahb_gates 44>, <&ahb_gates 46>,
<&dram_gates 26>; <&dram_gates 25>, <&dram_gates 26>;
status = "disabled"; status = "disabled";
}; };
...@@ -94,8 +96,9 @@ framebuffer@3 { ...@@ -94,8 +96,9 @@ framebuffer@3 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
<&ahb_gates 44>, <&ahb_gates 46>, <&ahb_gates 36>, <&ahb_gates 44>,
<&ahb_gates 46>,
<&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>;
status = "disabled"; status = "disabled";
}; };
......
arch/arm/boot/dts/sun5i-a10s.dtsi
View file @ 7825e0c4
...@@ -65,8 +65,8 @@ framebuffer@0 { ...@@ -65,8 +65,8 @@ framebuffer@0 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi"; allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
<&ahb_gates 44>; <&ahb_gates 43>, <&ahb_gates 44>;
status = "disabled"; status = "disabled";
}; };
...@@ -74,7 +74,8 @@ framebuffer@1 { ...@@ -74,7 +74,8 @@ framebuffer@1 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0"; allwinner,pipeline = "de_be0-lcd0";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
<&ahb_gates 44>;
status = "disabled"; status = "disabled";
}; };
...@@ -82,8 +83,8 @@ framebuffer@2 { ...@@ -82,8 +83,8 @@ framebuffer@2 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0"; allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
<&ahb_gates 44>; <&ahb_gates 36>, <&ahb_gates 44>;
status = "disabled"; status = "disabled";
}; };
}; };
......
arch/arm/boot/dts/sun5i-r8-chip.dts
View file @ 7825e0c4
...@@ -52,7 +52,7 @@ ...@@ -52,7 +52,7 @@
/ { / {
model = "NextThing C.H.I.P."; model = "NextThing C.H.I.P.";
compatible = "nextthing,chip", "allwinner,sun5i-r8"; compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13";
aliases { aliases {
i2c0 = &i2c0; i2c0 = &i2c0;
......
arch/arm/boot/dts/sun7i-a20.dtsi
View file @ 7825e0c4
...@@ -67,8 +67,9 @@ framebuffer@0 { ...@@ -67,8 +67,9 @@ framebuffer@0 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi"; allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
<&ahb_gates 44>, <&dram_gates 26>; <&ahb_gates 43>, <&ahb_gates 44>,
<&dram_gates 26>;
status = "disabled"; status = "disabled";
}; };
...@@ -76,8 +77,8 @@ framebuffer@1 { ...@@ -76,8 +77,8 @@ framebuffer@1 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0"; allwinner,pipeline = "de_be0-lcd0";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
<&dram_gates 26>; <&ahb_gates 44>, <&dram_gates 26>;
status = "disabled"; status = "disabled";
}; };
...@@ -85,7 +86,7 @@ framebuffer@2 { ...@@ -85,7 +86,7 @@ framebuffer@2 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0"; allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <&pll5 1>, clocks = <&pll3>, <&pll5 1>,
<&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>,
<&dram_gates 5>, <&dram_gates 26>; <&dram_gates 5>, <&dram_gates 26>;
status = "disabled"; status = "disabled";
...@@ -231,6 +232,7 @@ pll3: clk@01c20010 { ...@@ -231,6 +232,7 @@ pll3: clk@01c20010 {
pll3x2: pll3x2_clk { pll3x2: pll3x2_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&pll3>;
clock-div = <1>; clock-div = <1>;
clock-mult = <2>; clock-mult = <2>;
clock-output-names = "pll3-2x"; clock-output-names = "pll3-2x";
...@@ -272,6 +274,7 @@ pll7: clk@01c20030 { ...@@ -272,6 +274,7 @@ pll7: clk@01c20030 {
pll7x2: pll7x2_clk { pll7x2: pll7x2_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&pll7>;
clock-div = <1>; clock-div = <1>;
clock-mult = <2>; clock-mult = <2>;
clock-output-names = "pll7-2x"; clock-output-names = "pll7-2x";
......
arch/arm/boot/dts/tegra30-beaver.dts
View file @ 7825e0c4
...@@ -1843,7 +1843,7 @@ ldo4_reg: ldo4 { ...@@ -1843,7 +1843,7 @@ ldo4_reg: ldo4 {
ldo5_reg: ldo5 { ldo5_reg: ldo5 {
regulator-name = "vddio_sdmmc,avdd_vdac"; regulator-name = "vddio_sdmmc,avdd_vdac";
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-always-on; regulator-always-on;
}; };
...@@ -1914,6 +1914,7 @@ i2s@70080400 { ...@@ -1914,6 +1914,7 @@ i2s@70080400 {
sdhci@78000000 { sdhci@78000000 {
status = "okay"; status = "okay";
vqmmc-supply = <&ldo5_reg>;
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
......
arch/arm/mach-mvebu/Makefile
View file @ 7825e0c4
...@@ -7,9 +7,15 @@ CFLAGS_pmsu.o := -march=armv7-a ...@@ -7,9 +7,15 @@ CFLAGS_pmsu.o := -march=armv7-a
obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o
ifeq ($(CONFIG_MACH_MVEBU_V7),y) ifeq ($(CONFIG_MACH_MVEBU_V7),y)
obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o pm.o pm-board.o obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o
obj-$(CONFIG_PM) += pm.o pm-board.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
endif endif
obj-$(CONFIG_MACH_DOVE) += dove.o obj-$(CONFIG_MACH_DOVE) += dove.o
obj-$(CONFIG_MACH_KIRKWOOD) += kirkwood.o kirkwood-pm.o
ifeq ($(CONFIG_MACH_KIRKWOOD),y)
obj-y += kirkwood.o
obj-$(CONFIG_PM) += kirkwood-pm.o
endif
arch/arm/mach-mvebu/coherency.c
View file @ 7825e0c4
...@@ -162,22 +162,16 @@ static void __init armada_370_coherency_init(struct device_node *np) ...@@ -162,22 +162,16 @@ static void __init armada_370_coherency_init(struct device_node *np)
} }
/* /*
* This ioremap hook is used on Armada 375/38x to ensure that PCIe * This ioremap hook is used on Armada 375/38x to ensure that all MMIO
* memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is
* is needed as a workaround for a deadlock issue between the PCIe * needed for the HW I/O coherency mechanism to work properly without
* interface and the cache controller. * deadlock.
*/ */
static void __iomem * static void __iomem *
armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size, armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
unsigned int mtype, void *caller) unsigned int mtype, void *caller)
{ {
struct resource pcie_mem;
mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
mtype = MT_UNCACHED; mtype = MT_UNCACHED;
return __arm_ioremap_caller(phys_addr, size, mtype, caller); return __arm_ioremap_caller(phys_addr, size, mtype, caller);
} }
...@@ -186,7 +180,8 @@ static void __init armada_375_380_coherency_init(struct device_node *np) ...@@ -186,7 +180,8 @@ static void __init armada_375_380_coherency_init(struct device_node *np)
struct device_node *cache_dn; struct device_node *cache_dn;
coherency_cpu_base = of_iomap(np, 0); coherency_cpu_base = of_iomap(np, 0);
arch_ioremap_caller = armada_pcie_wa_ioremap_caller; arch_ioremap_caller = armada_wa_ioremap_caller;
pci_ioremap_set_mem_type(MT_UNCACHED);
/* /*
* We should switch the PL310 to I/O coherency mode only if * We should switch the PL310 to I/O coherency mode only if
......
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