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nexedi
linux
Commits
797b2fb8
Commit
797b2fb8
authored
May 19, 2017
by
Ben Skeggs
Browse files
Options
Browse Files
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Email Patches
Plain Diff
drm/nouveau/disp/g84-: port OR HDMI control to nvkm_ior
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
0df18246
Changes
29
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Showing
29 changed files
with
134 additions
and
219 deletions
+134
-219
drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
+1
-3
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
+1
-3
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
+0
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
+0
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
+0
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
+0
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c
+0
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c
+0
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
+0
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
+1
-3
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
+0
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.h
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c
+14
-47
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c
+13
-46
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c
+14
-47
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c
+14
-48
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
+11
-0
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
+1
-3
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c
+0
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
+0
-6
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
+39
-3
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg84.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg84.c
+3
-0
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
+3
-0
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c
+3
-0
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c
+3
-0
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
+3
-0
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c
+3
-0
drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp77.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp77.c
+3
-0
drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp89.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp89.c
+3
-0
No files found.
drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
View file @
797b2fb8
...
@@ -39,9 +39,7 @@ g84_disp = {
...
@@ -39,9 +39,7 @@ g84_disp = {
.
outp
.
external
.
tmds
=
nv50_pior_output_new
,
.
outp
.
external
.
tmds
=
nv50_pior_output_new
,
.
outp
.
external
.
dp
=
nv50_pior_dp_new
,
.
outp
.
external
.
dp
=
nv50_pior_dp_new
,
.
dac
=
{
.
nr
=
3
,
.
new
=
nv50_dac_new
},
.
dac
=
{
.
nr
=
3
,
.
new
=
nv50_dac_new
},
.
sor
.
nr
=
2
,
.
sor
=
{
.
nr
=
2
,
.
new
=
g84_sor_new
},
.
sor
.
new
=
g84_sor_new
,
.
sor
.
hdmi
=
g84_hdmi_ctrl
,
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
};
};
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
View file @
797b2fb8
...
@@ -40,9 +40,7 @@ g94_disp = {
...
@@ -40,9 +40,7 @@ g94_disp = {
.
outp
.
external
.
tmds
=
nv50_pior_output_new
,
.
outp
.
external
.
tmds
=
nv50_pior_output_new
,
.
outp
.
external
.
dp
=
nv50_pior_dp_new
,
.
outp
.
external
.
dp
=
nv50_pior_dp_new
,
.
dac
=
{
.
nr
=
3
,
.
new
=
nv50_dac_new
},
.
dac
=
{
.
nr
=
3
,
.
new
=
nv50_dac_new
},
.
sor
.
nr
=
4
,
.
sor
=
{
.
nr
=
4
,
.
new
=
g94_sor_new
},
.
sor
.
new
=
g94_sor_new
,
.
sor
.
hdmi
=
g84_hdmi_ctrl
,
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
};
};
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
View file @
797b2fb8
...
@@ -510,7 +510,6 @@ gf119_disp = {
...
@@ -510,7 +510,6 @@ gf119_disp = {
.
sor
.
nr
=
4
,
.
sor
.
nr
=
4
,
.
sor
.
new
=
gf119_sor_new
,
.
sor
.
new
=
gf119_sor_new
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hdmi
=
gf119_hdmi_ctrl
,
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
View file @
797b2fb8
...
@@ -42,7 +42,6 @@ gk104_disp = {
...
@@ -42,7 +42,6 @@ gk104_disp = {
.
sor
.
nr
=
4
,
.
sor
.
nr
=
4
,
.
sor
.
new
=
gk104_sor_new
,
.
sor
.
new
=
gk104_sor_new
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hdmi
=
gk104_hdmi_ctrl
,
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
View file @
797b2fb8
...
@@ -42,7 +42,6 @@ gk110_disp = {
...
@@ -42,7 +42,6 @@ gk110_disp = {
.
sor
.
nr
=
4
,
.
sor
.
nr
=
4
,
.
sor
.
new
=
gk104_sor_new
,
.
sor
.
new
=
gk104_sor_new
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hdmi
=
gk104_hdmi_ctrl
,
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
View file @
797b2fb8
...
@@ -42,7 +42,6 @@ gm107_disp = {
...
@@ -42,7 +42,6 @@ gm107_disp = {
.
sor
.
nr
=
4
,
.
sor
.
nr
=
4
,
.
sor
.
new
=
gm107_sor_new
,
.
sor
.
new
=
gm107_sor_new
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hdmi
=
gk104_hdmi_ctrl
,
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c
View file @
797b2fb8
...
@@ -42,7 +42,6 @@ gm200_disp = {
...
@@ -42,7 +42,6 @@ gm200_disp = {
.
sor
.
nr
=
4
,
.
sor
.
nr
=
4
,
.
sor
.
new
=
gm200_sor_new
,
.
sor
.
new
=
gm200_sor_new
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hdmi
=
gk104_hdmi_ctrl
,
.
sor
.
magic
=
gm200_sor_magic
,
.
sor
.
magic
=
gm200_sor_magic
,
};
};
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c
View file @
797b2fb8
...
@@ -40,7 +40,6 @@ gp100_disp = {
...
@@ -40,7 +40,6 @@ gp100_disp = {
.
sor
.
nr
=
4
,
.
sor
.
nr
=
4
,
.
sor
.
new
=
gm200_sor_new
,
.
sor
.
new
=
gm200_sor_new
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hdmi
=
gk104_hdmi_ctrl
,
.
sor
.
magic
=
gm200_sor_magic
,
.
sor
.
magic
=
gm200_sor_magic
,
};
};
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
View file @
797b2fb8
...
@@ -66,7 +66,6 @@ gp102_disp = {
...
@@ -66,7 +66,6 @@ gp102_disp = {
.
sor
.
nr
=
4
,
.
sor
.
nr
=
4
,
.
sor
.
new
=
gm200_sor_new
,
.
sor
.
new
=
gm200_sor_new
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hda_eld
=
gf119_hda_eld
,
.
sor
.
hdmi
=
gk104_hdmi_ctrl
,
.
sor
.
magic
=
gm200_sor_magic
,
.
sor
.
magic
=
gm200_sor_magic
,
};
};
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
View file @
797b2fb8
...
@@ -39,9 +39,7 @@ gt200_disp = {
...
@@ -39,9 +39,7 @@ gt200_disp = {
.
outp
.
external
.
tmds
=
nv50_pior_output_new
,
.
outp
.
external
.
tmds
=
nv50_pior_output_new
,
.
outp
.
external
.
dp
=
nv50_pior_dp_new
,
.
outp
.
external
.
dp
=
nv50_pior_dp_new
,
.
dac
=
{
.
nr
=
3
,
.
new
=
nv50_dac_new
},
.
dac
=
{
.
nr
=
3
,
.
new
=
nv50_dac_new
},
.
sor
.
nr
=
2
,
.
sor
=
{
.
nr
=
2
,
.
new
=
g84_sor_new
},
.
sor
.
new
=
g84_sor_new
,
.
sor
.
hdmi
=
g84_hdmi_ctrl
,
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
};
};
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
View file @
797b2fb8
...
@@ -43,7 +43,6 @@ gt215_disp = {
...
@@ -43,7 +43,6 @@ gt215_disp = {
.
sor
.
nr
=
4
,
.
sor
.
nr
=
4
,
.
sor
.
new
=
gt215_sor_new
,
.
sor
.
new
=
gt215_sor_new
,
.
sor
.
hda_eld
=
gt215_hda_eld
,
.
sor
.
hda_eld
=
gt215_hda_eld
,
.
sor
.
hdmi
=
gt215_hdmi_ctrl
,
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
};
};
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.h
View file @
797b2fb8
#ifndef __NVKM_DISP_HDMI_H__
#ifndef __NVKM_DISP_HDMI_H__
#define __NVKM_DISP_HDMI_H__
#define __NVKM_DISP_HDMI_H__
#include "
nv50
.h"
#include "
ior
.h"
struct
packed_hdmi_infoframe
{
struct
packed_hdmi_infoframe
{
u32
header
;
u32
header
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c
View file @
797b2fb8
...
@@ -23,65 +23,33 @@
...
@@ -23,65 +23,33 @@
*/
*/
#include "hdmi.h"
#include "hdmi.h"
#include <core/client.h>
void
g84_hdmi_ctrl
(
struct
nvkm_ior
*
ior
,
int
head
,
bool
enable
,
u8
max_ac_packet
,
#include <nvif/cl5070.h>
u8
rekey
,
u8
*
avi
,
u8
avi_size
,
u8
*
vendor
,
u8
vendor_size
)
#include <nvif/unpack.h>
int
g84_hdmi_ctrl
(
NV50_DISP_MTHD_V1
)
{
{
struct
nvkm_device
*
device
=
disp
->
base
.
engine
.
subdev
.
device
;
struct
nvkm_device
*
device
=
ior
->
disp
->
engine
.
subdev
.
device
;
const
u32
hoff
=
(
head
*
0x800
);
const
u32
ctrl
=
0x40000000
*
enable
|
union
{
0x1f000000
/* ??? */
|
struct
nv50_disp_sor_hdmi_pwr_v0
v0
;
max_ac_packet
<<
16
|
}
*
args
=
data
;
rekey
;
const
u32
hoff
=
head
*
0x800
;
struct
packed_hdmi_infoframe
avi_infoframe
;
struct
packed_hdmi_infoframe
avi_infoframe
;
struct
packed_hdmi_infoframe
vendor_infoframe
;
struct
packed_hdmi_infoframe
vendor_infoframe
;
u32
ctrl
;
int
ret
=
-
ENOSYS
;
nvif_ioctl
(
object
,
"disp sor hdmi ctrl size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
true
)))
{
nvif_ioctl
(
object
,
"disp sor hdmi ctrl vers %d state %d "
"max_ac_packet %d rekey %d
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
state
,
args
->
v0
.
max_ac_packet
,
args
->
v0
.
rekey
);
if
(
args
->
v0
.
max_ac_packet
>
0x1f
||
args
->
v0
.
rekey
>
0x7f
)
return
-
EINVAL
;
ctrl
=
0x40000000
*
!!
args
->
v0
.
state
;
ctrl
|=
args
->
v0
.
max_ac_packet
<<
16
;
ctrl
|=
args
->
v0
.
rekey
;
ctrl
|=
0x1f000000
;
/* ??? */
}
else
return
ret
;
if
((
args
->
v0
.
avi_infoframe_length
+
args
->
v0
.
vendor_infoframe_length
)
>
size
)
return
-
ENOSYS
;
else
if
((
args
->
v0
.
avi_infoframe_length
+
args
->
v0
.
vendor_infoframe_length
)
<
size
)
return
-
E2BIG
;
pack_hdmi_infoframe
(
&
avi_infoframe
,
data
,
args
->
v0
.
avi_infoframe_length
);
pack_hdmi_infoframe
(
&
vendor_infoframe
,
pack_hdmi_infoframe
(
&
avi_infoframe
,
avi
,
avi_size
);
data
+
args
->
v0
.
avi_infoframe_length
,
pack_hdmi_infoframe
(
&
vendor_infoframe
,
vendor
,
vendor_size
);
args
->
v0
.
vendor_infoframe_length
);
if
(
!
(
ctrl
&
0x40000000
))
{
if
(
!
(
ctrl
&
0x40000000
))
{
nvkm_mask
(
device
,
0x6165a4
+
hoff
,
0x40000000
,
0x00000000
);
nvkm_mask
(
device
,
0x6165a4
+
hoff
,
0x40000000
,
0x00000000
);
nvkm_mask
(
device
,
0x61653c
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x61653c
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x616520
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x616520
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x616500
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x616500
+
hoff
,
0x00000001
,
0x00000000
);
return
0
;
return
;
}
}
/* AVI InfoFrame */
/* AVI InfoFrame */
nvkm_mask
(
device
,
0x616520
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x616520
+
hoff
,
0x00000001
,
0x00000000
);
if
(
a
rgs
->
v0
.
avi_infoframe_length
)
{
if
(
a
vi_size
)
{
nvkm_wr32
(
device
,
0x616528
+
hoff
,
avi_infoframe
.
header
);
nvkm_wr32
(
device
,
0x616528
+
hoff
,
avi_infoframe
.
header
);
nvkm_wr32
(
device
,
0x61652c
+
hoff
,
avi_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x61652c
+
hoff
,
avi_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x616530
+
hoff
,
avi_infoframe
.
subpack0_high
);
nvkm_wr32
(
device
,
0x616530
+
hoff
,
avi_infoframe
.
subpack0_high
);
...
@@ -99,7 +67,7 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
...
@@ -99,7 +67,7 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
/* Vendor InfoFrame */
/* Vendor InfoFrame */
nvkm_mask
(
device
,
0x61653c
+
hoff
,
0x00010001
,
0x00010000
);
nvkm_mask
(
device
,
0x61653c
+
hoff
,
0x00010001
,
0x00010000
);
if
(
args
->
v0
.
vendor_infoframe_length
)
{
if
(
vendor_size
)
{
nvkm_wr32
(
device
,
0x616544
+
hoff
,
vendor_infoframe
.
header
);
nvkm_wr32
(
device
,
0x616544
+
hoff
,
vendor_infoframe
.
header
);
nvkm_wr32
(
device
,
0x616548
+
hoff
,
vendor_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x616548
+
hoff
,
vendor_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x61654c
+
hoff
,
vendor_infoframe
.
subpack0_high
);
nvkm_wr32
(
device
,
0x61654c
+
hoff
,
vendor_infoframe
.
subpack0_high
);
...
@@ -120,5 +88,4 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
...
@@ -120,5 +88,4 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
/* HDMI_CTRL */
/* HDMI_CTRL */
nvkm_mask
(
device
,
0x6165a4
+
hoff
,
0x5f1f007f
,
ctrl
);
nvkm_mask
(
device
,
0x6165a4
+
hoff
,
0x5f1f007f
,
ctrl
);
return
0
;
}
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c
View file @
797b2fb8
...
@@ -23,64 +23,32 @@
...
@@ -23,64 +23,32 @@
*/
*/
#include "hdmi.h"
#include "hdmi.h"
#include <core/client.h>
void
gf119_hdmi_ctrl
(
struct
nvkm_ior
*
ior
,
int
head
,
bool
enable
,
u8
max_ac_packet
,
#include <nvif/cl5070.h>
u8
rekey
,
u8
*
avi
,
u8
avi_size
,
u8
*
vendor
,
u8
vendor_size
)
#include <nvif/unpack.h>
int
gf119_hdmi_ctrl
(
NV50_DISP_MTHD_V1
)
{
{
struct
nvkm_device
*
device
=
disp
->
base
.
engine
.
subdev
.
device
;
struct
nvkm_device
*
device
=
ior
->
disp
->
engine
.
subdev
.
device
;
const
u32
hoff
=
(
head
*
0x800
);
const
u32
ctrl
=
0x40000000
*
enable
|
union
{
max_ac_packet
<<
16
|
struct
nv50_disp_sor_hdmi_pwr_v0
v0
;
rekey
;
}
*
args
=
data
;
const
u32
hoff
=
head
*
0x800
;
struct
packed_hdmi_infoframe
avi_infoframe
;
struct
packed_hdmi_infoframe
avi_infoframe
;
struct
packed_hdmi_infoframe
vendor_infoframe
;
struct
packed_hdmi_infoframe
vendor_infoframe
;
u32
ctrl
;
int
ret
=
-
ENOSYS
;
nvif_ioctl
(
object
,
"disp sor hdmi ctrl size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
true
)))
{
nvif_ioctl
(
object
,
"disp sor hdmi ctrl vers %d state %d "
"max_ac_packet %d rekey %d
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
state
,
args
->
v0
.
max_ac_packet
,
args
->
v0
.
rekey
);
if
(
args
->
v0
.
max_ac_packet
>
0x1f
||
args
->
v0
.
rekey
>
0x7f
)
return
-
EINVAL
;
ctrl
=
0x40000000
*
!!
args
->
v0
.
state
;
ctrl
|=
args
->
v0
.
max_ac_packet
<<
16
;
ctrl
|=
args
->
v0
.
rekey
;
}
else
return
ret
;
if
((
args
->
v0
.
avi_infoframe_length
+
args
->
v0
.
vendor_infoframe_length
)
>
size
)
return
-
ENOSYS
;
else
if
((
args
->
v0
.
avi_infoframe_length
+
args
->
v0
.
vendor_infoframe_length
)
<
size
)
return
-
E2BIG
;
pack_hdmi_infoframe
(
&
avi_infoframe
,
data
,
args
->
v0
.
avi_infoframe_length
);
pack_hdmi_infoframe
(
&
vendor_infoframe
,
pack_hdmi_infoframe
(
&
avi_infoframe
,
avi
,
avi_size
);
data
+
args
->
v0
.
avi_infoframe_length
,
pack_hdmi_infoframe
(
&
vendor_infoframe
,
vendor
,
vendor_size
);
args
->
v0
.
vendor_infoframe_length
);
if
(
!
(
ctrl
&
0x40000000
))
{
if
(
!
(
ctrl
&
0x40000000
))
{
nvkm_mask
(
device
,
0x616798
+
hoff
,
0x40000000
,
0x00000000
);
nvkm_mask
(
device
,
0x616798
+
hoff
,
0x40000000
,
0x00000000
);
nvkm_mask
(
device
,
0x616730
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x616730
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x6167a4
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x6167a4
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x616714
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x616714
+
hoff
,
0x00000001
,
0x00000000
);
return
0
;
return
;
}
}
/* AVI InfoFrame */
/* AVI InfoFrame */
nvkm_mask
(
device
,
0x616714
+
hoff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x616714
+
hoff
,
0x00000001
,
0x00000000
);
if
(
a
rgs
->
v0
.
avi_infoframe_length
)
{
if
(
a
vi_size
)
{
nvkm_wr32
(
device
,
0x61671c
+
hoff
,
avi_infoframe
.
header
);
nvkm_wr32
(
device
,
0x61671c
+
hoff
,
avi_infoframe
.
header
);
nvkm_wr32
(
device
,
0x616720
+
hoff
,
avi_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x616720
+
hoff
,
avi_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x616724
+
hoff
,
avi_infoframe
.
subpack0_high
);
nvkm_wr32
(
device
,
0x616724
+
hoff
,
avi_infoframe
.
subpack0_high
);
...
@@ -91,7 +59,7 @@ gf119_hdmi_ctrl(NV50_DISP_MTHD_V1)
...
@@ -91,7 +59,7 @@ gf119_hdmi_ctrl(NV50_DISP_MTHD_V1)
/* GENERIC(?) / Vendor InfoFrame? */
/* GENERIC(?) / Vendor InfoFrame? */
nvkm_mask
(
device
,
0x616730
+
hoff
,
0x00010001
,
0x00010000
);
nvkm_mask
(
device
,
0x616730
+
hoff
,
0x00010001
,
0x00010000
);
if
(
args
->
v0
.
vendor_infoframe_length
)
{
if
(
vendor_size
)
{
/*
/*
* These appear to be the audio infoframe registers,
* These appear to be the audio infoframe registers,
* but no other set of infoframe registers has yet
* but no other set of infoframe registers has yet
...
@@ -111,5 +79,4 @@ gf119_hdmi_ctrl(NV50_DISP_MTHD_V1)
...
@@ -111,5 +79,4 @@ gf119_hdmi_ctrl(NV50_DISP_MTHD_V1)
/* HDMI_CTRL */
/* HDMI_CTRL */
nvkm_mask
(
device
,
0x616798
+
hoff
,
0x401f007f
,
ctrl
);
nvkm_mask
(
device
,
0x616798
+
hoff
,
0x401f007f
,
ctrl
);
return
0
;
}
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c
View file @
797b2fb8
...
@@ -23,65 +23,33 @@
...
@@ -23,65 +23,33 @@
*/
*/
#include "hdmi.h"
#include "hdmi.h"
#include <core/client.h>
void
gk104_hdmi_ctrl
(
struct
nvkm_ior
*
ior
,
int
head
,
bool
enable
,
u8
max_ac_packet
,
#include <nvif/cl5070.h>
u8
rekey
,
u8
*
avi
,
u8
avi_size
,
u8
*
vendor
,
u8
vendor_size
)
#include <nvif/unpack.h>
int
gk104_hdmi_ctrl
(
NV50_DISP_MTHD_V1
)
{
{
struct
nvkm_device
*
device
=
disp
->
base
.
engine
.
subdev
.
device
;
struct
nvkm_device
*
device
=
ior
->
disp
->
engine
.
subdev
.
device
;
const
u32
hoff
=
(
head
*
0x800
);
const
u32
ctrl
=
0x40000000
*
enable
|
const
u32
hdmi
=
(
head
*
0x400
);
max_ac_packet
<<
16
|
union
{
rekey
;
struct
nv50_disp_sor_hdmi_pwr_v0
v
0
;
const
u32
hoff
=
head
*
0x80
0
;
}
*
args
=
data
;
const
u32
hdmi
=
head
*
0x400
;
struct
packed_hdmi_infoframe
avi_infoframe
;
struct
packed_hdmi_infoframe
avi_infoframe
;
struct
packed_hdmi_infoframe
vendor_infoframe
;
struct
packed_hdmi_infoframe
vendor_infoframe
;
u32
ctrl
;
int
ret
=
-
ENOSYS
;
nvif_ioctl
(
object
,
"disp sor hdmi ctrl size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
true
)))
{
nvif_ioctl
(
object
,
"disp sor hdmi ctrl vers %d state %d "
"max_ac_packet %d rekey %d
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
state
,
args
->
v0
.
max_ac_packet
,
args
->
v0
.
rekey
);
if
(
args
->
v0
.
max_ac_packet
>
0x1f
||
args
->
v0
.
rekey
>
0x7f
)
return
-
EINVAL
;
ctrl
=
0x40000000
*
!!
args
->
v0
.
state
;
ctrl
|=
args
->
v0
.
max_ac_packet
<<
16
;
ctrl
|=
args
->
v0
.
rekey
;
}
else
return
ret
;
if
((
args
->
v0
.
avi_infoframe_length
+
args
->
v0
.
vendor_infoframe_length
)
>
size
)
return
-
ENOSYS
;
else
if
((
args
->
v0
.
avi_infoframe_length
+
args
->
v0
.
vendor_infoframe_length
)
<
size
)
return
-
E2BIG
;
pack_hdmi_infoframe
(
&
avi_infoframe
,
data
,
args
->
v0
.
avi_infoframe_length
);
pack_hdmi_infoframe
(
&
vendor_infoframe
,
pack_hdmi_infoframe
(
&
avi_infoframe
,
avi
,
avi_size
);
data
+
args
->
v0
.
avi_infoframe_length
,
pack_hdmi_infoframe
(
&
vendor_infoframe
,
vendor
,
vendor_size
);
args
->
v0
.
vendor_infoframe_length
);
if
(
!
(
ctrl
&
0x40000000
))
{
if
(
!
(
ctrl
&
0x40000000
))
{
nvkm_mask
(
device
,
0x616798
+
hoff
,
0x40000000
,
0x00000000
);
nvkm_mask
(
device
,
0x616798
+
hoff
,
0x40000000
,
0x00000000
);
nvkm_mask
(
device
,
0x690100
+
hdmi
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x690100
+
hdmi
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x6900c0
+
hdmi
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x6900c0
+
hdmi
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x690000
+
hdmi
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x690000
+
hdmi
,
0x00000001
,
0x00000000
);
return
0
;
return
;
}
}
/* AVI InfoFrame */
/* AVI InfoFrame */
nvkm_mask
(
device
,
0x690000
+
hdmi
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x690000
+
hdmi
,
0x00000001
,
0x00000000
);
if
(
a
rgs
->
v0
.
avi_infoframe_length
)
{
if
(
a
vi_size
)
{
nvkm_wr32
(
device
,
0x690008
+
hdmi
,
avi_infoframe
.
header
);
nvkm_wr32
(
device
,
0x690008
+
hdmi
,
avi_infoframe
.
header
);
nvkm_wr32
(
device
,
0x69000c
+
hdmi
,
avi_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x69000c
+
hdmi
,
avi_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x690010
+
hdmi
,
avi_infoframe
.
subpack0_high
);
nvkm_wr32
(
device
,
0x690010
+
hdmi
,
avi_infoframe
.
subpack0_high
);
...
@@ -92,7 +60,7 @@ gk104_hdmi_ctrl(NV50_DISP_MTHD_V1)
...
@@ -92,7 +60,7 @@ gk104_hdmi_ctrl(NV50_DISP_MTHD_V1)
/* GENERIC(?) / Vendor InfoFrame? */
/* GENERIC(?) / Vendor InfoFrame? */
nvkm_mask
(
device
,
0x690100
+
hdmi
,
0x00010001
,
0x00000000
);
nvkm_mask
(
device
,
0x690100
+
hdmi
,
0x00010001
,
0x00000000
);
if
(
args
->
v0
.
vendor_infoframe_length
)
{
if
(
vendor_size
)
{
nvkm_wr32
(
device
,
0x690108
+
hdmi
,
vendor_infoframe
.
header
);
nvkm_wr32
(
device
,
0x690108
+
hdmi
,
vendor_infoframe
.
header
);
nvkm_wr32
(
device
,
0x69010c
+
hdmi
,
vendor_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x69010c
+
hdmi
,
vendor_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x690110
+
hdmi
,
vendor_infoframe
.
subpack0_high
);
nvkm_wr32
(
device
,
0x690110
+
hdmi
,
vendor_infoframe
.
subpack0_high
);
...
@@ -111,5 +79,4 @@ gk104_hdmi_ctrl(NV50_DISP_MTHD_V1)
...
@@ -111,5 +79,4 @@ gk104_hdmi_ctrl(NV50_DISP_MTHD_V1)
/* HDMI_CTRL */
/* HDMI_CTRL */
nvkm_mask
(
device
,
0x616798
+
hoff
,
0x401f007f
,
ctrl
);
nvkm_mask
(
device
,
0x616798
+
hoff
,
0x401f007f
,
ctrl
);
return
0
;
}
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c
View file @
797b2fb8
...
@@ -22,67 +22,34 @@
...
@@ -22,67 +22,34 @@
* Authors: Ben Skeggs
* Authors: Ben Skeggs
*/
*/
#include "hdmi.h"
#include "hdmi.h"
#include "outp.h"
#include <core/client.h>
void
gt215_hdmi_ctrl
(
struct
nvkm_ior
*
ior
,
int
head
,
bool
enable
,
u8
max_ac_packet
,
#include <nvif/cl5070.h>
u8
rekey
,
u8
*
avi
,
u8
avi_size
,
u8
*
vendor
,
u8
vendor_size
)
#include <nvif/unpack.h>
int
gt215_hdmi_ctrl
(
NV50_DISP_MTHD_V1
)
{
{
struct
nvkm_device
*
device
=
disp
->
base
.
engine
.
subdev
.
device
;
struct
nvkm_device
*
device
=
ior
->
disp
->
engine
.
subdev
.
device
;
const
u32
soff
=
outp
->
or
*
0x800
;
const
u32
ctrl
=
0x40000000
*
enable
|
union
{
0x1f000000
/* ??? */
|
struct
nv50_disp_sor_hdmi_pwr_v0
v0
;
max_ac_packet
<<
16
|
}
*
args
=
data
;
rekey
;
const
u32
soff
=
nv50_ior_base
(
ior
);
struct
packed_hdmi_infoframe
avi_infoframe
;
struct
packed_hdmi_infoframe
avi_infoframe
;
struct
packed_hdmi_infoframe
vendor_infoframe
;
struct
packed_hdmi_infoframe
vendor_infoframe
;
u32
ctrl
;
int
ret
=
-
ENOSYS
;
nvif_ioctl
(
object
,
"disp sor hdmi ctrl size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
true
)))
{
nvif_ioctl
(
object
,
"disp sor hdmi ctrl vers %d state %d "
"max_ac_packet %d rekey %d
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
state
,
args
->
v0
.
max_ac_packet
,
args
->
v0
.
rekey
);
if
(
args
->
v0
.
max_ac_packet
>
0x1f
||
args
->
v0
.
rekey
>
0x7f
)
return
-
EINVAL
;
ctrl
=
0x40000000
*
!!
args
->
v0
.
state
;
ctrl
|=
args
->
v0
.
max_ac_packet
<<
16
;
ctrl
|=
args
->
v0
.
rekey
;
ctrl
|=
0x1f000000
;
/* ??? */
}
else
return
ret
;
if
((
args
->
v0
.
avi_infoframe_length
+
args
->
v0
.
vendor_infoframe_length
)
>
size
)
return
-
ENOSYS
;
else
if
((
args
->
v0
.
avi_infoframe_length
+
args
->
v0
.
vendor_infoframe_length
)
<
size
)
return
-
E2BIG
;
pack_hdmi_infoframe
(
&
avi_infoframe
,
data
,
args
->
v0
.
avi_infoframe_length
);
pack_hdmi_infoframe
(
&
vendor_infoframe
,
pack_hdmi_infoframe
(
&
avi_infoframe
,
avi
,
avi_size
);
data
+
args
->
v0
.
avi_infoframe_length
,
pack_hdmi_infoframe
(
&
vendor_infoframe
,
vendor
,
vendor_size
);
args
->
v0
.
vendor_infoframe_length
);
if
(
!
(
ctrl
&
0x40000000
))
{
if
(
!
(
ctrl
&
0x40000000
))
{
nvkm_mask
(
device
,
0x61c5a4
+
soff
,
0x40000000
,
0x00000000
);
nvkm_mask
(
device
,
0x61c5a4
+
soff
,
0x40000000
,
0x00000000
);
nvkm_mask
(
device
,
0x61c53c
+
soff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x61c53c
+
soff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x61c520
+
soff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x61c520
+
soff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x61c500
+
soff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x61c500
+
soff
,
0x00000001
,
0x00000000
);
return
0
;
return
;
}
}
/* AVI InfoFrame */
/* AVI InfoFrame */
nvkm_mask
(
device
,
0x61c520
+
soff
,
0x00000001
,
0x00000000
);
nvkm_mask
(
device
,
0x61c520
+
soff
,
0x00000001
,
0x00000000
);
if
(
a
rgs
->
v0
.
avi_infoframe_length
)
{
if
(
a
vi_size
)
{
nvkm_wr32
(
device
,
0x61c528
+
soff
,
avi_infoframe
.
header
);
nvkm_wr32
(
device
,
0x61c528
+
soff
,
avi_infoframe
.
header
);
nvkm_wr32
(
device
,
0x61c52c
+
soff
,
avi_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x61c52c
+
soff
,
avi_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x61c530
+
soff
,
avi_infoframe
.
subpack0_high
);
nvkm_wr32
(
device
,
0x61c530
+
soff
,
avi_infoframe
.
subpack0_high
);
...
@@ -100,7 +67,7 @@ gt215_hdmi_ctrl(NV50_DISP_MTHD_V1)
...
@@ -100,7 +67,7 @@ gt215_hdmi_ctrl(NV50_DISP_MTHD_V1)
/* Vendor InfoFrame */
/* Vendor InfoFrame */
nvkm_mask
(
device
,
0x61c53c
+
soff
,
0x00010001
,
0x00010000
);
nvkm_mask
(
device
,
0x61c53c
+
soff
,
0x00010001
,
0x00010000
);
if
(
args
->
v0
.
vendor_infoframe_length
)
{
if
(
vendor_size
)
{
nvkm_wr32
(
device
,
0x61c544
+
soff
,
vendor_infoframe
.
header
);
nvkm_wr32
(
device
,
0x61c544
+
soff
,
vendor_infoframe
.
header
);
nvkm_wr32
(
device
,
0x61c548
+
soff
,
vendor_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x61c548
+
soff
,
vendor_infoframe
.
subpack0_low
);
nvkm_wr32
(
device
,
0x61c54c
+
soff
,
vendor_infoframe
.
subpack0_high
);
nvkm_wr32
(
device
,
0x61c54c
+
soff
,
vendor_infoframe
.
subpack0_high
);
...
@@ -121,5 +88,4 @@ gt215_hdmi_ctrl(NV50_DISP_MTHD_V1)
...
@@ -121,5 +88,4 @@ gt215_hdmi_ctrl(NV50_DISP_MTHD_V1)
/* HDMI_CTRL */
/* HDMI_CTRL */
nvkm_mask
(
device
,
0x61c5a4
+
soff
,
0x5f1f007f
,
ctrl
);
nvkm_mask
(
device
,
0x61c5a4
+
soff
,
0x5f1f007f
,
ctrl
);
return
0
;
}
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
View file @
797b2fb8
...
@@ -43,6 +43,12 @@ struct nvkm_ior_func {
...
@@ -43,6 +43,12 @@ struct nvkm_ior_func {
void
(
*
power
)(
struct
nvkm_ior
*
,
bool
normal
,
bool
pu
,
void
(
*
power
)(
struct
nvkm_ior
*
,
bool
normal
,
bool
pu
,
bool
data
,
bool
vsync
,
bool
hsync
);
bool
data
,
bool
vsync
,
bool
hsync
);
int
(
*
sense
)(
struct
nvkm_ior
*
,
u32
loadval
);
int
(
*
sense
)(
struct
nvkm_ior
*
,
u32
loadval
);
struct
{
void
(
*
ctrl
)(
struct
nvkm_ior
*
,
int
head
,
bool
enable
,
u8
max_ac_packet
,
u8
rekey
,
u8
*
avi
,
u8
avi_size
,
u8
*
vendor
,
u8
vendor_size
);
}
hdmi
;
};
};
int
nvkm_ior_new_
(
const
struct
nvkm_ior_func
*
func
,
struct
nvkm_disp
*
,
int
nvkm_ior_new_
(
const
struct
nvkm_ior_func
*
func
,
struct
nvkm_disp
*
,
...
@@ -65,6 +71,11 @@ void nv50_sor_power(struct nvkm_ior *, bool, bool, bool, bool, bool);
...
@@ -65,6 +71,11 @@ void nv50_sor_power(struct nvkm_ior *, bool, bool, bool, bool, bool);
void
g94_sor_state
(
struct
nvkm_ior
*
,
struct
nvkm_ior_state
*
);
void
g94_sor_state
(
struct
nvkm_ior
*
,
struct
nvkm_ior_state
*
);
void
gf119_sor_state
(
struct
nvkm_ior
*
,
struct
nvkm_ior_state
*
);
void
gf119_sor_state
(
struct
nvkm_ior
*
,
struct
nvkm_ior_state
*
);
void
g84_hdmi_ctrl
(
struct
nvkm_ior
*
,
int
,
bool
,
u8
,
u8
,
u8
*
,
u8
,
u8
*
,
u8
);
void
gt215_hdmi_ctrl
(
struct
nvkm_ior
*
,
int
,
bool
,
u8
,
u8
,
u8
*
,
u8
,
u8
*
,
u8
);
void
gf119_hdmi_ctrl
(
struct
nvkm_ior
*
,
int
,
bool
,
u8
,
u8
,
u8
*
,
u8
,
u8
*
,
u8
);
void
gk104_hdmi_ctrl
(
struct
nvkm_ior
*
,
int
,
bool
,
u8
,
u8
,
u8
*
,
u8
,
u8
*
,
u8
);
#define IOR_MSG(i,l,f,a...) do { \
#define IOR_MSG(i,l,f,a...) do { \
struct nvkm_ior *_ior = (i); \
struct nvkm_ior *_ior = (i); \
nvkm_##l(&_ior->disp->engine.subdev, "%s: "f, _ior->name, ##a); \
nvkm_##l(&_ior->disp->engine.subdev, "%s: "f, _ior->name, ##a); \
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
View file @
797b2fb8
...
@@ -38,9 +38,7 @@ mcp77_disp = {
...
@@ -38,9 +38,7 @@ mcp77_disp = {
.
outp
.
external
.
tmds
=
nv50_pior_output_new
,
.
outp
.
external
.
tmds
=
nv50_pior_output_new
,
.
outp
.
external
.
dp
=
nv50_pior_dp_new
,
.
outp
.
external
.
dp
=
nv50_pior_dp_new
,
.
dac
=
{
.
nr
=
3
,
.
new
=
nv50_dac_new
},
.
dac
=
{
.
nr
=
3
,
.
new
=
nv50_dac_new
},
.
sor
.
nr
=
4
,
.
sor
=
{
.
nr
=
4
,
.
new
=
mcp77_sor_new
},
.
sor
.
new
=
mcp77_sor_new
,
.
sor
.
hdmi
=
g84_hdmi_ctrl
,
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
};
};
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c
View file @
797b2fb8
...
@@ -41,7 +41,6 @@ mcp89_disp = {
...
@@ -41,7 +41,6 @@ mcp89_disp = {
.
sor
.
nr
=
4
,
.
sor
.
nr
=
4
,
.
sor
.
new
=
mcp89_sor_new
,
.
sor
.
new
=
mcp89_sor_new
,
.
sor
.
hda_eld
=
gt215_hda_eld
,
.
sor
.
hda_eld
=
gt215_hda_eld
,
.
sor
.
hdmi
=
gt215_hdmi_ctrl
,
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
.
pior
=
{
.
nr
=
3
,
.
new
=
nv50_pior_new
},
};
};
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
View file @
797b2fb8
...
@@ -34,11 +34,6 @@ void nv50_disp_super_1(struct nv50_disp *);
...
@@ -34,11 +34,6 @@ void nv50_disp_super_1(struct nv50_disp *);
int
gt215_hda_eld
(
NV50_DISP_MTHD_V1
);
int
gt215_hda_eld
(
NV50_DISP_MTHD_V1
);
int
gf119_hda_eld
(
NV50_DISP_MTHD_V1
);
int
gf119_hda_eld
(
NV50_DISP_MTHD_V1
);
int
g84_hdmi_ctrl
(
NV50_DISP_MTHD_V1
);
int
gt215_hdmi_ctrl
(
NV50_DISP_MTHD_V1
);
int
gf119_hdmi_ctrl
(
NV50_DISP_MTHD_V1
);
int
gk104_hdmi_ctrl
(
NV50_DISP_MTHD_V1
);
int
nv50_disp_new_
(
const
struct
nv50_disp_func
*
,
struct
nvkm_device
*
,
int
nv50_disp_new_
(
const
struct
nv50_disp_func
*
,
struct
nvkm_device
*
,
int
index
,
int
heads
,
struct
nvkm_disp
**
);
int
index
,
int
heads
,
struct
nvkm_disp
**
);
int
gf119_disp_new_
(
const
struct
nv50_disp_func
*
,
struct
nvkm_device
*
,
int
gf119_disp_new_
(
const
struct
nv50_disp_func
*
,
struct
nvkm_device
*
,
...
@@ -84,7 +79,6 @@ struct nv50_disp_func {
...
@@ -84,7 +79,6 @@ struct nv50_disp_func {
int
nr
;
int
nr
;
int
(
*
new
)(
struct
nvkm_disp
*
,
int
id
);
int
(
*
new
)(
struct
nvkm_disp
*
,
int
id
);
int
(
*
hda_eld
)(
NV50_DISP_MTHD_V1
);
int
(
*
hda_eld
)(
NV50_DISP_MTHD_V1
);
int
(
*
hdmi
)(
NV50_DISP_MTHD_V1
);
void
(
*
magic
)(
struct
nvkm_output
*
);
void
(
*
magic
)(
struct
nvkm_output
*
);
}
sor
;
}
sor
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
View file @
797b2fb8
...
@@ -116,10 +116,46 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
...
@@ -116,10 +116,46 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
if
(
!
func
->
sor
.
hda_eld
)
if
(
!
func
->
sor
.
hda_eld
)
return
-
ENODEV
;
return
-
ENODEV
;
return
func
->
sor
.
hda_eld
(
object
,
disp
,
data
,
size
,
hidx
,
outp
);
return
func
->
sor
.
hda_eld
(
object
,
disp
,
data
,
size
,
hidx
,
outp
);
case
NV50_DISP_MTHD_V1_SOR_HDMI_PWR
:
case
NV50_DISP_MTHD_V1_SOR_HDMI_PWR
:
{
if
(
!
func
->
sor
.
hdmi
)
union
{
struct
nv50_disp_sor_hdmi_pwr_v0
v0
;
}
*
args
=
data
;
u8
*
vendor
,
vendor_size
;
u8
*
avi
,
avi_size
;
int
ret
=
-
ENOSYS
;
nvif_ioctl
(
object
,
"disp sor hdmi ctrl size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
true
)))
{
nvif_ioctl
(
object
,
"disp sor hdmi ctrl vers %d state %d "
"max_ac_packet %d rekey %d
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
state
,
args
->
v0
.
max_ac_packet
,
args
->
v0
.
rekey
);
if
(
args
->
v0
.
max_ac_packet
>
0x1f
||
args
->
v0
.
rekey
>
0x7f
)
return
-
EINVAL
;
if
((
args
->
v0
.
avi_infoframe_length
+
args
->
v0
.
vendor_infoframe_length
)
>
size
)
return
-
EINVAL
;
else
if
((
args
->
v0
.
avi_infoframe_length
+
args
->
v0
.
vendor_infoframe_length
)
<
size
)
return
-
E2BIG
;
avi
=
data
;
avi_size
=
args
->
v0
.
avi_infoframe_length
;
vendor
=
avi
+
avi_size
;
vendor_size
=
args
->
v0
.
vendor_infoframe_length
;
}
else
return
ret
;
if
(
!
outp
->
ior
->
func
->
hdmi
.
ctrl
)
return
-
ENODEV
;
return
-
ENODEV
;
return
func
->
sor
.
hdmi
(
object
,
disp
,
data
,
size
,
hidx
,
outp
);
outp
->
ior
->
func
->
hdmi
.
ctrl
(
outp
->
ior
,
hidx
,
args
->
v0
.
state
,
args
->
v0
.
max_ac_packet
,
args
->
v0
.
rekey
,
avi
,
avi_size
,
vendor
,
vendor_size
);
return
0
;
}
break
;
case
NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT
:
{
case
NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT
:
{
union
{
union
{
struct
nv50_disp_sor_lvds_script_v0
v0
;
struct
nv50_disp_sor_lvds_script_v0
v0
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg84.c
View file @
797b2fb8
...
@@ -25,6 +25,9 @@ static const struct nvkm_ior_func
...
@@ -25,6 +25,9 @@ static const struct nvkm_ior_func
g84_sor
=
{
g84_sor
=
{
.
state
=
nv50_sor_state
,
.
state
=
nv50_sor_state
,
.
power
=
nv50_sor_power
,
.
power
=
nv50_sor_power
,
.
hdmi
=
{
.
ctrl
=
g84_hdmi_ctrl
,
},
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
View file @
797b2fb8
...
@@ -157,6 +157,9 @@ static const struct nvkm_ior_func
...
@@ -157,6 +157,9 @@ static const struct nvkm_ior_func
gf119_sor
=
{
gf119_sor
=
{
.
state
=
gf119_sor_state
,
.
state
=
gf119_sor_state
,
.
power
=
nv50_sor_power
,
.
power
=
nv50_sor_power
,
.
hdmi
=
{
.
ctrl
=
gf119_hdmi_ctrl
,
},
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c
View file @
797b2fb8
...
@@ -25,6 +25,9 @@ static const struct nvkm_ior_func
...
@@ -25,6 +25,9 @@ static const struct nvkm_ior_func
gk104_sor
=
{
gk104_sor
=
{
.
state
=
gf119_sor_state
,
.
state
=
gf119_sor_state
,
.
power
=
nv50_sor_power
,
.
power
=
nv50_sor_power
,
.
hdmi
=
{
.
ctrl
=
gk104_hdmi_ctrl
,
},
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c
View file @
797b2fb8
...
@@ -57,6 +57,9 @@ static const struct nvkm_ior_func
...
@@ -57,6 +57,9 @@ static const struct nvkm_ior_func
gm107_sor
=
{
gm107_sor
=
{
.
state
=
gf119_sor_state
,
.
state
=
gf119_sor_state
,
.
power
=
nv50_sor_power
,
.
power
=
nv50_sor_power
,
.
hdmi
=
{
.
ctrl
=
gk104_hdmi_ctrl
,
},
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
View file @
797b2fb8
...
@@ -134,6 +134,9 @@ static const struct nvkm_ior_func
...
@@ -134,6 +134,9 @@ static const struct nvkm_ior_func
gm200_sor
=
{
gm200_sor
=
{
.
state
=
gf119_sor_state
,
.
state
=
gf119_sor_state
,
.
power
=
nv50_sor_power
,
.
power
=
nv50_sor_power
,
.
hdmi
=
{
.
ctrl
=
gk104_hdmi_ctrl
,
},
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c
View file @
797b2fb8
...
@@ -25,6 +25,9 @@ static const struct nvkm_ior_func
...
@@ -25,6 +25,9 @@ static const struct nvkm_ior_func
gt215_sor
=
{
gt215_sor
=
{
.
state
=
g94_sor_state
,
.
state
=
g94_sor_state
,
.
power
=
nv50_sor_power
,
.
power
=
nv50_sor_power
,
.
hdmi
=
{
.
ctrl
=
gt215_hdmi_ctrl
,
},
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp77.c
View file @
797b2fb8
...
@@ -25,6 +25,9 @@ static const struct nvkm_ior_func
...
@@ -25,6 +25,9 @@ static const struct nvkm_ior_func
mcp77_sor
=
{
mcp77_sor
=
{
.
state
=
g94_sor_state
,
.
state
=
g94_sor_state
,
.
power
=
nv50_sor_power
,
.
power
=
nv50_sor_power
,
.
hdmi
=
{
.
ctrl
=
g84_hdmi_ctrl
,
},
};
};
int
int
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp89.c
View file @
797b2fb8
...
@@ -25,6 +25,9 @@ static const struct nvkm_ior_func
...
@@ -25,6 +25,9 @@ static const struct nvkm_ior_func
mcp89_sor
=
{
mcp89_sor
=
{
.
state
=
g94_sor_state
,
.
state
=
g94_sor_state
,
.
power
=
nv50_sor_power
,
.
power
=
nv50_sor_power
,
.
hdmi
=
{
.
ctrl
=
gt215_hdmi_ctrl
,
},
};
};
int
int
...
...
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