Commit 837e4a42 authored by Hariprasad Shenai's avatar Hariprasad Shenai Committed by David S. Miller

cxgb4/csiostor: Cleanup TP, MPS and TCAM related register defines

This patch cleanups all TP, MPS and TCAM related macros/register defines
that are defined in t4_regs.h and the affected files
Signed-off-by: default avatarHariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 89c3a86c
......@@ -359,8 +359,8 @@ MODULE_PARM_DESC(select_queue,
*/
enum {
TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
TP_VLAN_PRI_MAP_FIRST = FCOE_S,
TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_S,
};
static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
......@@ -1177,10 +1177,10 @@ freeout: t4_free_sge_resources(adap);
}
t4_write_reg(adap, is_t4(adap->params.chip) ?
MPS_TRC_RSS_CONTROL :
MPS_T5_TRC_RSS_CONTROL,
RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
MPS_TRC_RSS_CONTROL_A :
MPS_T5_TRC_RSS_CONTROL_A,
RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
return 0;
}
......@@ -4094,7 +4094,7 @@ static void uld_attach(struct adapter *adap, unsigned int uld)
lli.nports = adap->params.nports;
lli.wr_cred = adap->params.ofldq_wr_cred;
lli.adapter_type = adap->params.chip;
lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
lli.udb_density = 1 << adap->params.sge.eq_qpp;
lli.ucq_density = 1 << adap->params.sge.iq_qpp;
......@@ -4949,11 +4949,11 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
t4_sge_init(adap);
/* tweak some settings */
t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
v = t4_read_reg(adap, TP_PIO_DATA);
t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
v = t4_read_reg(adap, TP_PIO_DATA_A);
t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
/* first 4 Tx modulation queues point to consecutive Tx channels */
adap->params.tp.tx_modq_map = 0xE4;
......@@ -4962,11 +4962,11 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
/* associate each Tx modulation queue with consecutive Tx channels */
v = 0x84218421;
t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
&v, 1, A_TP_TX_SCHED_HDR);
t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
&v, 1, A_TP_TX_SCHED_FIFO);
t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
&v, 1, A_TP_TX_SCHED_PCMD);
#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
......@@ -5034,8 +5034,8 @@ static int adap_init0_tweaks(struct adapter *adapter)
* Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
* adds the pseudo header itself.
*/
t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
CSUM_HAS_PSEUDO_HDR, 0);
t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
CSUM_HAS_PSEUDO_HDR_F, 0);
return 0;
}
......@@ -5401,34 +5401,34 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
case 0:
/* compressed filter field not enabled */
break;
case FCOE_MASK:
case FCOE_F:
bits += 1;
break;
case PORT_MASK:
case PORT_F:
bits += 3;
break;
case VNIC_ID_MASK:
case VNIC_F:
bits += 17;
break;
case VLAN_MASK:
case VLAN_F:
bits += 17;
break;
case TOS_MASK:
case TOS_F:
bits += 8;
break;
case PROTOCOL_MASK:
case PROTOCOL_F:
bits += 8;
break;
case ETHERTYPE_MASK:
case ETHERTYPE_F:
bits += 16;
break;
case MACMATCH_MASK:
case MACMATCH_F:
bits += 9;
break;
case MPSHITTYPE_MASK:
case MPSHITTYPE_F:
bits += 3;
break;
case FRAGMENTATION_MASK:
case FRAGMENTATION_F:
bits += 1;
break;
}
......@@ -5442,8 +5442,8 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
}
}
v = tp_vlan_pri_map;
t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
&v, 1, TP_VLAN_PRI_MAP);
t4_write_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
&v, 1, TP_VLAN_PRI_MAP_A);
/*
* We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
......@@ -5456,17 +5456,17 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
* performance impact).
*/
if (tp_vlan_pri_map)
t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
FIVETUPLELOOKUP_MASK,
FIVETUPLELOOKUP_MASK);
t4_set_reg_field(adapter, TP_GLOBAL_CONFIG_A,
FIVETUPLELOOKUP_V(FIVETUPLELOOKUP_M),
FIVETUPLELOOKUP_V(FIVETUPLELOOKUP_M));
/*
* Tweak some settings.
*/
t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
t4_write_reg(adapter, TP_SHIFT_CNT_A, SYNSHIFTMAX_V(6) |
RXTSHIFTMAXR1_V(4) | RXTSHIFTMAXR2_V(15) |
PERSHIFTBACKOFFMAX_V(8) | PERSHIFTMAX_V(8) |
KEEPALIVEMAXR1_V(4) | KEEPALIVEMAXR2_V(9));
/*
* Get basic stuff going by issuing the Firmware Initialize command.
......
This diff is collapsed.
......@@ -188,9 +188,9 @@ void
csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsigned int addr,
unsigned int mask, unsigned int val)
{
csio_wr_reg32(hw, addr, TP_PIO_ADDR);
val |= csio_rd_reg32(hw, TP_PIO_DATA) & ~mask;
csio_wr_reg32(hw, val, TP_PIO_DATA);
csio_wr_reg32(hw, addr, TP_PIO_ADDR_A);
val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask;
csio_wr_reg32(hw, val, TP_PIO_DATA_A);
}
void
......@@ -2683,11 +2683,11 @@ static void csio_tp_intr_handler(struct csio_hw *hw)
{
static struct intr_info tp_intr_info[] = {
{ 0x3fffffff, "TP parity error", -1, 1 },
{ FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
{ FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, TP_INT_CAUSE, tp_intr_info))
if (csio_handle_intr_status(hw, TP_INT_CAUSE_A, tp_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2824,19 +2824,19 @@ static void csio_ulprx_intr_handler(struct csio_hw *hw)
static void csio_ulptx_intr_handler(struct csio_hw *hw)
{
static struct intr_info ulptx_intr_info[] = {
{ PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
0 },
{ PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
0 },
{ PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
0 },
{ PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
0 },
{ 0xfffffff, "ULPTX parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE, ulptx_intr_info))
if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2846,20 +2846,20 @@ static void csio_ulptx_intr_handler(struct csio_hw *hw)
static void csio_pmtx_intr_handler(struct csio_hw *hw)
{
static struct intr_info pmtx_intr_info[] = {
{ PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
{ ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
{ PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
{ ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
{ 0xffffff0, "PMTX framing error", -1, 1 },
{ OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1,
{ OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", -1,
1 },
{ ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
{ C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
{ ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
{ PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE, pmtx_intr_info))
if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE_A, pmtx_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2869,17 +2869,17 @@ static void csio_pmtx_intr_handler(struct csio_hw *hw)
static void csio_pmrx_intr_handler(struct csio_hw *hw)
{
static struct intr_info pmrx_intr_info[] = {
{ ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
{ ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
{ 0x3ffff0, "PMRX framing error", -1, 1 },
{ OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1,
{ OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", -1,
1 },
{ IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
{ E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
{ IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
{ PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE, pmrx_intr_info))
if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE_A, pmrx_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2930,19 +2930,22 @@ static void csio_mps_intr_handler(struct csio_hw *hw)
{ 0, NULL, 0, 0 }
};
static struct intr_info mps_tx_intr_info[] = {
{ TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
{ NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
{ TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
{ TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 },
{ BUBBLE, "MPS Tx underflow", -1, 1 },
{ SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
{ FRMERR, "MPS Tx framing error", -1, 1 },
{ TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
{ NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
{ TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
-1, 1 },
{ TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
-1, 1 },
{ BUBBLE_F, "MPS Tx underflow", -1, 1 },
{ SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
{ FRMERR_F, "MPS Tx framing error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info mps_trc_intr_info[] = {
{ FILTMEM, "MPS TRC filter parity error", -1, 1 },
{ PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
{ MISCPERR, "MPS TRC misc parity error", -1, 1 },
{ FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
{ PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
-1, 1 },
{ MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info mps_stat_sram_intr_info[] = {
......@@ -2958,31 +2961,31 @@ static void csio_mps_intr_handler(struct csio_hw *hw)
{ 0, NULL, 0, 0 }
};
static struct intr_info mps_cls_intr_info[] = {
{ MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
{ MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
{ HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
{ MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
{ MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
{ HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
int fat;
fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE,
fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE_A,
mps_rx_intr_info) +
csio_handle_intr_status(hw, MPS_TX_INT_CAUSE,
csio_handle_intr_status(hw, MPS_TX_INT_CAUSE_A,
mps_tx_intr_info) +
csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE,
csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE_A,
mps_trc_intr_info) +
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM,
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
mps_stat_sram_intr_info) +
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
mps_stat_tx_intr_info) +
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
mps_stat_rx_intr_info) +
csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE,
csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE_A,
mps_cls_intr_info);
csio_wr_reg32(hw, 0, MPS_INT_CAUSE);
csio_rd_reg32(hw, MPS_INT_CAUSE); /* flush */
csio_wr_reg32(hw, 0, MPS_INT_CAUSE_A);
csio_rd_reg32(hw, MPS_INT_CAUSE_A); /* flush */
if (fat)
csio_hw_fatal_err(hw);
}
......
......@@ -1350,8 +1350,8 @@ csio_wr_fixup_host_params(struct csio_hw *hw)
PKTSHIFT_V(PKTSHIFT_M),
PKTSHIFT_V(CSIO_SGE_RX_DMA_OFFSET));
csio_hw_tp_wr_bits_indirect(hw, TP_INGRESS_CONFIG,
CSUM_HAS_PSEUDO_HDR, 0);
csio_hw_tp_wr_bits_indirect(hw, TP_INGRESS_CONFIG_A,
CSUM_HAS_PSEUDO_HDR_F, 0);
}
static void
......
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