Commit 849dcce3 authored by David S. Miller's avatar David S. Miller

Merge branch 'amd-xgbe-updates'

Tom Lendacky says:

====================
amd-xgbe: AMD XGBE driver updates 2016-11-10

This patch series is targeted at adding support for a new PCI version
of the hardware. As part of the new PCI device, there is a new PCS/PHY
interaction, ECC support, I2C sideband communication, SFP+ support and
more.

The following updates and fixes are included in this driver update series:

- Hardware workaround for possible incorrectly generated interrupts
  during software reset
- Hardware workaround for Tx timestamp register access order
- Add support for a PCI version of the device
- Increase the Rx queue limit to take advantage of the increased number
  of DMA channels that might be available
- Add support for a new DMA channel interrupt mode
- Add ECC support for the device memory
- Add support for using the integrated I2C controller for sideband
  communication
- Expose the phylib phy_aneg_done() function so it can be called by the
  driver
- Add support for SFP+ modules
- Add support for MDIO attached PHYs
- Add support for KR re-driver between the PCS/SerDes and an external
  PHY

This patch series is based on net-next.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f0a40400 d7445d1f
......@@ -1290,15 +1290,6 @@ static int greth_mdio_probe(struct net_device *dev)
return 0;
}
static inline int phy_aneg_done(struct phy_device *phydev)
{
int retval;
retval = phy_read(phydev, MII_BMSR);
return (retval < 0) ? retval : (retval & BMSR_ANEGCOMPLETE);
}
static int greth_mdio_init(struct greth_private *greth)
{
int ret;
......
......@@ -173,11 +173,13 @@ config SUNLANCE
config AMD_XGBE
tristate "AMD 10GbE Ethernet driver"
depends on ((OF_NET && OF_ADDRESS) || ACPI) && HAS_IOMEM && HAS_DMA
depends on ARM64 || COMPILE_TEST
depends on ((OF_NET && OF_ADDRESS) || ACPI || PCI) && HAS_IOMEM && HAS_DMA
depends on X86 || ARM64 || COMPILE_TEST
select BITREVERSE
select CRC32
select PTP_1588_CLOCK
select PHYLIB
select AMD_XGBE_HAVE_ECC if X86
---help---
This driver supports the AMD 10GbE Ethernet device found on an
AMD SoC.
......@@ -195,4 +197,8 @@ config AMD_XGBE_DCB
If unsure, say N.
config AMD_XGBE_HAVE_ECC
bool
default n
endif # NET_VENDOR_AMD
......@@ -3,8 +3,9 @@ obj-$(CONFIG_AMD_XGBE) += amd-xgbe.o
amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \
xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \
xgbe-ptp.o \
xgbe-phy-v1.o \
xgbe-i2c.o xgbe-phy-v1.o xgbe-phy-v2.o \
xgbe-platform.o
amd-xgbe-$(CONFIG_PCI) += xgbe-pci.o
amd-xgbe-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o
amd-xgbe-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o
This diff is collapsed.
......@@ -316,6 +316,126 @@ static const struct file_operations xpcs_reg_value_fops = {
.write = xpcs_reg_value_write,
};
static ssize_t xprop_reg_addr_read(struct file *filp, char __user *buffer,
size_t count, loff_t *ppos)
{
struct xgbe_prv_data *pdata = filp->private_data;
return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xprop_reg);
}
static ssize_t xprop_reg_addr_write(struct file *filp,
const char __user *buffer,
size_t count, loff_t *ppos)
{
struct xgbe_prv_data *pdata = filp->private_data;
return xgbe_common_write(buffer, count, ppos,
&pdata->debugfs_xprop_reg);
}
static ssize_t xprop_reg_value_read(struct file *filp, char __user *buffer,
size_t count, loff_t *ppos)
{
struct xgbe_prv_data *pdata = filp->private_data;
unsigned int value;
value = XP_IOREAD(pdata, pdata->debugfs_xprop_reg);
return xgbe_common_read(buffer, count, ppos, value);
}
static ssize_t xprop_reg_value_write(struct file *filp,
const char __user *buffer,
size_t count, loff_t *ppos)
{
struct xgbe_prv_data *pdata = filp->private_data;
unsigned int value;
ssize_t len;
len = xgbe_common_write(buffer, count, ppos, &value);
if (len < 0)
return len;
XP_IOWRITE(pdata, pdata->debugfs_xprop_reg, value);
return len;
}
static const struct file_operations xprop_reg_addr_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.read = xprop_reg_addr_read,
.write = xprop_reg_addr_write,
};
static const struct file_operations xprop_reg_value_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.read = xprop_reg_value_read,
.write = xprop_reg_value_write,
};
static ssize_t xi2c_reg_addr_read(struct file *filp, char __user *buffer,
size_t count, loff_t *ppos)
{
struct xgbe_prv_data *pdata = filp->private_data;
return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xi2c_reg);
}
static ssize_t xi2c_reg_addr_write(struct file *filp,
const char __user *buffer,
size_t count, loff_t *ppos)
{
struct xgbe_prv_data *pdata = filp->private_data;
return xgbe_common_write(buffer, count, ppos,
&pdata->debugfs_xi2c_reg);
}
static ssize_t xi2c_reg_value_read(struct file *filp, char __user *buffer,
size_t count, loff_t *ppos)
{
struct xgbe_prv_data *pdata = filp->private_data;
unsigned int value;
value = XI2C_IOREAD(pdata, pdata->debugfs_xi2c_reg);
return xgbe_common_read(buffer, count, ppos, value);
}
static ssize_t xi2c_reg_value_write(struct file *filp,
const char __user *buffer,
size_t count, loff_t *ppos)
{
struct xgbe_prv_data *pdata = filp->private_data;
unsigned int value;
ssize_t len;
len = xgbe_common_write(buffer, count, ppos, &value);
if (len < 0)
return len;
XI2C_IOWRITE(pdata, pdata->debugfs_xi2c_reg, value);
return len;
}
static const struct file_operations xi2c_reg_addr_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.read = xi2c_reg_addr_read,
.write = xi2c_reg_addr_write,
};
static const struct file_operations xi2c_reg_value_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.read = xi2c_reg_value_read,
.write = xi2c_reg_value_write,
};
void xgbe_debugfs_init(struct xgbe_prv_data *pdata)
{
struct dentry *pfile;
......@@ -367,6 +487,38 @@ void xgbe_debugfs_init(struct xgbe_prv_data *pdata)
if (!pfile)
netdev_err(pdata->netdev, "debugfs_create_file failed\n");
if (pdata->xprop_regs) {
pfile = debugfs_create_file("xprop_register", 0600,
pdata->xgbe_debugfs, pdata,
&xprop_reg_addr_fops);
if (!pfile)
netdev_err(pdata->netdev,
"debugfs_create_file failed\n");
pfile = debugfs_create_file("xprop_register_value", 0600,
pdata->xgbe_debugfs, pdata,
&xprop_reg_value_fops);
if (!pfile)
netdev_err(pdata->netdev,
"debugfs_create_file failed\n");
}
if (pdata->xi2c_regs) {
pfile = debugfs_create_file("xi2c_register", 0600,
pdata->xgbe_debugfs, pdata,
&xi2c_reg_addr_fops);
if (!pfile)
netdev_err(pdata->netdev,
"debugfs_create_file failed\n");
pfile = debugfs_create_file("xi2c_register_value", 0600,
pdata->xgbe_debugfs, pdata,
&xi2c_reg_value_fops);
if (!pfile)
netdev_err(pdata->netdev,
"debugfs_create_file failed\n");
}
kfree(buf);
}
......
......@@ -646,6 +646,11 @@ static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
unsigned int dma_ch_isr, dma_ch_ier;
unsigned int i;
/* Set the interrupt mode if supported */
if (pdata->channel_irq_mode)
XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM,
pdata->channel_irq_mode);
channel = pdata->channel;
for (i = 0; i < pdata->channel_count; i++, channel++) {
/* Clear all the interrupts which are set */
......@@ -667,19 +672,21 @@ static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
if (channel->tx_ring) {
/* Enable the following Tx interrupts
* TIE - Transmit Interrupt Enable (unless using
* per channel interrupts)
* per channel interrupts in edge triggered
* mode)
*/
if (!pdata->per_channel_irq)
if (!pdata->per_channel_irq || pdata->channel_irq_mode)
XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
}
if (channel->rx_ring) {
/* Enable following Rx interrupts
* RBUE - Receive Buffer Unavailable Enable
* RIE - Receive Interrupt Enable (unless using
* per channel interrupts)
* per channel interrupts in edge triggered
* mode)
*/
XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
if (!pdata->per_channel_irq)
if (!pdata->per_channel_irq || pdata->channel_irq_mode)
XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
}
......@@ -715,6 +722,68 @@ static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
/* Enable all counter interrupts */
XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
/* Enable MDIO single command completion interrupt */
XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1);
}
static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata)
{
unsigned int ecc_isr, ecc_ier = 0;
if (!pdata->vdata->ecc_support)
return;
/* Clear all the interrupts which are set */
ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
/* Enable ECC interrupts */
XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 1);
XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 1);
XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 1);
XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 1);
XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 1);
XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 1);
XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
}
static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata)
{
unsigned int ecc_ier;
ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
/* Disable ECC DED interrupts */
XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 0);
XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 0);
XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 0);
XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
}
static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata,
enum xgbe_ecc_sec sec)
{
unsigned int ecc_ier;
ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
/* Disable ECC SEC interrupt */
switch (sec) {
case XGBE_ECC_SEC_TX:
XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 0);
break;
case XGBE_ECC_SEC_RX:
XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 0);
break;
case XGBE_ECC_SEC_DESC:
XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 0);
break;
}
XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
}
static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed)
......@@ -1026,6 +1095,36 @@ static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
return 0;
}
static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
{
unsigned int reg;
if (gpio > 16)
return -EINVAL;
reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
reg &= ~(1 << (gpio + 16));
XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
return 0;
}
static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
{
unsigned int reg;
if (gpio > 16)
return -EINVAL;
reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
reg |= (1 << (gpio + 16));
XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
return 0;
}
static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
int mmd_reg)
{
......@@ -1170,6 +1269,79 @@ static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
}
}
static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr,
int reg, u16 val)
{
unsigned int mdio_sca, mdio_sccd;
reinit_completion(&pdata->mdio_complete);
mdio_sca = 0;
XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg);
XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr);
XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
mdio_sccd = 0;
XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val);
XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1);
XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) {
netdev_err(pdata->netdev, "mdio write operation timed out\n");
return -ETIMEDOUT;
}
return 0;
}
static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr,
int reg)
{
unsigned int mdio_sca, mdio_sccd;
reinit_completion(&pdata->mdio_complete);
mdio_sca = 0;
XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg);
XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr);
XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
mdio_sccd = 0;
XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3);
XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) {
netdev_err(pdata->netdev, "mdio read operation timed out\n");
return -ETIMEDOUT;
}
return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA);
}
static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port,
enum xgbe_mdio_mode mode)
{
unsigned int reg_val = 0;
switch (mode) {
case XGBE_MDIO_MODE_CL22:
if (port > XGMAC_MAX_C22_PORT)
return -EINVAL;
reg_val |= (1 << port);
break;
case XGBE_MDIO_MODE_CL45:
break;
default:
return -EINVAL;
}
XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val);
return 0;
}
static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
{
return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
......@@ -1360,14 +1532,21 @@ static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
{
unsigned int tx_snr;
unsigned int tx_snr, tx_ssr;
u64 nsec;
if (pdata->vdata->tx_tstamp_workaround) {
tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
} else {
tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
}
if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
return 0;
nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
nsec = tx_ssr;
nsec *= NSEC_PER_SEC;
nsec += tx_snr;
......@@ -1897,7 +2076,7 @@ static int xgbe_disable_int(struct xgbe_channel *channel,
return 0;
}
static int xgbe_exit(struct xgbe_prv_data *pdata)
static int __xgbe_exit(struct xgbe_prv_data *pdata)
{
unsigned int count = 2000;
......@@ -1919,6 +2098,20 @@ static int xgbe_exit(struct xgbe_prv_data *pdata)
return 0;
}
static int xgbe_exit(struct xgbe_prv_data *pdata)
{
int ret;
/* To guard against possible incorrectly generated interrupts,
* issue the software reset twice.
*/
ret = __xgbe_exit(pdata);
if (ret)
return ret;
return __xgbe_exit(pdata);
}
static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
{
unsigned int i, count;
......@@ -3266,6 +3459,11 @@ static int xgbe_init(struct xgbe_prv_data *pdata)
xgbe_config_mmc(pdata);
xgbe_enable_mac_interrupts(pdata);
/*
* Initialize ECC related features
*/
xgbe_enable_ecc_interrupts(pdata);
DBGPR("<--xgbe_init\n");
return 0;
......@@ -3294,6 +3492,13 @@ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
hw_if->set_speed = xgbe_set_speed;
hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode;
hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs;
hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs;
hw_if->set_gpio = xgbe_set_gpio;
hw_if->clr_gpio = xgbe_clr_gpio;
hw_if->enable_tx = xgbe_enable_tx;
hw_if->disable_tx = xgbe_disable_tx;
hw_if->enable_rx = xgbe_enable_rx;
......@@ -3371,5 +3576,9 @@ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
/* For ECC */
hw_if->disable_ecc_ded = xgbe_disable_ecc_ded;
hw_if->disable_ecc_sec = xgbe_disable_ecc_sec;
DBGPR("<--xgbe_init_function_ptrs\n");
}
This diff is collapsed.
This diff is collapsed.
......@@ -161,6 +161,7 @@ static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
{
xgbe_init_function_ptrs_dev(&pdata->hw_if);
xgbe_init_function_ptrs_phy(&pdata->phy_if);
xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
xgbe_init_function_ptrs_desc(&pdata->desc_if);
pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
......@@ -186,10 +187,14 @@ struct xgbe_prv_data *xgbe_alloc_pdata(struct device *dev)
spin_lock_init(&pdata->xpcs_lock);
mutex_init(&pdata->rss_mutex);
spin_lock_init(&pdata->tstamp_lock);
mutex_init(&pdata->i2c_mutex);
init_completion(&pdata->i2c_complete);
init_completion(&pdata->mdio_complete);
pdata->msg_enable = netif_msg_init(debug, default_msg_level);
set_bit(XGBE_DOWN, &pdata->dev_state);
set_bit(XGBE_STOPPED, &pdata->dev_state);
return pdata;
}
......@@ -236,8 +241,7 @@ void xgbe_set_counts(struct xgbe_prv_data *pdata)
pdata->tx_q_count = pdata->tx_ring_count;
pdata->rx_ring_count = min_t(unsigned int,
netif_get_num_default_rss_queues(),
pdata->rx_ring_count = min_t(unsigned int, num_online_cpus(),
pdata->hw_feat.rx_ch_cnt);
pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
pdata->rx_max_channel_count);
......@@ -264,6 +268,14 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
netdev->base_addr = (unsigned long)pdata->xgmac_regs;
memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
/* Initialize ECC timestamps */
pdata->tx_sec_period = jiffies;
pdata->tx_ded_period = jiffies;
pdata->rx_sec_period = jiffies;
pdata->rx_ded_period = jiffies;
pdata->desc_sec_period = jiffies;
pdata->desc_ded_period = jiffies;
/* Issue software reset to device */
pdata->hw_if.exit(pdata);
......@@ -291,6 +303,19 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT);
pdata->rx_desc_count = XGBE_RX_DESC_CNT;
/* Adjust the number of queues based on interrupts assigned */
if (pdata->channel_irq_count) {
pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
pdata->channel_irq_count);
pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
pdata->channel_irq_count);
if (netif_msg_probe(pdata))
dev_dbg(pdata->dev,
"adjusted TX/RX DMA channel count = %u/%u\n",
pdata->tx_ring_count, pdata->rx_ring_count);
}
/* Set the number of queues */
ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
if (ret) {
......@@ -372,6 +397,14 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
netdev_name(netdev));
/* Create the ECC name based on netdev name */
snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
netdev_name(netdev));
/* Create the I2C name based on netdev name */
snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
netdev_name(netdev));
/* Create workqueues */
pdata->dev_workqueue =
create_singlethread_workqueue(netdev_name(netdev));
......@@ -393,6 +426,11 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
xgbe_debugfs_init(pdata);
netif_dbg(pdata, drv, pdata->netdev, "%u Tx software queues\n",
pdata->tx_ring_count);
netif_dbg(pdata, drv, pdata->netdev, "%u Rx software queues\n",
pdata->rx_ring_count);
return 0;
err_wq:
......@@ -431,11 +469,17 @@ static int __init xgbe_mod_init(void)
if (ret)
return ret;
ret = xgbe_pci_init();
if (ret)
return ret;
return 0;
}
static void __exit xgbe_mod_exit(void)
{
xgbe_pci_exit();
xgbe_platform_exit();
}
......
This diff is collapsed.
This diff is collapsed.
......@@ -295,6 +295,17 @@ static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
return mode;
}
static unsigned int xgbe_phy_an_advertising(struct xgbe_prv_data *pdata)
{
return pdata->phy.advertising;
}
static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
{
/* Nothing uniquely required for an configuration */
return 0;
}
static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
{
return XGBE_AN_MODE_CL73;
......@@ -607,10 +618,12 @@ static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
}
}
static int xgbe_phy_link_status(struct xgbe_prv_data *pdata)
static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
{
unsigned int reg;
*an_restart = 0;
/* Link status is latched low, so read once to clear
* and then read again to get current state
*/
......@@ -821,6 +834,10 @@ void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *phy_if)
phy_impl->an_mode = xgbe_phy_an_mode;
phy_impl->an_config = xgbe_phy_an_config;
phy_impl->an_advertising = xgbe_phy_an_advertising;
phy_impl->an_outcome = xgbe_phy_an_outcome;
phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
......
This diff is collapsed.
......@@ -426,8 +426,10 @@ static int xgbe_platform_probe(struct platform_device *pdev)
pdata->phy_mode = PHY_INTERFACE_MODE_XGMII;
/* Check for per channel interrupt support */
if (device_property_present(dev, XGBE_DMA_IRQS_PROPERTY))
if (device_property_present(dev, XGBE_DMA_IRQS_PROPERTY)) {
pdata->per_channel_irq = 1;
pdata->channel_irq_mode = XGBE_IRQ_MODE_EDGE;
}
/* Obtain device settings unique to ACPI/OF */
if (pdata->use_acpi)
......@@ -462,6 +464,9 @@ static int xgbe_platform_probe(struct platform_device *pdev)
/* Set the hardware channel and queue counts */
xgbe_set_counts(pdata);
/* Always have XGMAC and XPCS (auto-negotiation) interrupts */
pdata->irq_count = 2;
/* Get the device interrupt */
ret = platform_get_irq(pdev, 0);
if (ret < 0) {
......@@ -485,6 +490,10 @@ static int xgbe_platform_probe(struct platform_device *pdev)
pdata->channel_irq[i] = ret;
}
pdata->channel_irq_count = max;
pdata->irq_count += max;
}
/* Get the auto-negotiation interrupt */
......@@ -581,6 +590,7 @@ static const struct xgbe_version_data xgbe_v1 = {
.xpcs_access = XGBE_XPCS_ACCESS_V1,
.tx_max_fifo_size = 81920,
.rx_max_fifo_size = 81920,
.tx_tstamp_workaround = 1,
};
#ifdef CONFIG_ACPI
......@@ -608,7 +618,7 @@ static SIMPLE_DEV_PM_OPS(xgbe_platform_pm_ops,
static struct platform_driver xgbe_driver = {
.driver = {
.name = "amd-xgbe",
.name = XGBE_DRV_NAME,
#ifdef CONFIG_ACPI
.acpi_match_table = xgbe_acpi_match,
#endif
......
......@@ -127,6 +127,7 @@
#include <linux/timecounter.h>
#include <linux/net_tstamp.h>
#include <net/dcbnl.h>
#include <linux/completion.h>
#define XGBE_DRV_NAME "amd-xgbe"
#define XGBE_DRV_VERSION "1.0.3"
......@@ -171,6 +172,10 @@
#define XGBE_DMA_SYS_ARCACHE 0x0
#define XGBE_DMA_SYS_AWCACHE 0x0
/* DMA channel interrupt modes */
#define XGBE_IRQ_MODE_EDGE 0
#define XGBE_IRQ_MODE_LEVEL 1
#define XGBE_DMA_INTERRUPT_MASK 0x31c7
#define XGMAC_MIN_PACKET 60
......@@ -200,6 +205,20 @@
#define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
#define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
/* PCI BAR mapping */
#define XGBE_XGMAC_BAR 0
#define XGBE_XPCS_BAR 1
#define XGBE_MAC_PROP_OFFSET 0x1d000
#define XGBE_I2C_CTRL_OFFSET 0x1e000
/* PCI MSIx support */
#define XGBE_MSIX_BASE_COUNT 4
#define XGBE_MSIX_MIN_COUNT (XGBE_MSIX_BASE_COUNT + 1)
/* PCI clock frequencies */
#define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */
#define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */
/* Timestamp support - values based on 50MHz PTP clock
* 50MHz => 20 nsec
*/
......@@ -267,6 +286,12 @@
#define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
#define XGBE_SGMII_AN_LINK_DUPLEX BIT(4)
/* ECC correctable error notification window (seconds) */
#define XGBE_ECC_LIMIT 60
/* MDIO port types */
#define XGMAC_MAX_C22_PORT 3
struct xgbe_prv_data;
struct xgbe_packet_data {
......@@ -443,6 +468,7 @@ enum xgbe_state {
XGBE_DOWN,
XGBE_LINK_INIT,
XGBE_LINK_ERR,
XGBE_STOPPED,
};
enum xgbe_int {
......@@ -462,6 +488,12 @@ enum xgbe_int_state {
XGMAC_INT_STATE_RESTORE,
};
enum xgbe_ecc_sec {
XGBE_ECC_SEC_TX,
XGBE_ECC_SEC_RX,
XGBE_ECC_SEC_DESC,
};
enum xgbe_speed {
XGBE_SPEED_1000 = 0,
XGBE_SPEED_2500,
......@@ -476,6 +508,7 @@ enum xgbe_xpcs_access {
enum xgbe_an_mode {
XGBE_AN_MODE_CL73 = 0,
XGBE_AN_MODE_CL73_REDRV,
XGBE_AN_MODE_CL37,
XGBE_AN_MODE_CL37_SGMII,
XGBE_AN_MODE_NONE,
......@@ -501,6 +534,10 @@ enum xgbe_mode {
XGBE_MODE_KX_1000 = 0,
XGBE_MODE_KX_2500,
XGBE_MODE_KR,
XGBE_MODE_X,
XGBE_MODE_SGMII_100,
XGBE_MODE_SGMII_1000,
XGBE_MODE_SFI,
XGBE_MODE_UNKNOWN,
};
......@@ -509,6 +546,12 @@ enum xgbe_speedset {
XGBE_SPEEDSET_2500_10000,
};
enum xgbe_mdio_mode {
XGBE_MDIO_MODE_NONE = 0,
XGBE_MDIO_MODE_CL22,
XGBE_MDIO_MODE_CL45,
};
struct xgbe_phy {
u32 supported;
u32 advertising;
......@@ -527,6 +570,43 @@ struct xgbe_phy {
int rx_pause;
};
enum xgbe_i2c_cmd {
XGBE_I2C_CMD_READ = 0,
XGBE_I2C_CMD_WRITE,
};
struct xgbe_i2c_op {
enum xgbe_i2c_cmd cmd;
unsigned int target;
void *buf;
unsigned int len;
};
struct xgbe_i2c_op_state {
struct xgbe_i2c_op *op;
unsigned int tx_len;
unsigned char *tx_buf;
unsigned int rx_len;
unsigned char *rx_buf;
unsigned int tx_abort_source;
int ret;
};
struct xgbe_i2c {
unsigned int started;
unsigned int max_speed_mode;
unsigned int rx_fifo_size;
unsigned int tx_fifo_size;
struct xgbe_i2c_op_state op_state;
};
struct xgbe_mmc_stats {
/* Tx Stats */
u64 txoctetcount_gb;
......@@ -599,6 +679,14 @@ struct xgbe_hw_if {
void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
int (*set_speed)(struct xgbe_prv_data *, int);
int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int,
enum xgbe_mdio_mode);
int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int);
int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, u16);
int (*set_gpio)(struct xgbe_prv_data *, unsigned int);
int (*clr_gpio)(struct xgbe_prv_data *, unsigned int);
void (*enable_tx)(struct xgbe_prv_data *);
void (*disable_tx)(struct xgbe_prv_data *);
void (*enable_rx)(struct xgbe_prv_data *);
......@@ -676,6 +764,10 @@ struct xgbe_hw_if {
int (*disable_rss)(struct xgbe_prv_data *);
int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
/* For ECC */
void (*disable_ecc_ded)(struct xgbe_prv_data *);
void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec);
};
/* This structure represents implementation specific routines for an
......@@ -694,7 +786,7 @@ struct xgbe_phy_impl_if {
void (*stop)(struct xgbe_prv_data *);
/* Return the link status */
int (*link_status)(struct xgbe_prv_data *);
int (*link_status)(struct xgbe_prv_data *, int *);
/* Indicate if a particular speed is valid */
bool (*valid_speed)(struct xgbe_prv_data *, int);
......@@ -713,6 +805,12 @@ struct xgbe_phy_impl_if {
/* Retrieve current auto-negotiation mode */
enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
/* Configure auto-negotiation settings */
int (*an_config)(struct xgbe_prv_data *);
/* Set/override auto-negotiation advertisement settings */
unsigned int (*an_advertising)(struct xgbe_prv_data *);
/* Process results of auto-negotiation */
enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
......@@ -738,10 +836,28 @@ struct xgbe_phy_if {
/* For PHY settings validation */
bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
/* For single interrupt support */
irqreturn_t (*an_isr)(int, struct xgbe_prv_data *);
/* PHY implementation specific services */
struct xgbe_phy_impl_if phy_impl;
};
struct xgbe_i2c_if {
/* For initial I2C setup */
int (*i2c_init)(struct xgbe_prv_data *);
/* For I2C support when setting device up/down */
int (*i2c_start)(struct xgbe_prv_data *);
void (*i2c_stop)(struct xgbe_prv_data *);
/* For performing I2C operations */
int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);
/* For single interrupt support */
irqreturn_t (*i2c_isr)(int, struct xgbe_prv_data *);
};
struct xgbe_desc_if {
int (*alloc_ring_resources)(struct xgbe_prv_data *);
void (*free_ring_resources)(struct xgbe_prv_data *);
......@@ -805,10 +921,14 @@ struct xgbe_version_data {
unsigned int mmc_64bit;
unsigned int tx_max_fifo_size;
unsigned int rx_max_fifo_size;
unsigned int tx_tstamp_workaround;
unsigned int ecc_support;
unsigned int i2c_support;
};
struct xgbe_prv_data {
struct net_device *netdev;
struct pci_dev *pcidev;
struct platform_device *platdev;
struct acpi_device *adev;
struct device *dev;
......@@ -827,6 +947,8 @@ struct xgbe_prv_data {
void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
void __iomem *xprop_regs; /* XGBE property registers */
void __iomem *xi2c_regs; /* XGBE I2C CSRs */
/* Overall device lock */
spinlock_t lock;
......@@ -843,13 +965,39 @@ struct xgbe_prv_data {
/* Flags representing xgbe_state */
unsigned long dev_state;
/* ECC support */
unsigned long tx_sec_period;
unsigned long tx_ded_period;
unsigned long rx_sec_period;
unsigned long rx_ded_period;
unsigned long desc_sec_period;
unsigned long desc_ded_period;
unsigned int tx_sec_count;
unsigned int tx_ded_count;
unsigned int rx_sec_count;
unsigned int rx_ded_count;
unsigned int desc_ded_count;
unsigned int desc_sec_count;
struct msix_entry *msix_entries;
int dev_irq;
unsigned int per_channel_irq;
int ecc_irq;
int i2c_irq;
int channel_irq[XGBE_MAX_DMA_CHANNELS];
unsigned int per_channel_irq;
unsigned int irq_shared;
unsigned int irq_count;
unsigned int channel_irq_count;
unsigned int channel_irq_mode;
char ecc_name[IFNAMSIZ + 32];
struct xgbe_hw_if hw_if;
struct xgbe_phy_if phy_if;
struct xgbe_desc_if desc_if;
struct xgbe_i2c_if i2c_if;
/* AXI DMA settings */
unsigned int coherent;
......@@ -957,8 +1105,9 @@ struct xgbe_prv_data {
/* Hardware features of the device */
struct xgbe_hw_features hw_feat;
/* Device restart work structure */
/* Device work structures */
struct work_struct restart_work;
struct work_struct stopdev_work;
/* Keeps track of power mode */
unsigned int power_down;
......@@ -977,6 +1126,9 @@ struct xgbe_prv_data {
struct xgbe_phy phy;
int mdio_mmd;
unsigned long link_check;
struct completion mdio_complete;
unsigned int kr_redrv;
char an_name[IFNAMSIZ + 32];
struct workqueue_struct *an_workqueue;
......@@ -999,6 +1151,12 @@ struct xgbe_prv_data {
unsigned long an_start;
enum xgbe_an_mode an_mode;
/* I2C support */
struct xgbe_i2c i2c;
struct mutex i2c_mutex;
struct completion i2c_complete;
char i2c_name[IFNAMSIZ + 32];
unsigned int lpm_ctrl; /* CTRL1 for resume */
#ifdef CONFIG_DEBUG_FS
......@@ -1008,6 +1166,10 @@ struct xgbe_prv_data {
unsigned int debugfs_xpcs_mmd;
unsigned int debugfs_xpcs_reg;
unsigned int debugfs_xprop_reg;
unsigned int debugfs_xi2c_reg;
#endif
};
......@@ -1020,11 +1182,20 @@ void xgbe_deconfig_netdev(struct xgbe_prv_data *);
int xgbe_platform_init(void);
void xgbe_platform_exit(void);
#ifdef CONFIG_PCI
int xgbe_pci_init(void);
void xgbe_pci_exit(void);
#else
static inline int xgbe_pci_init(void) { return 0; }
static inline void xgbe_pci_exit(void) { }
#endif
void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *);
const struct net_device_ops *xgbe_get_netdev_ops(void);
const struct ethtool_ops *xgbe_get_ethtool_ops(void);
......
......@@ -143,13 +143,14 @@ static int phy_config_interrupt(struct phy_device *phydev, u32 interrupts)
* Returns > 0 on success or < 0 on error. 0 means that auto-negotiation
* is still pending.
*/
static inline int phy_aneg_done(struct phy_device *phydev)
int phy_aneg_done(struct phy_device *phydev)
{
if (phydev->drv->aneg_done)
return phydev->drv->aneg_done(phydev);
return genphy_aneg_done(phydev);
}
EXPORT_SYMBOL(phy_aneg_done);
/* A structure for mapping a particular speed and duplex
* combination to a particular SUPPORTED and ADVERTISED value
......
......@@ -786,6 +786,7 @@ void phy_detach(struct phy_device *phydev);
void phy_start(struct phy_device *phydev);
void phy_stop(struct phy_device *phydev);
int phy_start_aneg(struct phy_device *phydev);
int phy_aneg_done(struct phy_device *phydev);
int phy_stop_interrupts(struct phy_device *phydev);
......
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