Commit 86d60daa authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds

[PATCH] sn: Moved code out of pciio and into its own file - snia_if.c and renamed the functions

From: Pat Gefre <pfg@sgi.com>

Moved code out of pciio and into its own file - snia_if.c and renamed the
functions

pciio clean up
parent b9984b78
...@@ -9,5 +9,5 @@ ...@@ -9,5 +9,5 @@
# Makefile for the sn io routines. # Makefile for the sn io routines.
# #
obj-y += xswitch.o sgi_io_sim.o cdl.o \ obj-y += xswitch.o sgi_io_sim.o cdl.o snia_if.o \
io.o machvec/ drivers/ platform_init/ sn2/ hwgfs/ io.o machvec/ drivers/ platform_init/ sn2/ hwgfs/
...@@ -182,16 +182,16 @@ assign_widgets_to_volunteers(vertex_hdl_t xswitch, vertex_hdl_t hubv) ...@@ -182,16 +182,16 @@ assign_widgets_to_volunteers(vertex_hdl_t xswitch, vertex_hdl_t hubv)
* hub that owned it in the prom. * hub that owned it in the prom.
*/ */
if (is_master_baseio_nasid_widget(nasid, widgetnum)) { if (is_master_baseio_nasid_widget(nasid, widgetnum)) {
extern nasid_t get_master_baseio_nasid(void); extern nasid_t snia_get_master_baseio_nasid(void);
for (i=0; i<num_volunteer; i++) { for (i=0; i<num_volunteer; i++) {
hubv = xvolinfo->xswitch_volunteer[i]; hubv = xvolinfo->xswitch_volunteer[i];
hubinfo_get(hubv, &hubinfo); hubinfo_get(hubv, &hubinfo);
nasid = hubinfo->h_nasid; nasid = hubinfo->h_nasid;
if (nasid == get_master_baseio_nasid()) if (nasid == snia_get_master_baseio_nasid())
goto do_assignment; goto do_assignment;
} }
printk("Nasid == %d, console nasid == %d", printk("Nasid == %d, console nasid == %d",
nasid, get_master_baseio_nasid()); nasid, snia_get_master_baseio_nasid());
nasid = 0; nasid = 0;
} }
......
...@@ -1729,7 +1729,7 @@ pcibr_probe_slot_pic(bridge_t *bridge, ...@@ -1729,7 +1729,7 @@ pcibr_probe_slot_pic(bridge_t *bridge,
{ {
int rv; int rv;
picreg_t p_old_enable = (picreg_t)0, p_new_enable; picreg_t p_old_enable = (picreg_t)0, p_new_enable;
extern int badaddr_val(volatile void *, int, volatile void *); extern int snia_badaddr_val(volatile void *, int, volatile void *);
p_old_enable = bridge->p_int_enable_64; p_old_enable = bridge->p_int_enable_64;
p_new_enable = p_old_enable & ~(BRIDGE_IMR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT); p_new_enable = p_old_enable & ~(BRIDGE_IMR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT);
...@@ -1742,7 +1742,7 @@ pcibr_probe_slot_pic(bridge_t *bridge, ...@@ -1742,7 +1742,7 @@ pcibr_probe_slot_pic(bridge_t *bridge,
bridge->p_int_rst_stat_64 = (BRIDGE_IRR_PCI_GRP_CLR | PIC_PCIX_GRP_CLR); bridge->p_int_rst_stat_64 = (BRIDGE_IRR_PCI_GRP_CLR | PIC_PCIX_GRP_CLR);
(void) bridge->b_wid_tflush; /* flushbus */ (void) bridge->b_wid_tflush; /* flushbus */
} }
rv = badaddr_val((void *) cfg, 4, valp); rv = snia_badaddr_val((void *) cfg, 4, valp);
if (bridge->p_err_int_view_64 & (BRIDGE_ISR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT)) { if (bridge->p_err_int_view_64 & (BRIDGE_ISR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT)) {
bridge->p_int_rst_stat_64 = BRIDGE_IRR_MULTI_CLR; bridge->p_int_rst_stat_64 = BRIDGE_IRR_MULTI_CLR;
rv = 1; /* unoccupied slot */ rv = 1; /* unoccupied slot */
......
This diff is collapsed.
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 Silicon Graphics, Inc. All rights reserved.
*/
#include <asm/sn/sgi.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/pci/pci_bus_cvlink.h>
#include <asm/sn/simulator.h>
extern pciio_provider_t *pciio_to_provider_fns(vertex_hdl_t dev);
int
snia_badaddr_val(volatile void *addr, int len, volatile void *ptr)
{
int ret = 0;
volatile void *new_addr;
switch (len) {
case 4:
new_addr = (void *) addr;
ret = ia64_sn_probe_io_slot((long) new_addr, len, (void *) ptr);
break;
default:
printk(KERN_WARNING
"snia_badaddr_val given len %x but supports len of 4 only\n",
len);
}
if (ret < 0)
panic("snia_badaddr_val: unexpected status (%d) in probing",
ret);
return (ret);
}
nasid_t
snia_get_console_nasid(void)
{
extern nasid_t console_nasid;
extern nasid_t master_baseio_nasid;
if (console_nasid < 0) {
console_nasid = ia64_sn_get_console_nasid();
if (console_nasid < 0) {
// ZZZ What do we do if we don't get a console nasid on the hardware????
if (IS_RUNNING_ON_SIMULATOR())
console_nasid = master_baseio_nasid;
}
}
return console_nasid;
}
nasid_t
snia_get_master_baseio_nasid(void)
{
extern nasid_t master_baseio_nasid;
extern char master_baseio_wid;
if (master_baseio_nasid < 0) {
master_baseio_nasid = ia64_sn_get_master_baseio_nasid();
if (master_baseio_nasid >= 0) {
master_baseio_wid =
WIDGETID_GET(KL_CONFIG_CH_CONS_INFO
(master_baseio_nasid)->memory_base);
}
}
return master_baseio_nasid;
}
/*
* XXX: should probably be called __sn2_pci_rrb_alloc
* used by qla1280
*/
int
snia_pcibr_rrb_alloc(struct pci_dev *pci_dev,
int *count_vchan0, int *count_vchan1)
{
vertex_hdl_t dev = PCIDEV_VERTEX(pci_dev);
return pcibr_rrb_alloc(dev, count_vchan0, count_vchan1);
}
/*
* XXX: interface should be more like
*
* int __sn2_pci_enable_bwswap(struct pci_dev *dev);
* void __sn2_pci_disable_bswap(struct pci_dev *dev);
*/
/* used by ioc4 ide */
pciio_endian_t
snia_pciio_endian_set(struct pci_dev * pci_dev,
pciio_endian_t device_end, pciio_endian_t desired_end)
{
vertex_hdl_t dev = PCIDEV_VERTEX(pci_dev);
return ((pciio_to_provider_fns(dev))->endian_set)
(dev, device_end, desired_end);
}
EXPORT_SYMBOL(snia_pciio_endian_set);
EXPORT_SYMBOL(snia_pcibr_rrb_alloc);
...@@ -218,7 +218,7 @@ sn_setup(char **cmdline_p) ...@@ -218,7 +218,7 @@ sn_setup(char **cmdline_p)
long status, ticks_per_sec, drift; long status, ticks_per_sec, drift;
int pxm; int pxm;
int major = sn_sal_rev_major(), minor = sn_sal_rev_minor(); int major = sn_sal_rev_major(), minor = sn_sal_rev_minor();
extern nasid_t get_master_baseio_nasid(void); extern nasid_t snia_get_master_baseio_nasid(void);
extern void sn_cpu_init(void); extern void sn_cpu_init(void);
MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY; MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY;
...@@ -241,8 +241,8 @@ sn_setup(char **cmdline_p) ...@@ -241,8 +241,8 @@ sn_setup(char **cmdline_p)
} }
master_nasid = get_nasid(); master_nasid = get_nasid();
(void)get_console_nasid(); (void)snia_get_console_nasid();
(void)get_master_baseio_nasid(); (void)snia_get_master_baseio_nasid();
status = ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, &drift); status = ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, &drift);
if (status != 0 || ticks_per_sec < 100000) { if (status != 0 || ticks_per_sec < 100000) {
......
...@@ -196,6 +196,31 @@ typedef enum pciio_endian_e { ...@@ -196,6 +196,31 @@ typedef enum pciio_endian_e {
PCIDMA_ENDIAN_LITTLE PCIDMA_ENDIAN_LITTLE
} pciio_endian_t; } pciio_endian_t;
/*
* Generic PCI bus information
*/
typedef enum pciio_asic_type_e {
PCIIO_ASIC_TYPE_UNKNOWN,
PCIIO_ASIC_TYPE_MACE,
PCIIO_ASIC_TYPE_BRIDGE,
PCIIO_ASIC_TYPE_XBRIDGE,
PCIIO_ASIC_TYPE_PIC,
} pciio_asic_type_t;
typedef enum pciio_bus_type_e {
PCIIO_BUS_TYPE_UNKNOWN,
PCIIO_BUS_TYPE_PCI,
PCIIO_BUS_TYPE_PCIX
} pciio_bus_type_t;
typedef enum pciio_bus_speed_e {
PCIIO_BUS_SPEED_UNKNOWN,
PCIIO_BUS_SPEED_33,
PCIIO_BUS_SPEED_66,
PCIIO_BUS_SPEED_100,
PCIIO_BUS_SPEED_133
} pciio_bus_speed_t;
/* /*
* Interface to set PCI arbitration priority for devices that require * Interface to set PCI arbitration priority for devices that require
* realtime characteristics. pciio_priority_set is used to switch a * realtime characteristics. pciio_priority_set is used to switch a
...@@ -221,6 +246,9 @@ typedef struct pciio_piospace_s *pciio_piospace_t; ...@@ -221,6 +246,9 @@ typedef struct pciio_piospace_s *pciio_piospace_t;
typedef struct pciio_win_info_s *pciio_win_info_t; typedef struct pciio_win_info_s *pciio_win_info_t;
typedef struct pciio_win_map_s *pciio_win_map_t; typedef struct pciio_win_map_s *pciio_win_map_t;
typedef struct pciio_win_alloc_s *pciio_win_alloc_t; typedef struct pciio_win_alloc_s *pciio_win_alloc_t;
typedef struct pciio_bus_map_s *pciio_bus_map_t;
typedef struct pciio_businfo_s *pciio_businfo_t;
/* PIO MANAGEMENT */ /* PIO MANAGEMENT */
...@@ -451,6 +479,9 @@ pciio_driver_unreg_callback_f (vertex_hdl_t conn, /* pci connection point */ ...@@ -451,6 +479,9 @@ pciio_driver_unreg_callback_f (vertex_hdl_t conn, /* pci connection point */
typedef int typedef int
pciio_device_unregister_f (vertex_hdl_t conn); pciio_device_unregister_f (vertex_hdl_t conn);
typedef pciio_businfo_t
pciio_businfo_get_f (vertex_hdl_t conn);
/* /*
* Adapters that provide a PCI interface adhere to this software interface. * Adapters that provide a PCI interface adhere to this software interface.
*/ */
...@@ -499,6 +530,9 @@ typedef struct pciio_provider_s { ...@@ -499,6 +530,9 @@ typedef struct pciio_provider_s {
pciio_driver_reg_callback_f *driver_reg_callback; pciio_driver_reg_callback_f *driver_reg_callback;
pciio_driver_unreg_callback_f *driver_unreg_callback; pciio_driver_unreg_callback_f *driver_unreg_callback;
pciio_device_unregister_f *device_unregister; pciio_device_unregister_f *device_unregister;
/* GENERIC BUS INFO */
pciio_businfo_get_f *businfo_get;
} pciio_provider_t; } pciio_provider_t;
/* PCI devices use these standard PCI provider interfaces */ /* PCI devices use these standard PCI provider interfaces */
...@@ -743,8 +777,4 @@ sn_pci_set_vchan(struct pci_dev *pci_dev, ...@@ -743,8 +777,4 @@ sn_pci_set_vchan(struct pci_dev *pci_dev,
int snia_badaddr_val(volatile void *addr, int len, volatile void *ptr); int snia_badaddr_val(volatile void *addr, int len, volatile void *ptr);
nasid_t snia_get_console_nasid(void); nasid_t snia_get_console_nasid(void);
nasid_t snia_get_master_baseio_nasid(void); nasid_t snia_get_master_baseio_nasid(void);
/* XXX: should probably be called __sn2_pci_rrb_alloc */
int snia_pcibr_rrb_alloc(struct pci_dev *pci_dev, int *count_vchan0, int *count_vchan1);
pciio_endian_t snia_pciio_endian_set(struct pci_dev *pci_dev,
pciio_endian_t device_end, pciio_endian_t desired_end);
#endif /* _ASM_IA64_SN_PCI_PCIIO_H */ #endif /* _ASM_IA64_SN_PCI_PCIIO_H */
...@@ -58,6 +58,20 @@ struct pciio_intr_s { ...@@ -58,6 +58,20 @@ struct pciio_intr_s {
#define PCIIO_INTR_CONNECTED 1 /* interrupt handler/thread has been connected */ #define PCIIO_INTR_CONNECTED 1 /* interrupt handler/thread has been connected */
#define PCIIO_INTR_NOTHREAD 2 /* interrupt handler wants to be called at interrupt level */ #define PCIIO_INTR_NOTHREAD 2 /* interrupt handler wants to be called at interrupt level */
/*
* Generic PCI bus information
*/
struct pciio_businfo_s {
int bi_multi_master;/* Bus provider supports multiple */
/* dma masters behind a single slot. */
/* Needed to work around a thrashing */
/* issue in SGI Bridge ASIC and */
/* its derivatives. */
pciio_asic_type_t bi_asic_type; /* PCI ASIC type */
pciio_bus_type_t bi_bus_type; /* PCI bus type */
pciio_bus_speed_t bi_bus_speed; /* PCI bus speed */
};
/* /*
* Some PCI provider implementations keep track of PCI window Base Address * Some PCI provider implementations keep track of PCI window Base Address
* Register (BAR) address range assignment via the rmalloc()/rmfree() arena * Register (BAR) address range assignment via the rmalloc()/rmfree() arena
...@@ -98,6 +112,7 @@ struct pciio_win_alloc_s { ...@@ -98,6 +112,7 @@ struct pciio_win_alloc_s {
struct pciio_info_s { struct pciio_info_s {
char *c_fingerprint; char *c_fingerprint;
vertex_hdl_t c_vertex; /* back pointer to vertex */ vertex_hdl_t c_vertex; /* back pointer to vertex */
vertex_hdl_t c_hostvertex;/* top most device in tree */
pciio_bus_t c_bus; /* which bus the card is in */ pciio_bus_t c_bus; /* which bus the card is in */
pciio_slot_t c_slot; /* which slot the card is in */ pciio_slot_t c_slot; /* which slot the card is in */
pciio_function_t c_func; /* which func (on multi-func cards) */ pciio_function_t c_func; /* which func (on multi-func cards) */
...@@ -111,6 +126,8 @@ struct pciio_info_s { ...@@ -111,6 +126,8 @@ struct pciio_info_s {
struct pciio_win_info_s { /* state of BASE regs */ struct pciio_win_info_s { /* state of BASE regs */
pciio_space_t w_space; pciio_space_t w_space;
char w_code; /* low 4 bits of MEM BAR */
/* low 2 bits of IO BAR */
iopaddr_t w_base; iopaddr_t w_base;
size_t w_size; size_t w_size;
int w_devio_index; /* DevIO[] register used to int w_devio_index; /* DevIO[] register used to
...@@ -121,6 +138,7 @@ struct pciio_info_s { ...@@ -121,6 +138,7 @@ struct pciio_info_s {
#define c_rbase c_rwindow.w_base /* EXPANSION ROM base addr */ #define c_rbase c_rwindow.w_base /* EXPANSION ROM base addr */
#define c_rsize c_rwindow.w_size /* EXPANSION ROM size (bytes) */ #define c_rsize c_rwindow.w_size /* EXPANSION ROM size (bytes) */
pciio_piospace_t c_piospace; /* additional I/O spaces allocated */ pciio_piospace_t c_piospace; /* additional I/O spaces allocated */
int c_type1; /* use type1 addressing */
}; };
extern char pciio_info_fingerprint[]; extern char pciio_info_fingerprint[];
......
...@@ -22,7 +22,6 @@ extern void cpu_unenable(cpuid_t); ...@@ -22,7 +22,6 @@ extern void cpu_unenable(cpuid_t);
extern nasid_t get_lowest_nasid(void); extern nasid_t get_lowest_nasid(void);
extern __psunsigned_t get_master_bridge_base(void); extern __psunsigned_t get_master_bridge_base(void);
extern int check_nasid_equiv(nasid_t, nasid_t); extern int check_nasid_equiv(nasid_t, nasid_t);
extern nasid_t get_console_nasid(void);
extern char get_console_pcislot(void); extern char get_console_pcislot(void);
extern int is_master_baseio_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid); extern int is_master_baseio_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid);
......
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