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Commit 86ed3669 authored by Mark Brown's avatar Mark Brown
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ASoC: WM9081 mono DAC with integrated 2.6W class AB/D amplifier driver 

The WM9081 is designed to provide high power output at low distortion
levels in space-constrained portable applications.
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent b4852b79
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include/sound/wm9081.h 0 → 100644
View file @ 86ed3669
/*
* linux/sound/wm9081.h -- Platform data for WM9081
*
* Copyright 2009 Wolfson Microelectronics. PLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SND_WM_9081_H
#define __LINUX_SND_WM_9081_H
struct wm9081_retune_mobile_setting {
const char *name;
unsigned int rate;
u16 config[20];
};
struct wm9081_retune_mobile_config {
struct wm9081_retune_mobile_setting *configs;
int num_configs;
};
#endif
sound/soc/codecs/Kconfig
View file @ 86ed3669
......@@ -40,6 +40,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_WM8971 if I2C
select SND_SOC_WM8988 if SND_SOC_I2C_AND_SPI
select SND_SOC_WM8990 if I2C
select SND_SOC_WM9081 if I2C
select SND_SOC_WM9705 if SND_SOC_AC97_BUS
select SND_SOC_WM9712 if SND_SOC_AC97_BUS
select SND_SOC_WM9713 if SND_SOC_AC97_BUS
......@@ -156,6 +157,9 @@ config SND_SOC_WM8988
config SND_SOC_WM8990
tristate
config SND_SOC_WM9081
tristate
config SND_SOC_WM9705
tristate
......
sound/soc/codecs/Makefile
View file @ 86ed3669
......@@ -28,6 +28,7 @@ snd-soc-wm8960-objs := wm8960.o
snd-soc-wm8971-objs := wm8971.o
snd-soc-wm8988-objs := wm8988.o
snd-soc-wm8990-objs := wm8990.o
snd-soc-wm9081-objs := wm9081.o
snd-soc-wm9705-objs := wm9705.o
snd-soc-wm9712-objs := wm9712.o
snd-soc-wm9713-objs := wm9713.o
......@@ -62,6 +63,7 @@ obj-$(CONFIG_SND_SOC_WM8940) += snd-soc-wm8940.o
obj-$(CONFIG_SND_SOC_WM8960) += snd-soc-wm8960.o
obj-$(CONFIG_SND_SOC_WM8988) += snd-soc-wm8988.o
obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o
obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o
obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o
obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o
obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
sound/soc/codecs/wm9081.c 0 → 100644
View file @ 86ed3669
/*
* wm9081.c -- WM9081 ALSA SoC Audio driver
*
* Author: Mark Brown
*
* Copyright 2009 Wolfson Microelectronics plc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/wm9081.h>
#include "wm9081.h"
static u16 wm9081_reg_defaults[] = {
0x0000, /* R0 - Software Reset */
0x0000, /* R1 */
0x00B9, /* R2 - Analogue Lineout */
0x00B9, /* R3 - Analogue Speaker PGA */
0x0001, /* R4 - VMID Control */
0x0068, /* R5 - Bias Control 1 */
0x0000, /* R6 */
0x0000, /* R7 - Analogue Mixer */
0x0000, /* R8 - Anti Pop Control */
0x01DB, /* R9 - Analogue Speaker 1 */
0x0018, /* R10 - Analogue Speaker 2 */
0x0180, /* R11 - Power Management */
0x0000, /* R12 - Clock Control 1 */
0x0038, /* R13 - Clock Control 2 */
0x4000, /* R14 - Clock Control 3 */
0x0000, /* R15 */
0x0000, /* R16 - FLL Control 1 */
0x0200, /* R17 - FLL Control 2 */
0x0000, /* R18 - FLL Control 3 */
0x0204, /* R19 - FLL Control 4 */
0x0000, /* R20 - FLL Control 5 */
0x0000, /* R21 */
0x0000, /* R22 - Audio Interface 1 */
0x0002, /* R23 - Audio Interface 2 */
0x0008, /* R24 - Audio Interface 3 */
0x0022, /* R25 - Audio Interface 4 */
0x0000, /* R26 - Interrupt Status */
0x0006, /* R27 - Interrupt Status Mask */
0x0000, /* R28 - Interrupt Polarity */
0x0000, /* R29 - Interrupt Control */
0x00C0, /* R30 - DAC Digital 1 */
0x0008, /* R31 - DAC Digital 2 */
0x09AF, /* R32 - DRC 1 */
0x4201, /* R33 - DRC 2 */
0x0000, /* R34 - DRC 3 */
0x0000, /* R35 - DRC 4 */
0x0000, /* R36 */
0x0000, /* R37 */
0x0000, /* R38 - Write Sequencer 1 */
0x0000, /* R39 - Write Sequencer 2 */
0x0002, /* R40 - MW Slave 1 */
0x0000, /* R41 */
0x0000, /* R42 - EQ 1 */
0x0000, /* R43 - EQ 2 */
0x0FCA, /* R44 - EQ 3 */
0x0400, /* R45 - EQ 4 */
0x00B8, /* R46 - EQ 5 */
0x1EB5, /* R47 - EQ 6 */
0xF145, /* R48 - EQ 7 */
0x0B75, /* R49 - EQ 8 */
0x01C5, /* R50 - EQ 9 */
0x169E, /* R51 - EQ 10 */
0xF829, /* R52 - EQ 11 */
0x07AD, /* R53 - EQ 12 */
0x1103, /* R54 - EQ 13 */
0x1C58, /* R55 - EQ 14 */
0xF373, /* R56 - EQ 15 */
0x0A54, /* R57 - EQ 16 */
0x0558, /* R58 - EQ 17 */
0x0564, /* R59 - EQ 18 */
0x0559, /* R60 - EQ 19 */
0x4000, /* R61 - EQ 20 */
};
static struct {
int ratio;
int clk_sys_rate;
} clk_sys_rates[] = {
{ 64, 0 },
{ 128, 1 },
{ 192, 2 },
{ 256, 3 },
{ 384, 4 },
{ 512, 5 },
{ 768, 6 },
{ 1024, 7 },
{ 1408, 8 },
{ 1536, 9 },
};
static struct {
int rate;
int sample_rate;
} sample_rates[] = {
{ 8000, 0 },
{ 11025, 1 },
{ 12000, 2 },
{ 16000, 3 },
{ 22050, 4 },
{ 24000, 5 },
{ 32000, 6 },
{ 44100, 7 },
{ 48000, 8 },
{ 88200, 9 },
{ 96000, 10 },
};
static struct {
int div; /* *10 due to .5s */
int bclk_div;
} bclk_divs[] = {
{ 10, 0 },
{ 15, 1 },
{ 20, 2 },
{ 30, 3 },
{ 40, 4 },
{ 50, 5 },
{ 55, 6 },
{ 60, 7 },
{ 80, 8 },
{ 100, 9 },
{ 110, 10 },
{ 120, 11 },
{ 160, 12 },
{ 200, 13 },
{ 220, 14 },
{ 240, 15 },
{ 250, 16 },
{ 300, 17 },
{ 320, 18 },
{ 440, 19 },
{ 480, 20 },
};
struct wm9081_priv {
struct snd_soc_codec codec;
u16 reg_cache[WM9081_MAX_REGISTER + 1];
int sysclk_source;
int mclk_rate;
int sysclk_rate;
int fs;
int bclk;
int master;
int fll_fref;
int fll_fout;
struct wm9081_retune_mobile_config *retune;
};
static int wm9081_reg_is_volatile(int reg)
{
switch (reg) {
default:
return 0;
}
}
static unsigned int wm9081_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u16 *cache = codec->reg_cache;
BUG_ON(reg > WM9081_MAX_REGISTER);
return cache[reg];
}
static unsigned int wm9081_read_hw(struct snd_soc_codec *codec, u8 reg)
{
struct i2c_msg xfer[2];
u16 data;
int ret;
struct i2c_client *client = codec->control_data;
BUG_ON(reg > WM9081_MAX_REGISTER);
/* Write register */
xfer[0].addr = client->addr;
xfer[0].flags = 0;
xfer[0].len = 1;
xfer[0].buf = &reg;
/* Read data */
xfer[1].addr = client->addr;
xfer[1].flags = I2C_M_RD;
xfer[1].len = 2;
xfer[1].buf = (u8 *)&data;
ret = i2c_transfer(client->adapter, xfer, 2);
if (ret != 2) {
dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
return 0;
}
return (data >> 8) | ((data & 0xff) << 8);
}
static unsigned int wm9081_read(struct snd_soc_codec *codec, unsigned int reg)
{
if (wm9081_reg_is_volatile(reg))
return wm9081_read_hw(codec, reg);
else
return wm9081_read_reg_cache(codec, reg);
}
static int wm9081_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u16 *cache = codec->reg_cache;
u8 data[3];
BUG_ON(reg > WM9081_MAX_REGISTER);
if (!wm9081_reg_is_volatile(reg))
cache[reg] = value;
data[0] = reg;
data[1] = value >> 8;
data[2] = value & 0x00ff;
if (codec->hw_write(codec->control_data, data, 3) == 3)
return 0;
else
return -EIO;
}
static int wm9081_reset(struct snd_soc_codec *codec)
{
return wm9081_write(codec, WM9081_SOFTWARE_RESET, 0);
}
static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
static unsigned int drc_max_tlv[] = {
TLV_DB_RANGE_HEAD(4),
0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
};
static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
static const char *drc_high_text[] = {
"1",
"1/2",
"1/4",
"1/8",
"1/16",
"0",
};
static const struct soc_enum drc_high =
SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
static const char *drc_low_text[] = {
"1",
"1/2",
"1/4",
"1/8",
"0",
};
static const struct soc_enum drc_low =
SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
static const char *drc_atk_text[] = {
"181us",
"181us",
"363us",
"726us",
"1.45ms",
"2.9ms",
"5.8ms",
"11.6ms",
"23.2ms",
"46.4ms",
"92.8ms",
"185.6ms",
};
static const struct soc_enum drc_atk =
SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
static const char *drc_dcy_text[] = {
"186ms",
"372ms",
"743ms",
"1.49s",
"2.97s",
"5.94s",
"11.89s",
"23.78s",
"47.56s",
};
static const struct soc_enum drc_dcy =
SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
static const char *drc_qr_dcy_text[] = {
"0.725ms",
"1.45ms",
"5.8ms",
};
static const struct soc_enum drc_qr_dcy =
SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
static const char *dac_deemph_text[] = {
"None",
"32kHz",
"44.1kHz",
"48kHz",
};
static const struct soc_enum dac_deemph =
SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
static const char *speaker_mode_text[] = {
"Class D",
"Class AB",
};
static const struct soc_enum speaker_mode =
SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
static int speaker_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
unsigned int reg;
reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2);
if (reg & WM9081_SPK_MODE)
ucontrol->value.integer.value[0] = 1;
else
ucontrol->value.integer.value[0] = 0;
return 0;
}
/*
* Stop any attempts to change speaker mode while the speaker is enabled.
*
* We also have some special anti-pop controls dependant on speaker
* mode which must be changed along with the mode.
*/
static int speaker_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
unsigned int reg_pwr = wm9081_read(codec, WM9081_POWER_MANAGEMENT);
unsigned int reg2 = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2);
/* Are we changing anything? */
if (ucontrol->value.integer.value[0] ==
((reg2 & WM9081_SPK_MODE) != 0))
return 0;
/* Don't try to change modes while enabled */
if (reg_pwr & WM9081_SPK_ENA)
return -EINVAL;
if (ucontrol->value.integer.value[0]) {
/* Class AB */
reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
reg2 |= WM9081_SPK_MODE;
} else {
/* Class D */
reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
reg2 &= ~WM9081_SPK_MODE;
}
wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
return 0;
}
static const struct snd_kcontrol_new wm9081_snd_controls[] = {
SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
SOC_ENUM("DRC High Slope", drc_high),
SOC_ENUM("DRC Low Slope", drc_low),
SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
SOC_ENUM("DRC Attack", drc_atk),
SOC_ENUM("DRC Decay", drc_dcy),
SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
out_tlv),
SOC_ENUM("DAC Deemphasis", dac_deemph),
SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
};
static const struct snd_kcontrol_new wm9081_eq_controls[] = {
SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
};
static const struct snd_kcontrol_new mixer[] = {
SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
};
static int speaker_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
unsigned int reg = wm9081_read(codec, WM9081_POWER_MANAGEMENT);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
reg |= WM9081_SPK_ENA;
break;
case SND_SOC_DAPM_PRE_PMD:
reg &= ~WM9081_SPK_ENA;
break;
}
wm9081_write(codec, WM9081_POWER_MANAGEMENT, reg);
return 0;
}
struct _fll_div {
u16 fll_fratio;
u16 fll_outdiv;
u16 fll_clk_ref_div;
u16 n;
u16 k;
};
/* The size in bits of the FLL divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 16) * 10)
static struct {
unsigned int min;
unsigned int max;
u16 fll_fratio;
int ratio;
} fll_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
unsigned int Fout)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod, target;
unsigned int div;
int i;
/* Fref must be <=13.5MHz */
div = 1;
while ((Fref / div) > 13500000) {
div *= 2;
if (div > 8) {
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
Fref);
return -EINVAL;
}
}
fll_div->fll_clk_ref_div = div / 2;
pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
/* Apply the division for our remaining calculations */
Fref /= div;
/* Fvco should be 90-100MHz; don't check the upper bound */
div = 0;
target = Fout * 2;
while (target < 90000000) {
div++;
target *= 2;
if (div > 7) {
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
Fout);
return -EINVAL;
}
}
fll_div->fll_outdiv = div;
pr_debug("Fvco=%dHz\n", target);
/* Find an appropraite FLL_FRATIO and factor it out of the target */
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
target /= fll_fratios[i].ratio;
break;
}
}
if (i == ARRAY_SIZE(fll_fratios)) {
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
return -EINVAL;
}
/* Now, calculate N.K */
Ndiv = target / Fref;
fll_div->n = Ndiv;
Nmod = target % Fref;
pr_debug("Nmod=%d\n", Nmod);
/* Calculate fractional part - scale up so we can round. */
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, Fref);
K = Kpart & 0xFFFFFFFF;
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
fll_div->k = K / 10;
pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
fll_div->n, fll_div->k,
fll_div->fll_fratio, fll_div->fll_outdiv,
fll_div->fll_clk_ref_div);
return 0;
}
static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
unsigned int Fref, unsigned int Fout)
{
struct wm9081_priv *wm9081 = codec->private_data;
u16 reg1, reg4, reg5;
struct _fll_div fll_div;
int ret;
int clk_sys_reg;
/* Any change? */
if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
return 0;
/* Disable the FLL */
if (Fout == 0) {
dev_dbg(codec->dev, "FLL disabled\n");
wm9081->fll_fref = 0;
wm9081->fll_fout = 0;
return 0;
}
ret = fll_factors(&fll_div, Fref, Fout);
if (ret != 0)
return ret;
reg5 = wm9081_read(codec, WM9081_FLL_CONTROL_5);
reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
switch (fll_id) {
case WM9081_SYSCLK_FLL_MCLK:
reg5 |= 0x1;
break;
default:
dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
return -EINVAL;
}
/* Disable CLK_SYS while we reconfigure */
clk_sys_reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3);
if (clk_sys_reg & WM9081_CLK_SYS_ENA)
wm9081_write(codec, WM9081_CLOCK_CONTROL_3,
clk_sys_reg & ~WM9081_CLK_SYS_ENA);
/* Any FLL configuration change requires that the FLL be
* disabled first. */
reg1 = wm9081_read(codec, WM9081_FLL_CONTROL_1);
reg1 &= ~WM9081_FLL_ENA;
wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1);
/* Apply the configuration */
if (fll_div.k)
reg1 |= WM9081_FLL_FRAC_MASK;
else
reg1 &= ~WM9081_FLL_FRAC_MASK;
wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1);
wm9081_write(codec, WM9081_FLL_CONTROL_2,
(fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
(fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
wm9081_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
reg4 = wm9081_read(codec, WM9081_FLL_CONTROL_4);
reg4 &= ~WM9081_FLL_N_MASK;
reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
wm9081_write(codec, WM9081_FLL_CONTROL_4, reg4);
reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
wm9081_write(codec, WM9081_FLL_CONTROL_5, reg5);
/* Enable the FLL */
wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
/* Then bring CLK_SYS up again if it was disabled */
if (clk_sys_reg & WM9081_CLK_SYS_ENA)
wm9081_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
wm9081->fll_fref = Fref;
wm9081->fll_fout = Fout;
return 0;
}
static int configure_clock(struct snd_soc_codec *codec)
{
struct wm9081_priv *wm9081 = codec->private_data;
int new_sysclk, i, target;
unsigned int reg;
int ret = 0;
int mclkdiv = 0;
int fll = 0;
switch (wm9081->sysclk_source) {
case WM9081_SYSCLK_MCLK:
if (wm9081->mclk_rate > 12225000) {
mclkdiv = 1;
wm9081->sysclk_rate = wm9081->mclk_rate / 2;
} else {
wm9081->sysclk_rate = wm9081->mclk_rate;
}
wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
break;
case WM9081_SYSCLK_FLL_MCLK:
/* If we have a sample rate calculate a CLK_SYS that
* gives us a suitable DAC configuration, plus BCLK.
* Ideally we would check to see if we can clock
* directly from MCLK and only use the FLL if this is
* not the case, though care must be taken with free
* running mode.
*/
if (wm9081->master && wm9081->bclk) {
/* Make sure we can generate CLK_SYS and BCLK
* and that we've got 3MHz for optimal
* performance. */
for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
target = wm9081->fs * clk_sys_rates[i].ratio;
if (target >= wm9081->bclk &&
target > 3000000)
new_sysclk = target;
}
} else if (wm9081->fs) {
for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
new_sysclk = clk_sys_rates[i].ratio
* wm9081->fs;
if (new_sysclk > 3000000)
break;
}
} else {
new_sysclk = 12288000;
}
ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
wm9081->mclk_rate, new_sysclk);
if (ret == 0) {
wm9081->sysclk_rate = new_sysclk;
/* Switch SYSCLK over to FLL */
fll = 1;
} else {
wm9081->sysclk_rate = wm9081->mclk_rate;
}
break;
default:
return -EINVAL;
}
reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_1);
if (mclkdiv)
reg |= WM9081_MCLKDIV2;
else
reg &= ~WM9081_MCLKDIV2;
wm9081_write(codec, WM9081_CLOCK_CONTROL_1, reg);
reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3);
if (fll)
reg |= WM9081_CLK_SRC_SEL;
else
reg &= ~WM9081_CLK_SRC_SEL;
wm9081_write(codec, WM9081_CLOCK_CONTROL_3, reg);
dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
return ret;
}
static int clk_sys_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
struct wm9081_priv *wm9081 = codec->private_data;
/* This should be done on init() for bypass paths */
switch (wm9081->sysclk_source) {
case WM9081_SYSCLK_MCLK:
dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
break;
case WM9081_SYSCLK_FLL_MCLK:
dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
wm9081->mclk_rate);
break;
default:
dev_err(codec->dev, "System clock not configured\n");
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
configure_clock(codec);
break;
case SND_SOC_DAPM_POST_PMD:
/* Disable the FLL if it's running */
wm9081_set_fll(codec, 0, 0, 0);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1"),
SND_SOC_DAPM_INPUT("IN2"),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
mixer, ARRAY_SIZE(mixer)),
SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0,
speaker_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("LINEOUT"),
SND_SOC_DAPM_OUTPUT("SPKN"),
SND_SOC_DAPM_OUTPUT("SPKP"),
SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
};
static const struct snd_soc_dapm_route audio_paths[] = {
{ "DAC", NULL, "CLK_SYS" },
{ "DAC", NULL, "CLK_DSP" },
{ "Mixer", "IN1 Switch", "IN1" },
{ "Mixer", "IN2 Switch", "IN2" },
{ "Mixer", "Playback Switch", "DAC" },
{ "LINEOUT PGA", NULL, "Mixer" },
{ "LINEOUT PGA", NULL, "TOCLK" },
{ "LINEOUT PGA", NULL, "CLK_SYS" },
{ "LINEOUT", NULL, "LINEOUT PGA" },
{ "Speaker PGA", NULL, "Mixer" },
{ "Speaker PGA", NULL, "TOCLK" },
{ "Speaker PGA", NULL, "CLK_SYS" },
{ "SPKN", NULL, "Speaker PGA" },
{ "SPKP", NULL, "Speaker PGA" },
};
static int wm9081_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 reg;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VMID=2*40k */
reg = wm9081_read(codec, WM9081_VMID_CONTROL);
reg &= ~WM9081_VMID_SEL_MASK;
reg |= 0x2;
wm9081_write(codec, WM9081_VMID_CONTROL, reg);
/* Normal bias current */
reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
reg &= ~WM9081_STBY_BIAS_ENA;
wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg);
break;
case SND_SOC_BIAS_STANDBY:
/* Initial cold start */
if (codec->bias_level == SND_SOC_BIAS_OFF) {
/* Disable LINEOUT discharge */
reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL);
reg &= ~WM9081_LINEOUT_DISCH;
wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg);
/* Select startup bias source */
reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg);
/* VMID 2*4k; Soft VMID ramp enable */
reg = wm9081_read(codec, WM9081_VMID_CONTROL);
reg |= WM9081_VMID_RAMP | 0x6;
wm9081_write(codec, WM9081_VMID_CONTROL, reg);
mdelay(100);
/* Normal bias enable & soft start off */
reg |= WM9081_BIAS_ENA;
reg &= ~WM9081_VMID_RAMP;
wm9081_write(codec, WM9081_VMID_CONTROL, reg);
/* Standard bias source */
reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
reg &= ~WM9081_BIAS_SRC;
wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg);
}
/* VMID 2*240k */
reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
reg &= ~WM9081_VMID_SEL_MASK;
reg |= 0x40;
wm9081_write(codec, WM9081_VMID_CONTROL, reg);
/* Standby bias current on */
reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
reg |= WM9081_STBY_BIAS_ENA;
wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg);
break;
case SND_SOC_BIAS_OFF:
/* Startup bias source */
reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
reg |= WM9081_BIAS_SRC;
wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg);
/* Disable VMID and biases with soft ramping */
reg = wm9081_read(codec, WM9081_VMID_CONTROL);
reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
reg |= WM9081_VMID_RAMP;
wm9081_write(codec, WM9081_VMID_CONTROL, reg);
/* Actively discharge LINEOUT */
reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL);
reg |= WM9081_LINEOUT_DISCH;
wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg);
break;
}
codec->bias_level = level;
return 0;
}
static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = dai->codec;
struct wm9081_priv *wm9081 = codec->private_data;
unsigned int aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2);
aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
wm9081->master = 0;
break;
case SND_SOC_DAIFMT_CBS_CFM:
aif2 |= WM9081_LRCLK_DIR;
wm9081->master = 1;
break;
case SND_SOC_DAIFMT_CBM_CFS:
aif2 |= WM9081_BCLK_DIR;
wm9081->master = 1;
break;
case SND_SOC_DAIFMT_CBM_CFM:
aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
wm9081->master = 1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
aif2 |= WM9081_AIF_LRCLK_INV;
case SND_SOC_DAIFMT_DSP_A:
aif2 |= 0x3;
break;
case SND_SOC_DAIFMT_I2S:
aif2 |= 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aif2 |= 0x1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif2 |= WM9081_AIF_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif2 |= WM9081_AIF_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif2 |= WM9081_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
return 0;
}
static int wm9081_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct wm9081_priv *wm9081 = codec->private_data;
int ret, i, best, best_val, cur_val;
unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
clk_ctrl2 = wm9081_read(codec, WM9081_CLOCK_CONTROL_2);
clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1);
aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2);
aif2 &= ~WM9081_AIF_WL_MASK;
aif3 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_3);
aif3 &= ~WM9081_BCLK_DIV_MASK;
aif4 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_4);
aif4 &= ~WM9081_LRCLK_RATE_MASK;
/* What BCLK do we need? */
wm9081->fs = params_rate(params);
wm9081->bclk = 2 * wm9081->fs;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
wm9081->bclk *= 16;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
wm9081->bclk *= 20;
aif2 |= 0x4;
break;
case SNDRV_PCM_FORMAT_S24_LE:
wm9081->bclk *= 24;
aif2 |= 0x8;
break;
case SNDRV_PCM_FORMAT_S32_LE:
wm9081->bclk *= 32;
aif2 |= 0xc;
break;
default:
return -EINVAL;
}
if (aif1 & WM9081_AIFDAC_TDM_MODE_MASK) {
int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
wm9081->bclk *= slots;
}
dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
ret = configure_clock(codec);
if (ret != 0)
return ret;
/* Select nearest CLK_SYS_RATE */
best = 0;
best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
- wm9081->fs);
for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
cur_val = abs((wm9081->sysclk_rate /
clk_sys_rates[i].ratio) - wm9081->fs);;
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
clk_sys_rates[best].ratio);
clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
<< WM9081_CLK_SYS_RATE_SHIFT);
/* SAMPLE_RATE */
best = 0;
best_val = abs(wm9081->fs - sample_rates[0].rate);
for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
/* Closest match */
cur_val = abs(wm9081->fs - sample_rates[i].rate);
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
sample_rates[best].rate);
clk_ctrl2 |= (sample_rates[i].sample_rate << WM9081_SAMPLE_RATE_SHIFT);
/* BCLK_DIV */
best = 0;
best_val = INT_MAX;
for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
- wm9081->bclk;
if (cur_val < 0) /* Table is sorted */
break;
if (cur_val < best_val) {
best = i;
best_val = cur_val;
}
}
wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
bclk_divs[best].div, wm9081->bclk);
aif3 |= bclk_divs[best].bclk_div;
/* LRCLK is a simple fraction of BCLK */
dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
aif4 |= wm9081->bclk / wm9081->fs;
/* Apply a ReTune Mobile configuration if it's in use */
if (wm9081->retune) {
struct wm9081_retune_mobile_config *retune = wm9081->retune;
struct wm9081_retune_mobile_setting *s;
int eq1;
best = 0;
best_val = abs(retune->configs[0].rate - wm9081->fs);
for (i = 0; i < retune->num_configs; i++) {
cur_val = abs(retune->configs[i].rate - wm9081->fs);
if (cur_val < best_val) {
best_val = cur_val;
best = i;
}
}
s = &retune->configs[best];
dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
s->name, s->rate);
/* If the EQ is enabled then disable it while we write out */
eq1 = wm9081_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
if (eq1 & WM9081_EQ_ENA)
wm9081_write(codec, WM9081_EQ_1, 0);
/* Write out the other values */
for (i = 1; i < ARRAY_SIZE(s->config); i++)
wm9081_write(codec, WM9081_EQ_1 + i, s->config[i]);
eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
wm9081_write(codec, WM9081_EQ_1, eq1);
}
wm9081_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
wm9081_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
wm9081_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
return 0;
}
static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
{
struct snd_soc_codec *codec = codec_dai->codec;
unsigned int reg;
reg = wm9081_read(codec, WM9081_DAC_DIGITAL_2);
if (mute)
reg |= WM9081_DAC_MUTE;
else
reg &= ~WM9081_DAC_MUTE;
wm9081_write(codec, WM9081_DAC_DIGITAL_2, reg);
return 0;
}
static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct wm9081_priv *wm9081 = codec->private_data;
switch (clk_id) {
case WM9081_SYSCLK_MCLK:
case WM9081_SYSCLK_FLL_MCLK:
wm9081->sysclk_source = clk_id;
wm9081->mclk_rate = freq;
break;
default:
return -EINVAL;
}
return 0;
}
static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int mask, int slots)
{
struct snd_soc_codec *codec = dai->codec;
unsigned int aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1);
aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
if (slots < 1 || slots > 4)
return -EINVAL;
aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
switch (mask) {
case 1:
break;
case 2:
aif1 |= 0x10;
break;
case 4:
aif1 |= 0x20;
break;
case 8:
aif1 |= 0x30;
break;
default:
return -EINVAL;
}
wm9081_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
return 0;
}
#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
#define WM9081_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_ops wm9081_dai_ops = {
.hw_params = wm9081_hw_params,
.set_sysclk = wm9081_set_sysclk,
.set_fmt = wm9081_set_dai_fmt,
.digital_mute = wm9081_digital_mute,
.set_tdm_slot = wm9081_set_tdm_slot,
};
/* We report two channels because the CODEC processes a stereo signal, even
* though it is only capable of handling a mono output.
*/
struct snd_soc_dai wm9081_dai = {
.name = "WM9081",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM9081_RATES,
.formats = WM9081_FORMATS,
},
.ops = &wm9081_dai_ops,
};
EXPORT_SYMBOL_GPL(wm9081_dai);
static struct snd_soc_codec *wm9081_codec;
static int wm9081_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
struct wm9081_priv *wm9081;
int ret = 0;
if (wm9081_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = wm9081_codec;
codec = wm9081_codec;
wm9081 = codec->private_data;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
snd_soc_add_controls(codec, wm9081_snd_controls,
ARRAY_SIZE(wm9081_snd_controls));
if (!wm9081->retune) {
dev_dbg(codec->dev,
"No ReTune Mobile data, using normal EQ\n");
snd_soc_add_controls(codec, wm9081_eq_controls,
ARRAY_SIZE(wm9081_eq_controls));
}
snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets,
ARRAY_SIZE(wm9081_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
snd_soc_dapm_new_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
static int wm9081_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
#ifdef CONFIG_PM
static int wm9081_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm9081_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
u16 *reg_cache = codec->reg_cache;
int i;
for (i = 0; i < codec->reg_cache_size; i++) {
if (i == WM9081_SOFTWARE_RESET)
continue;
wm9081_write(codec, i, reg_cache[i]);
}
wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
return 0;
}
#else
#define wm9081_suspend NULL
#define wm9081_resume NULL
#endif
struct snd_soc_codec_device soc_codec_dev_wm9081 = {
.probe = wm9081_probe,
.remove = wm9081_remove,
.suspend = wm9081_suspend,
.resume = wm9081_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081);
static int wm9081_register(struct wm9081_priv *wm9081)
{
struct snd_soc_codec *codec = &wm9081->codec;
int ret;
u16 reg;
if (wm9081_codec) {
dev_err(codec->dev, "Another WM9081 is registered\n");
ret = -EINVAL;
goto err;
}
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = wm9081;
codec->name = "WM9081";
codec->owner = THIS_MODULE;
codec->read = wm9081_read;
codec->write = wm9081_write;
codec->dai = &wm9081_dai;
codec->num_dai = 1;
codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache);
codec->reg_cache = &wm9081->reg_cache;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->set_bias_level = wm9081_set_bias_level;
memcpy(codec->reg_cache, wm9081_reg_defaults,
sizeof(wm9081_reg_defaults));
reg = wm9081_read_hw(codec, WM9081_SOFTWARE_RESET);
if (reg != 0x9081) {
dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
ret = -EINVAL;
goto err;
}
ret = wm9081_reset(codec);
if (ret < 0) {
dev_err(codec->dev, "Failed to issue reset\n");
return ret;
}
wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
/* Enable zero cross by default */
reg = wm9081_read(codec, WM9081_ANALOGUE_LINEOUT);
wm9081_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
reg | WM9081_SPKPGAZC);
wm9081_dai.dev = codec->dev;
wm9081_codec = codec;
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
return ret;
}
ret = snd_soc_register_dai(&wm9081_dai);
if (ret != 0) {
dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
snd_soc_unregister_codec(codec);
return ret;
}
return 0;
err:
kfree(wm9081);
return ret;
}
static void wm9081_unregister(struct wm9081_priv *wm9081)
{
wm9081_set_bias_level(&wm9081->codec, SND_SOC_BIAS_OFF);
snd_soc_unregister_dai(&wm9081_dai);
snd_soc_unregister_codec(&wm9081->codec);
kfree(wm9081);
wm9081_codec = NULL;
}
static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct wm9081_priv *wm9081;
struct snd_soc_codec *codec;
wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
if (wm9081 == NULL)
return -ENOMEM;
codec = &wm9081->codec;
codec->hw_write = (hw_write_t)i2c_master_send;
wm9081->retune = i2c->dev.platform_data;
i2c_set_clientdata(i2c, wm9081);
codec->control_data = i2c;
codec->dev = &i2c->dev;
return wm9081_register(wm9081);
}
static __devexit int wm9081_i2c_remove(struct i2c_client *client)
{
struct wm9081_priv *wm9081 = i2c_get_clientdata(client);
wm9081_unregister(wm9081);
return 0;
}
static const struct i2c_device_id wm9081_i2c_id[] = {
{ "wm9081", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
static struct i2c_driver wm9081_i2c_driver = {
.driver = {
.name = "wm9081",
.owner = THIS_MODULE,
},
.probe = wm9081_i2c_probe,
.remove = __devexit_p(wm9081_i2c_remove),
.id_table = wm9081_i2c_id,
};
static int __init wm9081_modinit(void)
{
int ret;
ret = i2c_add_driver(&wm9081_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
ret);
}
return ret;
}
module_init(wm9081_modinit);
static void __exit wm9081_exit(void)
{
i2c_del_driver(&wm9081_i2c_driver);
}
module_exit(wm9081_exit);
MODULE_DESCRIPTION("ASoC WM9081 driver");
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_LICENSE("GPL");
sound/soc/codecs/wm9081.h 0 → 100644
View file @ 86ed3669
#ifndef WM9081_H
#define WM9081_H
/*
* wm9081.c -- WM9081 ALSA SoC Audio driver
*
* Author: Mark Brown
*
* Copyright 2009 Wolfson Microelectronics plc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <sound/soc.h>
extern struct snd_soc_dai wm9081_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm9081;
/*
* SYSCLK sources
*/
#define WM9081_SYSCLK_MCLK 1 /* Use MCLK without FLL */
#define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCLK, enabling FLL if required */
/*
* Register values.
*/
#define WM9081_SOFTWARE_RESET 0x00
#define WM9081_ANALOGUE_LINEOUT 0x02
#define WM9081_ANALOGUE_SPEAKER_PGA 0x03
#define WM9081_VMID_CONTROL 0x04
#define WM9081_BIAS_CONTROL_1 0x05
#define WM9081_ANALOGUE_MIXER 0x07
#define WM9081_ANTI_POP_CONTROL 0x08
#define WM9081_ANALOGUE_SPEAKER_1 0x09
#define WM9081_ANALOGUE_SPEAKER_2 0x0A
#define WM9081_POWER_MANAGEMENT 0x0B
#define WM9081_CLOCK_CONTROL_1 0x0C
#define WM9081_CLOCK_CONTROL_2 0x0D
#define WM9081_CLOCK_CONTROL_3 0x0E
#define WM9081_FLL_CONTROL_1 0x10
#define WM9081_FLL_CONTROL_2 0x11
#define WM9081_FLL_CONTROL_3 0x12
#define WM9081_FLL_CONTROL_4 0x13
#define WM9081_FLL_CONTROL_5 0x14
#define WM9081_AUDIO_INTERFACE_1 0x16
#define WM9081_AUDIO_INTERFACE_2 0x17
#define WM9081_AUDIO_INTERFACE_3 0x18
#define WM9081_AUDIO_INTERFACE_4 0x19
#define WM9081_INTERRUPT_STATUS 0x1A
#define WM9081_INTERRUPT_STATUS_MASK 0x1B
#define WM9081_INTERRUPT_POLARITY 0x1C
#define WM9081_INTERRUPT_CONTROL 0x1D
#define WM9081_DAC_DIGITAL_1 0x1E
#define WM9081_DAC_DIGITAL_2 0x1F
#define WM9081_DRC_1 0x20
#define WM9081_DRC_2 0x21
#define WM9081_DRC_3 0x22
#define WM9081_DRC_4 0x23
#define WM9081_WRITE_SEQUENCER_1 0x26
#define WM9081_WRITE_SEQUENCER_2 0x27
#define WM9081_MW_SLAVE_1 0x28
#define WM9081_EQ_1 0x2A
#define WM9081_EQ_2 0x2B
#define WM9081_EQ_3 0x2C
#define WM9081_EQ_4 0x2D
#define WM9081_EQ_5 0x2E
#define WM9081_EQ_6 0x2F
#define WM9081_EQ_7 0x30
#define WM9081_EQ_8 0x31
#define WM9081_EQ_9 0x32
#define WM9081_EQ_10 0x33
#define WM9081_EQ_11 0x34
#define WM9081_EQ_12 0x35
#define WM9081_EQ_13 0x36
#define WM9081_EQ_14 0x37
#define WM9081_EQ_15 0x38
#define WM9081_EQ_16 0x39
#define WM9081_EQ_17 0x3A
#define WM9081_EQ_18 0x3B
#define WM9081_EQ_19 0x3C
#define WM9081_EQ_20 0x3D
#define WM9081_REGISTER_COUNT 55
#define WM9081_MAX_REGISTER 0x3D
/*
* Field Definitions.
*/
/*
* R0 (0x00) - Software Reset
*/
#define WM9081_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
#define WM9081_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
#define WM9081_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
/*
* R2 (0x02) - Analogue Lineout
*/
#define WM9081_LINEOUT_MUTE 0x0080 /* LINEOUT_MUTE */
#define WM9081_LINEOUT_MUTE_MASK 0x0080 /* LINEOUT_MUTE */
#define WM9081_LINEOUT_MUTE_SHIFT 7 /* LINEOUT_MUTE */
#define WM9081_LINEOUT_MUTE_WIDTH 1 /* LINEOUT_MUTE */
#define WM9081_LINEOUTZC 0x0040 /* LINEOUTZC */
#define WM9081_LINEOUTZC_MASK 0x0040 /* LINEOUTZC */
#define WM9081_LINEOUTZC_SHIFT 6 /* LINEOUTZC */
#define WM9081_LINEOUTZC_WIDTH 1 /* LINEOUTZC */
#define WM9081_LINEOUT_VOL_MASK 0x003F /* LINEOUT_VOL - [5:0] */
#define WM9081_LINEOUT_VOL_SHIFT 0 /* LINEOUT_VOL - [5:0] */
#define WM9081_LINEOUT_VOL_WIDTH 6 /* LINEOUT_VOL - [5:0] */
/*
* R3 (0x03) - Analogue Speaker PGA
*/
#define WM9081_SPKPGA_MUTE 0x0080 /* SPKPGA_MUTE */
#define WM9081_SPKPGA_MUTE_MASK 0x0080 /* SPKPGA_MUTE */
#define WM9081_SPKPGA_MUTE_SHIFT 7 /* SPKPGA_MUTE */
#define WM9081_SPKPGA_MUTE_WIDTH 1 /* SPKPGA_MUTE */
#define WM9081_SPKPGAZC 0x0040 /* SPKPGAZC */
#define WM9081_SPKPGAZC_MASK 0x0040 /* SPKPGAZC */
#define WM9081_SPKPGAZC_SHIFT 6 /* SPKPGAZC */
#define WM9081_SPKPGAZC_WIDTH 1 /* SPKPGAZC */
#define WM9081_SPKPGA_VOL_MASK 0x003F /* SPKPGA_VOL - [5:0] */
#define WM9081_SPKPGA_VOL_SHIFT 0 /* SPKPGA_VOL - [5:0] */
#define WM9081_SPKPGA_VOL_WIDTH 6 /* SPKPGA_VOL - [5:0] */
/*
* R4 (0x04) - VMID Control
*/
#define WM9081_VMID_BUF_ENA 0x0020 /* VMID_BUF_ENA */
#define WM9081_VMID_BUF_ENA_MASK 0x0020 /* VMID_BUF_ENA */
#define WM9081_VMID_BUF_ENA_SHIFT 5 /* VMID_BUF_ENA */
#define WM9081_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
#define WM9081_VMID_RAMP 0x0008 /* VMID_RAMP */
#define WM9081_VMID_RAMP_MASK 0x0008 /* VMID_RAMP */
#define WM9081_VMID_RAMP_SHIFT 3 /* VMID_RAMP */
#define WM9081_VMID_RAMP_WIDTH 1 /* VMID_RAMP */
#define WM9081_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */
#define WM9081_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */
#define WM9081_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */
#define WM9081_VMID_FAST_ST 0x0001 /* VMID_FAST_ST */
#define WM9081_VMID_FAST_ST_MASK 0x0001 /* VMID_FAST_ST */
#define WM9081_VMID_FAST_ST_SHIFT 0 /* VMID_FAST_ST */
#define WM9081_VMID_FAST_ST_WIDTH 1 /* VMID_FAST_ST */
/*
* R5 (0x05) - Bias Control 1
*/
#define WM9081_BIAS_SRC 0x0040 /* BIAS_SRC */
#define WM9081_BIAS_SRC_MASK 0x0040 /* BIAS_SRC */
#define WM9081_BIAS_SRC_SHIFT 6 /* BIAS_SRC */
#define WM9081_BIAS_SRC_WIDTH 1 /* BIAS_SRC */
#define WM9081_STBY_BIAS_LVL 0x0020 /* STBY_BIAS_LVL */
#define WM9081_STBY_BIAS_LVL_MASK 0x0020 /* STBY_BIAS_LVL */
#define WM9081_STBY_BIAS_LVL_SHIFT 5 /* STBY_BIAS_LVL */
#define WM9081_STBY_BIAS_LVL_WIDTH 1 /* STBY_BIAS_LVL */
#define WM9081_STBY_BIAS_ENA 0x0010 /* STBY_BIAS_ENA */
#define WM9081_STBY_BIAS_ENA_MASK 0x0010 /* STBY_BIAS_ENA */
#define WM9081_STBY_BIAS_ENA_SHIFT 4 /* STBY_BIAS_ENA */
#define WM9081_STBY_BIAS_ENA_WIDTH 1 /* STBY_BIAS_ENA */
#define WM9081_BIAS_LVL_MASK 0x000C /* BIAS_LVL - [3:2] */
#define WM9081_BIAS_LVL_SHIFT 2 /* BIAS_LVL - [3:2] */
#define WM9081_BIAS_LVL_WIDTH 2 /* BIAS_LVL - [3:2] */
#define WM9081_BIAS_ENA 0x0002 /* BIAS_ENA */
#define WM9081_BIAS_ENA_MASK 0x0002 /* BIAS_ENA */
#define WM9081_BIAS_ENA_SHIFT 1 /* BIAS_ENA */
#define WM9081_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
#define WM9081_STARTUP_BIAS_ENA 0x0001 /* STARTUP_BIAS_ENA */
#define WM9081_STARTUP_BIAS_ENA_MASK 0x0001 /* STARTUP_BIAS_ENA */
#define WM9081_STARTUP_BIAS_ENA_SHIFT 0 /* STARTUP_BIAS_ENA */
#define WM9081_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
/*
* R7 (0x07) - Analogue Mixer
*/
#define WM9081_DAC_SEL 0x0010 /* DAC_SEL */
#define WM9081_DAC_SEL_MASK 0x0010 /* DAC_SEL */
#define WM9081_DAC_SEL_SHIFT 4 /* DAC_SEL */
#define WM9081_DAC_SEL_WIDTH 1 /* DAC_SEL */
#define WM9081_IN2_VOL 0x0008 /* IN2_VOL */
#define WM9081_IN2_VOL_MASK 0x0008 /* IN2_VOL */
#define WM9081_IN2_VOL_SHIFT 3 /* IN2_VOL */
#define WM9081_IN2_VOL_WIDTH 1 /* IN2_VOL */
#define WM9081_IN2_ENA 0x0004 /* IN2_ENA */
#define WM9081_IN2_ENA_MASK 0x0004 /* IN2_ENA */
#define WM9081_IN2_ENA_SHIFT 2 /* IN2_ENA */
#define WM9081_IN2_ENA_WIDTH 1 /* IN2_ENA */
#define WM9081_IN1_VOL 0x0002 /* IN1_VOL */
#define WM9081_IN1_VOL_MASK 0x0002 /* IN1_VOL */
#define WM9081_IN1_VOL_SHIFT 1 /* IN1_VOL */
#define WM9081_IN1_VOL_WIDTH 1 /* IN1_VOL */
#define WM9081_IN1_ENA 0x0001 /* IN1_ENA */
#define WM9081_IN1_ENA_MASK 0x0001 /* IN1_ENA */
#define WM9081_IN1_ENA_SHIFT 0 /* IN1_ENA */
#define WM9081_IN1_ENA_WIDTH 1 /* IN1_ENA */
/*
* R8 (0x08) - Anti Pop Control
*/
#define WM9081_LINEOUT_DISCH 0x0004 /* LINEOUT_DISCH */
#define WM9081_LINEOUT_DISCH_MASK 0x0004 /* LINEOUT_DISCH */
#define WM9081_LINEOUT_DISCH_SHIFT 2 /* LINEOUT_DISCH */
#define WM9081_LINEOUT_DISCH_WIDTH 1 /* LINEOUT_DISCH */
#define WM9081_LINEOUT_VROI 0x0002 /* LINEOUT_VROI */
#define WM9081_LINEOUT_VROI_MASK 0x0002 /* LINEOUT_VROI */
#define WM9081_LINEOUT_VROI_SHIFT 1 /* LINEOUT_VROI */
#define WM9081_LINEOUT_VROI_WIDTH 1 /* LINEOUT_VROI */
#define WM9081_LINEOUT_CLAMP 0x0001 /* LINEOUT_CLAMP */
#define WM9081_LINEOUT_CLAMP_MASK 0x0001 /* LINEOUT_CLAMP */
#define WM9081_LINEOUT_CLAMP_SHIFT 0 /* LINEOUT_CLAMP */
#define WM9081_LINEOUT_CLAMP_WIDTH 1 /* LINEOUT_CLAMP */
/*
* R9 (0x09) - Analogue Speaker 1
*/
#define WM9081_SPK_DCGAIN_MASK 0x0038 /* SPK_DCGAIN - [5:3] */
#define WM9081_SPK_DCGAIN_SHIFT 3 /* SPK_DCGAIN - [5:3] */
#define WM9081_SPK_DCGAIN_WIDTH 3 /* SPK_DCGAIN - [5:3] */
#define WM9081_SPK_ACGAIN_MASK 0x0007 /* SPK_ACGAIN - [2:0] */
#define WM9081_SPK_ACGAIN_SHIFT 0 /* SPK_ACGAIN - [2:0] */
#define WM9081_SPK_ACGAIN_WIDTH 3 /* SPK_ACGAIN - [2:0] */
/*
* R10 (0x0A) - Analogue Speaker 2
*/
#define WM9081_SPK_MODE 0x0040 /* SPK_MODE */
#define WM9081_SPK_MODE_MASK 0x0040 /* SPK_MODE */
#define WM9081_SPK_MODE_SHIFT 6 /* SPK_MODE */
#define WM9081_SPK_MODE_WIDTH 1 /* SPK_MODE */
#define WM9081_SPK_INV_MUTE 0x0010 /* SPK_INV_MUTE */
#define WM9081_SPK_INV_MUTE_MASK 0x0010 /* SPK_INV_MUTE */
#define WM9081_SPK_INV_MUTE_SHIFT 4 /* SPK_INV_MUTE */
#define WM9081_SPK_INV_MUTE_WIDTH 1 /* SPK_INV_MUTE */
#define WM9081_OUT_SPK_CTRL 0x0008 /* OUT_SPK_CTRL */
#define WM9081_OUT_SPK_CTRL_MASK 0x0008 /* OUT_SPK_CTRL */
#define WM9081_OUT_SPK_CTRL_SHIFT 3 /* OUT_SPK_CTRL */
#define WM9081_OUT_SPK_CTRL_WIDTH 1 /* OUT_SPK_CTRL */
/*
* R11 (0x0B) - Power Management
*/
#define WM9081_TSHUT_ENA 0x0100 /* TSHUT_ENA */
#define WM9081_TSHUT_ENA_MASK 0x0100 /* TSHUT_ENA */
#define WM9081_TSHUT_ENA_SHIFT 8 /* TSHUT_ENA */
#define WM9081_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
#define WM9081_TSENSE_ENA 0x0080 /* TSENSE_ENA */
#define WM9081_TSENSE_ENA_MASK 0x0080 /* TSENSE_ENA */
#define WM9081_TSENSE_ENA_SHIFT 7 /* TSENSE_ENA */
#define WM9081_TSENSE_ENA_WIDTH 1 /* TSENSE_ENA */
#define WM9081_TEMP_SHUT 0x0040 /* TEMP_SHUT */
#define WM9081_TEMP_SHUT_MASK 0x0040 /* TEMP_SHUT */
#define WM9081_TEMP_SHUT_SHIFT 6 /* TEMP_SHUT */
#define WM9081_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */
#define WM9081_LINEOUT_ENA 0x0010 /* LINEOUT_ENA */
#define WM9081_LINEOUT_ENA_MASK 0x0010 /* LINEOUT_ENA */
#define WM9081_LINEOUT_ENA_SHIFT 4 /* LINEOUT_ENA */
#define WM9081_LINEOUT_ENA_WIDTH 1 /* LINEOUT_ENA */
#define WM9081_SPKPGA_ENA 0x0004 /* SPKPGA_ENA */
#define WM9081_SPKPGA_ENA_MASK 0x0004 /* SPKPGA_ENA */
#define WM9081_SPKPGA_ENA_SHIFT 2 /* SPKPGA_ENA */
#define WM9081_SPKPGA_ENA_WIDTH 1 /* SPKPGA_ENA */
#define WM9081_SPK_ENA 0x0002 /* SPK_ENA */
#define WM9081_SPK_ENA_MASK 0x0002 /* SPK_ENA */
#define WM9081_SPK_ENA_SHIFT 1 /* SPK_ENA */
#define WM9081_SPK_ENA_WIDTH 1 /* SPK_ENA */
#define WM9081_DAC_ENA 0x0001 /* DAC_ENA */
#define WM9081_DAC_ENA_MASK 0x0001 /* DAC_ENA */
#define WM9081_DAC_ENA_SHIFT 0 /* DAC_ENA */
#define WM9081_DAC_ENA_WIDTH 1 /* DAC_ENA */
/*
* R12 (0x0C) - Clock Control 1
*/
#define WM9081_CLK_OP_DIV_MASK 0x1C00 /* CLK_OP_DIV - [12:10] */
#define WM9081_CLK_OP_DIV_SHIFT 10 /* CLK_OP_DIV - [12:10] */
#define WM9081_CLK_OP_DIV_WIDTH 3 /* CLK_OP_DIV - [12:10] */
#define WM9081_CLK_TO_DIV_MASK 0x0300 /* CLK_TO_DIV - [9:8] */
#define WM9081_CLK_TO_DIV_SHIFT 8 /* CLK_TO_DIV - [9:8] */
#define WM9081_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [9:8] */
#define WM9081_MCLKDIV2 0x0080 /* MCLKDIV2 */
#define WM9081_MCLKDIV2_MASK 0x0080 /* MCLKDIV2 */
#define WM9081_MCLKDIV2_SHIFT 7 /* MCLKDIV2 */
#define WM9081_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */
/*
* R13 (0x0D) - Clock Control 2
*/
#define WM9081_CLK_SYS_RATE_MASK 0x00F0 /* CLK_SYS_RATE - [7:4] */
#define WM9081_CLK_SYS_RATE_SHIFT 4 /* CLK_SYS_RATE - [7:4] */
#define WM9081_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [7:4] */
#define WM9081_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */
#define WM9081_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */
#define WM9081_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */
/*
* R14 (0x0E) - Clock Control 3
*/
#define WM9081_CLK_SRC_SEL 0x2000 /* CLK_SRC_SEL */
#define WM9081_CLK_SRC_SEL_MASK 0x2000 /* CLK_SRC_SEL */
#define WM9081_CLK_SRC_SEL_SHIFT 13 /* CLK_SRC_SEL */
#define WM9081_CLK_SRC_SEL_WIDTH 1 /* CLK_SRC_SEL */
#define WM9081_CLK_OP_ENA 0x0020 /* CLK_OP_ENA */
#define WM9081_CLK_OP_ENA_MASK 0x0020 /* CLK_OP_ENA */
#define WM9081_CLK_OP_ENA_SHIFT 5 /* CLK_OP_ENA */
#define WM9081_CLK_OP_ENA_WIDTH 1 /* CLK_OP_ENA */
#define WM9081_CLK_TO_ENA 0x0004 /* CLK_TO_ENA */
#define WM9081_CLK_TO_ENA_MASK 0x0004 /* CLK_TO_ENA */
#define WM9081_CLK_TO_ENA_SHIFT 2 /* CLK_TO_ENA */
#define WM9081_CLK_TO_ENA_WIDTH 1 /* CLK_TO_ENA */
#define WM9081_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */
#define WM9081_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */
#define WM9081_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */
#define WM9081_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
#define WM9081_CLK_SYS_ENA 0x0001 /* CLK_SYS_ENA */
#define WM9081_CLK_SYS_ENA_MASK 0x0001 /* CLK_SYS_ENA */
#define WM9081_CLK_SYS_ENA_SHIFT 0 /* CLK_SYS_ENA */
#define WM9081_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
/*
* R16 (0x10) - FLL Control 1
*/
#define WM9081_FLL_HOLD 0x0008 /* FLL_HOLD */
#define WM9081_FLL_HOLD_MASK 0x0008 /* FLL_HOLD */
#define WM9081_FLL_HOLD_SHIFT 3 /* FLL_HOLD */
#define WM9081_FLL_HOLD_WIDTH 1 /* FLL_HOLD */
#define WM9081_FLL_FRAC 0x0004 /* FLL_FRAC */
#define WM9081_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
#define WM9081_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
#define WM9081_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
#define WM9081_FLL_ENA 0x0001 /* FLL_ENA */
#define WM9081_FLL_ENA_MASK 0x0001 /* FLL_ENA */
#define WM9081_FLL_ENA_SHIFT 0 /* FLL_ENA */
#define WM9081_FLL_ENA_WIDTH 1 /* FLL_ENA */
/*
* R17 (0x11) - FLL Control 2
*/
#define WM9081_FLL_OUTDIV_MASK 0x0700 /* FLL_OUTDIV - [10:8] */
#define WM9081_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [10:8] */
#define WM9081_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [10:8] */
#define WM9081_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
#define WM9081_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
#define WM9081_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
#define WM9081_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
#define WM9081_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
#define WM9081_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
/*
* R18 (0x12) - FLL Control 3
*/
#define WM9081_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
#define WM9081_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
#define WM9081_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
/*
* R19 (0x13) - FLL Control 4
*/
#define WM9081_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
#define WM9081_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
#define WM9081_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
#define WM9081_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
#define WM9081_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
#define WM9081_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
/*
* R20 (0x14) - FLL Control 5
*/
#define WM9081_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
#define WM9081_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
#define WM9081_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
#define WM9081_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
#define WM9081_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
#define WM9081_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
/*
* R22 (0x16) - Audio Interface 1
*/
#define WM9081_AIFDAC_CHAN 0x0040 /* AIFDAC_CHAN */
#define WM9081_AIFDAC_CHAN_MASK 0x0040 /* AIFDAC_CHAN */
#define WM9081_AIFDAC_CHAN_SHIFT 6 /* AIFDAC_CHAN */
#define WM9081_AIFDAC_CHAN_WIDTH 1 /* AIFDAC_CHAN */
#define WM9081_AIFDAC_TDM_SLOT_MASK 0x0030 /* AIFDAC_TDM_SLOT - [5:4] */
#define WM9081_AIFDAC_TDM_SLOT_SHIFT 4 /* AIFDAC_TDM_SLOT - [5:4] */
#define WM9081_AIFDAC_TDM_SLOT_WIDTH 2 /* AIFDAC_TDM_SLOT - [5:4] */
#define WM9081_AIFDAC_TDM_MODE_MASK 0x000C /* AIFDAC_TDM_MODE - [3:2] */
#define WM9081_AIFDAC_TDM_MODE_SHIFT 2 /* AIFDAC_TDM_MODE - [3:2] */
#define WM9081_AIFDAC_TDM_MODE_WIDTH 2 /* AIFDAC_TDM_MODE - [3:2] */
#define WM9081_DAC_COMP 0x0002 /* DAC_COMP */
#define WM9081_DAC_COMP_MASK 0x0002 /* DAC_COMP */
#define WM9081_DAC_COMP_SHIFT 1 /* DAC_COMP */
#define WM9081_DAC_COMP_WIDTH 1 /* DAC_COMP */
#define WM9081_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */
#define WM9081_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */
#define WM9081_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */
#define WM9081_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
/*
* R23 (0x17) - Audio Interface 2
*/
#define WM9081_AIF_TRIS 0x0200 /* AIF_TRIS */
#define WM9081_AIF_TRIS_MASK 0x0200 /* AIF_TRIS */
#define WM9081_AIF_TRIS_SHIFT 9 /* AIF_TRIS */
#define WM9081_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
#define WM9081_DAC_DAT_INV 0x0100 /* DAC_DAT_INV */
#define WM9081_DAC_DAT_INV_MASK 0x0100 /* DAC_DAT_INV */
#define WM9081_DAC_DAT_INV_SHIFT 8 /* DAC_DAT_INV */
#define WM9081_DAC_DAT_INV_WIDTH 1 /* DAC_DAT_INV */
#define WM9081_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */
#define WM9081_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */
#define WM9081_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */
#define WM9081_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
#define WM9081_BCLK_DIR 0x0040 /* BCLK_DIR */
#define WM9081_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */
#define WM9081_BCLK_DIR_SHIFT 6 /* BCLK_DIR */
#define WM9081_BCLK_DIR_WIDTH 1 /* BCLK_DIR */
#define WM9081_LRCLK_DIR 0x0020 /* LRCLK_DIR */
#define WM9081_LRCLK_DIR_MASK 0x0020 /* LRCLK_DIR */
#define WM9081_LRCLK_DIR_SHIFT 5 /* LRCLK_DIR */
#define WM9081_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */
#define WM9081_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */
#define WM9081_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */
#define WM9081_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */
#define WM9081_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
#define WM9081_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */
#define WM9081_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */
#define WM9081_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */
#define WM9081_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */
#define WM9081_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */
#define WM9081_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */
/*
* R24 (0x18) - Audio Interface 3
*/
#define WM9081_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */
#define WM9081_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */
#define WM9081_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */
/*
* R25 (0x19) - Audio Interface 4
*/
#define WM9081_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */
#define WM9081_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */
#define WM9081_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */
/*
* R26 (0x1A) - Interrupt Status
*/
#define WM9081_WSEQ_BUSY_EINT 0x0004 /* WSEQ_BUSY_EINT */
#define WM9081_WSEQ_BUSY_EINT_MASK 0x0004 /* WSEQ_BUSY_EINT */
#define WM9081_WSEQ_BUSY_EINT_SHIFT 2 /* WSEQ_BUSY_EINT */
#define WM9081_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */
#define WM9081_TSHUT_EINT 0x0001 /* TSHUT_EINT */
#define WM9081_TSHUT_EINT_MASK 0x0001 /* TSHUT_EINT */
#define WM9081_TSHUT_EINT_SHIFT 0 /* TSHUT_EINT */
#define WM9081_TSHUT_EINT_WIDTH 1 /* TSHUT_EINT */
/*
* R27 (0x1B) - Interrupt Status Mask
*/
#define WM9081_IM_WSEQ_BUSY_EINT 0x0004 /* IM_WSEQ_BUSY_EINT */
#define WM9081_IM_WSEQ_BUSY_EINT_MASK 0x0004 /* IM_WSEQ_BUSY_EINT */
#define WM9081_IM_WSEQ_BUSY_EINT_SHIFT 2 /* IM_WSEQ_BUSY_EINT */
#define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */
#define WM9081_IM_TSHUT_EINT 0x0001 /* IM_TSHUT_EINT */
#define WM9081_IM_TSHUT_EINT_MASK 0x0001 /* IM_TSHUT_EINT */
#define WM9081_IM_TSHUT_EINT_SHIFT 0 /* IM_TSHUT_EINT */
#define WM9081_IM_TSHUT_EINT_WIDTH 1 /* IM_TSHUT_EINT */
/*
* R28 (0x1C) - Interrupt Polarity
*/
#define WM9081_TSHUT_INV 0x0001 /* TSHUT_INV */
#define WM9081_TSHUT_INV_MASK 0x0001 /* TSHUT_INV */
#define WM9081_TSHUT_INV_SHIFT 0 /* TSHUT_INV */
#define WM9081_TSHUT_INV_WIDTH 1 /* TSHUT_INV */
/*
* R29 (0x1D) - Interrupt Control
*/
#define WM9081_IRQ_POL 0x8000 /* IRQ_POL */
#define WM9081_IRQ_POL_MASK 0x8000 /* IRQ_POL */
#define WM9081_IRQ_POL_SHIFT 15 /* IRQ_POL */
#define WM9081_IRQ_POL_WIDTH 1 /* IRQ_POL */
#define WM9081_IRQ_OP_CTRL 0x0001 /* IRQ_OP_CTRL */
#define WM9081_IRQ_OP_CTRL_MASK 0x0001 /* IRQ_OP_CTRL */
#define WM9081_IRQ_OP_CTRL_SHIFT 0 /* IRQ_OP_CTRL */
#define WM9081_IRQ_OP_CTRL_WIDTH 1 /* IRQ_OP_CTRL */
/*
* R30 (0x1E) - DAC Digital 1
*/
#define WM9081_DAC_VOL_MASK 0x00FF /* DAC_VOL - [7:0] */
#define WM9081_DAC_VOL_SHIFT 0 /* DAC_VOL - [7:0] */
#define WM9081_DAC_VOL_WIDTH 8 /* DAC_VOL - [7:0] */
/*
* R31 (0x1F) - DAC Digital 2
*/
#define WM9081_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */
#define WM9081_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */
#define WM9081_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */
#define WM9081_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
#define WM9081_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */
#define WM9081_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */
#define WM9081_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */
#define WM9081_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
#define WM9081_DAC_MUTE 0x0008 /* DAC_MUTE */
#define WM9081_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */
#define WM9081_DAC_MUTE_SHIFT 3 /* DAC_MUTE */
#define WM9081_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
#define WM9081_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
#define WM9081_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
#define WM9081_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
/*
* R32 (0x20) - DRC 1
*/
#define WM9081_DRC_ENA 0x8000 /* DRC_ENA */
#define WM9081_DRC_ENA_MASK 0x8000 /* DRC_ENA */
#define WM9081_DRC_ENA_SHIFT 15 /* DRC_ENA */
#define WM9081_DRC_ENA_WIDTH 1 /* DRC_ENA */
#define WM9081_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */
#define WM9081_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */
#define WM9081_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */
#define WM9081_DRC_FF_DLY 0x0020 /* DRC_FF_DLY */
#define WM9081_DRC_FF_DLY_MASK 0x0020 /* DRC_FF_DLY */
#define WM9081_DRC_FF_DLY_SHIFT 5 /* DRC_FF_DLY */
#define WM9081_DRC_FF_DLY_WIDTH 1 /* DRC_FF_DLY */
#define WM9081_DRC_QR 0x0004 /* DRC_QR */
#define WM9081_DRC_QR_MASK 0x0004 /* DRC_QR */
#define WM9081_DRC_QR_SHIFT 2 /* DRC_QR */
#define WM9081_DRC_QR_WIDTH 1 /* DRC_QR */
#define WM9081_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */
#define WM9081_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */
#define WM9081_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */
#define WM9081_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
/*
* R33 (0x21) - DRC 2
*/
#define WM9081_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */
#define WM9081_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */
#define WM9081_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */
#define WM9081_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */
#define WM9081_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */
#define WM9081_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */
#define WM9081_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */
#define WM9081_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */
#define WM9081_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */
#define WM9081_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */
#define WM9081_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */
#define WM9081_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */
#define WM9081_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */
#define WM9081_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */
#define WM9081_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */
#define WM9081_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
#define WM9081_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
#define WM9081_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
/*
* R34 (0x22) - DRC 3
*/
#define WM9081_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
#define WM9081_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
#define WM9081_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
#define WM9081_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
#define WM9081_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
#define WM9081_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
/*
* R35 (0x23) - DRC 4
*/
#define WM9081_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
#define WM9081_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
#define WM9081_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
#define WM9081_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
#define WM9081_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
#define WM9081_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
/*
* R38 (0x26) - Write Sequencer 1
*/
#define WM9081_WSEQ_ENA 0x8000 /* WSEQ_ENA */
#define WM9081_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
#define WM9081_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
#define WM9081_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
#define WM9081_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
#define WM9081_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
#define WM9081_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
#define WM9081_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
#define WM9081_WSEQ_START 0x0100 /* WSEQ_START */
#define WM9081_WSEQ_START_MASK 0x0100 /* WSEQ_START */
#define WM9081_WSEQ_START_SHIFT 8 /* WSEQ_START */
#define WM9081_WSEQ_START_WIDTH 1 /* WSEQ_START */
#define WM9081_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
#define WM9081_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
#define WM9081_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
/*
* R39 (0x27) - Write Sequencer 2
*/
#define WM9081_WSEQ_CURRENT_INDEX_MASK 0x07F0 /* WSEQ_CURRENT_INDEX - [10:4] */
#define WM9081_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [10:4] */
#define WM9081_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [10:4] */
#define WM9081_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
#define WM9081_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
#define WM9081_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
#define WM9081_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
/*
* R40 (0x28) - MW Slave 1
*/
#define WM9081_SPI_CFG 0x0020 /* SPI_CFG */
#define WM9081_SPI_CFG_MASK 0x0020 /* SPI_CFG */
#define WM9081_SPI_CFG_SHIFT 5 /* SPI_CFG */
#define WM9081_SPI_CFG_WIDTH 1 /* SPI_CFG */
#define WM9081_SPI_4WIRE 0x0010 /* SPI_4WIRE */
#define WM9081_SPI_4WIRE_MASK 0x0010 /* SPI_4WIRE */
#define WM9081_SPI_4WIRE_SHIFT 4 /* SPI_4WIRE */
#define WM9081_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
#define WM9081_ARA_ENA 0x0008 /* ARA_ENA */
#define WM9081_ARA_ENA_MASK 0x0008 /* ARA_ENA */
#define WM9081_ARA_ENA_SHIFT 3 /* ARA_ENA */
#define WM9081_ARA_ENA_WIDTH 1 /* ARA_ENA */
#define WM9081_AUTO_INC 0x0002 /* AUTO_INC */
#define WM9081_AUTO_INC_MASK 0x0002 /* AUTO_INC */
#define WM9081_AUTO_INC_SHIFT 1 /* AUTO_INC */
#define WM9081_AUTO_INC_WIDTH 1 /* AUTO_INC */
/*
* R42 (0x2A) - EQ 1
*/
#define WM9081_EQ_B1_GAIN_MASK 0xF800 /* EQ_B1_GAIN - [15:11] */
#define WM9081_EQ_B1_GAIN_SHIFT 11 /* EQ_B1_GAIN - [15:11] */
#define WM9081_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [15:11] */
#define WM9081_EQ_B2_GAIN_MASK 0x07C0 /* EQ_B2_GAIN - [10:6] */
#define WM9081_EQ_B2_GAIN_SHIFT 6 /* EQ_B2_GAIN - [10:6] */
#define WM9081_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [10:6] */
#define WM9081_EQ_B4_GAIN_MASK 0x003E /* EQ_B4_GAIN - [5:1] */
#define WM9081_EQ_B4_GAIN_SHIFT 1 /* EQ_B4_GAIN - [5:1] */
#define WM9081_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [5:1] */
#define WM9081_EQ_ENA 0x0001 /* EQ_ENA */
#define WM9081_EQ_ENA_MASK 0x0001 /* EQ_ENA */
#define WM9081_EQ_ENA_SHIFT 0 /* EQ_ENA */
#define WM9081_EQ_ENA_WIDTH 1 /* EQ_ENA */
/*
* R43 (0x2B) - EQ 2
*/
#define WM9081_EQ_B3_GAIN_MASK 0xF800 /* EQ_B3_GAIN - [15:11] */
#define WM9081_EQ_B3_GAIN_SHIFT 11 /* EQ_B3_GAIN - [15:11] */
#define WM9081_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [15:11] */
#define WM9081_EQ_B5_GAIN_MASK 0x07C0 /* EQ_B5_GAIN - [10:6] */
#define WM9081_EQ_B5_GAIN_SHIFT 6 /* EQ_B5_GAIN - [10:6] */
#define WM9081_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [10:6] */
/*
* R44 (0x2C) - EQ 3
*/
#define WM9081_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */
#define WM9081_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */
#define WM9081_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */
/*
* R45 (0x2D) - EQ 4
*/
#define WM9081_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */
#define WM9081_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */
#define WM9081_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */
/*
* R46 (0x2E) - EQ 5
*/
#define WM9081_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */
#define WM9081_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */
#define WM9081_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */
/*
* R47 (0x2F) - EQ 6
*/
#define WM9081_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */
#define WM9081_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */
#define WM9081_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */
/*
* R48 (0x30) - EQ 7
*/
#define WM9081_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */
#define WM9081_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */
#define WM9081_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */
/*
* R49 (0x31) - EQ 8
*/
#define WM9081_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */
#define WM9081_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */
#define WM9081_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */
/*
* R50 (0x32) - EQ 9
*/
#define WM9081_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */
#define WM9081_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */
#define WM9081_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */
/*
* R51 (0x33) - EQ 10
*/
#define WM9081_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */
#define WM9081_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */
#define WM9081_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */
/*
* R52 (0x34) - EQ 11
*/
#define WM9081_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */
#define WM9081_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */
#define WM9081_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */
/*
* R53 (0x35) - EQ 12
*/
#define WM9081_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */
#define WM9081_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */
#define WM9081_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */
/*
* R54 (0x36) - EQ 13
*/
#define WM9081_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */
#define WM9081_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */
#define WM9081_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */
/*
* R55 (0x37) - EQ 14
*/
#define WM9081_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */
#define WM9081_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */
#define WM9081_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */
/*
* R56 (0x38) - EQ 15
*/
#define WM9081_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */
#define WM9081_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */
#define WM9081_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */
/*
* R57 (0x39) - EQ 16
*/
#define WM9081_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */
#define WM9081_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */
#define WM9081_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */
/*
* R58 (0x3A) - EQ 17
*/
#define WM9081_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */
#define WM9081_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */
#define WM9081_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */
/*
* R59 (0x3B) - EQ 18
*/
#define WM9081_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */
#define WM9081_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */
#define WM9081_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */
/*
* R60 (0x3C) - EQ 19
*/
#define WM9081_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */
#define WM9081_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */
#define WM9081_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */
/*
* R61 (0x3D) - EQ 20
*/
#define WM9081_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */
#define WM9081_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */
#define WM9081_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */
#endif
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