Commit 87b2b8f5 authored by David S. Miller's avatar David S. Miller

Merge davem@nuts.davemloft.net:/disk1/BK/tg3-2.6

into kernel.bkbits.net:/home/davem/tg3-2.6
parents 004a3668 91de7e2c
This diff is collapsed.
/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $ /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
* tg3.h: Definitions for Broadcom Tigon3 ethernet driver. * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
* *
* Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
* Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
* Copyright (C) 2004 Sun Microsystems Inc.
*/ */
#ifndef _T3_H #ifndef _T3_H
...@@ -116,6 +117,7 @@ ...@@ -116,6 +117,7 @@
#define CHIPREV_ID_5704_A0 0x2000 #define CHIPREV_ID_5704_A0 0x2000
#define CHIPREV_ID_5704_A1 0x2001 #define CHIPREV_ID_5704_A1 0x2001
#define CHIPREV_ID_5704_A2 0x2002 #define CHIPREV_ID_5704_A2 0x2002
#define CHIPREV_ID_5704_A3 0x2003
#define CHIPREV_ID_5705_A0 0x3000 #define CHIPREV_ID_5705_A0 0x3000
#define CHIPREV_ID_5705_A1 0x3001 #define CHIPREV_ID_5705_A1 0x3001
#define CHIPREV_ID_5705_A2 0x3002 #define CHIPREV_ID_5705_A2 0x3002
...@@ -518,8 +520,50 @@ ...@@ -518,8 +520,50 @@
#define MAC_EXTADDR_11_HIGH 0x00000588 #define MAC_EXTADDR_11_HIGH 0x00000588
#define MAC_EXTADDR_11_LOW 0x0000058c #define MAC_EXTADDR_11_LOW 0x0000058c
#define MAC_SERDES_CFG 0x00000590 #define MAC_SERDES_CFG 0x00000590
#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
#define MAC_SERDES_STAT 0x00000594 #define MAC_SERDES_STAT 0x00000594
/* 0x598 --> 0x600 unused */ /* 0x598 --> 0x5b0 unused */
#define SG_DIG_CTRL 0x000005b0
#define SG_DIG_USING_HW_AUTONEG 0x80000000
#define SG_DIG_SOFT_RESET 0x40000000
#define SG_DIG_DISABLE_LINKRDY 0x20000000
#define SG_DIG_CRC16_CLEAR_N 0x01000000
#define SG_DIG_EN10B 0x00800000
#define SG_DIG_CLEAR_STATUS 0x00400000
#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
#define SG_DIG_LOCAL_LINK_STATUS 0x00100000
#define SG_DIG_SPEED_STATUS_MASK 0x000c0000
#define SG_DIG_SPEED_STATUS_SHIFT 18
#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
#define SG_DIG_RESTART_AUTONEG 0x00010000
#define SG_DIG_FIBER_MODE 0x00008000
#define SG_DIG_REMOTE_FAULT_MASK 0x00006000
#define SG_DIG_PAUSE_MASK 0x00001800
#define SG_DIG_GBIC_ENABLE 0x00000400
#define SG_DIG_CHECK_END_ENABLE 0x00000200
#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
#define SG_DIG_GMII_INPUT_SELECT 0x00000040
#define SG_DIG_MRADV_CRC16_SELECT 0x00000020
#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
#define SG_DIG_REMOTE_LOOPBACK 0x00000002
#define SG_DIG_LOOPBACK 0x00000001
#define SG_DIG_STATUS 0x000005b4
#define SG_DIG_CRC16_BUS_MASK 0xffff0000
#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
#define SG_DIG_COMMA_DETECTOR 0x00000008
#define SG_DIG_MAC_ACK_STATUS 0x00000004
#define SG_DIG_AUTONEG_COMPLETE 0x00000002
#define SG_DIG_AUTONEG_ERROR 0x00000001
/* 0x5b8 --> 0x600 unused */
#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
/* 0x624 --> 0x800 unused */ /* 0x624 --> 0x800 unused */
...@@ -2044,6 +2088,7 @@ struct tg3 { ...@@ -2044,6 +2088,7 @@ struct tg3 {
#define TG3_FLG2_PHY_BER_BUG 0x00000100 #define TG3_FLG2_PHY_BER_BUG 0x00000100
#define TG3_FLG2_PCI_EXPRESS 0x00000200 #define TG3_FLG2_PCI_EXPRESS 0x00000200
#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400 #define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
#define TG3_FLG2_HW_AUTONEG 0x00000800
u32 split_mode_max_reqs; u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3 #define SPLIT_MODE_5704_MAX_REQ 3
......
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