Commit 88010b81 authored by Oleksij Rempel's avatar Oleksij Rempel Committed by Shawn Guo

ARM: dts: add Protonic WD2 board

Add support for the Protonic WD2 board, which is an internal development
platform for low-cost agricultural Virtual Terminals based on COTS tablets
and web applications.
It inherits from the PRTI6Q base class.
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarDavid Jander <david@protonic.nl>
Signed-off-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 0d446a50
...@@ -544,6 +544,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ ...@@ -544,6 +544,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-pico-pi.dtb \ imx6q-pico-pi.dtb \
imx6q-pistachio.dtb \ imx6q-pistachio.dtb \
imx6q-prti6q.dtb \ imx6q-prti6q.dtb \
imx6q-prtwd2.dtb \
imx6q-rex-pro.dtb \ imx6q-rex-pro.dtb \
imx6q-sabreauto.dtb \ imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \ imx6q-sabrelite.dtb \
......
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2018 Protonic Holland
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-prti6q.dtsi"
#include <dt-bindings/leds/common.h>
/ {
model = "Protonic WD2 board";
compatible = "prt,prtwd2", "fsl,imx6q";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_npd>;
reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
};
/* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */
i2c@4 {
compatible = "i2c-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
i2c-gpio,delay-us = <20>; /* ~10 kHz */
i2c-gpio,scl-output-only;
#address-cells = <1>;
#size-cells = <0>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>;
clock-names = "ipg", "ahb";
status = "okay";
fixed-link {
speed = <100>;
pause;
full-duplex;
};
};
&i2c3 {
adc@49 {
compatible = "ti,ads1015";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
/* V in */
channel@4 {
reg = <4>;
ti,gain = <1>;
ti,datarate = <3>;
};
/* I charge */
channel@5 {
reg = <5>;
ti,gain = <1>;
ti,datarate = <3>;
};
/* V bus */
channel@6 {
reg = <6>;
ti,gain = <1>;
ti,datarate = <3>;
};
/* nc */
channel@7 {
reg = <7>;
ti,gain = <1>;
ti,datarate = <3>;
};
};
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_eth_chg>;
pinctrl_can1phy: can1phy {
fsl,pins = <
/* CAN1_SR */
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
/* MX6QDL_ENET_PINGRP4 */
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x130b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
/* Phy reset */
MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0
/* nINTRP */
MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1f8b0
MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f8b0
>;
};
pinctrl_usb_eth_chg: usbethchggrp {
fsl,pins = <
/* USB charging control */
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
pinctrl_wifi_npd: wifinpd {
fsl,pins = <
/* WL_REG_ON */
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069
>;
};
};
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