[PATCH] ppc32: PPC4xx cleanup

From: Matt Porter <mporter@kernel.crashing.org> The following patch removes some obsolete PPC4xx platforms that Paul and I have discussed and some minor cleanup.

[PATCH] ppc32: PPC4xx cleanup
From: Matt Porter <mporter@kernel.crashing.org> The following patch removes some obsolete PPC4xx platforms that Paul and I have discussed and some minor cleanup.
889043f6 · Andrew Morton · Linus Torvalds · cec6721d · 889043f6 · 889043f6
Commit 889043f6 authored Feb 12, 2004 by Andrew Morton Committed by Linus Torvalds Feb 12, 2004
19 changed files
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -13,48 +13,43 @@ choice
 config ASH
 	bool "Ash"
+	help
-config BEECH
+	  This option enables support for the IBM NP405H evaluation board.
-	bool "Beech"
-config CEDAR
-	bool "Cedar"
 config CPCI405
 	bool "CPCI405"
+	help
+	  This option enables support for the CPCI405 board.
 config EP405
 	bool "EP405/EP405PC"
+	help
+	  This option enables support for the EP405/EP405PC boards.
 config OAK
 	bool "Oak"
 	help
-	  Select Oak if you have an IBM 403GCX "Oak" Evaluation Board.
+	  This option enables support for the IBM 403GCX evaluation board.
-	  Select Walnut if you have an IBM 405GP "Walnut" Evaluation Board.
-	  More information on these boards is available at:
-	  <http://www.chips.ibm.com/products/powerpc/tools/evk_pn.html#GCX>.
-config REDWOOD_4
-	bool "Redwood-4"
 config REDWOOD_5
 	bool "Redwood-5"
+	help
+	  This option enables support for the IBM STB04 evaluation board.
 config REDWOOD_6
 	bool "Redwood-6"
+	help
+	  This option enables support for the IBM STBx25xx evaluation board.
 config SYCAMORE
 	bool "Sycamore"
+	help
-config TIVO
+	  This option enables support for the IBM PPC405GPr evaluation board.
-	bool "Tivo"
 config WALNUT
 	bool "Walnut"
 	help
-	  Select Walnut if you have an IBM 405GP "Walnut" Evaluation Board.
+	  This option enables support for the IBM PPC405GP evaluation board.
 endchoice
@@ -120,12 +115,6 @@ config IBM405_ERR51
 	depends on 40x && !405GPR
 	default y
-config PIN_TLB
-	bool
-	depends on 44x
-	default y
 config BOOKE
 	bool
 	depends on 44x
@@ -133,7 +122,7 @@ config BOOKE
 config IBM_OCP
 	bool
-	depends on ASH || BEECH || CEDAR || CPCI405 || EBONY || EP405 || OCOTEA || REDWOOD_4 || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
+	depends on ASH || CPCI405 || EBONY || EP405 || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
 	default y
 config IBM_EMAC4
@@ -141,19 +130,14 @@ config IBM_EMAC4
 	depends on 440GX
 	default y
-config NP405L
-	bool
-	depends on CEDAR
-	default y
 config BIOS_FIXUP
 	bool
-	depends on CEDAR || EP405 || SYCAMORE || WALNUT
+	depends on EP405 || SYCAMORE || WALNUT
 	default y
 config 403GCX
 	bool
-	depends OAK || TIVO
+	depends OAK
 	default y
 config 405GP
@@ -165,13 +149,9 @@ config 405GPR
 	bool
 	depends on SYCAMORE
-config 405LP
-	bool
-	depends on CEDAR
 config STB03xxx
 	bool
-	depends on REDWOOD_5 || REDWOOD_4 || REDWOOD_6
+	depends on REDWOOD_5 || REDWOOD_6
 	default y
 config EMBEDDEDBOOT
@@ -181,13 +161,9 @@ config EMBEDDEDBOOT
 config IBM_OPENBIOS
 	bool
-	depends on ASH || BEECH || CEDAR || REDWOOD_4 || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
+	depends on ASH || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
 	default y
-config 405_DMA
-	bool "Blue Logic DMA"
-	depends on 40x
 config PM
 	bool "Power Management support (EXPERIMENTAL)"
 	depends on 4xx && EXPERIMENTAL

--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -2,27 +2,20 @@
 # Makefile for the PowerPC 4xx linux kernel.
 obj-$(CONFIG_ASH)		+= ash.o
-obj-$(CONFIG_BEECH)		+= beech.o
-obj-$(CONFIG_CEDAR)		+= cedar.o
 obj-$(CONFIG_CPCI405)		+= cpci405.o
 obj-$(CONFIG_EBONY)		+= ebony.o
 obj-$(CONFIG_EP405)		+= ep405.o
 obj-$(CONFIG_OAK)		+= oak.o
 obj-$(CONFIG_OCOTEA)		+= ocotea.o
-obj-$(CONFIG_REDWOOD_4)		+= redwood.o
 obj-$(CONFIG_REDWOOD_5)		+= redwood5.o
 obj-$(CONFIG_REDWOOD_6)		+= redwood6.o
 obj-$(CONFIG_SYCAMORE)		+= sycamore.o
 obj-$(CONFIG_WALNUT)		+= walnut.o
-obj-$(CONFIG_NP405L)		+= ibmnp405l.o
 obj-$(CONFIG_405GP)		+= ibm405gp.o
-obj-$(CONFIG_REDWOOD_4)		+= ibmstb3.o
 obj-$(CONFIG_REDWOOD_5)		+= ibmstb4.o
 obj-$(CONFIG_NP405H)		+= ibmnp405h.o
 obj-$(CONFIG_REDWOOD_6)		+= ibmstbx25.o
-obj-$(CONFIG_NP4GS3)		+= ibmnp4gs.o
-obj-$(CONFIG_405LP)		+= ibm405lp.o
 obj-$(CONFIG_EBONY)		+= ibm440gp.o
 obj-$(CONFIG_OCOTEA)		+= ibm440gx.o
 obj-$(CONFIG_405GPR)		+= ibm405gpr.o
--- a/arch/ppc/platforms/4xx/beech.c
+++ b/arch/ppc/platforms/4xx/beech.c
-/*
- * arch/ppc/platforms/beech.c  Platform setup for the IBM Beech board
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Copyright (C) 2002, International Business Machines Corporation
- * All Rights Reserved
- *
- * Bishop Brock
- * IBM Research, Austin Center for Low-Power Computing
- * bcbrock@us.ibm.com
- * March, 2002
- *
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/param.h>
-#include <linux/rtc.h>
-#include <linux/string.h>
-#include <asm/delay.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-static void beech_ebc_setup(void);
-static void beech_fpga_setup(void);
-/*
-   Beech board physical memory map:
-   Main Memory (Initialized by the BIOS)
-   =======================================================================
-   SDRAM (64 MB)     0x00000000 - 0x04000000
-   OPB Space: (Mapped virtual = physical in ppc4xx_setup.c)
-   =======================================================================
-   UART0               	      0xEF600300
-   UART1               	      0xEF600400
-   IIC                 	      0xEF600500
-   OPB Arbiter         	      0xEF600600
-   GPIO Controller     	      0xEF600700
-   CODEC Interface            0xEF600900
-   Touch Panel Controller     0xEF600A00
-   DES Controller             0xEF600B00
-   EBC Space: (Mapped virtual = physical in ppc4xx_map_io(); EBC setup
-               for PCMCIA left to 4xx_pccf)
-   Space             EBC Bank    Physical Addresses  EBC Base Address
-   =========================================================================
-   PCMCIA (32 MB)        x       F0000000 - F1FFFFFF  F0000000
-   Expansion             2       F8000000 - F8FFFFFF  F8000000
-   Linux Flash (16 MB)           F9000000 - F9FFFFFF
-   NVRAM (32 KB)         1       FFE00000 - FFE07FFF  FFE00000
-   Ethernet(I/O)	 1	 FFE20300 - FFE2030F  FFE00000
-           (MEM)	 	 FFE40000 - FFE40FFF
-   FPGA_REG_4            1       FFE60000 - FFE60000  FFE00000
-   FPGA_REG_0            1       FFE80000 - FFE80000  FFE00000
-   FPGA_REG_1            1       FFEA0000 - FFEA0000  FFE00000
-   FPGA_REG_2            1       FFEC0000 - FFEC0000  FFE00000
-   FPGA_REG_3            1       FFEE0000 - FFEE0000  FFE00000
-   SRAM (512 KB)         0       FFF00000 - FFF7FFFF  FFF00000
-   Boot Flash  (512 KB)  0       FFF80000 - FFFFFFFF  FFF00000
-   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   NB: On Beech 1, address ranges for Bank 2 were reversed
-*/
-void __init
-beech_setup_arch(void)
-{
-	ppc4xx_setup_arch();
-	TODC_INIT(TODC_TYPE_DCR146818, NULL, NULL, NULL, 8);
-	/* Set up Beech FPGA. */
-	beech_fpga_setup();
-}
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-	ppc_md.setup_arch = beech_setup_arch;
-#ifdef CONFIG_PPC_RTC
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_dcr146818_read_val;
-	ppc_md.nvram_write_val = todc_dcr146818_write_val;
-#endif
-	/* Disable the LCD controller, which may have been left on by the
-	   BIOS.  Then do initialization of the EBC. */
-	mtdcri(DCRN_LCD0, DER, 0);
-	beech_ebc_setup();
-}
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
- + Non-standard board support follows
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-/****************************************************************************
- * EBC Setup
- ****************************************************************************/
-/* The EBC is set up for Beech.  This may simply replicate the setup already
-   done by the IBM BIOS for Beech (possibly with some address map changes), or
-   may be the first initialization if the board is booting from another BIOS.
-   Virtually all that is required to boot Linux on Beech is that the BIOS
-   enable the memory controller, load a Linux image from flash, and run it.
-   For optimal dynamic frequency scaling the EBC settings will also vary as the
-   frequency varies.
-*/
-static void __init
-beech_ebc_setup(void)
-{
-	ebc0_bnap_t ap;
-	ebc0_bncr_t cr;
-	/* Set EBC bank 0 for the SRAM and boot flash.
-	   Access parameters assume 120ns AMD flash @ 66.66 MHz maximum bus
-	   speed = 8 cycle access with 2 turnaround cycles (30 ns).
-	   These parameters will work for the SRAM as well, which is a 70 ns
-	   part.
-	   NB: IBM BIOS sets this bank to burst, however bursting will never
-	   happen in Linux because this region is mapped non-cacheable and
-	   guarded, so it is set non-burst here. */
-	cr.reg = (BEECH_BANK0_PADDR & 0xfff00000) |
-	    (mfdcri(DCRN_EBC0, BnCR(0)) & EBC0_BnCR_MASK);
-	cr.fields.bs = BEECH_BANK0_EBC_SIZE;
-	cr.fields.bu = EBC0_BnCR_BU_RW;
-	cr.fields.bw = EBC0_BnCR_BW_16;
-	mtdcri(DCRN_EBC0, BnCR(0), cr.reg);
-	ap.reg = mfdcri(DCRN_EBC0, BnAP(0)) & EBC0_BnAP_MASK;
-	ap.fields.twt = 8;
-	ap.fields.th = 2;
-	mtdcri(DCRN_EBC0, BnAP(0), ap.reg);
-	/*  EBC bank 1 is used for many purposes: NVRAM, Ethernet, and FPGA
-	   registers. This is a 1 MB, 16-bit bank. The access parameters must
-	   handle the worst case of all of the devices.
-	   The Ethernet chip needs 20 ns setup of the addresses to the I/O
-	   write signal (generated from the chip select), a minimum 150 ns
-	   cycle, and 30 ns of turnaround.  These settings will work for the
-	   other devices as well.
-	 */
-	cr.reg = (BEECH_BANK1_PADDR & 0xfff00000) |
-	    (mfdcri(DCRN_EBC0, BnCR(1)) & EBC0_BnCR_MASK);
-	cr.fields.bs = BEECH_BANK1_EBC_SIZE;
-	cr.fields.bu = EBC0_BnCR_BU_RW;
-	cr.fields.bw = EBC0_BnCR_BW_16;
-	mtdcri(DCRN_EBC0, BnCR(1), cr.reg);
-	ap.reg = mfdcri(DCRN_EBC0, BnAP(1)) & EBC0_BnAP_MASK;
-	ap.fields.twt = 10;
-	ap.fields.csn = 2;
-	ap.fields.th = 2;
-	mtdcri(DCRN_EBC0, BnAP(1), ap.reg);
-	/* Set EBC bank 2 for the big (Linux) flash.  There is 16 MB of flash,
-	   but the CPLD decodes a 32 MB region.
-	   Access parameters assume 90ns AMD flash @ 66.66 MHz maximum bus
-	   speed = 6 cycle access with 2 turnaround cycles (30 ns).
-	   NB: IBM BIOS sets this bank to burst, however bursting will never
-	   happen in Linux because this region is mapped non-cacheable and
-	   guarded, so it is set non-burst here. */
-	cr.reg = (BEECH_BANK2_PADDR & 0xfff00000) |
-	    (mfdcri(DCRN_EBC0, BnCR(2)) & EBC0_BnCR_MASK);
-	cr.fields.bs = BEECH_BANK2_EBC_SIZE;
-	cr.fields.bu = EBC0_BnCR_BU_RW;
-	cr.fields.bw = EBC0_BnCR_BW_8;
-	mtdcri(DCRN_EBC0, BnCR(2), cr.reg);
-	ap.reg = mfdcri(DCRN_EBC0, BnAP(2)) & EBC0_BnAP_MASK;
-	ap.fields.twt = 6;
-	ap.fields.th = 2;
-	mtdcri(DCRN_EBC0, BnAP(2), ap.reg);
-}
-/****************************************************************************
- * FPGA Setup
- ****************************************************************************/
-/* The Beech FPGA is set up for Linux. */
-static void __init
-beech_fpga_setup(void)
-{
-	volatile u8 *fpga_reg_2;
-	fpga_reg_2 = (volatile u8 *)
-	    ioremap(BEECH_FPGA_REG_2_PADDR, BEECH_FPGA_REG_2_SIZE);
-	/* Set RTS/CTS mode for UART 1 */
-	*fpga_reg_2 |= FPGA_REG_2_DEFAULT_UART1_N;
-}
-/*
- * Local variables:
- * c-basic-offset: 8
- * End:
- */
--- a/arch/ppc/platforms/4xx/beech.h
+++ b/arch/ppc/platforms/4xx/beech.h
-/*
- * include/asm-ppc/platforms/beech.h   Platform definitions for the IBM Beech
- *                                     board
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Copyright (C) 2002, International Business Machines Corporation
- * All Rights Reserved.
- *
- * Bishop Brock
- * IBM Research, Austin Center for Low-Power Computing
- * bcbrock@us.ibm.com
- * March, 2002
- *
- */
-#ifdef __KERNEL__
-#ifndef __ASM_BEECH_H__
-#define __ASM_BEECH_H__
-#include <platforms/4xx/ibm405lp.h>
-#ifndef __ASSEMBLY__
-/*
- * Data structure defining board information maintained by the standard boot
- * ROM on the IBM Beech board. An effort has been made to
- * keep the field names consistent with the 8xx 'bd_t' board info
- * structures.
- */
-typedef struct board_info {
-	unsigned char bi_s_version[4];	/* Version of this structure */
-	unsigned long bi_tbfreq;	/* Frequency of SysTmrClk */
-	unsigned char bi_r_version[30];	/* Version of the IBM ROM */
-	unsigned int bi_memsize;	/* DRAM installed, in bytes */
-	unsigned long sysclock_period;	/* SysClk period in ns */
-	unsigned long sys_speed;	/* SysCLk frequency in Hz */
-	unsigned long bi_intfreq;	/* Processor speed, in Hz */
-	unsigned long vco_speed;	/* PLL VCO speed, in Hz */
-	unsigned long bi_busfreq;	/* PLB Bus speed, in Hz */
-	unsigned long opb_speed;	/* OPB Bus speed, in Hz */
-	unsigned long ebc_speed;	/* EBC Bus speed, in Hz */
-} bd_t;
-/* See beech.c for a concise diagram of the Beech physical memory map. */
-#define PPC4xx_ONB_IO_PADDR    ((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR    PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE     ((uint)4*1024)
-/* EBC Bank 0 controls the boot flash and SRAM */
-#define BEECH_BANK0_PADDR      ((uint)0xfff00000)
-#define BEECH_BANK0_EBC_SIZE   EBC0_BnCR_BS_1MB
-#define BEECH_SRAM_PADDR		BEECH_BANK0_PADDR
-#define BEECH_SRAM_SIZE			((uint)(512 * 1024))
-#define BEECH_BOOTFLASH_PADDR		(BEECH_BANK0_PADDR + (512 * 1024))
-#define BEECH_BOOTFLASH_SIZE		((uint)(512 * 1024))
-/* EBC bank 1 controls the NVRAM, Ethernet and CPLD registers. The different
-   areas are mapped in as small an area as possible to help catch any kernel
-   addressing errors.
-   NVRAM is improperly connected on Beech Pass 1.  Only every other location is
-   accessible.  This is a 32 KB NVRAM.
-   The Ethernet chip maps 13 address lines. We only map the "I/O" space used by
-   the current driver.
-   The FPGA "registers" are decoded on 128 KB boundarys. Each is mapped in a
-   separate page. */
-#define BEECH_BANK1_PADDR       ((uint)0xffe00000)
-#define BEECH_BANK1_EBC_SIZE    EBC0_BnCR_BS_1MB
-#define BEECH_NVRAM_PADDR		BEECH_BANK1_PADDR
-#define BEECH_NVRAM_SIZE		((uint) (32 * 1024))
-#define BEECH_ETHERNET_PADDR		(BEECH_BANK1_PADDR + 0x00020000)
-#define BEECH_ETHERNET_SIZE		((uint) (8 * 1024))
-#define BEECH_FPGA_REG_0_PADDR		(BEECH_BANK1_PADDR + 0x00080000)
-#define BEECH_FPGA_REG_0_SIZE		PAGE_SIZE
-#define BEECH_FPGA_REG_1_PADDR		(BEECH_BANK1_PADDR + 0x000A0000)
-#define BEECH_FPGA_REG_1_SIZE		PAGE_SIZE
-#define BEECH_FPGA_REG_2_PADDR		(BEECH_BANK1_PADDR + 0x000C0000)
-#define BEECH_FPGA_REG_2_SIZE		PAGE_SIZE
-#define BEECH_FPGA_REG_3_PADDR		(BEECH_BANK1_PADDR + 0x000E0000)
-#define BEECH_FPGA_REG_3_SIZE		PAGE_SIZE
-#define BEECH_FPGA_REG_4_PADDR		(BEECH_BANK1_PADDR + 0x00060000)
-#define BEECH_FPGA_REG_4_SIZE		PAGE_SIZE
-/* FPGA Register Bits (From IBM BIOS) [ May not be valid for Beech Pass 1 ]*/
-#define FPGA_REG_0_FLASH_N		0x01
-#define FPGA_REG_0_FLASH_ONBD_N		0x02
-#define FPGA_REG_0_HITA_TOSH_N		0x04	/* New in Pass 2 */
-#define FPGA_REG_0_STAT_OC		0x20
-#define FPGA_REG_0_AC_SOURCE_SEL_N	0x40
-#define FPGA_REG_0_AC_ACTIVE_N		0x80
-#define FPGA_REG_1_USB_ACTIVE		0x01	/* New in Pass 2 */
-#define FPGA_REG_1_CLK_VARIABLE		0x02
-#define FPGA_REG_1_CLK_TEST		0x04
-#define FPGA_REG_1_CLK_SS		0x08
-#define FPGA_REG_1_EXT_IRQ_N		0x10
-#define FPGA_REG_1_SMI_MODE_N		0x20
-#define FPGA_REG_1_BATT_LOW_N		0x40
-#define FPGA_REG_1_PCMCIA_PWR_FAULT_N	0x80
-#define FPGA_REG_2_DEFAULT_UART1_N	0x01
-#define FPGA_REG_2_EN_1_8V_PLL_N	0x02
-#define FPGA_REG_2_PC_BUF_EN_N		0x08
-#define FPGA_REG_2_CODEC_RESET_N	0x10	/* New in Pass 2 */
-#define FPGA_REG_2_TP_JSTICK_N		0x20	/* New in Pass 2 */
-#define FPGA_REG_3_GAS_GAUGE_IO		0x01
-#define FPGA_REG_4_SDRAM_CLK3_ENAB	0x01
-#define FPGA_REG_4_SDRAM_CLK2_ENAB	0x02
-#define FPGA_REG_4_SDRAM_CLK1_ENAB	0x04
-#define FPGA_REG_4_SDRAM_CLK0_ENAB	0x08
-#define FPGA_REG_4_PCMCIA_5V		0x10	/* New in Pass 2 */
-#define FPGA_REG_4_IRQ3			0x20	/* New in Pass 2 */
-/* EBC Bank 2 contains the 16 MB "Linux" flash. The FPGA decodes a 32 MB
-   bank. The lower 16 MB are available for expansion devices.  The upper 16 MB
-   are used for the "Linux" flash.
-   Partitioning information is for the benefit of the MTD driver.  See
-   drivers/mtd/maps/ibm4xx.c. We currently allocate the lower 1 MB for a
-   kernel, and the other 15 MB for a filesystem.
-*/
-/* Bank 2 mappings changed between Beech Pass 1 and Pass 2 */
-#ifdef CONFIG_BEECH_PASS1
-#define BEECH_BIGFLASH_OFFSET 0
-#else
-#define BEECH_BIGFLASH_OFFSET (16 * 1024 * 1024)
-#endif
-#define BEECH_BANK2_PADDR      ((uint)0xf8000000)
-#define BEECH_BANK2_EBC_SIZE   EBC0_BnCR_BS_32MB
-#define BEECH_BIGFLASH_PADDR		(BEECH_BANK2_PADDR + BEECH_BIGFLASH_OFFSET)
-#define BEECH_BIGFLASH_SIZE		(16 * 1024 * 1024)
-#define BEECH_KERNEL_OFFSET    0
-#define BEECH_KERNEL_SIZE      (1 * 1024 * 1024)
-#define BEECH_FREE_AREA_OFFSET BEECH_KERNEL_SIZE
-#define BEECH_FREE_AREA_SIZE   (BEECH_BIGFLASH_SIZE - BEECH_KERNEL_SIZE)
-/* The PCMCIA controller driver 4xx_pccf.c is responsible for the EBC setup of
-   PCMCIA.  Externally, EBC bank selects 3..7 take on PCMCIA functions when
-   PCMCIA is enabled. */
-#define BEECH_PCMCIA_PADDR		((uint)0xf0000000)
-#define BEECH_PCMCIA_SIZE		((uint)(32 * 1024 * 1024))
-/* We do not currently support the internal clock mode for the UART.  This
-   limits the minimum OPB frequency to just over 2X the UART oscillator
-   frequency. At OPB frequencies less than this the serial port will not
-   function due to the way that SerClk is sampled. */
-#define PPC4xx_SERCLK_FREQ		11059200
-#define BASE_BAUD			(PPC4xx_SERCLK_FREQ / 16)
-#define PPC4xx_MACHINE_NAME		"IBM 405LP Beech"
-/****************************************************************************
- * Non-standard board support follows
- ****************************************************************************/
-extern int beech_sram_free(void *p);
-extern int ibm405lp_set_pixclk(unsigned pixclk_low, unsigned pixclk_high);
-extern void *beech_sram_alloc(size_t size);
-#endif				/* !__ASSEMBLY__ */
-#endif				/* __ASM_BEECH_H__ */
-#endif				/* __KERNEL__ */
--- a/arch/ppc/platforms/4xx/cedar.c
+++ b/arch/ppc/platforms/4xx/cedar.c
-/*
- * arch/ppc/platforms/4xx/cedar.c
- *
- * Support for the IBM NP405L ceder eval board
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/pagemap.h>
-#include <asm/machdep.h>
-#include <asm/io.h>
-#include <asm/todc.h>
-void *cedar_rtc_base;
-void __init
-cedar_setup_arch(void)
-{
-	bd_t *bip = &__res;
-	/* RTC step for the walnut */
-	cedar_rtc_base = (void *) CEDAR_RTC_VADDR;
-	TODC_INIT(TODC_TYPE_DS1743, cedar_rtc_base, cedar_rtc_base,
-		  cedar_rtc_base, 8);
-#ifdef CONFIG_DEBUG_BRINGUP
-	printk("\n");
-	printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
-	printk("\n");
-	printk("bi_s_version\t %s\n", bip->bi_s_version);
-	printk("bi_r_version\t %s\n", bip->bi_r_version);
-	printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
-	       bip->bi_memsize / (1024 * 1000));
-	printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
-	       bip->bi_enetaddr[0][0], bip->bi_enetaddr[0][1],
-	       bip->bi_enetaddr[0][2], bip->bi_enetaddr[0][3],
-	       bip->bi_enetaddr[0][4], bip->bi_enetaddr[0][5]);
-	printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 1,
-	       bip->bi_enetaddr[1][0], bip->bi_enetaddr[1][1],
-	       bip->bi_enetaddr[1][2], bip->bi_enetaddr[1][3],
-	       bip->bi_enetaddr[1][4], bip->bi_enetaddr[1][5]);
-	printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
-	       bip->bi_intfreq, bip->bi_intfreq / 1000000);
-	printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
-	       bip->bi_busfreq, bip->bi_busfreq / 1000000);
-	printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
-	       bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000);
-	printk("\n");
-#endif
-	/* Identify the system */
-	printk
-	    ("IBM Cedar port (C) 2002 MontaVista Software, Inc. (source@mvista.com)\n");
-}
-void __init
-cedar_map_io(void)
-{
-	ppc4xx_map_io();
-	io_block_mapping(CEDAR_RTC_VADDR,
-			 CEDAR_RTC_PADDR, CEDAR_RTC_SIZE, _PAGE_IO);
-}
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-	ppc_md.setup_arch = cedar_setup_arch;
-	ppc_md.setup_io_mappings = cedar_map_io;
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-}
--- a/arch/ppc/platforms/4xx/cedar.h
+++ b/arch/ppc/platforms/4xx/cedar.h
-/*
- * arch/ppc/platforms/4xx/cedar.h
- *
- * Macros, definitions, and data structures specific to the IBM PowerPC
- * Cedar eval board.
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_CEDAR_H__
-#define __ASM_CEDAR_H__
-#include <platforms/4xx/ibmnp405l.h>
-#ifndef __ASSEMBLY__
-/*
- * Data structure defining board information maintained by the boot
- * ROM on IBM's "Cedar" evaluation board. An effort has been made to
- * keep the field names consistent with the 8xx 'bd_t' board info
- * structures.
- */
-typedef struct board_info {
-	unsigned char	 bi_s_version[4];	/* Version of this structure */
-	unsigned char	 bi_r_version[30];	/* Version of the IBM ROM */
-	unsigned int	 bi_memsize;		/* DRAM installed, in bytes */
-	unsigned char	 bi_enetaddr[2][6];	/* Local Ethernet MAC address */
-	unsigned char	 bi_pci_mac[6];
-	unsigned int	 bi_intfreq;		/* Processor speed, in Hz */
-	unsigned int	 bi_busfreq;		/* PLB Bus speed, in Hz */
-	unsigned int	 bi_pci_busfreq;	/* PCI speed in Hz */
-} bd_t;
-/* Some 4xx parts use a different timebase frequency from the internal clock.
-*/
-#define bi_tbfreq bi_intfreq
-/* Memory map for the IBM "Cedar" NP405 evaluation board.
- */
-extern  void *cedar_rtc_base;
-#define CEDAR_RTC_PADDR		((uint)0xf0000000)
-#define CEDAR_RTC_VADDR		CEDAR_RTC_PADDR
-#define CEDAR_RTC_SIZE		((uint)8*1024)
-/* Early initialization address mapping for block_io.
- * Standard 405GP map.
- */
-#define PPC4xx_ONB_IO_PADDR	((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR	PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
-#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
-#define BASE_BAUD		201600
-#else
-#define BASE_BAUD		691200
-#endif
-#define PPC4xx_MACHINE_NAME "IBM NP405L Cedar"
-#endif /* !__ASSEMBLY__ */
-#endif /* __ASM_CEDAR_H__ */
-#endif /* __KERNEL__ */
--- a/arch/ppc/platforms/4xx/ibm405lp.c
+++ b/arch/ppc/platforms/4xx/ibm405lp.c
-/*
- * arch/ppc/platforms/ibm405lp.c  405LP-specific code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Copyright (C) 2002, International Business Machines Corporation
- * All Rights Reserved.
- *
- * Bishop Brock
- * IBM Research, Austin Center for Low-Power Computing
- * bcbrock@us.ibm.com
- * March, 2002
- */
-#include <linux/config.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/proc_fs.h>
-#include <linux/stat.h>
-#include <linux/string.h>
-#include <asm/delay.h>
-#include <asm/hardirq.h>
-#include <asm/ibm4xx.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <asm/time.h>
-#include <asm/uaccess.h>
-#include <asm/ocp.h>
-struct ocp_def core_ocp[]  __initdata = {
-	{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB0_BASE, OCP_IRQ_NA, OCP_CPM_NA},
-	{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0},
-	{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
-	{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
-	{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
-	{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
-};
-#ifdef CONFIG_PM
-/* Set up the 405LP clock and power management unit for aggressive power
-   management.
-   Briefly, there are 3 CPM "classes":
-   Class 1 - Either completely asleep or awake.  The "force" state is
-             equivalent to the "enabled" state.  Many Class 1 units are
-             critical system components and are never power managed.
-   Class 2 - Can be enabled for power management, where sleep requests are
-             made by the peripheral, typically after an inactivity timeout.
-	     When sleeping, critical interfaces remain active, and
-	     awaken the unit whenever it is targeted with a transaction.
-   Class 3 - Can be enabled for power management, where sleep requests are
-             made by the CPM.  Power management for these units typically
-             will require intelligence in a device driver.
-   In the current implementation, the "force" bits are only used on Class 1
-   devices, and only when the associated driver has the intelligence necessary
-   to "unforce" the power management state.  A previous scheme, which tried to
-   enable power management based on whether a particular driver was compiled
-   with the kernel, caused many problems and is never used here.
-   Class 2 devices with timeouts are normally initialized for the most
-   aggressive values.  There is no power management benefit of "forcing" Class
-   2 devices over letting their inactivity timeouts take effect.  Therefore,
-   after being set up here, Class 2 device drivers don't need to worry about
-   CPM.
-   No Class 3 devices are handled yet.  */
-void __init
-ibm405lp_setup_cpm(void)
-{
-	u32 force = 0;
-	u32 enable = 0;
-	dma0_slp_t dma0_slp;
-	dcp0_cfg_t dcp0_cfg;
-	ebc0_cfg_t ebc0_cfg;
-	sdram0_cfg_t sdram0_cfg;
-	sdram0_pmit_t sdram0_pmit;
-	sla0_slpmd_t sla0_slpmd;
-	/* Initialize the CPM state */
-	mtdcr(DCRN_CPMFR, force);
-	mtdcr(DCRN_CPMER, enable);
-	/* IIC - Class 3 - Not handled yet.  The driver should at least be able
-	   to force/unforce itself. */
-	/* CPU - class 2 - There doesn't appear to be a timeout associated with
-	   this, and the exact function is not documented anywhere.  It saves a
-	   lot of power, though. I assume this gates core clocks when the CPU
-	   core is asleep, and probably adds a couple of cycles of latency when
-	   the CPU core wakes up. */
-	enable |= IBM_CPM_CPU;
-	/* DMA - class 2. Set for the minimum timeout, which is 32 cycles. */
-	dma0_slp.reg = mfdcr(DCRN_SLP);
-	dma0_slp.fields.sme = 1;
-	dma0_slp.fields.idu = 0;
-	mtdcr(DCRN_SLP, dma0_slp.reg);
-	enable |= IBM_CPM_DMA;
-	/* BRG - Class 2.  Seems to crash the system when enabled in 405LP Pass
-	   1
-	   DCP (CodePack) - Class 2.  The semantics of the sleep delay are not
-	   documented. We'll use 32 (what the heck). */
-	dcp0_cfg.reg = mfdcri(DCRN_DCP0, CFG);
-	dcp0_cfg.fields.slen = 1;
-	dcp0_cfg.fields.sldy = 32;
-	mtdcri(DCRN_DCP0, CFG, dcp0_cfg.reg);
-	enable |= IBM_CPM_DCP;
-	/* EBC - Class 2.  Set for minimum timeout, which is 32 cycles. [ I
-	   think this is 32. It may be 64. I don't trust the documentation. ]
-	 */
-	ebc0_cfg.reg = mfdcri(DCRN_EBC0, CFG);
-	ebc0_cfg.fields.pme = 1;
-	ebc0_cfg.fields.pmt = 1;
-	mtdcri(DCRN_EBC0, CFG, ebc0_cfg.reg);
-	enable |= IBM_CPM_EBC;
-	/* SDRAM - Class 2.  Set for the minimum 32-cycle timeout.
-	   The documentation on this core is clear - waking a sleeping SDRAM
-	   controller takes 2 PLB cycles, which is added to the latency of the
-	   memory operation. If someone can prove that this is affecting
-	   performance we can easily back this off.  */
-	sdram0_cfg.reg = mfdcri(DCRN_SDRAM0, CFG);
-	sdram0_cfg.fields.pme = 1;
-	mtdcri(DCRN_SDRAM0, CFG, sdram0_cfg.reg);
-	sdram0_pmit.reg = mfdcri(DCRN_SDRAM0, PMIT);
-	sdram0_pmit.fields.cnt = 0;
-	mtdcri(DCRN_SDRAM0, PMIT, sdram0_pmit.reg);
-	enable |= IBM_CPM_SDRAM0;
-	/* PLB - Class 2.  Seems to crash the system when enabled in 405LP Pass
-	   1.
-	   GPIO - Class 1.  This unit is used for many things, and no single
-	   driver controls all GPIO.  It's best left unmanaged (it doesn't use
-	   much power anyway). NB: 405LP Pass 1 erratum - forcing PM on GPIO
-	   kills the TPC.
-	   UART0 - Class 1
-	   UART1 - Class 1
-	   Someone should work on the serial port drivers to enable PM support
-	   for them. Any takers?
-	   UIC        - Class 1
-	   CPU_TMRCLK - Class 1
-	   These system resources are never power managed.  */
-	/* SLA - Class 2.  Set for the minimum 32-cycle timeout. */
-	sla0_slpmd.reg = mfdcri(DCRN_SLA0, SLPMD);
-	sla0_slpmd.fields.slen = 1;
-	sla0_slpmd.fields.slcr = 0;
-	mtdcri(DCRN_SLA0, SLPMD, sla0_slpmd.reg);
-	enable |= IBM_CPM_SLA;
-	/* CSI  - Class 1.
-	   TPC  - Class 1.
-	   TDES - Class 1.
-	   The drivers for these units are power-aware, and manage the device
-	   properly. By default these units are forced off at boot. */
-	force |= IBM_CPM_CSI;
-	force |= IBM_CPM_TPC;
-	force |= IBM_CPM_TDES;
-	/* Set the CPM state */
-	mtdcr(DCRN_CPMFR, force);
-	mtdcr(DCRN_CPMER, enable);
-}
-#endif
-/* This routine is included here because the framebuffer driver needs a way to
-   tell the system the Pixel clock frequency it needs, regardless of whether
-   run-time frequency scaling is configured.  A hook and a couple of global
-   variables are always present and will be used by the RTVFS driver if it is
-   loaded.
-   Pixel clock setting is kind of a hack, as the frequency steps available from
-   the PLB/PixClk divider may be too large to guarantee that we'll hit within
-   the given limits.  We never set the frequency above the upper bound, but due
-   to quantization may need to set the frequency below the lower bound.  So far
-   it works OK for the panels we've tried.
-   In general, the choice of a system clock frequency should be made with
-   consideration of the LCD panel to be attached, to guarantee a good clock
-   divider for the Pixel clock regardless of frequency scaling.
-   Clock frequencies are in KHz. If pixclk_min or pixclk_max are zero, we set
-   the lowest possible frequency to conserve energy. */
-int (*set_pixclk_hook) (unsigned pixclk_min, unsigned pixclk_max) = NULL;
-unsigned last_pixclk_min = 0;
-unsigned last_pixclk_max = 0;
-EXPORT_SYMBOL(set_pixclk_hook);
-EXPORT_SYMBOL(last_pixclk_min);
-EXPORT_SYMBOL(last_pixclk_max);
-int
-ibm405lp_set_pixclk(unsigned pixclk_min, unsigned pixclk_max)
-{
-	unsigned divider;
-	bd_t *bip = (bd_t *) __res;
-	unsigned plb_khz = bip->bi_busfreq / 1000;
-	cpc0_cgcr1_t cgcr1;
-	if (set_pixclk_hook) {
-		return (set_pixclk_hook) (pixclk_min, pixclk_max);
-	} else {
-		if ((pixclk_min == 0) || (pixclk_max == 0))
-			divider = CPC0_DIV_MAX;
-		else {
-			divider = plb_khz / pixclk_min;
-			if (divider == 0)
-				divider = 1;
-			if ((divider < CPC0_DIV_MAX) &&
-			    ((plb_khz / divider) > pixclk_max))
-				divider++;
-		}
-		cgcr1.reg = mfdcr(DCRN_CPC0_CGCR1);
-		cgcr1.fields.ppxl = CPC0_DIV_ENCODE(divider);
-		mtdcr(DCRN_CPC0_CGCR1, cgcr1.reg);
-		last_pixclk_min = pixclk_min;
-		last_pixclk_max = pixclk_max;
-		return 0;
-	}
-}
--- a/arch/ppc/platforms/4xx/ibm405lp.h
+++ b/arch/ppc/platforms/4xx/ibm405lp.h
--- a/arch/ppc/platforms/4xx/ibmnp405l.c
+++ b/arch/ppc/platforms/4xx/ibmnp405l.c
-/*
- * arch/ppc/platforms/4xx/ibmnp405l.c
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <platforms/4xx/ibmnp405l.h>
-struct ocp_def core_ocp[] = {
-	{UART, UART0_IO_BASE, UART0_INT, IBM_CPM_UART0},
-	{UART, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
-	{IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
-	{GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
-	{OPB, OPB0_BASE, OCP_IRQ_NA, IBM_CPM_OPB},
-	{EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0},
-	{EMAC, EMAC1_BASE, BL_MAC_ETH1, IBM_CPM_EMAC1},
-	{ZMII, ZMII0_BASE, OCP_IRQ_NA, OCP_CPM_NA},
-	{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
-};
--- a/arch/ppc/platforms/4xx/ibmnp405l.h
+++ b/arch/ppc/platforms/4xx/ibmnp405l.h
-/*
- * arch/ppc/platforms/4xx/ibmnp405l.h
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_IBMNP405L_H__
-#define __ASM_IBMNP405L_H__
-#include <linux/config.h>
-/* serial port defines */
-#define RS_TABLE_SIZE	2
-#define UART0_INT	0
-#define UART1_INT	1
-#define UART0_IO_BASE	0xEF600300
-#define UART1_IO_BASE	0xEF600400
-#define IIC0_BASE	0xEF600500
-#define OPB0_BASE	0xEF600600
-#define GPIO0_BASE	0xEF600700
-#define EMAC0_BASE	0xEF600800
-#define EMAC1_BASE	0xEF600900
-#define ZMII0_BASE	0xEF600C10
-#define BL_MAC_WOL	41	/* WOL */
-#define BL_MAL_SERR	45	/* MAL SERR */
-#define BL_MAL_TXDE	46	/* MAL TXDE */
-#define BL_MAL_RXDE	47	/* MAL RXDE */
-#define BL_MAL_TXEOB	17	/* MAL TX EOB */
-#define BL_MAL_RXEOB	18	/* MAL RX EOB */
-#define BL_MAC_ETH0	37	/* MAC */
-#define BL_MAC_ETH1	38	/* MAC */
-#define EMAC_NUMS	2
-#define IIC0_IRQ	2
-#undef NR_UICS
-#define NR_UICS	2
-#define UIC_CASCADE_MASK 0x0003	/* bits 30 & 31 */
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base:(u8 *) UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
-#define SERIAL_PORT_DFNS        \
-        STD_UART_OP(0)          \
-        STD_UART_OP(1)
-#endif
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE	UART1_IO_BASE
-#define SERIAL_PORT_DFNS        \
-        STD_UART_OP(1)          \
-        STD_UART_OP(0)
-#endif
-/* DCR defines */
-/* ------------------------------------------------------------------------- */
-#define DCRN_CHCR_BASE	0x0F1
-#define DCRN_CHPSR_BASE	0x0B4
-#define DCRN_CPMSR_BASE	0x0BA
-#define DCRN_CPMFR_BASE	0x0B9
-#define DCRN_CPMER_BASE	0x0B8
-#define IBM_CPM_EMAC0	0x00800000	/* on-chip ethernet MM unit */
-#define IBM_CPM_EMAC1	0x00100000	/* EMAC 1 MII */
-#define IBM_CPM_UIC1	0x00020000	/* Universal Interrupt Controller */
-#define IBM_CPM_UIC0	0x00010000	/* Universal Interrupt Controller */
-#define IBM_CPM_CPU	0x00008000	/* processor core */
-#define IBM_CPM_EBC	0x00004000	/* ROM/SRAM peripheral controller */
-#define IBM_CPM_SDRAM0	0x00002000	/* SDRAM memory controller */
-#define IBM_CPM_GPIO0	0x00001000	/* General Purpose IO (??) */
-#define IBM_CPM_HDLC	0x00000800	/* HDCL */
-#define IBM_CPM_TMRCLK	0x00000400	/* CPU timers */
-#define IBM_CPM_PLB	0x00000100	/* PLB bus arbiter */
-#define IBM_CPM_OPB	0x00000080	/* PLB to OPB bridge */
-#define IBM_CPM_DMA	0x00000040	/* DMA controller */
-#define IBM_CPM_IIC0	0x00000010	/* IIC interface */
-#define IBM_CPM_UART0	0x00000002	/* serial port 0 */
-#define IBM_CPM_UART1	0x00000001	/* serial port 1 */
-#define DFLT_IBM4xx_PM	~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU	\
-			| IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB	\
-			| IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA	\
-			| IBM_CPM_EMAC0 | IBM_CPM_EMAC1)
-#define DCRN_DMA0_BASE	0x100
-#define DCRN_DMA1_BASE	0x108
-#define DCRN_DMA2_BASE	0x110
-#define DCRN_DMA3_BASE	0x118
-#define DCRNCAP_DMA_SG	1	/* have DMA scatter/gather capability */
-#define DCRN_DMASR_BASE	0x120
-#define DCRN_EBC_BASE	0x012
-#define DCRN_DCP0_BASE	0x014
-#define DCRN_MAL_BASE	0x180
-#define DCRN_MAL1_BASE	0x200
-#define DCRN_OCM0_BASE	0x018
-#define DCRN_PLB0_BASE	0x084
-#define DCRN_PLLMR_BASE	0x0F0
-#define DCRN_POB0_BASE	0x0A0
-#define DCRN_SDRAM0_BASE 0x010
-#define DCRN_UIC0_BASE	0x0C0
-#define DCRN_UIC1_BASE	0x0D0
-#define DCRN_CPC0_EPRCSR 0x0F3
-#define UIC0_UIC1NC      30	/* UIC1 non-critical interrupt */
-#define UIC0_UIC1CR      31	/* UIC1 critical interrupt */
-#define CHR1_CETE	0x00000004	/* CPU external timer enable */
-#define UIC0	DCRN_UIC0_BASE
-#define UIC1	DCRN_UIC1_BASE
-#define SDRAM_CFG	0x20
-#define SDRAM0_ECCCFG	0x94
-#define SDRAM_NO_ECC	0x10000000
-#include <asm/ibm405.h>
-#endif				/* __ASM_IBMNP405L_H__ */
-#endif				/* __KERNEL__ */
--- a/arch/ppc/platforms/4xx/ibmnp4gs.c
+++ b/arch/ppc/platforms/4xx/ibmnp4gs.c
-/*
- * arch/ppc/platforms/4xx/ibmnp4gs.c
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/init.h>
-#include "ibmnp4gs.h"
-#include <asm/ocp.h>
-struct ocp_def core_ocp[] = {
-	{UART, UART0_IO_BASE, UART0_INT, IBM_CPM_UART0},
-	{PCI, PCIL0_BASE, OCP_IRQ_NA, IBM_CPM_PCI},
-	{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
-};
--- a/arch/ppc/platforms/4xx/ibmnp4gs.h
+++ b/arch/ppc/platforms/4xx/ibmnp4gs.h
-/*
- * arch/ppc/platforms/4xx/ibmnp4gs.h
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_IBMNP4GS_H__
-#define __ASM_IBMNP4GS_H__
-#include <linux/config.h>
-#include <asm/ibm_ocp.h>
-/* ibm405.h at bottom of this file */
-/* PCI
- * PCI Bridge config reg definitions
- * see 17-19 of manual
- */
-#define PPC405_PCI_CONFIG_ADDR	0xeec00000
-#define PPC405_PCI_CONFIG_DATA	0xeec00004
-#define PPC405_PCI_PHY_MEM_BASE	0x80000000	/* hose_a->pci_mem_offset */
-						/* setbat */
-#define PPC405_PCI_MEM_BASE	PPC405_PCI_PHY_MEM_BASE	/* setbat */
-#define PPC405_PCI_PHY_IO_BASE	0xe8000000	/* setbat */
-#define PPC405_PCI_IO_BASE	PPC405_PCI_PHY_IO_BASE	/* setbat */
-#define PPC405_PCI_LOWER_MEM	0x80000000	/* hose_a->mem_space.start */
-#define PPC405_PCI_UPPER_MEM	0xBfffffff	/* hose_a->mem_space.end */
-#define PPC405_PCI_LOWER_IO	0x00000000	/* hose_a->io_space.start */
-#define PPC405_PCI_UPPER_IO	0x0000ffff	/* hose_a->io_space.end */
-#define PPC405_ISA_IO_BASE	PPC405_PCI_IO_BASE
-#define PPC4xx_PCI_IO_PADDR	((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR	PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR	((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR	PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR	((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR	PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
-#define PPC4xx_ONB_IO_PADDR	((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR	PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
-#define PCI_CONFIG_ADDR_MASK		0x7F000000
-#define PCI_CONFIG_CYCLE_ENABLE		0x80000000
-#define PCI_BASE_ADDRESS_2		0x18	/* 32 bits [htype 0 only] */
-#define PCI_BASE_ADDRESS_MEM_PREFETCH	0x08
-#define PCI_CONFIG_ADDR_MASK		0x7F000000
-#define PCI_CONFIG_CYCLE_ENABLE		0x80000000
-#define PCI_BASE_ADDRESS_MEM_CARD1	0x80000000
-#define PCI_BASE_ADDRESS_MEM_CARD2	0x90000000
-#define PPC405_UART0_INT		1
-#define PPC_405RAINIER2_IO_PAGE		((void*)0xe8001000)
-#define PPC_405RAINIER1_IO_PAGE		((void*)0xe8002000)
-#define PPC405_UART0_IO_BASE		0x300	/* mostly use (rainier_io_page+0x300) */
-#define RAINIER_IO_PAGE_INTERPOSER_PADDR 0xe8000000
-#define RAINIER_IO_PAGE_INTERPOSER_VADDR RAINIER_IO_PAGE_INTERPOSER_PADDR
-#define RAINIER_IO_PAGE_PCI_PADDR	0xeec00000
-#define RAINIER_IO_PAGE_PCI_VADDR	RAINIER_IO_PAGE_PCI_PADDR
-/* serial port defines */
-#define RS_TABLE_SIZE	1
-#define UART0_INT	1
-#define PCIL0_BASE	0xEF400000
-#define UART0_IO_BASE	PPC_405RAINIER1_IO_PAGE + PPC405_UART0_IO_BASE
-#define UART_NUMS	1
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (u8 *)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)
-#endif
-/* DCR defines */
-#define DCRN_CHCR_BASE		0x0B1
-#define DCRN_CHPSR_BASE		0x0B4
-#define DCRN_CPMSR_BASE		0x0B8
-#define DCRN_CPMFR_BASE		0x0BA
-#define  PSR_PLL_FWD_MASK        0xC0000000
-#define  PSR_PLL_FDBACK_MASK     0x30000000
-#define  PSR_PLL_TUNING_MASK     0x0E000000
-#define  PSR_PLB_CPU_MASK        0x01800000
-#define  PSR_OPB_PLB_MASK        0x00600000
-#define  PSR_PCI_PLB_MASK        0x00180000
-#define  PSR_EB_PLB_MASK         0x00060000
-#define  PSR_ROM_WIDTH_MASK      0x00018000
-#define  PSR_ROM_LOC             0x00004000
-#define  PSR_PCI_ASYNC_EN        0x00001000
-#define  PSR_PCI_ARBIT_EN        0x00000400
-#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
-#define IBM_CPM_PCI		0x40000000	/* PCI bridge */
-#define IBM_CPM_CPU		0x20000000	/* processor core */
-#define IBM_CPM_DMA		0x10000000	/* DMA controller */
-#define IBM_CPM_BRG		0x08000000	/* PLB to OPB bridge */
-#define IBM_CPM_DCP		0x04000000	/* CodePack */
-#define IBM_CPM_EBC		0x02000000	/* ROM/SRAM peripheral controller */
-#define IBM_CPM_SDRAM0		0x01000000	/* SDRAM memory controller */
-#define IBM_CPM_PLB		0x00800000	/* PLB bus arbiter */
-#define IBM_CPM_GPIO0		0x00400000	/* General Purpose IO (??) */
-#define IBM_CPM_UART0		0x00200000	/* serial port 0 */
-#define IBM_CPM_UART1		0x00100000	/* serial port 1 */
-#define IBM_CPM_UIC		0x00080000	/* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK		0x00040000	/* CPU timers */
-#define DFLT_IBM4xx_PM		0
-#define DCRN_DMA0_BASE		0x100
-#define DCRN_DMA1_BASE		0x108
-#define DCRN_DMA2_BASE		0x110
-#define DCRN_DMA3_BASE		0x118
-#define DCRNCAP_DMA_SG		1	/* have DMA scatter/gather capability */
-#define DCRN_DMASR_BASE		0x120
-#define DCRN_EBC_BASE		0x012
-#define DCRN_DCP0_BASE		0x014
-#define DCRN_MAL_BASE		0x180
-#define DCRN_OCM0_BASE		0x018
-#define DCRN_PLB0_BASE		0x084
-#define DCRN_PLLMR_BASE		0x0B0
-#define DCRN_POB0_BASE		0x0A0
-#define DCRN_SDRAM0_BASE	0x010
-#define DCRN_UIC0_BASE		0x0C0
-#define UIC0 DCRN_UIC0_BASE
-#include <asm/ibm405.h>
-#endif				/* __ASM_IBMNP4GS_H__ */
-#endif				/* __KERNEL__ */
--- a/arch/ppc/platforms/4xx/ibmstb3.c
+++ b/arch/ppc/platforms/4xx/ibmstb3.c
-/*
- * arch/ppc/platforms/4xx/ibmstb3.c
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/config.h>
-#include "ibmstb3.h"
-#include <asm/ocp.h>
-struct ocp_def core_ocp[] = {
-	{UART, UART0_IO_BASE, UART0_INT, IBM_CPM_UART0},
-	{IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
-	{IIC, IIC1_BASE, IIC1_IRQ, IBM_CPM_IIC1},
-	{GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
-	{OPB, OPB0_BASE, OCP_IRQ_NA, OCP_CPM_NA},
-	{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
-};
--- a/arch/ppc/platforms/4xx/ibmstb3.h
+++ b/arch/ppc/platforms/4xx/ibmstb3.h
-/*
- * arch/ppc/platforms/4xx/ibmstb3.h
- *
- * Authors: Armin Kuster <akuster@mvista.com>, Tom Rini <trini@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_IBMSTBX_H__
-#define __ASM_IBMSTBX_H__
-#include <linux/config.h>
-#include <platforms/4xx/ibm_ocp.h>
-/* ibm405.h at bottom of this file */
-/*
- * Memory map for the IBM "Redwood-4" STB03xxx evaluation board.
- *
- * The  STB03xxx internal i/o addresses don't work for us 1:1,
- * so we need to map them at a well know virtual address.
- *
- * 4000 000x   uart1           -> 0xe000 000x
- * 4001 00xx   ppu
- * 4002 00xx   smart card
- * 4003 000x   iic
- * 4004 000x   uart0
- * 4005 0xxx   timer
- * 4006 00xx   gpio
- * 4007 00xx   smart card
- * 400b 000x   iic
- * 400c 000x   scp
- * 400d 000x   modem
- */
-#define STB03xxx_IO_BASE	((uint)0xe0000000)
-#define PPC4xx_ONB_IO_PADDR	((uint)0x40000000)
-#define PPC4xx_ONB_IO_VADDR	STB03xxx_IO_BASE
-#define PPC4xx_ONB_IO_SIZE	((uint)14*64*1024)
-/* Since we're into address mapping hacks, at least try to hide
- * it under a macro.....
- */
-#define STB03xxx_MAP_IO_ADDR(a)	(((uint)(a) & 0x000fffff) + PPC4xx_ONB_IO_VADDR)
-#define RS_TABLE_SIZE		1
-#define UART0_INT		20
-#ifdef __BOOTER__
-#define UART0_IO_BASE		0x40040000
-#else
-#define UART0_IO_BASE		0xe0040000
-#endif
- /* UART 0 is duped here so when the SICC is the default console
-  * then ttys1 is configured properly - armin
-  */
-#define UART1_INT		20
-#ifdef __BOOTER__
-#define UART1_IO_BASE		0x40040000
-#else
-#define UART1_IO_BASE		0xe0040000
-#endif
-/* need to make this work in scheme - armin */
-#define SICC0_INTRX		21
-#define SICC0_INTTX		22
-#define SICC0_IO_BASE		((uint* )0x40000000)
-#define IDE0_BASE		0xf2100000
-#define REDWOOD_IDE_CTRL	0xf4100000
-#define IIC0_BASE	0x40030000
-#define IIC1_BASE	0x400b0000
-#define OPB0_BASE	0x40010000
-#define GPIO0_BASE	0x40060000
-#define IIC0_IRQ	9
-#define IIC1_IRQ	10
-#define IIC_OWN		0x55
-#define IIC_CLOCK	50
-#define IDE0_IRQ 	25
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (u8 *)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)
-#endif
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE	UART1_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(1)
-#endif
-/* ------------------------------------------------------------------------- */
-#define DCRN_DCRX_BASE		0x020
-#define DCRN_CIC_BASE 		0x030
-#define DCRN_UIC0_BASE		0x040
-#define DCRN_PLB0_BASE		0x054
-#define DCRN_PLB1_BASE		0x064
-#define DCRN_EBIMC_BASE		0x070
-#define DCRN_POB0_BASE		0x0B0
-#define DCRN_BE_BASE		0x090
-#define DCRN_DMA0_BASE		0x0C0
-#define DCRN_DMA1_BASE		0x0C8
-#define DCRN_DMA2_BASE		0x0D0
-#define DCRN_DMA3_BASE		0x0D8
-#define DCRNCAP_DMA_CC		1	/* have DMA chained count capability */
-#define DCRN_DMASR_BASE		0x0E0
-#define DCRN_CPMFR_BASE		0x102
-#define DCRN_SCCR_BASE		0x120
-#define UIC0 DCRN_UIC0_BASE
-#define IBM_CPM_IIC0	0x80000000	/* IIC 0 interface */
-#define IBM_CPM_I1284	0x40000000	/* IEEE-1284 */
-#define IBM_CPM_IIC1	0x20000000	/* IIC 1 interface */
-#define IBM_CPM_CPU	0x10000000	/* PPC405B3 clock control */
-#define IBM_CPM_AUD	0x08000000	/* Audio Decoder */
-#define IBM_CPM_EBIU	0x04000000	/* External Bus Interface Unit */
-#define IBM_CPM_SDRAM1	0x02000000	/* SDRAM 1 memory controller */
-#define IBM_CPM_DMA	0x01000000	/* DMA controller */
-#define IBM_CPM_UART1	0x00100000	/* Serial 1 / Infrared */
-#define IBM_CPM_UART0	0x00080000	/* Serial 0 / 16550 */
-#define IBM_CPM_DCRX	0x00040000	/* DCR Extension */
-#define IBM_CPM_SC0	0x00020000	/* Smart Card 0 */
-#define IBM_CPM_SC1	0x00008000	/* Smart Card 1 */
-#define IBM_CPM_SDRAM0	0x00004000	/* SDRAM 0 memory controller */
-#define IBM_CPM_XPT54	0x00002000	/* Transport - 54 Mhz */
-#define IBM_CPM_CBS	0x00001000	/* Cross Bar Switch */
-#define IBM_CPM_GPT	0x00000800	/* GPTPWM */
-#define IBM_CPM_GPIO0	0x00000400	/* General Purpose IO 0 */
-#define IBM_CPM_DENC	0x00000200	/* Digital video Encoder */
-#define IBM_CPM_TMRCLK	0x00000100	/* CPU timers */
-#define IBM_CPM_XPT27	0x00000080	/* Transport - 27 Mhz */
-#define IBM_CPM_UIC	0x00000040	/* Universal Interrupt Controller */
-#define IBM_CPM_MSI	0x00000010	/* Modem Serial Interface (SSP) */
-#define IBM_CPM_UART2	0x00000008	/* Serial Control Port */
-#define IBM_CPM_DSCR	0x00000004	/* Descrambler */
-#define IBM_CPM_VID2	0x00000002	/* Video Decoder clock domain 2 */
-#define DFLT_IBM4xx_PM	~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
-			| IBM_CPM_DMA | IBM_CPM_CBS | IBM_CPM_SDRAM0 \
-			| IBM_CPM_XPT54 | IBM_CPM_TMRCLK | IBM_CPM_XPT27 \
-			| IBM_CPM_UIC)
-#ifdef DCRN_CIC_BASE
-#define DCRN_CICCR	(DCRN_CIC_BASE + 0x0)	/* CIC Control Register */
-#define DCRN_DMAS1	(DCRN_CIC_BASE + 0x1)	/* DMA Select1 Register */
-#define DCRN_DMAS2	(DCRN_CIC_BASE + 0x2)	/* DMA Select2 Register */
-#define DCRN_CICVCR	(DCRN_CIC_BASE + 0x3)	/* CIC Video COntro Register */
-#define DCRN_CICSEL3	(DCRN_CIC_BASE + 0x5)	/* CIC Select 3 Register */
-#define DCRN_SGPO	(DCRN_CIC_BASE + 0x6)	/* CIC GPIO Output Register */
-#define DCRN_SGPOD	(DCRN_CIC_BASE + 0x7)	/* CIC GPIO OD Register */
-#define DCRN_SGPTC	(DCRN_CIC_BASE + 0x8)	/* CIC GPIO Tristate Ctrl Reg */
-#define DCRN_SGPI	(DCRN_CIC_BASE + 0x9)	/* CIC GPIO Input Reg */
-#endif
-#ifdef DCRN_DCRX_BASE
-#define DCRN_DCRXICR	(DCRN_DCRX_BASE + 0x0)	/* Internal Control Register */
-#define DCRN_DCRXISR	(DCRN_DCRX_BASE + 0x1)	/* Internal Status Register */
-#define DCRN_DCRXECR	(DCRN_DCRX_BASE + 0x2)	/* External Control Register */
-#define DCRN_DCRXESR	(DCRN_DCRX_BASE + 0x3)	/* External Status Register */
-#define DCRN_DCRXTAR	(DCRN_DCRX_BASE + 0x4)	/* Target Address Register */
-#define DCRN_DCRXTDR	(DCRN_DCRX_BASE + 0x5)	/* Target Data Register */
-#define DCRN_DCRXIGR	(DCRN_DCRX_BASE + 0x6)	/* Interrupt Generation Register */
-#define DCRN_DCRXBCR	(DCRN_DCRX_BASE + 0x7)	/* Line Buffer Control Register */
-#endif
-#ifdef DCRN_EBC_BASE
-#define DCRN_EBCCFGADR	(DCRN_EBC_BASE + 0x0)	/* Peripheral Controller Address */
-#define DCRN_EBCCFGDATA	(DCRN_EBC_BASE + 0x1)	/* Peripheral Controller Data */
-#endif
-#ifdef DCRN_EBIMC_BASE
-#define DCRN_BRCRH0	(DCRN_EBIMC_BASE + 0x0)	/* Bus Region Config High 0 */
-#define DCRN_BRCRH1	(DCRN_EBIMC_BASE + 0x1)	/* Bus Region Config High 1 */
-#define DCRN_BRCRH2	(DCRN_EBIMC_BASE + 0x2)	/* Bus Region Config High 2 */
-#define DCRN_BRCRH3	(DCRN_EBIMC_BASE + 0x3)	/* Bus Region Config High 3 */
-#define DCRN_BRCRH4	(DCRN_EBIMC_BASE + 0x4)	/* Bus Region Config High 4 */
-#define DCRN_BRCRH5	(DCRN_EBIMC_BASE + 0x5)	/* Bus Region Config High 5 */
-#define DCRN_BRCRH6	(DCRN_EBIMC_BASE + 0x6)	/* Bus Region Config High 6 */
-#define DCRN_BRCRH7	(DCRN_EBIMC_BASE + 0x7)	/* Bus Region Config High 7 */
-#define DCRN_BRCR0	(DCRN_EBIMC_BASE + 0x10)	/* BRC 0 */
-#define DCRN_BRCR1	(DCRN_EBIMC_BASE + 0x11)	/* BRC 1 */
-#define DCRN_BRCR2	(DCRN_EBIMC_BASE + 0x12)	/* BRC 2 */
-#define DCRN_BRCR3	(DCRN_EBIMC_BASE + 0x13)	/* BRC 3 */
-#define DCRN_BRCR4	(DCRN_EBIMC_BASE + 0x14)	/* BRC 4 */
-#define DCRN_BRCR5	(DCRN_EBIMC_BASE + 0x15)	/* BRC 5 */
-#define DCRN_BRCR6	(DCRN_EBIMC_BASE + 0x16)	/* BRC 6 */
-#define DCRN_BRCR7	(DCRN_EBIMC_BASE + 0x17)	/* BRC 7 */
-#define DCRN_BEAR0	(DCRN_EBIMC_BASE + 0x20)	/* Bus Error Address Register */
-#define DCRN_BESR0	(DCRN_EBIMC_BASE + 0x21)	/* Bus Error Status Register */
-#define DCRN_BIUCR	(DCRN_EBIMC_BASE + 0x2A)	/* Bus Interfac Unit Ctrl Reg */
-#endif
-#ifdef DCRN_SCCR_BASE
-#define DCRN_SCCR	(DCRN_SCCR_BASE + 0x0)
-#endif
-#ifdef DCRN_SDRAM0_BASE
-#define DCRN_SDRAM0_CFGADDR	(DCRN_SDRAM0_BASE + 0x0)	/* Memory Controller Address */
-#define DCRN_SDRAM0_CFGDATA	(DCRN_SDRAM0_BASE + 0x1)	/* Memory Controller Data */
-#endif
-#ifdef DCRN_OCM0_BASE
-#define DCRN_OCMISARC	(DCRN_OCM0_BASE + 0x0)	/* OCM Instr Side Addr Range Compare */
-#define DCRN_OCMISCR	(DCRN_OCM0_BASE + 0x1)	/* OCM Instr Side Control */
-#define DCRN_OCMDSARC	(DCRN_OCM0_BASE + 0x2)	/* OCM Data Side Addr Range Compare */
-#define DCRN_OCMDSCR	(DCRN_OCM0_BASE + 0x3)	/* OCM Data Side Control */
-#endif
-#include <asm/ibm405.h>
-#endif				/* __ASM_IBMSTBX_H__ */
-#endif				/* __KERNEL__ */
--- a/arch/ppc/platforms/4xx/oak_setup.c
+++ b/arch/ppc/platforms/4xx/oak_setup.c
@@ -2,7 +2,7 @@
 *
 *    Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
 *
- *    Module name: oak_setup.c
+ *    Module name: oak.c
 *
 *    Description:
 *      Architecture- / platform-specific boot-time initialization code for
@@ -29,7 +29,7 @@
 #include <asm/ppc4xx_pic.h>
 #include <asm/time.h>
-#include "oak_setup.h"
+#include "oak.h"
 /* Function Prototypes */

--- a/arch/ppc/platforms/4xx/oak.h
+++ b/arch/ppc/platforms/4xx/oak.h
@@ -60,6 +60,31 @@ typedef struct board_info {
 	unsigned int	 bi_busfreq;		/* Bus speed, in Hz */
 } bd_t;
+#ifdef __cplusplus
+extern "C" {
+#endif
+extern void		 oak_init(unsigned long r3,
+				  unsigned long ird_start,
+				  unsigned long ird_end,
+				  unsigned long cline_start,
+				  unsigned long cline_end);
+extern void		 oak_setup_arch(void);
+extern int		 oak_setup_residual(char *buffer);
+extern void		 oak_init_IRQ(void);
+extern int		 oak_get_irq(struct pt_regs *regs);
+extern void		 oak_restart(char *cmd);
+extern void		 oak_power_off(void);
+extern void		 oak_halt(void);
+extern void		 oak_time_init(void);
+extern int		 oak_set_rtc_time(unsigned long now);
+extern unsigned long	 oak_get_rtc_time(void);
+extern void		 oak_calibrate_decr(void);
+#ifdef __cplusplus
+}
+#endif
 /* Some 4xx parts use a different timebase frequency from the internal clock.
 */
 #define bi_tbfreq bi_intfreq

--- a/arch/ppc/platforms/4xx/redwood.c
+++ b/arch/ppc/platforms/4xx/redwood.c
-/*
- * arch/ppc/platforms/4xx/redwood.c
- *
- * Author: Frank Rowand <frank_rowand@mvista.com>, or source@mvista.com
- *
- * 2000-2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <asm/pgtable.h>
-#include <asm/ibm4xx.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-void __init
-redwood_setup_arch(void)
-{
-	ppc4xx_setup_arch();
-#ifdef CONFIG_IDE
-	void *xilinx, *xilinx_1, *xilinx_2;
-	unsigned short reg5;
-	xilinx = ioremap(IDE_XLINUX_MUX_BASE, 0x10);
-	/* init xilinx control registers - enable ide mux, clear reset bit */
-	if (!xilinx) {
-		printk(KERN_CRIT
-		       "redwood4_setup_arch() xilinx ioremap failed\n");
-		return;
-	}
-	xilinx_1 = xilinx;
-	xilinx_2 = xilinx + 0xe;
-	reg5 = readw(xilinx_1);
-	writeb(reg5 |= ~(0x8001), xilinx_1);
-	writeb(0, xilinx_2);
-	udelay(10 * 1000);
-	writeb(reg5 & 0x8001, xilinx_1);
-	writeb(0, xilinx_2);
-       	/* add RE & OEN to value set by boot rom */
-        mtdcr(DCRN_BRCR3, 0x407cfffe);
-#endif
-}
-void __init
-redwood_map_io(void)
-{
-	int i;
-	ppc4xx_map_io();
-	io_block_mapping(OAKNET_IO_VADDR,
-			 OAKNET_IO_PADDR, OAKNET_IO_SIZE, _PAGE_IO);
-}
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-	ppc_md.setup_arch = redwood_setup_arch;
-	ppc_md.setup_io_mappings = redwood_map_io;
-}
--- a/arch/ppc/platforms/4xx/redwood.h
+++ b/arch/ppc/platforms/4xx/redwood.h
-/*
- * arch/ppc/platforms/4xx/redwood.h
- *
- * Macros, definitions, and data structures specific to the IBM PowerPC
- * STB03xxx "Redwood" evaluation board.
- *
- * Author: Frank Rowand <frank_rowand@mvista.com>, or source@mvista.com
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_REDWOOD_H__
-#define __ASM_REDWOOD_H__
-/* Redwoods have an STB03xxx or STB04xxx core */
-#include <platforms/4xx/ibmstb3.h>
-#ifndef __ASSEMBLY__
-typedef struct board_info {
-	unsigned char	bi_s_version[4];	/* Version of this structure */
-	unsigned char	bi_r_version[30];	/* Version of the IBM ROM */
-	unsigned int	bi_memsize;		/* DRAM installed, in bytes */
-	unsigned int	bi_dummy;		/* field shouldn't exist */
-	unsigned char	bi_enetaddr[6];		/* Ethernet MAC address */
-	unsigned int	bi_intfreq;		/* Processor speed, in Hz */
-	unsigned int	bi_busfreq;		/* Bus speed, in Hz */
-} bd_t;
-#define bi_tbfreq bi_intfreq
-#endif /* !__ASSEMBLY__ */
-#define bi_tbfreq bi_intfreq
-#define OAKNET_IO_PADDR		((uint)0xf2000000)
-#define OAKNET_IO_VADDR		OAKNET_IO_PADDR
-#define OAKNET_IO_BASE		OAKNET_IO_VADDR
-/* ftr revisit- io size was 0xffff in old-line, is 0x40 in oak.h */
-#define OAKNET_IO_SIZE		0xffff
-#define OAKNET_INT		26	/* EXTINT1 */
-#define IDE_XLINUX_MUX_BASE        0xf2040000
-#define IDE_DMA_ADDR	0xfce00000
-#define _IO_BASE	0
-#define _ISA_MEM_BASE	0
-#define PCI_DRAM_OFFSET	0
-#define BASE_BAUD		(378000000 / 18 / 16)
-#define PPC4xx_MACHINE_NAME	"IBM Redwood"
-#endif /* __ASM_REDWOOD_H__ */
-#endif /* __KERNEL__ */
--- a/arch/ppc/syslib/ppc4xx_setup.c
+++ b/arch/ppc/syslib/ppc4xx_setup.c
@@ -170,7 +170,7 @@ ppc4xx_calibrate_decr(void)
 	unsigned int freq;
 	bd_t *bip = &__res;
-#if defined(CONFIG_WALNUT) || defined(CONFIG_CEDER)|| defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE)
+#if defined(CONFIG_WALNUT) || defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE)
 	/* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */
 	mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
 #endif