Commit 8b0860ec authored by Bartosz Golaszewski's avatar Bartosz Golaszewski Committed by Sekhar Nori

ARM: davinci: aintc: remove the timer-specific irq_set_handler()

I've been unable to figure out exactly why, but the IRQ_TINT1_TINT34
interrupt is being handled as level irq and it's configured in the
irq chip driver instead of set by the irq_set_type() callback.

Since this is probably some legacy hack for out-of-tree code - remove it.
Signed-off-by: default avatarBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
parent 882bed72
...@@ -18,8 +18,6 @@ ...@@ -18,8 +18,6 @@
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/exception.h> #include <asm/exception.h>
#include "irqs.h"
#define DAVINCI_AINTC_FIQ_REG0 0x00 #define DAVINCI_AINTC_FIQ_REG0 0x00
#define DAVINCI_AINTC_FIQ_REG1 0x04 #define DAVINCI_AINTC_FIQ_REG1 0x04
#define DAVINCI_AINTC_IRQ_REG0 0x08 #define DAVINCI_AINTC_IRQ_REG0 0x08
...@@ -165,6 +163,5 @@ void __init davinci_aintc_init(const struct davinci_aintc_config *config) ...@@ -165,6 +163,5 @@ void __init davinci_aintc_init(const struct davinci_aintc_config *config)
davinci_aintc_setup_gc(davinci_aintc_base + reg_off, davinci_aintc_setup_gc(davinci_aintc_base + reg_off,
irq_base + irq_off, 32); irq_base + irq_off, 32);
irq_set_handler(DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34), handle_level_irq);
set_handle_irq(davinci_aintc_handle_irq); set_handle_irq(davinci_aintc_handle_irq);
} }
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