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Commit 8c17e55a authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk 

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents 65d33ad6 53797196
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Showing with 499 additions and 161 deletions
arch/arm/boot/compressed/head-clps7500.S
View file @ 8c17e55a
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
mov r0, #0x30 mov r0, #0x30
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
mov r0, #0x13 mov r0, #0x13
msr cpsr, r0 msr cpsr_cxsf, r0
mov r12, #0x03000000 @ point to LEDs mov r12, #0x03000000 @ point to LEDs
orr r12, r12, #0x00020000 orr r12, r12, #0x00020000
orr r12, r12, #0xba00 orr r12, r12, #0xba00
...@@ -71,7 +71,7 @@ ...@@ -71,7 +71,7 @@
/* Ensure all interrupts are off and MMU disabled */ /* Ensure all interrupts are off and MMU disabled */
mrs r0, cpsr mrs r0, cpsr
orr r0, r0, #0xc0 orr r0, r0, #0xc0
msr cpsr, r0 msr cpsr_cxsf, r0
adr lr, 1b adr lr, 1b
orr lr, lr, #0x10000000 orr lr, lr, #0x10000000
......
arch/arm/configs/bast_defconfig
View file @ 8c17e55a
...@@ -20,17 +20,24 @@ CONFIG_BROKEN_ON_SMP=y ...@@ -20,17 +20,24 @@ CONFIG_BROKEN_ON_SMP=y
# #
CONFIG_SWAP=y CONFIG_SWAP=y
CONFIG_SYSVIPC=y CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=16 # CONFIG_AUDIT is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_HOTPLUG is not set
# CONFIG_IKCONFIG is not set # CONFIG_IKCONFIG is not set
# CONFIG_EMBEDDED is not set # CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_FUTEX=y CONFIG_FUTEX=y
CONFIG_EPOLL=y CONFIG_EPOLL=y
CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# #
# Loadable module support # Loadable module support
...@@ -44,57 +51,32 @@ CONFIG_KMOD=y ...@@ -44,57 +51,32 @@ CONFIG_KMOD=y
# #
# System Type # System Type
# #
# CONFIG_ARCH_ADIFCC is not set
# CONFIG_ARCH_ANAKIN is not set
# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_CAMELOT is not set # CONFIG_ARCH_CAMELOT is not set
# CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_IOP3XX is not set # CONFIG_ARCH_IOP3XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set # CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_SHARK is not set
CONFIG_ARCH_S3C2410=y CONFIG_ARCH_S3C2410=y
# CONFIG_ARCH_SHARK is not set
# # CONFIG_ARCH_LH7A40X is not set
# CLPS711X/EP721X Implementations # CONFIG_ARCH_OMAP is not set
# # CONFIG_ARCH_VERSATILE_PB is not set
#
# Epxa10db
#
#
# Footbridge Implementations
#
#
# IOP3xx Implementation Options
#
# CONFIG_ARCH_IOP310 is not set
# CONFIG_ARCH_IOP321 is not set
#
# IOP3xx Chipset Features
#
#
# Intel PXA250/210 Implementations
#
#
# SA11x0 Implementations
#
# #
# S3C2410 Implementations # S3C2410 Implementations
# #
CONFIG_ARCH_BAST=y CONFIG_ARCH_BAST=y
# CONFIG_ARCH_H1940 is not set
# CONFIG_ARCH_SMDK2410 is not set
CONFIG_MACH_VR1000=y
# #
# Processor Type # Processor Type
...@@ -119,9 +101,8 @@ CONFIG_CPU_TLB_V4WBI=y ...@@ -119,9 +101,8 @@ CONFIG_CPU_TLB_V4WBI=y
# General setup # General setup
# #
# CONFIG_ZBOOT_ROM is not set # CONFIG_ZBOOT_ROM is not set
CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0 CONFIG_ZBOOT_ROM_BSS=0x0
# CONFIG_HOTPLUG is not set
# #
# At least one math emulation must be selected # At least one math emulation must be selected
...@@ -129,6 +110,7 @@ CONFIG_ZBOOT_ROM_BSS=0 ...@@ -129,6 +110,7 @@ CONFIG_ZBOOT_ROM_BSS=0
CONFIG_FPE_NWFPE=y CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y CONFIG_FPE_NWFPE_XP=y
# CONFIG_FPE_FASTFPE is not set # CONFIG_FPE_FASTFPE is not set
# CONFIG_VFP is not set
CONFIG_BINFMT_ELF=y CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_AOUT=y CONFIG_BINFMT_AOUT=y
# CONFIG_BINFMT_MISC is not set # CONFIG_BINFMT_MISC is not set
...@@ -136,9 +118,13 @@ CONFIG_BINFMT_AOUT=y ...@@ -136,9 +118,13 @@ CONFIG_BINFMT_AOUT=y
# #
# Generic Driver Options # Generic Driver Options
# #
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_PM is not set # CONFIG_PM is not set
# CONFIG_PREEMPT is not set # CONFIG_PREEMPT is not set
# CONFIG_ARTHUR is not set # CONFIG_ARTHUR is not set
CONFIG_S3C2410_DMA=y
# CONFIG_S3C2410_DMA_DEBUG is not set
CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0" CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
CONFIG_ALIGNMENT_TRAP=y CONFIG_ALIGNMENT_TRAP=y
...@@ -148,7 +134,6 @@ CONFIG_ALIGNMENT_TRAP=y ...@@ -148,7 +134,6 @@ CONFIG_ALIGNMENT_TRAP=y
CONFIG_PARPORT=y CONFIG_PARPORT=y
CONFIG_PARPORT_PC=y CONFIG_PARPORT_PC=y
CONFIG_PARPORT_PC_CML1=y CONFIG_PARPORT_PC_CML1=y
# CONFIG_PARPORT_SERIAL is not set
CONFIG_PARPORT_PC_FIFO=y CONFIG_PARPORT_PC_FIFO=y
CONFIG_PARPORT_PC_SUPERIO=y CONFIG_PARPORT_PC_SUPERIO=y
# CONFIG_PARPORT_ARC is not set # CONFIG_PARPORT_ARC is not set
...@@ -217,7 +202,6 @@ CONFIG_MTD_CFI_INTELEXT=y ...@@ -217,7 +202,6 @@ CONFIG_MTD_CFI_INTELEXT=y
# #
# Plug and Play support # Plug and Play support
# #
# CONFIG_PNP is not set
# #
# Block devices # Block devices
...@@ -258,23 +242,21 @@ CONFIG_IP_PNP_BOOTP=y ...@@ -258,23 +242,21 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_NET_IPIP is not set # CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set # CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set # CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set # CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set # CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set # CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set # CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set # CONFIG_IPV6 is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_NETFILTER is not set # CONFIG_NETFILTER is not set
# #
# SCTP Configuration (EXPERIMENTAL) # SCTP Configuration (EXPERIMENTAL)
# #
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set # CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set # CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set # CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set # CONFIG_LLC2 is not set
# CONFIG_IPX is not set # CONFIG_IPX is not set
# CONFIG_ATALK is not set # CONFIG_ATALK is not set
...@@ -290,11 +272,17 @@ CONFIG_IPV6_SCTP__=y ...@@ -290,11 +272,17 @@ CONFIG_IPV6_SCTP__=y
# QoS and/or fair queueing # QoS and/or fair queueing
# #
# CONFIG_NET_SCHED is not set # CONFIG_NET_SCHED is not set
# CONFIG_NET_CLS_ROUTE is not set
# #
# Network testing # Network testing
# #
# CONFIG_NET_PKTGEN is not set # CONFIG_NET_PKTGEN is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set # CONFIG_DUMMY is not set
# CONFIG_BONDING is not set # CONFIG_BONDING is not set
...@@ -315,40 +303,25 @@ CONFIG_NET_ETHERNET=y ...@@ -315,40 +303,25 @@ CONFIG_NET_ETHERNET=y
# #
# Ethernet (10000 Mbit) # Ethernet (10000 Mbit)
# #
# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# #
# Wireless LAN (non-hamradio) # Token Ring devices
# #
# CONFIG_NET_RADIO is not set
# CONFIG_HOSTAP is not set
# #
# Token Ring devices # Wireless LAN (non-hamradio)
# #
# CONFIG_SHAPER is not set # CONFIG_NET_RADIO is not set
# #
# Wan interfaces # Wan interfaces
# #
# CONFIG_WAN is not set # CONFIG_WAN is not set
# CONFIG_PLIP is not set
# # CONFIG_PPP is not set
# Amateur Radio support # CONFIG_SLIP is not set
# # CONFIG_SHAPER is not set
# CONFIG_HAMRADIO is not set # CONFIG_NETCONSOLE is not set
#
# IrDA (infrared) support
#
# CONFIG_IRDA is not set
#
# Bluetooth support
#
# CONFIG_BT is not set
# #
# ATA/ATAPI/MFM/RLL support # ATA/ATAPI/MFM/RLL support
...@@ -359,9 +332,9 @@ CONFIG_BLK_DEV_IDE=y ...@@ -359,9 +332,9 @@ CONFIG_BLK_DEV_IDE=y
# #
# Please see Documentation/ide.txt for help/info on IDE drives # Please see Documentation/ide.txt for help/info on IDE drives
# #
# CONFIG_BLK_DEV_IDE_SATA is not set
CONFIG_BLK_DEV_IDEDISK=y CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set # CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_IDEDISK_STROKE is not set
CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD=y
CONFIG_BLK_DEV_IDETAPE=m CONFIG_BLK_DEV_IDETAPE=m
CONFIG_BLK_DEV_IDEFLOPPY=m CONFIG_BLK_DEV_IDEFLOPPY=m
...@@ -371,10 +344,10 @@ CONFIG_BLK_DEV_IDEFLOPPY=m ...@@ -371,10 +344,10 @@ CONFIG_BLK_DEV_IDEFLOPPY=m
# #
# IDE chipset support/bugfixes # IDE chipset support/bugfixes
# #
CONFIG_BLK_DEV_IDE_BAST=y CONFIG_IDE_GENERIC=y
# CONFIG_IDE_ARM is not set
# CONFIG_BLK_DEV_IDEDMA is not set # CONFIG_BLK_DEV_IDEDMA is not set
# CONFIG_IDEDMA_AUTO is not set # CONFIG_IDEDMA_AUTO is not set
# CONFIG_DMA_NONPCI is not set
# CONFIG_BLK_DEV_HD is not set # CONFIG_BLK_DEV_HD is not set
# #
...@@ -382,6 +355,15 @@ CONFIG_BLK_DEV_IDE_BAST=y ...@@ -382,6 +355,15 @@ CONFIG_BLK_DEV_IDE_BAST=y
# #
# CONFIG_SCSI is not set # CONFIG_SCSI is not set
#
# Fusion MPT device support
#
#
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
# #
# I2O device support # I2O device support
# #
...@@ -389,7 +371,7 @@ CONFIG_BLK_DEV_IDE_BAST=y ...@@ -389,7 +371,7 @@ CONFIG_BLK_DEV_IDE_BAST=y
# #
# ISDN subsystem # ISDN subsystem
# #
# CONFIG_ISDN_BOOL is not set # CONFIG_ISDN is not set
# #
# Input device support # Input device support
...@@ -405,7 +387,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ...@@ -405,7 +387,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_TSLIBDEV is not set
# CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set # CONFIG_INPUT_EVBUG is not set
...@@ -415,7 +396,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ...@@ -415,7 +396,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_GAMEPORT is not set # CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y CONFIG_SERIO=y
CONFIG_SERIO_I8042=y # CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PARKBD is not set # CONFIG_SERIO_PARKBD is not set
...@@ -424,14 +405,15 @@ CONFIG_SERIO_SERPORT=y ...@@ -424,14 +405,15 @@ CONFIG_SERIO_SERPORT=y
# Input Device Drivers # Input Device Drivers
# #
CONFIG_INPUT_KEYBOARD=y CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_NEWTON is not set
CONFIG_INPUT_MOUSE=y CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2=y
# CONFIG_MOUSE_PS2_SYNAPTICS is not set
# CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set # CONFIG_INPUT_MISC is not set
...@@ -478,15 +460,40 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y ...@@ -478,15 +460,40 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
# #
CONFIG_SERIAL_S3C2410=y CONFIG_SERIAL_S3C2410=y
CONFIG_SERIAL_S3C2410_CONSOLE=y CONFIG_SERIAL_S3C2410_CONSOLE=y
# CONFIG_SERIAL_DZ is not set # CONFIG_SERIAL_BAST_SIO is not set
CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256 CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_PRINTER=y CONFIG_PRINTER=y
# CONFIG_LP_CONSOLE is not set # CONFIG_LP_CONSOLE is not set
CONFIG_PPDEV=y CONFIG_PPDEV=y
# CONFIG_TIPAR is not set # CONFIG_TIPAR is not set
# CONFIG_QIC02_TAPE is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
CONFIG_RTC=y
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# #
# I2C support # I2C support
...@@ -505,55 +512,44 @@ CONFIG_I2C_ALGOBIT=m ...@@ -505,55 +512,44 @@ CONFIG_I2C_ALGOBIT=m
# #
# CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_PHILIPSPAR is not set # CONFIG_I2C_ISA is not set
# CONFIG_I2C_PARPORT is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_SCx200_ACB is not set # CONFIG_SCx200_ACB is not set
# #
# I2C Hardware Sensors Chip support # Hardware Sensors Chip support
# #
CONFIG_I2C_SENSOR=m CONFIG_I2C_SENSOR=m
# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1021 is not set
CONFIG_SENSORS_EEPROM=m # CONFIG_SENSORS_ASB100 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_FSCHER is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_IT87 is not set
CONFIG_SENSORS_LM75=m CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM78=m CONFIG_SENSORS_LM78=m
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
CONFIG_SENSORS_LM85=m CONFIG_SENSORS_LM85=m
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83627HF is not set
# #
# L3 serial bus support # Other I2C Chip support
#
# CONFIG_L3 is not set
#
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# IPMI
# #
# CONFIG_IPMI_HANDLER is not set CONFIG_SENSORS_EEPROM=m
# CONFIG_SENSORS_PCF8574 is not set
# # CONFIG_SENSORS_PCF8591 is not set
# Watchdog Cards # CONFIG_SENSORS_RTC8564 is not set
# # CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_WATCHDOG is not set # CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_NVRAM is not set # CONFIG_I2C_DEBUG_BUS is not set
CONFIG_RTC=y # CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# #
# Multimedia devices # Multimedia devices
...@@ -565,11 +561,6 @@ CONFIG_RTC=y ...@@ -565,11 +561,6 @@ CONFIG_RTC=y
# #
# CONFIG_DVB is not set # CONFIG_DVB is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
# #
# File systems # File systems
# #
...@@ -603,14 +594,16 @@ CONFIG_ROMFS_FS=y ...@@ -603,14 +594,16 @@ CONFIG_ROMFS_FS=y
CONFIG_FAT_FS=y CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set # CONFIG_NTFS_FS is not set
# #
# Pseudo filesystems # Pseudo filesystems
# #
CONFIG_PROC_FS=y CONFIG_PROC_FS=y
CONFIG_SYSFS=y
# CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
# CONFIG_DEVPTS_FS_XATTR is not set # CONFIG_DEVPTS_FS_XATTR is not set
# CONFIG_TMPFS is not set # CONFIG_TMPFS is not set
# CONFIG_HUGETLBFS is not set # CONFIG_HUGETLBFS is not set
...@@ -623,6 +616,7 @@ CONFIG_RAMFS=y ...@@ -623,6 +616,7 @@ CONFIG_RAMFS=y
# CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set # CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set # CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set # CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set # CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set # CONFIG_EFS_FS is not set
...@@ -650,12 +644,11 @@ CONFIG_ROOT_NFS=y ...@@ -650,12 +644,11 @@ CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y CONFIG_LOCKD=y
# CONFIG_EXPORTFS is not set # CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set # CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_SMB_FS is not set # CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set # CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set # CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set # CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set # CONFIG_AFS_FS is not set
# #
...@@ -679,16 +672,15 @@ CONFIG_BSD_DISKLABEL=y ...@@ -679,16 +672,15 @@ CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y CONFIG_SOLARIS_X86_PARTITION=y
# CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set # CONFIG_LDM_PARTITION is not set
# CONFIG_NEC98_PARTITION is not set
# CONFIG_SGI_PARTITION is not set # CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set # CONFIG_SUN_PARTITION is not set
# CONFIG_EFI_PARTITION is not set # CONFIG_EFI_PARTITION is not set
CONFIG_NLS=y
# #
# Native Language Support # Native Language Support
# #
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set # CONFIG_NLS_CODEPAGE_437 is not set
# CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_737 is not set
...@@ -713,6 +705,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" ...@@ -713,6 +705,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set # CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_3 is not set
...@@ -728,6 +721,11 @@ CONFIG_NLS_DEFAULT="iso8859-1" ...@@ -728,6 +721,11 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set # CONFIG_NLS_UTF8 is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
# #
# Graphics support # Graphics support
# #
...@@ -748,21 +746,20 @@ CONFIG_DUMMY_CONSOLE=y ...@@ -748,21 +746,20 @@ CONFIG_DUMMY_CONSOLE=y
# CONFIG_LOGO is not set # CONFIG_LOGO is not set
# #
# Misc devices # Sound
# #
# CONFIG_SOUND is not set
# #
# Multimedia Capabilities Port drivers # Misc devices
# #
# CONFIG_MCP is not set
# #
# Console Switches # USB support
# #
# CONFIG_SWITCHES is not set
# #
# USB support # USB Gadget Support
# #
# CONFIG_USB_GADGET is not set # CONFIG_USB_GADGET is not set
...@@ -780,7 +777,7 @@ CONFIG_DEBUG_KERNEL=y ...@@ -780,7 +777,7 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_ERRORS is not set # CONFIG_DEBUG_ERRORS is not set
CONFIG_DEBUG_LL=y CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_PRINTK=y # CONFIG_DEBUG_ICEDCC is not set
CONFIG_DEBUG_S3C2410_PORT=y CONFIG_DEBUG_S3C2410_PORT=y
CONFIG_DEBUG_S3C2410_UART=0 CONFIG_DEBUG_S3C2410_UART=0
...@@ -797,6 +794,8 @@ CONFIG_DEBUG_S3C2410_UART=0 ...@@ -797,6 +794,8 @@ CONFIG_DEBUG_S3C2410_UART=0
# #
# Library routines # Library routines
# #
# CONFIG_CRC_CCITT is not set
CONFIG_CRC32=y CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_DEFLATE=y
arch/arm/kernel/entry-armv.S
View file @ 8c17e55a
...@@ -952,7 +952,7 @@ __dabt_svc: sub sp, sp, #S_FRAME_SIZE ...@@ -952,7 +952,7 @@ __dabt_svc: sub sp, sp, #S_FRAME_SIZE
bl do_DataAbort bl do_DataAbort
disable_irq r0 disable_irq r0
ldr r0, [sp, #S_PSR] ldr r0, [sp, #S_PSR]
msr spsr, r0 msr spsr_cxsf, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
.align 5 .align 5
...@@ -988,7 +988,7 @@ preempt_return: ...@@ -988,7 +988,7 @@ preempt_return:
strne r0, [r0, -r0] @ bug() strne r0, [r0, -r0] @ bug()
#endif #endif
ldr r0, [sp, #S_PSR] @ irqs are already disabled ldr r0, [sp, #S_PSR] @ irqs are already disabled
msr spsr, r0 msr spsr_cxsf, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
.ltorg .ltorg
...@@ -1031,7 +1031,7 @@ __und_svc: sub sp, sp, #S_FRAME_SIZE ...@@ -1031,7 +1031,7 @@ __und_svc: sub sp, sp, #S_FRAME_SIZE
1: disable_irq r0 1: disable_irq r0
ldr lr, [sp, #S_PSR] @ Get SVC cpsr ldr lr, [sp, #S_PSR] @ Get SVC cpsr
msr spsr, lr msr spsr_cxsf, lr
ldmia sp, {r0 - pc}^ @ Restore SVC registers ldmia sp, {r0 - pc}^ @ Restore SVC registers
.align 5 .align 5
...@@ -1052,7 +1052,7 @@ __pabt_svc: sub sp, sp, #S_FRAME_SIZE ...@@ -1052,7 +1052,7 @@ __pabt_svc: sub sp, sp, #S_FRAME_SIZE
bl do_PrefetchAbort @ call abort handler bl do_PrefetchAbort @ call abort handler
disable_irq r0 disable_irq r0
ldr r0, [sp, #S_PSR] ldr r0, [sp, #S_PSR]
msr spsr, r0 msr spsr_cxsf, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
.align 5 .align 5
...@@ -1303,7 +1303,7 @@ vector_IRQ: @ ...@@ -1303,7 +1303,7 @@ vector_IRQ: @
mrs r13, cpsr mrs r13, cpsr
bic r13, r13, #MODE_MASK bic r13, r13, #MODE_MASK
orr r13, r13, #MODE_SVC orr r13, r13, #MODE_SVC
msr spsr, r13 @ switch to SVC_32 mode msr spsr_cxsf, r13 @ switch to SVC_32 mode
and lr, lr, #15 and lr, lr, #15
ldr lr, [pc, lr, lsl #2] ldr lr, [pc, lr, lsl #2]
...@@ -1346,7 +1346,7 @@ vector_data: @ ...@@ -1346,7 +1346,7 @@ vector_data: @
mrs r13, cpsr mrs r13, cpsr
bic r13, r13, #MODE_MASK bic r13, r13, #MODE_MASK
orr r13, r13, #MODE_SVC orr r13, r13, #MODE_SVC
msr spsr, r13 @ switch to SVC_32 mode msr spsr_cxsf, r13 @ switch to SVC_32 mode
and lr, lr, #15 and lr, lr, #15
ldr lr, [pc, lr, lsl #2] ldr lr, [pc, lr, lsl #2]
...@@ -1390,7 +1390,7 @@ vector_prefetch: ...@@ -1390,7 +1390,7 @@ vector_prefetch:
mrs r13, cpsr mrs r13, cpsr
bic r13, r13, #MODE_MASK bic r13, r13, #MODE_MASK
orr r13, r13, #MODE_SVC orr r13, r13, #MODE_SVC
msr spsr, r13 @ switch to SVC_32 mode msr spsr_cxsf, r13 @ switch to SVC_32 mode
ands lr, lr, #15 ands lr, lr, #15
ldr lr, [pc, lr, lsl #2] ldr lr, [pc, lr, lsl #2]
...@@ -1433,7 +1433,7 @@ vector_undefinstr: ...@@ -1433,7 +1433,7 @@ vector_undefinstr:
mrs r13, cpsr mrs r13, cpsr
bic r13, r13, #MODE_MASK bic r13, r13, #MODE_MASK
orr r13, r13, #MODE_SVC orr r13, r13, #MODE_SVC
msr spsr, r13 @ switch to SVC_32 mode msr spsr_cxsf, r13 @ switch to SVC_32 mode
and lr, lr, #15 and lr, lr, #15
ldr lr, [pc, lr, lsl #2] ldr lr, [pc, lr, lsl #2]
......
arch/arm/kernel/entry-common.S
View file @ 8c17e55a
...@@ -102,7 +102,7 @@ ENTRY(ret_from_fork) ...@@ -102,7 +102,7 @@ ENTRY(ret_from_fork)
ldr r0, [sp, #S_PSR] @ Get calling cpsr ldr r0, [sp, #S_PSR] @ Get calling cpsr
sub lr, lr, #4 sub lr, lr, #4
str lr, [r8] str lr, [r8]
msr spsr, r0 msr spsr_cxsf, r0
ldmia sp, {r0 - lr}^ @ Get calling r0 - lr ldmia sp, {r0 - lr}^ @ Get calling r0 - lr
mov r0, r0 mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC ldr lr, [sp, #S_PC] @ Get PC
......
arch/arm/kernel/entry-header.S
View file @ 8c17e55a
...@@ -99,7 +99,7 @@ ...@@ -99,7 +99,7 @@
ldr r1, [sp, #S_PSR] @ Get calling cpsr ldr r1, [sp, #S_PSR] @ Get calling cpsr
disable_irq ip @ disable IRQs disable_irq ip @ disable IRQs
ldr lr, [sp, #S_PC]! @ Get PC ldr lr, [sp, #S_PC]! @ Get PC
msr spsr, r1 @ save in spsr_svc msr spsr_cxsf, r1 @ save in spsr_svc
ldmdb sp, {r0 - lr}^ @ Get calling r0 - lr ldmdb sp, {r0 - lr}^ @ Get calling r0 - lr
mov r0, r0 mov r0, r0
add sp, sp, #S_FRAME_SIZE - S_PC add sp, sp, #S_FRAME_SIZE - S_PC
...@@ -112,7 +112,7 @@ ...@@ -112,7 +112,7 @@
.macro fast_restore_user_regs .macro fast_restore_user_regs
ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr
ldr lr, [sp, #S_OFF + S_PC]! @ get pc ldr lr, [sp, #S_OFF + S_PC]! @ get pc
msr spsr, r1 @ save in spsr_svc msr spsr_cxsf, r1 @ save in spsr_svc
ldmdb sp, {r1 - lr}^ @ get calling r1 - lr ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
mov r0, r0 mov r0, r0
add sp, sp, #S_FRAME_SIZE - S_PC add sp, sp, #S_FRAME_SIZE - S_PC
...@@ -125,7 +125,7 @@ ...@@ -125,7 +125,7 @@
.macro slow_restore_user_regs .macro slow_restore_user_regs
ldr r1, [sp, #S_PSR] @ get calling cpsr ldr r1, [sp, #S_PSR] @ get calling cpsr
ldr lr, [sp, #S_PC]! @ get pc ldr lr, [sp, #S_PC]! @ get pc
msr spsr, r1 @ save in spsr_svc msr spsr_cxsf, r1 @ save in spsr_svc
ldmdb sp, {r0 - lr}^ @ get calling r1 - lr ldmdb sp, {r0 - lr}^ @ get calling r1 - lr
mov r0, r0 mov r0, r0
add sp, sp, #S_FRAME_SIZE - S_PC add sp, sp, #S_FRAME_SIZE - S_PC
......
arch/arm/lib/ecard.S
View file @ 8c17e55a
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
#define CPSR2SPSR(rt) \ #define CPSR2SPSR(rt) \
mrs rt, cpsr; \ mrs rt, cpsr; \
msr spsr, rt msr spsr_cxsf, rt
@ Purpose: call an expansion card loader to read bytes. @ Purpose: call an expansion card loader to read bytes.
@ Proto : char read_loader(int offset, char *card_base, char *loader); @ Proto : char read_loader(int offset, char *card_base, char *loader);
......
arch/arm/mach-s3c2410/Makefile
View file @ 8c17e55a
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
# Object file lists. # Object file lists.
obj-y := s3c2410.o irq.o time.o obj-y := s3c2410.o irq.o time.o gpio.o
obj-m := obj-m :=
obj-n := obj-n :=
obj- := obj- :=
......
arch/arm/mach-s3c2410/gpio.c 0 → 100644
View file @ 8c17e55a
/* linux/arch/arm/mach-s3c2410/gpio.c
*
* Copyright (c) 2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 GPIO support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/arch/regs-gpio.h>
void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
{
unsigned long base = S3C2410_GPIO_BASE(pin);
unsigned long shift = 1;
unsigned long mask = 3;
unsigned long con;
unsigned long flags;
if (pin < S3C2410_GPIO_BANKB) {
shift = 0;
mask = 1;
}
mask <<= S3C2410_GPIO_OFFSET(pin);
local_irq_save(flags);
con = __raw_readl(base + 0x00);
con &= mask << shift;
con |= function;
__raw_writel(con, base + 0x00);
local_irq_restore(flags);
}
void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
{
unsigned long base = S3C2410_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
unsigned long flags;
unsigned long up;
if (pin < S3C2410_GPIO_BANKB)
return;
local_irq_save(flags);
up = __raw_readl(base + 0x08);
up &= 1 << offs;
up |= to << offs;
__raw_writel(up, base + 0x08);
local_irq_restore(flags);
}
void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
{
unsigned long base = S3C2410_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
unsigned long flags;
unsigned long dat;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= 1 << offs;
dat |= to << offs;
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
}
arch/arm/mach-s3c2410/mach-h1940.c
View file @ 8c17e55a
...@@ -52,7 +52,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = { ...@@ -52,7 +52,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = {
[0] = { [0] = {
.hwport = 0, .hwport = 0,
.flags = 0, .flags = 0,
.clock = &s3c2410_hclk, .clock = &s3c2410_pclk,
.ucon = 0x3c5, .ucon = 0x3c5,
.ulcon = 0x03, .ulcon = 0x03,
.ufcon = 0x51, .ufcon = 0x51,
...@@ -60,7 +60,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = { ...@@ -60,7 +60,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = {
[1] = { [1] = {
.hwport = 1, .hwport = 1,
.flags = 0, .flags = 0,
.clock = &s3c2410_hclk, .clock = &s3c2410_pclk,
.ucon = 0x245, .ucon = 0x245,
.ulcon = 0x03, .ulcon = 0x03,
.ufcon = 0x00, .ufcon = 0x00,
...@@ -69,7 +69,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = { ...@@ -69,7 +69,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = {
[2] = { [2] = {
.hwport = 2, .hwport = 2,
.flags = 0, .flags = 0,
.clock = &s3c2410_hclk, .clock = &s3c2410_pclk,
.ucon = 0x3c5, .ucon = 0x3c5,
.ulcon = 0x43, .ulcon = 0x43,
.ufcon = 0x51, .ufcon = 0x51,
......
arch/arm/mach-s3c2410/s3c2410.h
View file @ 8c17e55a
...@@ -4,5 +4,5 @@ extern void s3c2410_map_io(struct map_desc *, int count); ...@@ -4,5 +4,5 @@ extern void s3c2410_map_io(struct map_desc *, int count);
extern void s3c2410_init_irq(void); extern void s3c2410_init_irq(void);
extern s3c2410_init_time(void); extern void s3c2410_init_time(void);
arch/arm/mach-sa1100/collie.c
View file @ 8c17e55a
...@@ -141,4 +141,5 @@ MACHINE_START(COLLIE, "Sharp-Collie") ...@@ -141,4 +141,5 @@ MACHINE_START(COLLIE, "Sharp-Collie")
MAPIO(collie_map_io) MAPIO(collie_map_io)
INITIRQ(sa1100_init_irq) INITIRQ(sa1100_init_irq)
INIT_MACHINE(collie_init) INIT_MACHINE(collie_init)
INITTIME(sa1100_init_time)
MACHINE_END MACHINE_END
arch/arm/mm/blockops.c
View file @ 8c17e55a
...@@ -130,6 +130,7 @@ static struct undef_hook blockops_hook __initdata = { ...@@ -130,6 +130,7 @@ static struct undef_hook blockops_hook __initdata = {
static int __init blockops_check(void) static int __init blockops_check(void)
{ {
register unsigned int err asm("r4") = 0; register unsigned int err asm("r4") = 0;
unsigned int err_pos = 1;
unsigned int cache_type; unsigned int cache_type;
int i; int i;
...@@ -156,8 +157,8 @@ static int __init blockops_check(void) ...@@ -156,8 +157,8 @@ static int __init blockops_check(void)
unregister_undef_hook(&blockops_hook); unregister_undef_hook(&blockops_hook);
for (i = 0; i < ARRAY_SIZE(func); i++, err >>= 1) for (i = 0; i < ARRAY_SIZE(func); i++, err_pos <<= 1)
printk("%30s: %ssupported\n", func[i], err & 1 ? "not " : ""); printk("%30s: %ssupported\n", func[i], err & err_pos ? "not " : "");
if ((err & 8) == 0) { if ((err & 8) == 0) {
printk(" --> Using %s block cache invalidate\n", printk(" --> Using %s block cache invalidate\n",
......
include/asm-arm/arch-s3c2410/hardware.h
View file @ 8c17e55a
...@@ -26,6 +26,41 @@ extern unsigned long s3c2410_pclk; ...@@ -26,6 +26,41 @@ extern unsigned long s3c2410_pclk;
extern unsigned long s3c2410_hclk; extern unsigned long s3c2410_hclk;
extern unsigned long s3c2410_fclk; extern unsigned long s3c2410_fclk;
/* external functions for GPIO support
*
* These allow various different clients to access the same GPIO
* registers without conflicting. If your driver only owns the entire
* GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
*/
/* s3c2410_gpio_cfgpin
*
* set the configuration of the given pin to the value passed.
*
* eg:
* s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
* s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
*/
extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
/* s3c2410_gpio_pullup
*
* configure the pull-up control on the given pin
*
* to = 1 => disable the pull-up
* 0 => enable the pull-up
*
* eg;
*
* s3c2410_gpio_pullup(S3C2410_GPB0, 0);
* s3c2410_gpio_pullup(S3C2410_GPE8, 0);
*/
extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#include <asm/sizes.h> #include <asm/sizes.h>
......
include/asm-arm/arch-s3c2410/regs-gpio.h
View file @ 8c17e55a
/* linux/include/asm/hardware/s3c2410/ /* linux/include/asm/hardware/s3c2410/
* *
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/ * http://www.simtec.co.uk/products/SWLINUX/
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -13,12 +13,31 @@ ...@@ -13,12 +13,31 @@
* 19-06-2003 BJD Created file * 19-06-2003 BJD Created file
* 23-06-2003 BJD Updated GSTATUS registers * 23-06-2003 BJD Updated GSTATUS registers
* 12-03-2004 BJD Updated include protection * 12-03-2004 BJD Updated include protection
* 20-07-2004 BJD Added GPIO pin numbers, added Port A definitions
*/ */
#ifndef __ASM_ARCH_REGS_GPIO_H #ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $" #define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
#define S3C2410_GPIO_BANKA (32*0)
#define S3C2410_GPIO_BANKB (32*1)
#define S3C2410_GPIO_BANKC (32*2)
#define S3C2410_GPIO_BANKD (32*3)
#define S3C2410_GPIO_BANKE (32*4)
#define S3C2410_GPIO_BANKF (32*5)
#define S3C2410_GPIO_BANKG (32*6)
#define S3C2410_GPIO_BANKH (32*7)
#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C2410_VA_GPIO)
#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
/* general configuration options */
#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
/* configure GPIO ports A..G */ /* configure GPIO ports A..G */
#define S3C2410_GPIOREG(x) ((x) + S3C2410_VA_GPIO) #define S3C2410_GPIOREG(x) ((x) + S3C2410_VA_GPIO)
...@@ -29,6 +48,98 @@ ...@@ -29,6 +48,98 @@
#define S3C2410_GPACON S3C2410_GPIOREG(0x00) #define S3C2410_GPACON S3C2410_GPIOREG(0x00)
#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) #define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
#define S3C2410_GPA0_OUT (0<<0)
#define S3C2410_GPA0_ADDR0 (1<<0)
#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
#define S3C2410_GPA1_OUT (0<<1)
#define S3C2410_GPA1_ADDR16 (1<<1)
#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
#define S3C2410_GPA2_OUT (0<<2)
#define S3C2410_GPA2_ADDR17 (1<<2)
#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
#define S3C2410_GPA3_OUT (0<<3)
#define S3C2410_GPA3_ADDR18 (1<<3)
#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
#define S3C2410_GPA4_OUT (0<<4)
#define S3C2410_GPA4_ADDR19 (1<<4)
#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
#define S3C2410_GPA5_OUT (0<<5)
#define S3C2410_GPA5_ADDR20 (1<<5)
#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
#define S3C2410_GPA6_OUT (0<<6)
#define S3C2410_GPA6_ADDR21 (1<<6)
#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
#define S3C2410_GPA7_OUT (0<<7)
#define S3C2410_GPA7_ADDR22 (1<<7)
#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
#define S3C2410_GPA8_OUT (0<<8)
#define S3C2410_GPA8_ADDR23 (1<<8)
#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
#define S3C2410_GPA9_OUT (0<<9)
#define S3C2410_GPA9_ADDR24 (1<<9)
#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
#define S3C2410_GPA10_OUT (0<<10)
#define S3C2410_GPA10_ADDR25 (1<<10)
#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
#define S3C2410_GPA11_OUT (0<<11)
#define S3C2410_GPA11_ADDR26 (1<<11)
#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
#define S3C2410_GPA12_OUT (0<<12)
#define S3C2410_GPA12_nGCS1 (1<<12)
#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
#define S3C2410_GPA13_OUT (0<<13)
#define S3C2410_GPA13_nGCS2 (1<<13)
#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
#define S3C2410_GPA14_OUT (0<<14)
#define S3C2410_GPA14_nGCS3 (1<<14)
#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
#define S3C2410_GPA15_OUT (0<<15)
#define S3C2410_GPA15_nGCS4 (1<<15)
#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
#define S3C2410_GPA16_OUT (0<<16)
#define S3C2410_GPA16_nGCS5 (1<<16)
#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
#define S3C2410_GPA17_OUT (0<<17)
#define S3C2410_GPA17_CLE (1<<17)
#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
#define S3C2410_GPA18_OUT (0<<18)
#define S3C2410_GPA18_ALE (1<<18)
#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
#define S3C2410_GPA19_OUT (0<<19)
#define S3C2410_GPA19_nFWE (1<<19)
#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
#define S3C2410_GPA20_OUT (0<<20)
#define S3C2410_GPA20_nFRE (1<<20)
#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
#define S3C2410_GPA21_OUT (0<<21)
#define S3C2410_GPA21_nRSTOUT (1<<21)
#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
#define S3C2410_GPA22_OUT (0<<22)
#define S3C2410_GPA22_nFCE (1<<22)
/* 0x08 and 0x0c are reserved */ /* 0x08 and 0x0c are reserved */
/* GPB is 10 IO pins, each configured by 2 bits each in GPBCON. /* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
...@@ -44,49 +155,60 @@ ...@@ -44,49 +155,60 @@
/* no i/o pin in port b can have value 3! */ /* no i/o pin in port b can have value 3! */
#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
#define S3C2410_GPB0_INP (0x00 << 0) #define S3C2410_GPB0_INP (0x00 << 0)
#define S3C2410_GPB0_OUTP (0x01 << 0) #define S3C2410_GPB0_OUTP (0x01 << 0)
#define S3C2410_GPB0_TOUT0 (0x02 << 0) #define S3C2410_GPB0_TOUT0 (0x02 << 0)
#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
#define S3C2410_GPB1_INP (0x00 << 2) #define S3C2410_GPB1_INP (0x00 << 2)
#define S3C2410_GPB1_OUTP (0x01 << 2) #define S3C2410_GPB1_OUTP (0x01 << 2)
#define S3C2410_GPB1_TOUT1 (0x02 << 2) #define S3C2410_GPB1_TOUT1 (0x02 << 2)
#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
#define S3C2410_GPB2_INP (0x00 << 4) #define S3C2410_GPB2_INP (0x00 << 4)
#define S3C2410_GPB2_OUTP (0x01 << 4) #define S3C2410_GPB2_OUTP (0x01 << 4)
#define S3C2410_GPB2_TOUT2 (0x02 << 4) #define S3C2410_GPB2_TOUT2 (0x02 << 4)
#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
#define S3C2410_GPB3_INP (0x00 << 6) #define S3C2410_GPB3_INP (0x00 << 6)
#define S3C2410_GPB3_OUTP (0x01 << 6) #define S3C2410_GPB3_OUTP (0x01 << 6)
#define S3C2410_GPB3_TOUT3 (0x02 << 6) #define S3C2410_GPB3_TOUT3 (0x02 << 6)
#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
#define S3C2410_GPB4_INP (0x00 << 8) #define S3C2410_GPB4_INP (0x00 << 8)
#define S3C2410_GPB4_OUTP (0x01 << 8) #define S3C2410_GPB4_OUTP (0x01 << 8)
#define S3C2410_GPB4_TCLK0 (0x02 << 8) #define S3C2410_GPB4_TCLK0 (0x02 << 8)
#define S3C2410_GPB4_MASK (0x03 << 8) #define S3C2410_GPB4_MASK (0x03 << 8)
#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
#define S3C2410_GPB5_INP (0x00 << 10) #define S3C2410_GPB5_INP (0x00 << 10)
#define S3C2410_GPB5_OUTP (0x01 << 10) #define S3C2410_GPB5_OUTP (0x01 << 10)
#define S3C2410_GPB5_nXBACK (0x02 << 10) #define S3C2410_GPB5_nXBACK (0x02 << 10)
#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
#define S3C2410_GPB6_INP (0x00 << 12) #define S3C2410_GPB6_INP (0x00 << 12)
#define S3C2410_GPB6_OUTP (0x01 << 12) #define S3C2410_GPB6_OUTP (0x01 << 12)
#define S3C2410_GPB6_nXBREQ (0x02 << 12) #define S3C2410_GPB6_nXBREQ (0x02 << 12)
#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
#define S3C2410_GPB7_INP (0x00 << 14) #define S3C2410_GPB7_INP (0x00 << 14)
#define S3C2410_GPB7_OUTP (0x01 << 14) #define S3C2410_GPB7_OUTP (0x01 << 14)
#define S3C2410_GPB7_nXDACK1 (0x02 << 14) #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
#define S3C2410_GPB8_INP (0x00 << 16) #define S3C2410_GPB8_INP (0x00 << 16)
#define S3C2410_GPB8_OUTP (0x01 << 16) #define S3C2410_GPB8_OUTP (0x01 << 16)
#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
#define S3C2410_GPB9_INP (0x00 << 18) #define S3C2410_GPB9_INP (0x00 << 18)
#define S3C2410_GPB9_OUTP (0x01 << 18) #define S3C2410_GPB9_OUTP (0x01 << 18)
#define S3C2410_GPB9_nXDACK0 (0x02 << 18) #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
#define S3C2410_GPB10_INP (0x00 << 18) #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
#define S3C2410_GPB10_OUTP (0x01 << 18) #define S3C2410_GPB10_INP (0x00 << 18)
#define S3C2410_GPB10_OUTP (0x01 << 18)
#define S3C2410_GPB10_nXDRE0 (0x02 << 18) #define S3C2410_GPB10_nXDRE0 (0x02 << 18)
/* Port C consits of 16 GPIO/Special function /* Port C consits of 16 GPIO/Special function
...@@ -99,66 +221,82 @@ ...@@ -99,66 +221,82 @@
#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) #define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
#define S3C2410_GPC0_INP (0x00 << 0) #define S3C2410_GPC0_INP (0x00 << 0)
#define S3C2410_GPC0_OUTP (0x01 << 0) #define S3C2410_GPC0_OUTP (0x01 << 0)
#define S3C2410_GPC0_LEND (0x02 << 0) #define S3C2410_GPC0_LEND (0x02 << 0)
#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
#define S3C2410_GPC1_INP (0x00 << 2) #define S3C2410_GPC1_INP (0x00 << 2)
#define S3C2410_GPC1_OUTP (0x01 << 2) #define S3C2410_GPC1_OUTP (0x01 << 2)
#define S3C2410_GPC1_VCLK (0x02 << 2) #define S3C2410_GPC1_VCLK (0x02 << 2)
#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
#define S3C2410_GPC2_INP (0x00 << 4) #define S3C2410_GPC2_INP (0x00 << 4)
#define S3C2410_GPC2_OUTP (0x01 << 4) #define S3C2410_GPC2_OUTP (0x01 << 4)
#define S3C2410_GPC2_VLINE (0x02 << 4) #define S3C2410_GPC2_VLINE (0x02 << 4)
#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
#define S3C2410_GPC3_INP (0x00 << 6) #define S3C2410_GPC3_INP (0x00 << 6)
#define S3C2410_GPC3_OUTP (0x01 << 6) #define S3C2410_GPC3_OUTP (0x01 << 6)
#define S3C2410_GPC3_VFRAME (0x02 << 6) #define S3C2410_GPC3_VFRAME (0x02 << 6)
#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
#define S3C2410_GPC4_INP (0x00 << 8) #define S3C2410_GPC4_INP (0x00 << 8)
#define S3C2410_GPC4_OUTP (0x01 << 8) #define S3C2410_GPC4_OUTP (0x01 << 8)
#define S3C2410_GPC4_VM (0x02 << 8) #define S3C2410_GPC4_VM (0x02 << 8)
#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
#define S3C2410_GPC5_INP (0x00 << 10) #define S3C2410_GPC5_INP (0x00 << 10)
#define S3C2410_GPC5_OUTP (0x01 << 10) #define S3C2410_GPC5_OUTP (0x01 << 10)
#define S3C2410_GPC5_LCDVF0 (0x02 << 10) #define S3C2410_GPC5_LCDVF0 (0x02 << 10)
#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
#define S3C2410_GPC6_INP (0x00 << 12) #define S3C2410_GPC6_INP (0x00 << 12)
#define S3C2410_GPC6_OUTP (0x01 << 12) #define S3C2410_GPC6_OUTP (0x01 << 12)
#define S3C2410_GPC6_LCDVF1 (0x02 << 12) #define S3C2410_GPC6_LCDVF1 (0x02 << 12)
#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
#define S3C2410_GPC7_INP (0x00 << 14) #define S3C2410_GPC7_INP (0x00 << 14)
#define S3C2410_GPC7_OUTP (0x01 << 14) #define S3C2410_GPC7_OUTP (0x01 << 14)
#define S3C2410_GPC7_LCDVF2 (0x02 << 14) #define S3C2410_GPC7_LCDVF2 (0x02 << 14)
#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
#define S3C2410_GPC8_INP (0x00 << 16) #define S3C2410_GPC8_INP (0x00 << 16)
#define S3C2410_GPC8_OUTP (0x01 << 16) #define S3C2410_GPC8_OUTP (0x01 << 16)
#define S3C2410_GPC8_VD0 (0x02 << 16) #define S3C2410_GPC8_VD0 (0x02 << 16)
#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
#define S3C2410_GPC9_INP (0x00 << 18) #define S3C2410_GPC9_INP (0x00 << 18)
#define S3C2410_GPC9_OUTP (0x01 << 18) #define S3C2410_GPC9_OUTP (0x01 << 18)
#define S3C2410_GPC9_VD1 (0x02 << 18) #define S3C2410_GPC9_VD1 (0x02 << 18)
#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
#define S3C2410_GPC10_INP (0x00 << 20) #define S3C2410_GPC10_INP (0x00 << 20)
#define S3C2410_GPC10_OUTP (0x01 << 20) #define S3C2410_GPC10_OUTP (0x01 << 20)
#define S3C2410_GPC10_VD2 (0x02 << 20) #define S3C2410_GPC10_VD2 (0x02 << 20)
#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
#define S3C2410_GPC11_INP (0x00 << 22) #define S3C2410_GPC11_INP (0x00 << 22)
#define S3C2410_GPC11_OUTP (0x01 << 22) #define S3C2410_GPC11_OUTP (0x01 << 22)
#define S3C2410_GPC11_VD3 (0x02 << 22) #define S3C2410_GPC11_VD3 (0x02 << 22)
#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
#define S3C2410_GPC12_INP (0x00 << 24) #define S3C2410_GPC12_INP (0x00 << 24)
#define S3C2410_GPC12_OUTP (0x01 << 24) #define S3C2410_GPC12_OUTP (0x01 << 24)
#define S3C2410_GPC12_VD4 (0x02 << 24) #define S3C2410_GPC12_VD4 (0x02 << 24)
#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
#define S3C2410_GPC13_INP (0x00 << 26) #define S3C2410_GPC13_INP (0x00 << 26)
#define S3C2410_GPC13_OUTP (0x01 << 26) #define S3C2410_GPC13_OUTP (0x01 << 26)
#define S3C2410_GPC13_VD5 (0x02 << 26) #define S3C2410_GPC13_VD5 (0x02 << 26)
#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
#define S3C2410_GPC14_INP (0x00 << 28) #define S3C2410_GPC14_INP (0x00 << 28)
#define S3C2410_GPC14_OUTP (0x01 << 28) #define S3C2410_GPC14_OUTP (0x01 << 28)
#define S3C2410_GPC14_VD6 (0x02 << 28) #define S3C2410_GPC14_VD6 (0x02 << 28)
#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
#define S3C2410_GPC15_INP (0x00 << 30) #define S3C2410_GPC15_INP (0x00 << 30)
#define S3C2410_GPC15_OUTP (0x01 << 30) #define S3C2410_GPC15_OUTP (0x01 << 30)
#define S3C2410_GPC15_VD7 (0x02 << 30) #define S3C2410_GPC15_VD7 (0x02 << 30)
...@@ -173,66 +311,82 @@ ...@@ -173,66 +311,82 @@
#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) #define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
#define S3C2410_GPD0_INP (0x00 << 0) #define S3C2410_GPD0_INP (0x00 << 0)
#define S3C2410_GPD0_OUTP (0x01 << 0) #define S3C2410_GPD0_OUTP (0x01 << 0)
#define S3C2410_GPD0_VD8 (0x02 << 0) #define S3C2410_GPD0_VD8 (0x02 << 0)
#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
#define S3C2410_GPD1_INP (0x00 << 2) #define S3C2410_GPD1_INP (0x00 << 2)
#define S3C2410_GPD1_OUTP (0x01 << 2) #define S3C2410_GPD1_OUTP (0x01 << 2)
#define S3C2410_GPD1_VD9 (0x02 << 2) #define S3C2410_GPD1_VD9 (0x02 << 2)
#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
#define S3C2410_GPD2_INP (0x00 << 4) #define S3C2410_GPD2_INP (0x00 << 4)
#define S3C2410_GPD2_OUTP (0x01 << 4) #define S3C2410_GPD2_OUTP (0x01 << 4)
#define S3C2410_GPD2_VD10 (0x02 << 4) #define S3C2410_GPD2_VD10 (0x02 << 4)
#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
#define S3C2410_GPD3_INP (0x00 << 6) #define S3C2410_GPD3_INP (0x00 << 6)
#define S3C2410_GPD3_OUTP (0x01 << 6) #define S3C2410_GPD3_OUTP (0x01 << 6)
#define S3C2410_GPD3_VD11 (0x02 << 6) #define S3C2410_GPD3_VD11 (0x02 << 6)
#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
#define S3C2410_GPD4_INP (0x00 << 8) #define S3C2410_GPD4_INP (0x00 << 8)
#define S3C2410_GPD4_OUTP (0x01 << 8) #define S3C2410_GPD4_OUTP (0x01 << 8)
#define S3C2410_GPD4_VD12 (0x02 << 8) #define S3C2410_GPD4_VD12 (0x02 << 8)
#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
#define S3C2410_GPD5_INP (0x00 << 10) #define S3C2410_GPD5_INP (0x00 << 10)
#define S3C2410_GPD5_OUTP (0x01 << 10) #define S3C2410_GPD5_OUTP (0x01 << 10)
#define S3C2410_GPD5_VD13 (0x02 << 10) #define S3C2410_GPD5_VD13 (0x02 << 10)
#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
#define S3C2410_GPD6_INP (0x00 << 12) #define S3C2410_GPD6_INP (0x00 << 12)
#define S3C2410_GPD6_OUTP (0x01 << 12) #define S3C2410_GPD6_OUTP (0x01 << 12)
#define S3C2410_GPD6_VD14 (0x02 << 12) #define S3C2410_GPD6_VD14 (0x02 << 12)
#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
#define S3C2410_GPD7_INP (0x00 << 14) #define S3C2410_GPD7_INP (0x00 << 14)
#define S3C2410_GPD7_OUTP (0x01 << 14) #define S3C2410_GPD7_OUTP (0x01 << 14)
#define S3C2410_GPD7_VD15 (0x02 << 14) #define S3C2410_GPD7_VD15 (0x02 << 14)
#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
#define S3C2410_GPD8_INP (0x00 << 16) #define S3C2410_GPD8_INP (0x00 << 16)
#define S3C2410_GPD8_OUTP (0x01 << 16) #define S3C2410_GPD8_OUTP (0x01 << 16)
#define S3C2410_GPD8_VD16 (0x02 << 16) #define S3C2410_GPD8_VD16 (0x02 << 16)
#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
#define S3C2410_GPD9_INP (0x00 << 18) #define S3C2410_GPD9_INP (0x00 << 18)
#define S3C2410_GPD9_OUTP (0x01 << 18) #define S3C2410_GPD9_OUTP (0x01 << 18)
#define S3C2410_GPD9_VD17 (0x02 << 18) #define S3C2410_GPD9_VD17 (0x02 << 18)
#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
#define S3C2410_GPD10_INP (0x00 << 20) #define S3C2410_GPD10_INP (0x00 << 20)
#define S3C2410_GPD10_OUTP (0x01 << 20) #define S3C2410_GPD10_OUTP (0x01 << 20)
#define S3C2410_GPD10_VD18 (0x02 << 20) #define S3C2410_GPD10_VD18 (0x02 << 20)
#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
#define S3C2410_GPD11_INP (0x00 << 22) #define S3C2410_GPD11_INP (0x00 << 22)
#define S3C2410_GPD11_OUTP (0x01 << 22) #define S3C2410_GPD11_OUTP (0x01 << 22)
#define S3C2410_GPD11_VD19 (0x02 << 22) #define S3C2410_GPD11_VD19 (0x02 << 22)
#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
#define S3C2410_GPD12_INP (0x00 << 24) #define S3C2410_GPD12_INP (0x00 << 24)
#define S3C2410_GPD12_OUTP (0x01 << 24) #define S3C2410_GPD12_OUTP (0x01 << 24)
#define S3C2410_GPD12_VD20 (0x02 << 24) #define S3C2410_GPD12_VD20 (0x02 << 24)
#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
#define S3C2410_GPD13_INP (0x00 << 26) #define S3C2410_GPD13_INP (0x00 << 26)
#define S3C2410_GPD13_OUTP (0x01 << 26) #define S3C2410_GPD13_OUTP (0x01 << 26)
#define S3C2410_GPD13_VD21 (0x02 << 26) #define S3C2410_GPD13_VD21 (0x02 << 26)
#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
#define S3C2410_GPD14_INP (0x00 << 28) #define S3C2410_GPD14_INP (0x00 << 28)
#define S3C2410_GPD14_OUTP (0x01 << 28) #define S3C2410_GPD14_OUTP (0x01 << 28)
#define S3C2410_GPD14_VD22 (0x02 << 28) #define S3C2410_GPD14_VD22 (0x02 << 28)
#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
#define S3C2410_GPD15_INP (0x00 << 30) #define S3C2410_GPD15_INP (0x00 << 30)
#define S3C2410_GPD15_OUTP (0x01 << 30) #define S3C2410_GPD15_OUTP (0x01 << 30)
#define S3C2410_GPD15_VD23 (0x02 << 30) #define S3C2410_GPD15_VD23 (0x02 << 30)
...@@ -247,71 +401,87 @@ ...@@ -247,71 +401,87 @@
#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) #define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
#define S3C2410_GPE0_INP (0x00 << 0) #define S3C2410_GPE0_INP (0x00 << 0)
#define S3C2410_GPE0_OUTP (0x01 << 0) #define S3C2410_GPE0_OUTP (0x01 << 0)
#define S3C2410_GPE0_I2SLRCK (0x02 << 0) #define S3C2410_GPE0_I2SLRCK (0x02 << 0)
#define S3C2410_GPE0_MASK (0x03 << 0) #define S3C2410_GPE0_MASK (0x03 << 0)
#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
#define S3C2410_GPE1_INP (0x00 << 2) #define S3C2410_GPE1_INP (0x00 << 2)
#define S3C2410_GPE1_OUTP (0x01 << 2) #define S3C2410_GPE1_OUTP (0x01 << 2)
#define S3C2410_GPE1_I2SSCLK (0x02 << 2) #define S3C2410_GPE1_I2SSCLK (0x02 << 2)
#define S3C2410_GPE1_MASK (0x03 << 2) #define S3C2410_GPE1_MASK (0x03 << 2)
#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
#define S3C2410_GPE2_INP (0x00 << 4) #define S3C2410_GPE2_INP (0x00 << 4)
#define S3C2410_GPE2_OUTP (0x01 << 4) #define S3C2410_GPE2_OUTP (0x01 << 4)
#define S3C2410_GPE2_CDCLK (0x02 << 4) #define S3C2410_GPE2_CDCLK (0x02 << 4)
#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
#define S3C2410_GPE3_INP (0x00 << 6) #define S3C2410_GPE3_INP (0x00 << 6)
#define S3C2410_GPE3_OUTP (0x01 << 6) #define S3C2410_GPE3_OUTP (0x01 << 6)
#define S3C2410_GPE3_I2SSDI (0x02 << 6) #define S3C2410_GPE3_I2SSDI (0x02 << 6)
#define S3C2410_GPE3_MASK (0x03 << 6) #define S3C2410_GPE3_MASK (0x03 << 6)
#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
#define S3C2410_GPE4_INP (0x00 << 8) #define S3C2410_GPE4_INP (0x00 << 8)
#define S3C2410_GPE4_OUTP (0x01 << 8) #define S3C2410_GPE4_OUTP (0x01 << 8)
#define S3C2410_GPE4_I2SSDO (0x02 << 8) #define S3C2410_GPE4_I2SSDO (0x02 << 8)
#define S3C2410_GPE4_MASK (0x03 << 8) #define S3C2410_GPE4_MASK (0x03 << 8)
#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
#define S3C2410_GPE5_INP (0x00 << 10) #define S3C2410_GPE5_INP (0x00 << 10)
#define S3C2410_GPE5_OUTP (0x01 << 10) #define S3C2410_GPE5_OUTP (0x01 << 10)
#define S3C2410_GPE5_SDCLK (0x02 << 10) #define S3C2410_GPE5_SDCLK (0x02 << 10)
#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
#define S3C2410_GPE6_INP (0x00 << 12) #define S3C2410_GPE6_INP (0x00 << 12)
#define S3C2410_GPE6_OUTP (0x01 << 12) #define S3C2410_GPE6_OUTP (0x01 << 12)
#define S3C2410_GPE6_SDCLK (0x02 << 12) #define S3C2410_GPE6_SDCLK (0x02 << 12)
#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
#define S3C2410_GPE7_INP (0x00 << 14) #define S3C2410_GPE7_INP (0x00 << 14)
#define S3C2410_GPE7_OUTP (0x01 << 14) #define S3C2410_GPE7_OUTP (0x01 << 14)
#define S3C2410_GPE7_SDCMD (0x02 << 14) #define S3C2410_GPE7_SDCMD (0x02 << 14)
#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
#define S3C2410_GPE8_INP (0x00 << 16) #define S3C2410_GPE8_INP (0x00 << 16)
#define S3C2410_GPE8_OUTP (0x01 << 16) #define S3C2410_GPE8_OUTP (0x01 << 16)
#define S3C2410_GPE8_SDDAT1 (0x02 << 16) #define S3C2410_GPE8_SDDAT1 (0x02 << 16)
#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
#define S3C2410_GPE9_INP (0x00 << 18) #define S3C2410_GPE9_INP (0x00 << 18)
#define S3C2410_GPE9_OUTP (0x01 << 18) #define S3C2410_GPE9_OUTP (0x01 << 18)
#define S3C2410_GPE9_SDDAT2 (0x02 << 18) #define S3C2410_GPE9_SDDAT2 (0x02 << 18)
#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
#define S3C2410_GPE10_INP (0x00 << 20) #define S3C2410_GPE10_INP (0x00 << 20)
#define S3C2410_GPE10_OUTP (0x01 << 20) #define S3C2410_GPE10_OUTP (0x01 << 20)
#define S3C2410_GPE10_SDDAT3 (0x02 << 20) #define S3C2410_GPE10_SDDAT3 (0x02 << 20)
#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
#define S3C2410_GPE11_INP (0x00 << 22) #define S3C2410_GPE11_INP (0x00 << 22)
#define S3C2410_GPE11_OUTP (0x01 << 22) #define S3C2410_GPE11_OUTP (0x01 << 22)
#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
#define S3C2410_GPE12_INP (0x00 << 24) #define S3C2410_GPE12_INP (0x00 << 24)
#define S3C2410_GPE12_OUTP (0x01 << 24) #define S3C2410_GPE12_OUTP (0x01 << 24)
#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
#define S3C2410_GPE13_INP (0x00 << 26) #define S3C2410_GPE13_INP (0x00 << 26)
#define S3C2410_GPE13_OUTP (0x01 << 26) #define S3C2410_GPE13_OUTP (0x01 << 26)
#define S3C2410_GPE13_SPICLK0 (0x02 << 26) #define S3C2410_GPE13_SPICLK0 (0x02 << 26)
#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
#define S3C2410_GPE14_INP (0x00 << 28) #define S3C2410_GPE14_INP (0x00 << 28)
#define S3C2410_GPE14_OUTP (0x01 << 28) #define S3C2410_GPE14_OUTP (0x01 << 28)
#define S3C2410_GPE14_IICSCL (0x02 << 28) #define S3C2410_GPE14_IICSCL (0x02 << 28)
#define S3C2410_GPE14_MASK (0x03 << 28) #define S3C2410_GPE14_MASK (0x03 << 28)
#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
#define S3C2410_GPE15_INP (0x00 << 30) #define S3C2410_GPE15_INP (0x00 << 30)
#define S3C2410_GPE15_OUTP (0x01 << 30) #define S3C2410_GPE15_OUTP (0x01 << 30)
#define S3C2410_GPE15_IICSDA (0x02 << 30) #define S3C2410_GPE15_IICSDA (0x02 << 30)
...@@ -333,35 +503,42 @@ ...@@ -333,35 +503,42 @@
#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) #define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
#define S3C2410_GPF0_INP (0x00 << 0) #define S3C2410_GPF0_INP (0x00 << 0)
#define S3C2410_GPF0_OUTP (0x01 << 0) #define S3C2410_GPF0_OUTP (0x01 << 0)
#define S3C2410_GPF0_EINT0 (0x02 << 0) #define S3C2410_GPF0_EINT0 (0x02 << 0)
#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
#define S3C2410_GPF1_INP (0x00 << 2) #define S3C2410_GPF1_INP (0x00 << 2)
#define S3C2410_GPF1_OUTP (0x01 << 2) #define S3C2410_GPF1_OUTP (0x01 << 2)
#define S3C2410_GPF1_EINT1 (0x02 << 2) #define S3C2410_GPF1_EINT1 (0x02 << 2)
#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
#define S3C2410_GPF2_INP (0x00 << 4) #define S3C2410_GPF2_INP (0x00 << 4)
#define S3C2410_GPF2_OUTP (0x01 << 4) #define S3C2410_GPF2_OUTP (0x01 << 4)
#define S3C2410_GPF2_EINT2 (0x02 << 4) #define S3C2410_GPF2_EINT2 (0x02 << 4)
#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
#define S3C2410_GPF3_INP (0x00 << 6) #define S3C2410_GPF3_INP (0x00 << 6)
#define S3C2410_GPF3_OUTP (0x01 << 6) #define S3C2410_GPF3_OUTP (0x01 << 6)
#define S3C2410_GPF3_EINT3 (0x02 << 6) #define S3C2410_GPF3_EINT3 (0x02 << 6)
#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
#define S3C2410_GPF4_INP (0x00 << 8) #define S3C2410_GPF4_INP (0x00 << 8)
#define S3C2410_GPF4_OUTP (0x01 << 8) #define S3C2410_GPF4_OUTP (0x01 << 8)
#define S3C2410_GPF4_EINT4 (0x02 << 8) #define S3C2410_GPF4_EINT4 (0x02 << 8)
#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
#define S3C2410_GPF5_INP (0x00 << 10) #define S3C2410_GPF5_INP (0x00 << 10)
#define S3C2410_GPF5_OUTP (0x01 << 10) #define S3C2410_GPF5_OUTP (0x01 << 10)
#define S3C2410_GPF5_EINT5 (0x02 << 10) #define S3C2410_GPF5_EINT5 (0x02 << 10)
#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
#define S3C2410_GPF6_INP (0x00 << 12) #define S3C2410_GPF6_INP (0x00 << 12)
#define S3C2410_GPF6_OUTP (0x01 << 12) #define S3C2410_GPF6_OUTP (0x01 << 12)
#define S3C2410_GPF6_EINT6 (0x02 << 12) #define S3C2410_GPF6_EINT6 (0x02 << 12)
#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
#define S3C2410_GPF7_INP (0x00 << 14) #define S3C2410_GPF7_INP (0x00 << 14)
#define S3C2410_GPF7_OUTP (0x01 << 14) #define S3C2410_GPF7_OUTP (0x01 << 14)
#define S3C2410_GPF7_EINT7 (0x02 << 14) #define S3C2410_GPF7_EINT7 (0x02 << 14)
...@@ -378,74 +555,90 @@ ...@@ -378,74 +555,90 @@
#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) #define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
#define S3C2410_GPG0_INP (0x00 << 0) #define S3C2410_GPG0_INP (0x00 << 0)
#define S3C2410_GPG0_OUTP (0x01 << 0) #define S3C2410_GPG0_OUTP (0x01 << 0)
#define S3C2410_GPG0_EINT8 (0x02 << 0) #define S3C2410_GPG0_EINT8 (0x02 << 0)
#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
#define S3C2410_GPG1_INP (0x00 << 2) #define S3C2410_GPG1_INP (0x00 << 2)
#define S3C2410_GPG1_OUTP (0x01 << 2) #define S3C2410_GPG1_OUTP (0x01 << 2)
#define S3C2410_GPG1_EINT9 (0x02 << 2) #define S3C2410_GPG1_EINT9 (0x02 << 2)
#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
#define S3C2410_GPG2_INP (0x00 << 4) #define S3C2410_GPG2_INP (0x00 << 4)
#define S3C2410_GPG2_OUTP (0x01 << 4) #define S3C2410_GPG2_OUTP (0x01 << 4)
#define S3C2410_GPG2_EINT10 (0x02 << 4) #define S3C2410_GPG2_EINT10 (0x02 << 4)
#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
#define S3C2410_GPG3_INP (0x00 << 6) #define S3C2410_GPG3_INP (0x00 << 6)
#define S3C2410_GPG3_OUTP (0x01 << 6) #define S3C2410_GPG3_OUTP (0x01 << 6)
#define S3C2410_GPG3_EINT11 (0x02 << 6) #define S3C2410_GPG3_EINT11 (0x02 << 6)
#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
#define S3C2410_GPG4_INP (0x00 << 8) #define S3C2410_GPG4_INP (0x00 << 8)
#define S3C2410_GPG4_OUTP (0x01 << 8) #define S3C2410_GPG4_OUTP (0x01 << 8)
#define S3C2410_GPG4_EINT12 (0x02 << 8) #define S3C2410_GPG4_EINT12 (0x02 << 8)
#define S3C2410_GPG4_LCDPWREN (0x03 << 8) #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
#define S3C2410_GPG5_INP (0x00 << 10) #define S3C2410_GPG5_INP (0x00 << 10)
#define S3C2410_GPG5_OUTP (0x01 << 10) #define S3C2410_GPG5_OUTP (0x01 << 10)
#define S3C2410_GPG5_EINT13 (0x02 << 10) #define S3C2410_GPG5_EINT13 (0x02 << 10)
#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
#define S3C2410_GPG6_INP (0x00 << 12) #define S3C2410_GPG6_INP (0x00 << 12)
#define S3C2410_GPG6_OUTP (0x01 << 12) #define S3C2410_GPG6_OUTP (0x01 << 12)
#define S3C2410_GPG6_EINT14 (0x02 << 12) #define S3C2410_GPG6_EINT14 (0x02 << 12)
#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
#define S3C2410_GPG7_INP (0x00 << 14) #define S3C2410_GPG7_INP (0x00 << 14)
#define S3C2410_GPG7_OUTP (0x01 << 14) #define S3C2410_GPG7_OUTP (0x01 << 14)
#define S3C2410_GPG7_EINT15 (0x02 << 14) #define S3C2410_GPG7_EINT15 (0x02 << 14)
#define S3C2410_GPG7_SPICLK1 (0x03 << 14) #define S3C2410_GPG7_SPICLK1 (0x03 << 14)
#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
#define S3C2410_GPG8_INP (0x00 << 16) #define S3C2410_GPG8_INP (0x00 << 16)
#define S3C2410_GPG8_OUTP (0x01 << 16) #define S3C2410_GPG8_OUTP (0x01 << 16)
#define S3C2410_GPG8_EINT16 (0x02 << 16) #define S3C2410_GPG8_EINT16 (0x02 << 16)
#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
#define S3C2410_GPG9_INP (0x00 << 18) #define S3C2410_GPG9_INP (0x00 << 18)
#define S3C2410_GPG9_OUTP (0x01 << 18) #define S3C2410_GPG9_OUTP (0x01 << 18)
#define S3C2410_GPG9_EINT17 (0x02 << 18) #define S3C2410_GPG9_EINT17 (0x02 << 18)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG10_INP (0x00 << 20) #define S3C2410_GPG10_INP (0x00 << 20)
#define S3C2410_GPG10_OUTP (0x01 << 20) #define S3C2410_GPG10_OUTP (0x01 << 20)
#define S3C2410_GPG10_EINT18 (0x02 << 20) #define S3C2410_GPG10_EINT18 (0x02 << 20)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG11_INP (0x00 << 22) #define S3C2410_GPG11_INP (0x00 << 22)
#define S3C2410_GPG11_OUTP (0x01 << 22) #define S3C2410_GPG11_OUTP (0x01 << 22)
#define S3C2410_GPG11_EINT19 (0x02 << 22) #define S3C2410_GPG11_EINT19 (0x02 << 22)
#define S3C2410_GPG11_TCLK1 (0x03 << 22) #define S3C2410_GPG11_TCLK1 (0x03 << 22)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG12_INP (0x00 << 24) #define S3C2410_GPG12_INP (0x00 << 24)
#define S3C2410_GPG12_OUTP (0x01 << 24) #define S3C2410_GPG12_OUTP (0x01 << 24)
#define S3C2410_GPG12_EINT18 (0x02 << 24) #define S3C2410_GPG12_EINT18 (0x02 << 24)
#define S3C2410_GPG12_XMON (0x03 << 24) #define S3C2410_GPG12_XMON (0x03 << 24)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG13_INP (0x00 << 26) #define S3C2410_GPG13_INP (0x00 << 26)
#define S3C2410_GPG13_OUTP (0x01 << 26) #define S3C2410_GPG13_OUTP (0x01 << 26)
#define S3C2410_GPG13_EINT18 (0x02 << 26) #define S3C2410_GPG13_EINT18 (0x02 << 26)
#define S3C2410_GPG13_nXPON (0x03 << 26) #define S3C2410_GPG13_nXPON (0x03 << 26)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG14_INP (0x00 << 28) #define S3C2410_GPG14_INP (0x00 << 28)
#define S3C2410_GPG14_OUTP (0x01 << 28) #define S3C2410_GPG14_OUTP (0x01 << 28)
#define S3C2410_GPG14_EINT18 (0x02 << 28) #define S3C2410_GPG14_EINT18 (0x02 << 28)
#define S3C2410_GPG14_YMON (0x03 << 28) #define S3C2410_GPG14_YMON (0x03 << 28)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG15_INP (0x00 << 30) #define S3C2410_GPG15_INP (0x00 << 30)
#define S3C2410_GPG15_OUTP (0x01 << 30) #define S3C2410_GPG15_OUTP (0x01 << 30)
#define S3C2410_GPG15_EINT18 (0x02 << 30) #define S3C2410_GPG15_EINT18 (0x02 << 30)
...@@ -466,51 +659,62 @@ ...@@ -466,51 +659,62 @@
#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) #define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
#define S3C2410_GPH0_INP (0x00 << 0) #define S3C2410_GPH0_INP (0x00 << 0)
#define S3C2410_GPH0_OUTP (0x01 << 0) #define S3C2410_GPH0_OUTP (0x01 << 0)
#define S3C2410_GPH0_nCTS0 (0x02 << 0) #define S3C2410_GPH0_nCTS0 (0x02 << 0)
#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
#define S3C2410_GPH1_INP (0x00 << 2) #define S3C2410_GPH1_INP (0x00 << 2)
#define S3C2410_GPH1_OUTP (0x01 << 2) #define S3C2410_GPH1_OUTP (0x01 << 2)
#define S3C2410_GPH1_nRTS0 (0x02 << 2) #define S3C2410_GPH1_nRTS0 (0x02 << 2)
#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
#define S3C2410_GPH2_INP (0x00 << 4) #define S3C2410_GPH2_INP (0x00 << 4)
#define S3C2410_GPH2_OUTP (0x01 << 4) #define S3C2410_GPH2_OUTP (0x01 << 4)
#define S3C2410_GPH2_TXD0 (0x02 << 4) #define S3C2410_GPH2_TXD0 (0x02 << 4)
#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
#define S3C2410_GPH3_INP (0x00 << 6) #define S3C2410_GPH3_INP (0x00 << 6)
#define S3C2410_GPH3_OUTP (0x01 << 6) #define S3C2410_GPH3_OUTP (0x01 << 6)
#define S3C2410_GPH3_RXD0 (0x02 << 6) #define S3C2410_GPH3_RXD0 (0x02 << 6)
#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
#define S3C2410_GPH4_INP (0x00 << 8) #define S3C2410_GPH4_INP (0x00 << 8)
#define S3C2410_GPH4_OUTP (0x01 << 8) #define S3C2410_GPH4_OUTP (0x01 << 8)
#define S3C2410_GPH4_TXD1 (0x02 << 8) #define S3C2410_GPH4_TXD1 (0x02 << 8)
#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
#define S3C2410_GPH5_INP (0x00 << 10) #define S3C2410_GPH5_INP (0x00 << 10)
#define S3C2410_GPH5_OUTP (0x01 << 10) #define S3C2410_GPH5_OUTP (0x01 << 10)
#define S3C2410_GPH5_RXD1 (0x02 << 10) #define S3C2410_GPH5_RXD1 (0x02 << 10)
#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
#define S3C2410_GPH6_INP (0x00 << 12) #define S3C2410_GPH6_INP (0x00 << 12)
#define S3C2410_GPH6_OUTP (0x01 << 12) #define S3C2410_GPH6_OUTP (0x01 << 12)
#define S3C2410_GPH6_TXD2 (0x02 << 12) #define S3C2410_GPH6_TXD2 (0x02 << 12)
#define S3C2410_GPH6_nRTS1 (0x03 << 12) #define S3C2410_GPH6_nRTS1 (0x03 << 12)
#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
#define S3C2410_GPH7_INP (0x00 << 14) #define S3C2410_GPH7_INP (0x00 << 14)
#define S3C2410_GPH7_OUTP (0x01 << 14) #define S3C2410_GPH7_OUTP (0x01 << 14)
#define S3C2410_GPH7_RXD2 (0x02 << 14) #define S3C2410_GPH7_RXD2 (0x02 << 14)
#define S3C2410_GPH7_nCTS1 (0x03 << 14) #define S3C2410_GPH7_nCTS1 (0x03 << 14)
#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
#define S3C2410_GPH8_INP (0x00 << 16) #define S3C2410_GPH8_INP (0x00 << 16)
#define S3C2410_GPH8_OUTP (0x01 << 16) #define S3C2410_GPH8_OUTP (0x01 << 16)
#define S3C2410_GPH8_UCLK (0x02 << 16) #define S3C2410_GPH8_UCLK (0x02 << 16)
#define S3C2410_GPH9_INP (0x00 << 18) #define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
#define S3C2410_GPH9_OUTP (0x01 << 18) #define S3C2410_GPH9_INP (0x00 << 18)
#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) #define S3C2410_GPH9_OUTP (0x01 << 18)
#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
#define S3C2410_GPH10_INP (0x00 << 20) #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
#define S3C2410_GPH10_OUTP (0x01 << 20) #define S3C2410_GPH10_INP (0x00 << 20)
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) #define S3C2410_GPH10_OUTP (0x01 << 20)
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
/* miscellaneous control */ /* miscellaneous control */
......
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