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Commit 8e95a53b authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lliubbo/blackfin 

Pull blackfin changes from Bob Liu:
 "The biggest change was added an new processor(bf60x series).

  Bf60x series processor of blackfin can up to 1GHz with Hardware
  Support for HD Video Analytics, it use the same blackfin ISA but with
  some changes on system buses, interrupt controller and peripheral
  devices.

  Added dir arch/blackfin/mach-bf609/ and did some changes to the
  framework made linux working fine on the reference board bf609-ezkit
  now."

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lliubbo/blackfin: (41 commits)
  blackfin: fix build after add bf60x mach/pm.h
  blackfin: twi: include linux/i2c.h
  blackfin: bf60x: add head file for crc controller
  blackfin: bf60x: twi: work around temporary anomaly 0501001
  blackfin: twi: Move TWI MMR access macro to twi head file
  blackfin: twi: Move TWI peripheral pin request array to platform data
  blackfin: bf60x: anomaly: Add a temporary anomaly 0501001
  blackfin: bf60x: Rename the DDR controller macro
  blackfin: mach-bf609: pm: cleanup bfin_deepsleep
  blackfin: bf60x: cleanup get clock code
  blackfin: bf60x: pm: Add a debug option to calculate kernel wakeup time.
  blackfin: bf60x: add wakeup source select
  blackfin: bf60x: make clock changeable in kernel menuconfig
  blackfin:mach-bf609: fix norflash for bf609-ezkit
  blackfin: mach-bf609: add can_wakeup to ethernet device
  blackfin: remove redundant CONFIG_BF60x macro
  blackfin: rotary: Add pm_wakeup flag to platform data structure.
  bfin_gpio: fix bf548-ezkit kernel fail to boot
  bfin_dma: fix initcall return error in proc_dma_init()
  Blackfin: delete fork func
  ...
parents cd975ae0 672552ad
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arch/blackfin/ADI_BSD.txt deleted 100644 → 0
View file @ cd975ae0
This BSD-Style License applies to a few files in ./arch/blackfin directory,
and is included here, so people understand which code they can use outside
the Linux kernel, in non-GPL based projects.
Using the files released under the "ADI BSD" license, must comply with
these license terms.
--------------------------------------------------------------------------
Copyright Analog Devices, Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
- Neither the name of Analog Devices, Inc. nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
- The use of this software may or may not infringe the patent rights
of one or more patent holders. This license does not release you
from the requirement that you obtain separate licenses from these
patent holders to use this software.
THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
arch/blackfin/Clear_BSD.txt 0 → 100644
View file @ 8e95a53b
The Clear BSD license:
Copyright (c) 2012, Analog Devices, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted (subject to the limitations in the
disclaimer below) provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
* Neither the name of Analog Devices, Inc. nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
arch/blackfin/Kconfig
View file @ 8e95a53b
......@@ -226,6 +226,12 @@ config BF561
help
BF561 Processor Support.
config BF609
bool "BF609"
select CLKDEV_LOOKUP
help
BF609 Processor Support.
endchoice
config SMP
......@@ -251,27 +257,27 @@ config HOTPLUG_CPU
config BF_REV_MIN
int
default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
default 2 if (BF537 || BF536 || BF534)
default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
default 4 if (BF538 || BF539)
config BF_REV_MAX
int
default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
default 3 if (BF537 || BF536 || BF534 || BF54xM)
default 5 if (BF561 || BF538 || BF539)
default 6 if (BF533 || BF532 || BF531)
choice
prompt "Silicon Rev"
default BF_REV_0_0 if (BF51x || BF52x)
default BF_REV_0_0 if (BF51x || BF52x || BF60x)
default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
config BF_REV_0_0
bool "0.0"
depends on (BF51x || BF52x || (BF54x && !BF54xM))
depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
config BF_REV_0_1
bool "0.1"
......@@ -350,6 +356,7 @@ source "arch/blackfin/mach-bf561/Kconfig"
source "arch/blackfin/mach-bf537/Kconfig"
source "arch/blackfin/mach-bf538/Kconfig"
source "arch/blackfin/mach-bf548/Kconfig"
source "arch/blackfin/mach-bf609/Kconfig"
menu "Board customizations"
......@@ -379,6 +386,12 @@ config BOOT_LOAD
memory region is used to capture NULL pointer references as well
as some core kernel functions.
config PHY_RAM_BASE_ADDRESS
hex "Physical RAM Base"
default 0x0
help
set BF609 FPGA physical SRAM base address
config ROM_BASE
hex "Kernel ROM Base"
depends on ROMKERNEL
......@@ -422,7 +435,7 @@ config BFIN_KERNEL_CLOCK
config PLL_BYPASS
bool "Bypass PLL"
depends on BFIN_KERNEL_CLOCK
depends on BFIN_KERNEL_CLOCK && (!BF60x)
default n
config CLKIN_HALF
......@@ -441,7 +454,7 @@ config VCO_MULT
default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
default "22" if BFIN533_BLUETECHNIX_CM
default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
default "20" if BFIN561_EZKIT
default "20" if (BFIN561_EZKIT || BF609)
default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
default "25" if BFIN527_AD7160EVAL
help
......@@ -473,12 +486,45 @@ config SCLK_DIV
int "System Clock Divider"
depends on BFIN_KERNEL_CLOCK
range 1 15
default 5
default 4
help
This sets the frequency of the system clock (including SDRAM or DDR).
This sets the frequency of the system clock (including SDRAM or DDR) on
!BF60x else it set the clock for system buses and provides the
source from which SCLK0 and SCLK1 are derived.
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
config SCLK0_DIV
int "System Clock0 Divider"
depends on BFIN_KERNEL_CLOCK && BF60x
range 1 15
default 1
help
This sets the frequency of the system clock0 for PVP and all other
peripherals not clocked by SCLK1.
This can be between 1 and 15
System Clock0 = (System Clock) / (this setting)
config SCLK1_DIV
int "System Clock1 Divider"
depends on BFIN_KERNEL_CLOCK && BF60x
range 1 15
default 1
help
This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
This can be between 1 and 15
System Clock1 = (System Clock) / (this setting)
config DCLK_DIV
int "DDR Clock Divider"
depends on BFIN_KERNEL_CLOCK && BF60x
range 1 15
default 2
help
This sets the frequency of the DDR memory.
This can be between 1 and 15
DDR Clock = (PLL frequency) / (this setting)
choice
prompt "DDR SDRAM Chip Type"
depends on BFIN_KERNEL_CLOCK
......@@ -494,7 +540,7 @@ endchoice
choice
prompt "DDR/SDRAM Timing"
depends on BFIN_KERNEL_CLOCK
depends on BFIN_KERNEL_CLOCK && !BF60x
default BFIN_KERNEL_CLOCK_MEMINIT_CALC
help
This option allows you to specify Blackfin SDRAM/DDR Timing parameters
......@@ -576,6 +622,7 @@ config MAX_VCO_HZ
default 600000000 if BF548
default 533333333 if BF549
default 600000000 if BF561
default 800000000 if BF609
config MIN_VCO_HZ
int
......@@ -583,6 +630,7 @@ config MIN_VCO_HZ
config MAX_SCLK_HZ
int
default 200000000 if BF609
default 133333333
config MIN_SCLK_HZ
......@@ -1051,7 +1099,7 @@ endchoice
config BFIN_L2_DCACHEABLE
bool "Enable DCACHE for L2 SRAM"
depends on BFIN_DCACHE
depends on (BF54x || BF561) && !SMP
depends on (BF54x || BF561 || BF60x) && !SMP
default n
choice
prompt "L2 SRAM DCACHE policy"
......@@ -1077,6 +1125,7 @@ config MPU
comment "Asynchronous Memory Configuration"
menu "EBIU_AMGCTL Global Control"
depends on !BF60x
config C_AMCKEN
bool "Enable CLKOUT"
default y
......@@ -1127,6 +1176,7 @@ endchoice
endmenu
menu "EBIU_AMBCTL Control"
depends on !BF60x
config BANK_0
hex "Bank 0 (AMBCTL0.L)"
default 0x7BB0
......@@ -1206,7 +1256,7 @@ config ARCH_SUSPEND_POSSIBLE
choice
prompt "Standby Power Saving Mode"
depends on PM
depends on PM && !BF60x
default PM_BFIN_SLEEP_DEEPER
config PM_BFIN_SLEEP_DEEPER
bool "Sleep Deeper"
......@@ -1261,6 +1311,118 @@ config PM_BFIN_WAKE_GP
On ADSP-BF549 this option enables the the same functionality on the
/MRXON pin also PH7.
config PM_BFIN_WAKE_PA15
bool "Allow Wake-Up from PA15"
depends on PM && BF60x
default n
help
Enable PA15 Wake-Up
config PM_BFIN_WAKE_PA15_POL
int "Wake-up priority"
depends on PM_BFIN_WAKE_PA15
default 0
help
Wake-Up priority 0(low) 1(high)
config PM_BFIN_WAKE_PB15
bool "Allow Wake-Up from PB15"
depends on PM && BF60x
default n
help
Enable PB15 Wake-Up
config PM_BFIN_WAKE_PB15_POL
int "Wake-up priority"
depends on PM_BFIN_WAKE_PB15
default 0
help
Wake-Up priority 0(low) 1(high)
config PM_BFIN_WAKE_PC15
bool "Allow Wake-Up from PC15"
depends on PM && BF60x
default n
help
Enable PC15 Wake-Up
config PM_BFIN_WAKE_PC15_POL
int "Wake-up priority"
depends on PM_BFIN_WAKE_PC15
default 0
help
Wake-Up priority 0(low) 1(high)
config PM_BFIN_WAKE_PD06
bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
depends on PM && BF60x
default n
help
Enable PD06(ETH0_PHYINT) Wake-up
config PM_BFIN_WAKE_PD06_POL
int "Wake-up priority"
depends on PM_BFIN_WAKE_PD06
default 0
help
Wake-Up priority 0(low) 1(high)
config PM_BFIN_WAKE_PE12
bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
depends on PM && BF60x
default n
help
Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
config PM_BFIN_WAKE_PE12_POL
int "Wake-up priority"
depends on PM_BFIN_WAKE_PE12
default 0
help
Wake-Up priority 0(low) 1(high)
config PM_BFIN_WAKE_PG04
bool "Allow Wake-Up from PG04(CAN0_RX)"
depends on PM && BF60x
default n
help
Enable PG04(CAN0_RX) Wake-up
config PM_BFIN_WAKE_PG04_POL
int "Wake-up priority"
depends on PM_BFIN_WAKE_PG04
default 0
help
Wake-Up priority 0(low) 1(high)
config PM_BFIN_WAKE_PG13
bool "Allow Wake-Up from PG13"
depends on PM && BF60x
default n
help
Enable PG13 Wake-Up
config PM_BFIN_WAKE_PG13_POL
int "Wake-up priority"
depends on PM_BFIN_WAKE_PG13
default 0
help
Wake-Up priority 0(low) 1(high)
config PM_BFIN_WAKE_USB
bool "Allow Wake-Up from (USB)"
depends on PM && BF60x
default n
help
Enable (USB) Wake-up
config PM_BFIN_WAKE_USB_POL
int "Wake-up priority"
depends on PM_BFIN_WAKE_USB
default 0
help
Wake-Up priority 0(low) 1(high)
endmenu
menu "CPU Frequency scaling"
......
arch/blackfin/Kconfig.debug
View file @ 8e95a53b
......@@ -253,4 +253,11 @@ config BFIN_PSEUDODBG_INSNS
Most people should say N here.
config BFIN_PM_WAKEUP_TIME_BENCH
bool "Display the total time for kernel to resume from power saving mode"
default n
help
Display the total time when kernel resumes normal from standby or
suspend to mem mode.
endmenu
arch/blackfin/Makefile
View file @ 8e95a53b
......@@ -54,6 +54,7 @@ machine-$(CONFIG_BF548M) := bf548
machine-$(CONFIG_BF549) := bf548
machine-$(CONFIG_BF549M) := bf548
machine-$(CONFIG_BF561) := bf561
machine-$(CONFIG_BF609) := bf609
MACHINE := $(machine-y)
export MACHINE
......@@ -86,6 +87,7 @@ cpu-$(CONFIG_BF548M) := bf548m
cpu-$(CONFIG_BF549) := bf549
cpu-$(CONFIG_BF549M) := bf549m
cpu-$(CONFIG_BF561) := bf561
cpu-$(CONFIG_BF609) := bf609
rev-$(CONFIG_BF_REV_0_0) := 0.0
rev-$(CONFIG_BF_REV_0_1) := 0.1
......
arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
View file @ 8e95a53b
......@@ -21,14 +21,12 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_BF561=y
CONFIG_SMP=y
CONFIG_IRQ_TIMER0=10
CONFIG_CLKIN_HZ=30000000
CONFIG_HIGH_RES_TIMERS=y
CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
CONFIG_BFIN_GPTIMERS=m
CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
CONFIG_BFIN_L2_DCACHEABLE=y
CONFIG_BFIN_L2_WRITETHROUGH=y
CONFIG_C_CDPRIO=y
CONFIG_BANK_3=0xAAC2
CONFIG_BINFMT_FLAT=y
......
arch/blackfin/configs/BF609-EZKIT_defconfig 0 → 100644
View file @ 8e95a53b
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_ELF_CORE is not set
# CONFIG_FUTEX is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_BF609=y
CONFIG_PINT1_ASSIGN=0x01010000
CONFIG_PINT2_ASSIGN=0x07000101
CONFIG_PINT3_ASSIGN=0x02020303
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IP_CHECKSUM_L1=y
CONFIG_SYSCALL_TAB_L1=y
CONFIG_CPLB_SWITCH_TAB_L1=y
# CONFIG_APP_STACK_L1 is not set
# CONFIG_BFIN_INS_LOWOVERHEAD is not set
CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y
CONFIG_PM_BFIN_WAKE_PE12=y
CONFIG_PM_BFIN_WAKE_PE12_POL=1
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
CONFIG_CAN=y
CONFIG_CAN_BFIN=y
CONFIG_IRDA=y
CONFIG_IRTTY_SIR=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_FW_LOADER=m
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_UBI=m
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_IEEE1588=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_BFIN_ROTARY=y
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_BFIN_SIMPLE_TIMER=m
CONFIG_BFIN_LINKPORT=y
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_BFIN=y
CONFIG_SERIAL_BFIN_CONSOLE=y
CONFIG_SERIAL_BFIN_UART0=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_BLACKFIN_TWI=y
CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
CONFIG_SPI=y
CONFIG_SPI_BFIN6XX=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_BFIN_WDT=y
CONFIG_SOUND=m
CONFIG_SND=m
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_SPI is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=m
CONFIG_SND_BF6XX_I2S=m
CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61=m
CONFIG_SND_SOC_ALL_CODECS=m
CONFIG_USB=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_BLACKFIN=m
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MUSB_HDRC=y
CONFIG_USB_ZERO=y
CONFIG_MMC=y
CONFIG_SDH_BFIN=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_JFFS2_FS=m
CONFIG_UBIFS_FS=m
CONFIG_NFS_FS=m
CONFIG_NFS_V3=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_INFO=y
CONFIG_FRAME_POINTER=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_BFIN_PSEUDODBG_INSNS=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_ARC4=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
arch/blackfin/include/asm/bfin-global.h
View file @ 8e95a53b
......@@ -35,6 +35,11 @@ extern void bfin_setup_cpudata(unsigned int cpu);
extern unsigned long get_cclk(void);
extern unsigned long get_sclk(void);
#ifdef CONFIG_BF60x
extern unsigned long get_sclk0(void);
extern unsigned long get_sclk1(void);
extern unsigned long get_dclk(void);
#endif
extern unsigned long sclk_to_usecs(unsigned long sclk);
extern unsigned long usecs_to_sclk(unsigned long usecs);
......
arch/blackfin/include/asm/bfin6xx_spi.h 0 → 100644
View file @ 8e95a53b
This diff is collapsed.
arch/blackfin/include/asm/bfin_crc.h 0 → 100644
View file @ 8e95a53b
/*
* bfin_crc.h - interface to Blackfin CRC controllers
*
* Copyright 2012 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_CRC_H__
#define __BFIN_CRC_H__
/* Function driver which use hardware crc must initialize the structure */
struct crc_info {
/* Input data address */
unsigned char *in_addr;
/* Output data address */
unsigned char *out_addr;
/* Input or output bytes */
unsigned long datasize;
union {
/* CRC to compare with that of input buffer */
unsigned long crc_compare;
/* Value to compare with input data */
unsigned long val_verify;
/* Value to fill */
unsigned long val_fill;
};
/* Value to program the 32b CRC Polynomial */
unsigned long crc_poly;
union {
/* CRC calculated from the input data */
unsigned long crc_result;
/* First failed position to verify input data */
unsigned long pos_verify;
};
/* CRC mirror flags */
unsigned int bitmirr:1;
unsigned int bytmirr:1;
unsigned int w16swp:1;
unsigned int fdsel:1;
unsigned int rsltmirr:1;
unsigned int polymirr:1;
unsigned int cmpmirr:1;
};
/* Userspace interface */
#define CRC_IOC_MAGIC 'C'
#define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int)
#define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int)
#define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int)
#define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int)
#ifdef __KERNEL__
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/miscdevice.h>
struct crc_register {
u32 control;
u32 datacnt;
u32 datacntrld;
u32 __pad_1[2];
u32 compare;
u32 fillval;
u32 datafifo;
u32 intren;
u32 intrenset;
u32 intrenclr;
u32 poly;
u32 __pad_2[4];
u32 status;
u32 datacntcap;
u32 __pad_3;
u32 result;
u32 curresult;
u32 __pad_4[3];
u32 revid;
};
struct bfin_crc {
struct miscdevice mdev;
struct list_head list;
int irq;
int dma_ch_src;
int dma_ch_dest;
volatile struct crc_register *regs;
struct crc_info *info;
struct mutex mutex;
struct completion c;
unsigned short opmode;
char name[20];
};
/* CRC_STATUS Masks */
#define CMPERR 0x00000002 /* Compare error */
#define DCNTEXP 0x00000010 /* datacnt register expired */
#define IBR 0x00010000 /* Input buffer ready */
#define OBR 0x00020000 /* Output buffer ready */
#define IRR 0x00040000 /* Immediate result readt */
#define LUTDONE 0x00080000 /* Look-up table generation done */
#define FSTAT 0x00700000 /* FIFO status */
#define MAX_FIFO 4 /* Max fifo size */
/* CRC_CONTROL Masks */
#define BLKEN 0x00000001 /* Block enable */
#define OPMODE 0x000000F0 /* Operation mode */
#define OPMODE_OFFSET 4 /* Operation mode mask offset*/
#define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */
#define MODE_DATA_FILL 2 /* MTM data fill */
#define MODE_CALC_CRC 3 /* MSM CRC compute and compare */
#define MODE_DATA_VERIFY 4 /* MSM data verify */
#define AUTOCLRZ 0x00000100 /* Auto clear to zero */
#define AUTOCLRF 0x00000200 /* Auto clear to one */
#define OBRSTALL 0x00001000 /* Stall on output buffer ready */
#define IRRSTALL 0x00002000 /* Stall on immediate result ready */
#define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */
#define BITMIRR_OFFSET 16 /* Mirror bits offset */
#define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */
#define BYTMIRR_OFFSET 17 /* Mirror bytes offset */
#define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */
#define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */
#define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */
#define FDSEL_OFFSET 19 /* Mirror FIFO offset */
#define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */
#define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */
#define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */
#define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */
#define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */
#define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */
/* CRC_INTREN Masks */
#define CMPERRI 0x02 /* CRC_ERROR_INTR */
#define DCNTEXPI 0x10 /* CRC_STATUS_INTR */
#endif
#endif
arch/blackfin/include/asm/bfin_dma.h
View file @ 8e95a53b
......@@ -15,12 +15,55 @@
#define DMAEN 0x0001 /* DMA Channel Enable */
#define WNR 0x0002 /* Channel Direction (W/R*) */
#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
#ifdef CONFIG_BF60x
#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */
#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */
#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */
#define DI_EN DI_EN_X /* Data Interrupt Enable */
#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */
#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */
#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */
#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */
#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */
#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */
#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */
#define NDSIZE 0x00070000 /* Next Descriptor Size */
#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */
#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */
#define DMAFLOW_LARGE DMAFLOW_LIST
#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */
#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */
#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */
#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */
#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */
#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */
#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */
#else
#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */
#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */
#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
#define RESTART 0x0020 /* DMA Buffer Clear */
#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
#define DI_EN 0x0080 /* Data Interrupt Enable */
#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/
#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
......@@ -32,18 +75,26 @@
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
#define NDSIZE 0x0f00 /* Next Descriptor Size */
#define DMAFLOW 0x7000 /* Flow Control */
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
#endif
#define DMAFLOW 0x7000 /* Flow Control */
#define DMAFLOW_STOP 0x0000 /* Stop Mode */
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
/* DMA_IRQ_STATUS Masks */
#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
#ifdef CONFIG_BF60x
#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */
#else
#define DMA_PIRQ 0
#endif
/*
* All Blackfin system MMRs are padded to 32bits even if the register
......@@ -57,6 +108,26 @@
struct bfin_dma_regs {
u32 next_desc_ptr;
u32 start_addr;
#ifdef CONFIG_BF60x
u32 cfg;
u32 x_count;
u32 x_modify;
u32 y_count;
u32 y_modify;
u32 pad1;
u32 pad2;
u32 curr_desc_ptr;
u32 prev_desc_ptr;
u32 curr_addr;
u32 irq_status;
u32 curr_x_count;
u32 curr_y_count;
u32 pad3;
u32 bw_limit_count;
u32 curr_bw_limit_count;
u32 bw_monitor_count;
u32 curr_bw_monitor_count;
#else
__BFP(config);
u32 __pad0;
__BFP(x_count);
......@@ -71,8 +142,10 @@ struct bfin_dma_regs {
u32 __pad1;
__BFP(curr_y_count);
u32 __pad2;
#endif
};
#ifndef CONFIG_BF60x
/*
* bfin handshake mdma registers layout
*/
......@@ -85,6 +158,7 @@ struct bfin_hmdma_regs {
__BFP(ecount);
__BFP(bcount);
};
#endif
#undef __BFP
......
arch/blackfin/include/asm/bfin_pfmon.h
View file @ 8e95a53b
......@@ -3,7 +3,7 @@
*
* Copyright 2005-2011 Analog Devices Inc.
*
* Licensed under the ADI BSD license or GPL-2 (or later).
* Licensed under the Clear BSD license or GPL-2 (or later).
*/
#ifndef __ASM_BFIN_PFMON_H__
......
arch/blackfin/include/asm/bfin_ppi.h
View file @ 8e95a53b
......@@ -10,6 +10,7 @@
#define __ASM_BFIN_PPI_H__
#include <linux/types.h>
#include <asm/blackfin.h>
/*
* All Blackfin system MMRs are padded to 32bits even if the register
......@@ -48,6 +49,133 @@ struct bfin_eppi_regs {
u32 clip;
};
/*
* bfin eppi3 registers layout
*/
struct bfin_eppi3_regs {
u32 stat;
u32 hcnt;
u32 hdly;
u32 vcnt;
u32 vdly;
u32 frame;
u32 line;
u32 clkdiv;
u32 ctl;
u32 fs1_wlhb;
u32 fs1_paspl;
u32 fs2_wlvb;
u32 fs2_palpf;
u32 imsk;
u32 oddclip;
u32 evenclip;
u32 fs1_dly;
u32 fs2_dly;
u32 ctl2;
};
#undef __BFP
#ifdef EPPI0_CTL2
#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */
#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */
#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */
#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */
#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */
#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */
#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */
#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */
#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */
#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */
#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */
#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */
#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */
#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */
#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */
#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */
#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */
#define EPPI_CTL_EN 0x00000001 /* PPI Enable */
#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */
#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */
#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */
#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */
#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */
#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */
#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */
#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */
#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */
#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */
#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */
#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */
#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */
#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */
#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */
#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */
#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */
#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */
#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */
#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */
#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */
#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */
#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */
#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */
#define EPPI_CTL_DLEN 0x00070000 /* Data Length */
#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */
#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */
#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */
#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */
#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */
#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */
#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */
#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */
#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */
#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */
#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */
#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */
#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */
#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */
#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */
#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */
#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */
#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */
#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */
#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */
#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */
#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */
#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */
#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */
#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */
#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */
#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */
#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */
#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */
#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000
#define EPPI_ODDCLIP_LOWODD 0x0000FFFF
#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000
#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF
#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */
#endif
#endif
arch/blackfin/include/asm/bfin_rotary.h
View file @ 8e95a53b
......@@ -39,6 +39,7 @@ struct bfin_rotary_platform_data {
unsigned int rotary_rel_code;
unsigned short debounce; /* 0..17 */
unsigned short mode;
unsigned short pm_wakeup;
};
/* CNT_CONFIG bitmasks */
......
arch/blackfin/include/asm/bfin_serial.h
View file @ 8e95a53b
This diff is collapsed.
arch/blackfin/include/asm/bfin_sport.h
View file @ 8e95a53b
......@@ -24,6 +24,7 @@
struct sport_config {
/* TDM (multichannels), I2S or other mode */
unsigned int mode:3;
unsigned int polled; /* use poll instead of irq when set */
/* if TDM mode is selected, channels must be set */
int channels; /* Must be in 8 units */
......
arch/blackfin/include/asm/bfin_sport3.h 0 → 100644
View file @ 8e95a53b
/*
* bfin_sport - Analog Devices BF6XX SPORT registers
*
* Copyright (c) 2012 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _BFIN_SPORT3_H_
#define _BFIN_SPORT3_H_
#include <linux/types.h>
#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */
#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */
#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */
#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */
#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */
#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */
#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */
#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */
#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */
#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */
#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */
#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */
#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */
#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */
#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */
#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */
#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */
#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */
#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */
#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrrupt enable select */
#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */
#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */
#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */
#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */
#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */
#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */
#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */
#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */
#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */
#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */
#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */
#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */
#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */
#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */
#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */
#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */
#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */
#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */
#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */
#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */
#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */
#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */
#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */
#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */
#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */
#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */
#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */
#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */
#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */
#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */
#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */
#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */
struct sport_register {
u32 spctl;
u32 div;
u32 spmctl;
u32 spcs0;
u32 spcs1;
u32 spcs2;
u32 spcs3;
u32 spcnt;
u32 sperrctl;
u32 spmstat;
u32 spctl2;
u32 txa;
u32 rxa;
u32 txb;
u32 rxb;
u32 revid;
};
struct bfin_snd_platform_data {
const unsigned short *pin_req;
};
#endif
arch/blackfin/include/asm/bfin_twi.h
View file @ 8e95a53b
......@@ -10,6 +10,7 @@
#define __ASM_BFIN_TWI_H__
#include <linux/types.h>
#include <linux/i2c.h>
/*
* All Blackfin system MMRs are padded to 32bits even if the register
......@@ -42,4 +43,145 @@ struct bfin_twi_regs {
#undef __BFP
struct bfin_twi_iface {
int irq;
spinlock_t lock;
char read_write;
u8 command;
u8 *transPtr;
int readNum;
int writeNum;
int cur_mode;
int manual_stop;
int result;
struct i2c_adapter adap;
struct completion complete;
struct i2c_msg *pmsg;
int msg_num;
int cur_msg;
u16 saved_clkdiv;
u16 saved_control;
struct bfin_twi_regs *regs_base;
};
#define DEFINE_TWI_REG(reg_name, reg) \
static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
{ return iface->regs_base->reg; } \
static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
{ iface->regs_base->reg = v; }
DEFINE_TWI_REG(CLKDIV, clkdiv)
DEFINE_TWI_REG(CONTROL, control)
DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
DEFINE_TWI_REG(MASTER_CTL, master_ctl)
DEFINE_TWI_REG(MASTER_STAT, master_stat)
DEFINE_TWI_REG(MASTER_ADDR, master_addr)
DEFINE_TWI_REG(INT_STAT, int_stat)
DEFINE_TWI_REG(INT_MASK, int_mask)
DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
#if !ANOMALY_05001001
DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
#else
static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
{
u16 ret;
unsigned long flags;
flags = hard_local_irq_save();
ret = iface->regs_base->rcv_data8;
hard_local_irq_restore(flags);
return ret;
}
static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
{
u16 ret;
unsigned long flags;
flags = hard_local_irq_save();
ret = iface->regs_base->rcv_data16;
hard_local_irq_restore(flags);
return ret;
}
#endif
/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
/* TWI_PRESCALE Masks */
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
#define TWI_ENA 0x0080 /* TWI Enable */
#define SCCB 0x0200 /* SCCB Compatibility Enable */
/* TWI_SLAVE_CTL Masks */
#define SEN 0x0001 /* Slave Enable */
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
#define GEN 0x0010 /* General Call Address Matching Enabled */
/* TWI_SLAVE_STAT Masks */
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
#define GCALL 0x0002 /* General Call Indicator */
/* TWI_MASTER_CTL Masks */
#define MEN 0x0001 /* Master Mode Enable */
#define MADD_LEN 0x0002 /* Master Address Length */
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
#define FAST 0x0008 /* Use Fast Mode Timing Specs */
#define STOP 0x0010 /* Issue Stop Condition */
#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
#define DCNT 0x3FC0 /* Data Bytes To Transfer */
#define SDAOVR 0x4000 /* Serial Data Override */
#define SCLOVR 0x8000 /* Serial Clock Override */
/* TWI_MASTER_STAT Masks */
#define MPROG 0x0001 /* Master Transfer In Progress */
#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
#define ANAK 0x0004 /* Address Not Acknowledged */
#define DNAK 0x0008 /* Data Not Acknowledged */
#define BUFRDERR 0x0010 /* Buffer Read Error */
#define BUFWRERR 0x0020 /* Buffer Write Error */
#define SDASEN 0x0040 /* Serial Data Sense */
#define SCLSEN 0x0080 /* Serial Clock Sense */
#define BUSBUSY 0x0100 /* Bus Busy Indicator */
/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
#define SINIT 0x0001 /* Slave Transfer Initiated */
#define SCOMP 0x0002 /* Slave Transfer Complete */
#define SERR 0x0004 /* Slave Transfer Error */
#define SOVF 0x0008 /* Slave Overflow */
#define MCOMP 0x0010 /* Master Transfer Complete */
#define MERR 0x0020 /* Master Transfer Error */
#define XMTSERV 0x0040 /* Transmit FIFO Service */
#define RCVSERV 0x0080 /* Receive FIFO Service */
/* TWI_FIFO_CTRL Masks */
#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
/* TWI_FIFO_STAT Masks */
#define XMTSTAT 0x0003 /* Transmit FIFO Status */
#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
#define RCVSTAT 0x000C /* Receive FIFO Status */
#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
#endif
arch/blackfin/include/asm/blackfin.h
View file @ 8e95a53b
......@@ -63,20 +63,16 @@ static inline void CSYNC(void)
#if ANOMALY_05000312 || ANOMALY_05000244
#define SSYNC(scratch) \
do { \
cli scratch; \
nop; nop; nop; \
SSYNC; \
sti scratch; \
} while (0)
sti scratch;
#define CSYNC(scratch) \
do { \
cli scratch; \
nop; nop; nop; \
CSYNC; \
sti scratch; \
} while (0)
sti scratch;
#else
#define SSYNC(scratch) SSYNC;
......
arch/blackfin/include/asm/clkdev.h 0 → 100644
View file @ 8e95a53b
#ifndef __ASM_CLKDEV__H_
#define __ASM_CLKDEV__H_
#include <linux/slab.h>
static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
{
return kzalloc(size, GFP_KERNEL);
}
#define __clk_put(clk)
#define __clk_get(clk) ({ 1; })
#endif
arch/blackfin/include/asm/clocks.h
View file @ 8e95a53b
......@@ -48,4 +48,27 @@
# define CONFIG_VCO_MULT 0
#endif
#include <linux/clk.h>
struct clk_ops {
unsigned long (*get_rate)(struct clk *clk);
unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
int (*set_rate)(struct clk *clk, unsigned long rate);
int (*enable)(struct clk *clk);
int (*disable)(struct clk *clk);
};
struct clk {
struct clk *parent;
const char *name;
unsigned long rate;
spinlock_t lock;
u32 flags;
const struct clk_ops *ops;
void __iomem *reg;
u32 mask;
u32 shift;
};
int clk_init(void);
#endif
arch/blackfin/include/asm/cplb.h
View file @ 8e95a53b
......@@ -62,6 +62,10 @@
#define SIZE_4K 0x00001000 /* 4K */
#define SIZE_1M 0x00100000 /* 1M */
#define SIZE_4M 0x00400000 /* 4M */
#define SIZE_16K 0x00004000 /* 16K */
#define SIZE_64K 0x00010000 /* 64K */
#define SIZE_16M 0x01000000 /* 16M */
#define SIZE_64M 0x04000000 /* 64M */
#define MAX_CPLBS 16
......
arch/blackfin/include/asm/def_LPBlackfin.h
View file @ 8e95a53b
......@@ -3,7 +3,7 @@
*
* Copyright 2005-2008 Analog Devices Inc.
*
* Licensed under the ADI BSD license or GPL-2 (or later).
* Licensed under the Clear BSD license or GPL-2 (or later).
*/
#ifndef _DEF_LPBLACKFIN_H
......@@ -622,6 +622,10 @@ do { \
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
* mapped to L1
*/
......
arch/blackfin/include/asm/dma.h
View file @ 8e95a53b
......@@ -22,12 +22,22 @@
#define DATA_SIZE_8 0
#define DATA_SIZE_16 1
#define DATA_SIZE_32 2
#ifdef CONFIG_BF60x
#define DATA_SIZE_64 3
#endif
#define DMA_FLOW_STOP 0
#define DMA_FLOW_AUTO 1
#ifdef CONFIG_BF60x
#define DMA_FLOW_LIST 4
#define DMA_FLOW_ARRAY 5
#define DMA_FLOW_LIST_DEMAND 6
#define DMA_FLOW_ARRAY_DEMAND 7
#else
#define DMA_FLOW_ARRAY 4
#define DMA_FLOW_SMALL 6
#define DMA_FLOW_LARGE 7
#endif
#define DIMENSION_LINEAR 0
#define DIMENSION_2D 1
......@@ -36,26 +46,80 @@
#define DIR_WRITE 1
#define INTR_DISABLE 0
#ifdef CONFIG_BF60x
#define INTR_ON_PERI 1
#endif
#define INTR_ON_BUF 2
#define INTR_ON_ROW 3
#define DMA_NOSYNC_KEEP_DMA_BUF 0
#define DMA_SYNC_RESTART 1
#ifdef DMA_MMR_SIZE_32
#define DMA_MMR_SIZE_TYPE long
#define DMA_MMR_READ bfin_read32
#define DMA_MMR_WRITE bfin_write32
#else
#define DMA_MMR_SIZE_TYPE short
#define DMA_MMR_READ bfin_read16
#define DMA_MMR_WRITE bfin_write16
#endif
struct dma_desc_array {
unsigned long start_addr;
unsigned DMA_MMR_SIZE_TYPE cfg;
unsigned DMA_MMR_SIZE_TYPE x_count;
DMA_MMR_SIZE_TYPE x_modify;
} __attribute__((packed));
struct dmasg {
void *next_desc_addr;
unsigned long start_addr;
unsigned short cfg;
unsigned short x_count;
short x_modify;
unsigned short y_count;
short y_modify;
unsigned DMA_MMR_SIZE_TYPE cfg;
unsigned DMA_MMR_SIZE_TYPE x_count;
DMA_MMR_SIZE_TYPE x_modify;
unsigned DMA_MMR_SIZE_TYPE y_count;
DMA_MMR_SIZE_TYPE y_modify;
} __attribute__((packed));
struct dma_register {
void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
unsigned long start_addr; /* DMA Start address register */
#ifdef CONFIG_BF60x
unsigned long cfg; /* DMA Configuration register */
unsigned long x_count; /* DMA x_count register */
long x_modify; /* DMA x_modify register */
unsigned long y_count; /* DMA y_count register */
long y_modify; /* DMA y_modify register */
unsigned long reserved;
unsigned long reserved2;
void *curr_desc_ptr; /* DMA Current Descriptor Pointer
register */
void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer
register */
unsigned long curr_addr_ptr; /* DMA Current Address Pointer
register */
unsigned long irq_status; /* DMA irq status register */
unsigned long curr_x_count; /* DMA Current x-count register */
unsigned long curr_y_count; /* DMA Current y-count register */
unsigned long reserved3;
unsigned long bw_limit_count; /* DMA band width limit count register */
unsigned long curr_bw_limit_count; /* DMA Current band width limit
count register */
unsigned long bw_monitor_count; /* DMA band width limit count register */
unsigned long curr_bw_monitor_count; /* DMA Current band width limit
count register */
#else
unsigned short cfg; /* DMA Configuration register */
unsigned short dummy1; /* DMA Configuration register */
......@@ -92,6 +156,7 @@ struct dma_register {
unsigned short dummy9;
unsigned long reserved3;
#endif
};
......@@ -131,23 +196,23 @@ static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
{
dma_ch[channel].regs->curr_desc_ptr = addr;
}
static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
{
dma_ch[channel].regs->x_count = x_count;
}
static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
{
dma_ch[channel].regs->y_count = y_count;
}
static inline void set_dma_x_modify(unsigned int channel, short x_modify)
static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
{
dma_ch[channel].regs->x_modify = x_modify;
}
static inline void set_dma_y_modify(unsigned int channel, short y_modify)
static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
{
dma_ch[channel].regs->y_modify = y_modify;
}
static inline void set_dma_config(unsigned int channel, unsigned short config)
static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
{
dma_ch[channel].regs->cfg = config;
}
......@@ -156,23 +221,55 @@ static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
dma_ch[channel].regs->curr_addr_ptr = addr;
}
static inline unsigned short
#ifdef CONFIG_BF60x
static inline unsigned long
set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
char dma_mode, char mem_width, char syncmode, char peri_width)
{
unsigned long config = 0;
switch (intr_mode) {
case INTR_ON_BUF:
if (dma_mode == DIMENSION_2D)
config = DI_EN_Y;
else
config = DI_EN_X;
break;
case INTR_ON_ROW:
config = DI_EN_X;
break;
case INTR_ON_PERI:
config = DI_EN_P;
break;
};
return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
(flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
}
#endif
static inline unsigned DMA_MMR_SIZE_TYPE
set_bfin_dma_config(char direction, char flow_mode,
char intr_mode, char dma_mode, char width, char syncmode)
char intr_mode, char dma_mode, char mem_width, char syncmode)
{
return (direction << 1) | (width << 2) | (dma_mode << 4) |
#ifdef CONFIG_BF60x
return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
mem_width, syncmode, mem_width);
#else
return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
(intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
#endif
}
static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
{
return dma_ch[channel].regs->irq_status;
}
static inline unsigned short get_dma_curr_xcount(unsigned int channel)
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
{
return dma_ch[channel].regs->curr_x_count;
}
static inline unsigned short get_dma_curr_ycount(unsigned int channel)
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
{
return dma_ch[channel].regs->curr_y_count;
}
......@@ -184,7 +281,7 @@ static inline void *get_dma_curr_desc_ptr(unsigned int channel)
{
return dma_ch[channel].regs->curr_desc_ptr;
}
static inline unsigned short get_dma_config(unsigned int channel)
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
{
return dma_ch[channel].regs->cfg;
}
......@@ -203,8 +300,8 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize
dma_ch[channel].regs->next_desc_ptr = sg;
dma_ch[channel].regs->cfg =
(dma_ch[channel].regs->cfg & ~(0xf << 8)) |
((ndsize & 0xf) << 8);
(dma_ch[channel].regs->cfg & ~NDSIZE) |
((ndsize << NDSIZE_OFFSET) & NDSIZE);
}
static inline int dma_channel_active(unsigned int channel)
......@@ -239,7 +336,7 @@ static inline void dma_enable_irq(unsigned int channel)
}
static inline void clear_dma_irqstat(unsigned int channel)
{
dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
}
void *dma_memcpy(void *dest, const void *src, size_t count);
......
arch/blackfin/include/asm/dpmc.h
View file @ 8e95a53b
This diff is collapsed.
arch/blackfin/include/asm/fixed_code.h
View file @ 8e95a53b
......@@ -29,24 +29,28 @@ extern void sigreturn_stub(void);
#endif
#endif
#define FIXED_CODE_START 0x400
#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
#endif
#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
#define SIGRETURN_STUB 0x400
#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
#define ATOMIC_SEQS_START 0x410
#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
#define ATOMIC_XCHG32 0x410
#define ATOMIC_CAS32 0x420
#define ATOMIC_ADD32 0x430
#define ATOMIC_SUB32 0x440
#define ATOMIC_IOR32 0x450
#define ATOMIC_AND32 0x460
#define ATOMIC_XOR32 0x470
#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
#define ATOMIC_SEQS_END 0x480
#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
#define SAFE_USER_INSTRUCTION 0x480
#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
#define FIXED_CODE_END 0x490
#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
#endif
arch/blackfin/include/asm/gpio.h
View file @ 8e95a53b
......@@ -26,6 +26,7 @@
#ifndef __ASSEMBLY__
#include <linux/compiler.h>
#include <linux/gpio.h>
/***********************************************************
*
......@@ -244,6 +245,49 @@ static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
return -EINVAL;
}
static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
{
int err;
err = bfin_gpio_request(gpio, label);
if (err)
return err;
if (flags & GPIOF_DIR_IN)
err = bfin_gpio_direction_input(gpio);
else
err = bfin_gpio_direction_output(gpio,
(flags & GPIOF_INIT_HIGH) ? 1 : 0);
if (err)
bfin_gpio_free(gpio);
return err;
}
static inline int gpio_request_array(const struct gpio *array, size_t num)
{
int i, err;
for (i = 0; i < num; i++, array++) {
err = gpio_request_one(array->gpio, array->flags, array->label);
if (err)
goto err_free;
}
return 0;
err_free:
while (i--)
bfin_gpio_free((--array)->gpio);
return err;
}
static inline void gpio_free_array(const struct gpio *array, size_t num)
{
while (num--)
bfin_gpio_free((array++)->gpio);
}
static inline int __gpio_get_value(unsigned gpio)
{
return bfin_gpio_get_value(gpio);
......
arch/blackfin/include/asm/gptimers.h
View file @ 8e95a53b
......@@ -43,6 +43,13 @@
# define TIMER8_GROUP_REG TMRS4_ENABLE
# define TIMER_GROUP2 1
#endif
/*
* BF609: 8 timers:
*/
#if defined(CONFIG_BF60x)
# define MAX_BLACKFIN_GPTIMERS 8
# define TIMER0_GROUP_REG TIMER_RUN
#endif
/*
* All others: 3 timers:
*/
......@@ -104,6 +111,72 @@
# define FS2_TIMER_BIT TIMER1bit
#endif
#ifdef CONFIG_BF60x
/*
* Timer Configuration Register Bits
*/
#define TIMER_EMU_RUN 0x8000
#define TIMER_BPER_EN 0x4000
#define TIMER_BWID_EN 0x2000
#define TIMER_BDLY_EN 0x1000
#define TIMER_OUT_DIS 0x0800
#define TIMER_TIN_SEL 0x0400
#define TIMER_CLK_SEL 0x0300
#define TIMER_CLK_SCLK 0x0000
#define TIMER_CLK_ALT_CLK0 0x0100
#define TIMER_CLK_ALT_CLK1 0x0300
#define TIMER_PULSE_HI 0x0080
#define TIMER_SLAVE_TRIG 0x0040
#define TIMER_IRQ_MODE 0x0030
#define TIMER_IRQ_ACT_EDGE 0x0000
#define TIMER_IRQ_DLY 0x0010
#define TIMER_IRQ_WID_DLY 0x0020
#define TIMER_IRQ_PER 0x0030
#define TIMER_MODE 0x000f
#define TIMER_MODE_WDOG_P 0x0008
#define TIMER_MODE_WDOG_W 0x0009
#define TIMER_MODE_PWM_CONT 0x000c
#define TIMER_MODE_PWM 0x000d
#define TIMER_MODE_WDTH 0x000a
#define TIMER_MODE_WDTH_D 0x000b
#define TIMER_MODE_EXT_CLK 0x000e
#define TIMER_MODE_PININT 0x000f
/*
* Timer Status Register Bits
*/
#define TIMER_STATUS_TIMIL0 0x0001
#define TIMER_STATUS_TIMIL1 0x0002
#define TIMER_STATUS_TIMIL2 0x0004
#define TIMER_STATUS_TIMIL3 0x0008
#define TIMER_STATUS_TIMIL4 0x0010
#define TIMER_STATUS_TIMIL5 0x0020
#define TIMER_STATUS_TIMIL6 0x0040
#define TIMER_STATUS_TIMIL7 0x0080
#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */
#define TIMER_STATUS_TOVF1 0x0002
#define TIMER_STATUS_TOVF2 0x0004
#define TIMER_STATUS_TOVF3 0x0008
#define TIMER_STATUS_TOVF4 0x0010
#define TIMER_STATUS_TOVF5 0x0020
#define TIMER_STATUS_TOVF6 0x0040
#define TIMER_STATUS_TOVF7 0x0080
/*
* Timer Slave Enable Status : write 1 to clear
*/
#define TIMER_STATUS_TRUN0 0x0001
#define TIMER_STATUS_TRUN1 0x0002
#define TIMER_STATUS_TRUN2 0x0004
#define TIMER_STATUS_TRUN3 0x0008
#define TIMER_STATUS_TRUN4 0x0010
#define TIMER_STATUS_TRUN5 0x0020
#define TIMER_STATUS_TRUN6 0x0040
#define TIMER_STATUS_TRUN7 0x0080
#else
/*
* Timer Configuration Register Bits
*/
......@@ -170,12 +243,18 @@
#define TIMER_STATUS_TRUN10 0x4000
#define TIMER_STATUS_TRUN11 0x8000
#endif
/* The actual gptimer API */
void set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
uint32_t get_gptimer_pwidth(unsigned int timer_id);
void set_gptimer_period(unsigned int timer_id, uint32_t period);
uint32_t get_gptimer_period(unsigned int timer_id);
#ifdef CONFIG_BF60x
void set_gptimer_delay(unsigned int timer_id, uint32_t delay);
uint32_t get_gptimer_delay(unsigned int timer_id);
#endif
uint32_t get_gptimer_count(unsigned int timer_id);
int get_gptimer_intr(unsigned int timer_id);
void clear_gptimer_intr(unsigned int timer_id);
......@@ -217,16 +296,41 @@ struct bfin_gptimer_regs {
u32 counter;
u32 period;
u32 width;
#ifdef CONFIG_BF60x
u32 delay;
#endif
};
/*
* bfin group timer registers layout
*/
#ifndef CONFIG_BF60x
struct bfin_gptimer_group_regs {
__BFP(enable);
__BFP(disable);
u32 status;
};
#else
struct bfin_gptimer_group_regs {
__BFP(run);
__BFP(enable);
__BFP(disable);
__BFP(stop_cfg);
__BFP(stop_cfg_set);
__BFP(stop_cfg_clr);
__BFP(data_imsk);
__BFP(stat_imsk);
__BFP(tr_msk);
__BFP(tr_ie);
__BFP(data_ilat);
__BFP(stat_ilat);
__BFP(err_status);
__BFP(bcast_per);
__BFP(bcast_wid);
__BFP(bcast_dly);
};
#endif
#undef __BFP
......
arch/blackfin/include/asm/irqflags.h
View file @ 8e95a53b
......@@ -67,7 +67,11 @@ static inline notrace unsigned long __hard_local_irq_save(void)
static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
{
#ifdef CONFIG_BF60x
return (flags & IMASK_IVG11) == 0;
#else
return (flags & ~0x3f) == 0;
#endif
}
static inline notrace int hard_irqs_disabled(void)
......@@ -224,7 +228,7 @@ static inline notrace void hard_local_irq_restore(unsigned long flags)
* Direct interface to linux/irqflags.h.
*/
#define arch_local_save_flags() hard_local_save_flags()
#define arch_local_irq_save(flags) __hard_local_irq_save()
#define arch_local_irq_save() __hard_local_irq_save()
#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
#define arch_local_irq_enable() __hard_local_irq_enable()
#define arch_local_irq_disable() __hard_local_irq_disable()
......
arch/blackfin/include/asm/page.h
View file @ 8e95a53b
......@@ -7,14 +7,15 @@
#ifndef _BLACKFIN_PAGE_H
#define _BLACKFIN_PAGE_H
#include <asm-generic/page.h>
#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT)
#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT)
#define VM_DATA_DEFAULT_FLAGS \
(VM_READ | VM_WRITE | \
((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#include <asm-generic/page.h>
#include <asm-generic/memory_model.h>
#include <asm-generic/getorder.h>
......
arch/blackfin/include/asm/pda.h
View file @ 8e95a53b
......@@ -13,7 +13,9 @@
#ifndef __ASSEMBLY__
struct blackfin_pda { /* Per-processor Data Area */
#ifdef CONFIG_SMP
struct blackfin_pda *next;
#endif
unsigned long syscfg;
#ifdef CONFIG_SMP
......
arch/blackfin/include/asm/pm.h 0 → 100644
View file @ 8e95a53b
/*
* Blackfin bf609 power management
*
* Copyright 2011 Analog Devices Inc.
*
* Licensed under the GPL-2
*/
#ifndef __PM_H__
#define __PM_H__
#include <linux/suspend.h>
struct bfin_cpu_pm_fns {
void (*save)(unsigned long *);
void (*restore)(unsigned long *);
int (*valid)(suspend_state_t state);
void (*enter)(suspend_state_t state);
int (*prepare)(void);
void (*finish)(void);
};
extern struct bfin_cpu_pm_fns *bfin_cpu_pm;
# ifdef CONFIG_BFIN_COREB
void bfin_coreb_start(void);
void bfin_coreb_stop(void);
void bfin_coreb_reset(void);
# endif
#endif
arch/blackfin/include/asm/unistd.h
View file @ 8e95a53b
......@@ -11,7 +11,7 @@
*/
#define __NR_restart_syscall 0
#define __NR_exit 1
#define __NR_fork 2
/* 2 __NR_fork not supported on nommu */
#define __NR_read 3
#define __NR_write 4
#define __NR_open 5
......
arch/blackfin/kernel/bfin_dma.c
View file @ 8e95a53b
......@@ -45,9 +45,15 @@ static int __init blackfin_dma_init(void)
atomic_set(&dma_ch[i].chan_status, 0);
dma_ch[i].regs = dma_io_base_addr[i];
}
#ifdef CH_MEM_STREAM3_SRC
/* Mark MEMDMA Channel 3 as requested since we're using it internally */
request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
#else
/* Mark MEMDMA Channel 0 as requested since we're using it internally */
request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
#endif
#if defined(CONFIG_DEB_DMA_URGENT)
bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
......@@ -84,7 +90,8 @@ static const struct file_operations proc_dma_operations = {
static int __init proc_dma_init(void)
{
return proc_create("dma", 0, NULL, &proc_dma_operations) != NULL;
proc_create("dma", 0, NULL, &proc_dma_operations);
return 0;
}
late_initcall(proc_dma_init);
#endif
......@@ -204,6 +211,7 @@ EXPORT_SYMBOL(free_dma);
# ifndef MAX_DMA_SUSPEND_CHANNELS
# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
# endif
# ifndef CONFIG_BF60x
int blackfin_dma_suspend(void)
{
int i;
......@@ -213,7 +221,6 @@ int blackfin_dma_suspend(void)
printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
return -EBUSY;
}
if (i < MAX_DMA_SUSPEND_CHANNELS)
dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
}
......@@ -230,7 +237,6 @@ void blackfin_dma_resume(void)
for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
dma_ch[i].regs->cfg = 0;
if (i < MAX_DMA_SUSPEND_CHANNELS)
dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
}
......@@ -238,6 +244,16 @@ void blackfin_dma_resume(void)
bfin_write_DMAC_TC_PER(0x0111);
#endif
}
# else
int blackfin_dma_suspend(void)
{
return 0;
}
void blackfin_dma_resume(void)
{
}
#endif
#endif
/**
......@@ -279,10 +295,10 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
}
if (!bfin_read16(&src_ch->cfg))
if (!DMA_MMR_READ(&src_ch->cfg))
break;
else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
bfin_write16(&src_ch->cfg, 0);
else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
DMA_MMR_WRITE(&src_ch->cfg, 0);
break;
}
}
......@@ -295,22 +311,31 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
/* Destination */
bfin_write32(&dst_ch->start_addr, dst);
bfin_write16(&dst_ch->x_count, size >> 2);
bfin_write16(&dst_ch->x_modify, 1 << 2);
bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
/* Source */
bfin_write32(&src_ch->start_addr, src);
bfin_write16(&src_ch->x_count, size >> 2);
bfin_write16(&src_ch->x_modify, 1 << 2);
bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR);
DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
/* Enable */
bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32);
bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32);
DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
/* Since we are atomic now, don't use the workaround ssync */
__builtin_bfin_ssync();
#ifdef CONFIG_BF60x
/* Work around a possible MDMA anomaly. Running 2 MDMA channels to
* transfer DDR data to L1 SRAM may corrupt data.
* Should be reverted after this issue is root caused.
*/
while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
continue;
#endif
}
void __init early_dma_memcpy_done(void)
......@@ -336,6 +361,42 @@ void __init early_dma_memcpy_done(void)
__builtin_bfin_ssync();
}
#ifdef CH_MEM_STREAM3_SRC
#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
#else
#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
#endif
/**
* __dma_memcpy - program the MDMA registers
*
......@@ -358,8 +419,8 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u
*/
__builtin_bfin_ssync();
if (bfin_read_MDMA_S0_CONFIG())
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
if (bfin_read_MDMA_S_CONFIG())
while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
continue;
if (conf & DMA2D) {
......@@ -374,39 +435,42 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u
u32 shift = abs(dmod) >> 1;
size_t ycnt = cnt >> (16 - shift);
cnt = 1 << (16 - shift);
bfin_write_MDMA_D0_Y_COUNT(ycnt);
bfin_write_MDMA_S0_Y_COUNT(ycnt);
bfin_write_MDMA_D0_Y_MODIFY(dmod);
bfin_write_MDMA_S0_Y_MODIFY(smod);
bfin_write_MDMA_D_Y_COUNT(ycnt);
bfin_write_MDMA_S_Y_COUNT(ycnt);
bfin_write_MDMA_D_Y_MODIFY(dmod);
bfin_write_MDMA_S_Y_MODIFY(smod);
}
bfin_write_MDMA_D0_START_ADDR(daddr);
bfin_write_MDMA_D0_X_COUNT(cnt);
bfin_write_MDMA_D0_X_MODIFY(dmod);
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
bfin_write_MDMA_D_START_ADDR(daddr);
bfin_write_MDMA_D_X_COUNT(cnt);
bfin_write_MDMA_D_X_MODIFY(dmod);
bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
bfin_write_MDMA_S0_START_ADDR(saddr);
bfin_write_MDMA_S0_X_COUNT(cnt);
bfin_write_MDMA_S0_X_MODIFY(smod);
bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
bfin_write_MDMA_S_START_ADDR(saddr);
bfin_write_MDMA_S_X_COUNT(cnt);
bfin_write_MDMA_S_X_MODIFY(smod);
bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
bfin_write_MDMA_S0_CONFIG(DMAEN | conf);
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf);
bfin_write_MDMA_S_CONFIG(DMAEN | conf);
if (conf & DMA2D)
bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
else
bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
spin_unlock_irqrestore(&mdma_lock, flags);
SSYNC();
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
if (bfin_read_MDMA_S0_CONFIG())
while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
if (bfin_read_MDMA_S_CONFIG())
continue;
else
return;
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
bfin_write_MDMA_S0_CONFIG(0);
bfin_write_MDMA_D0_CONFIG(0);
bfin_write_MDMA_S_CONFIG(0);
bfin_write_MDMA_D_CONFIG(0);
}
/**
......@@ -448,8 +512,10 @@ static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
}
size >>= shift;
#ifndef DMA_MMR_SIZE_32
if (size > 0x10000)
conf |= DMA2D;
#endif
__dma_memcpy(dst, mod, src, mod, size, conf);
......@@ -488,6 +554,9 @@ EXPORT_SYMBOL(dma_memcpy);
*/
void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
{
#ifdef DMA_MMR_SIZE_32
_dma_memcpy(pdst, psrc, size);
#else
size_t bulk, rest;
bulk = size & ~0xffff;
......@@ -495,6 +564,7 @@ void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
if (bulk)
_dma_memcpy(pdst, psrc, bulk);
_dma_memcpy(pdst + bulk, psrc + bulk, rest);
#endif
return pdst;
}
EXPORT_SYMBOL(dma_memcpy_nocache);
......@@ -514,14 +584,14 @@ void *safe_dma_memcpy(void *dst, const void *src, size_t size)
}
EXPORT_SYMBOL(safe_dma_memcpy);
static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len,
static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
u16 size, u16 dma_size)
{
blackfin_dcache_flush_range(buf, buf + len * size);
__dma_memcpy(addr, 0, buf, size, len, dma_size);
}
static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
u16 size, u16 dma_size)
{
blackfin_dcache_invalidate_range(buf, buf + len * size);
......@@ -529,7 +599,7 @@ static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
}
#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \
void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
{ \
_dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
} \
......
arch/blackfin/kernel/bfin_gpio.c
View file @ 8e95a53b
......@@ -58,7 +58,7 @@ static struct gpio_port_t * const gpio_array[] = {
(struct gpio_port_t *) FIO0_FLAG_D,
(struct gpio_port_t *) FIO1_FLAG_D,
(struct gpio_port_t *) FIO2_FLAG_D,
#elif defined(CONFIG_BF54x)
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
(struct gpio_port_t *)PORTA_FER,
(struct gpio_port_t *)PORTB_FER,
(struct gpio_port_t *)PORTC_FER,
......@@ -66,9 +66,11 @@ static struct gpio_port_t * const gpio_array[] = {
(struct gpio_port_t *)PORTE_FER,
(struct gpio_port_t *)PORTF_FER,
(struct gpio_port_t *)PORTG_FER,
# if defined(CONFIG_BF54x)
(struct gpio_port_t *)PORTH_FER,
(struct gpio_port_t *)PORTI_FER,
(struct gpio_port_t *)PORTJ_FER,
# endif
#else
# error no gpio arrays defined
#endif
......@@ -210,7 +212,7 @@ static void port_setup(unsigned gpio, unsigned short usage)
else
*port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
SSYNC();
#elif defined(CONFIG_BF54x)
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
if (usage == GPIO_USAGE)
gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
else
......@@ -299,7 +301,7 @@ static void portmux_setup(unsigned short per)
pmux |= (function << offset);
bfin_write_PORT_MUX(pmux);
}
#elif defined(CONFIG_BF54x)
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
inline void portmux_setup(unsigned short per)
{
u16 ident = P_IDENT(per);
......@@ -377,7 +379,7 @@ static int portmux_group_check(unsigned short per)
}
#endif
#ifndef CONFIG_BF54x
#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
/***********************************************************
*
* FUNCTIONS: Blackfin General Purpose Ports Access Functions
......@@ -680,7 +682,7 @@ void bfin_gpio_pm_hibernate_restore(void)
#endif
#else /* CONFIG_BF54x */
#else /* CONFIG_BF54x || CONFIG_BF60x */
#ifdef CONFIG_PM
int bfin_pm_standby_ctrl(unsigned ctrl)
......@@ -726,7 +728,7 @@ unsigned short get_gpio_dir(unsigned gpio)
}
EXPORT_SYMBOL(get_gpio_dir);
#endif /* CONFIG_BF54x */
#endif /* CONFIG_BF54x || CONFIG_BF60x */
/***********************************************************
*
......@@ -783,7 +785,7 @@ int peripheral_request(unsigned short per, const char *label)
* be requested and used by several drivers
*/
#ifdef CONFIG_BF54x
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
#else
if (!(per & P_MAYSHARE)) {
......@@ -937,7 +939,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
" (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
}
#ifndef CONFIG_BF54x
#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
else { /* Reset POLAR setting when acquiring a gpio for the first time */
set_gpio_polar(gpio, 0);
}
......@@ -1110,7 +1112,7 @@ void bfin_gpio_irq_free(unsigned gpio)
static inline void __bfin_gpio_direction_input(unsigned gpio)
{
#ifdef CONFIG_BF54x
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
......@@ -1138,13 +1140,13 @@ EXPORT_SYMBOL(bfin_gpio_direction_input);
void bfin_gpio_irq_prepare(unsigned gpio)
{
#ifdef CONFIG_BF54x
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
unsigned long flags;
#endif
port_setup(gpio, GPIO_USAGE);
#ifdef CONFIG_BF54x
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
flags = hard_local_irq_save();
__bfin_gpio_direction_input(gpio);
hard_local_irq_restore(flags);
......@@ -1173,7 +1175,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
gpio_set_value(gpio, value);
#ifdef CONFIG_BF54x
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
......@@ -1188,7 +1190,7 @@ EXPORT_SYMBOL(bfin_gpio_direction_output);
int bfin_gpio_get_value(unsigned gpio)
{
#ifdef CONFIG_BF54x
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
#else
unsigned long flags;
......
arch/blackfin/kernel/cplb-nompu/cplbinit.c
View file @ 8e95a53b
......@@ -139,7 +139,7 @@ void __init generate_cplb_tables_all(void)
dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
dcplb_bounds[i_d++].data = 0;
/* BootROM -- largest one should be less than 1 meg. */
dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
if (L2_LENGTH) {
/* Addressing hole up to L2 SRAM. */
......@@ -178,7 +178,7 @@ void __init generate_cplb_tables_all(void)
icplb_bounds[i_i].eaddr = BOOT_ROM_START;
icplb_bounds[i_i++].data = 0;
/* BootROM -- largest one should be less than 1 meg. */
icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
icplb_bounds[i_i++].data = SDRAM_IGENERIC;
if (L2_LENGTH) {
......
arch/blackfin/kernel/cplb-nompu/cplbmgr.c
View file @ 8e95a53b
......@@ -179,6 +179,12 @@ MGR_ATTR static int dcplb_miss(int cpu)
addr = addr1;
}
#ifdef CONFIG_BF60x
if ((addr >= ASYNC_BANK0_BASE)
&& (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
d_data |= PAGE_SIZE_64MB;
#endif
/* Pick entry to evict */
idx = evict_one_dcplb(cpu);
......
arch/blackfin/kernel/debug-mmrs.c
View file @ 8e95a53b
......@@ -105,6 +105,7 @@ DEFINE_SYSREG(seqstat, , );
DEFINE_SYSREG(syscfg, , CSYNC());
#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
#ifndef CONFIG_BF60x
/*
* CAN
*/
......@@ -223,8 +224,10 @@ bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdm
__DMA(CURR_DESC_PTR, curr_desc_ptr);
__DMA(CURR_ADDR, curr_addr);
__DMA(IRQ_STATUS, irq_status);
#ifndef CONFIG_BF60x
if (strcmp(pfx, "IMDMA") != 0)
__DMA(PERIPHERAL_MAP, peripheral_map);
#endif
__DMA(CURR_X_COUNT, curr_x_count);
__DMA(CURR_Y_COUNT, curr_y_count);
}
......@@ -568,7 +571,7 @@ bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
#endif
}
#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
#endif /* CONFIG_BF60x */
/*
* The actual debugfs generation
*/
......@@ -740,7 +743,7 @@ static int __init bfin_debug_mmrs_init(void)
D32(WPDACNT0);
D32(WPDACNT1);
D32(WPSTAT);
#ifndef CONFIG_BF60x
/* System MMRs */
#ifdef ATAPI_CONTROL
parent = debugfs_create_dir("atapi", top);
......@@ -1873,7 +1876,7 @@ static int __init bfin_debug_mmrs_init(void)
}
#endif /* BF54x */
#endif /* CONFIG_BF60x */
debug_mmrs_dentry = top;
return 0;
......
arch/blackfin/kernel/entry.S
View file @ 8e95a53b
......@@ -64,16 +64,6 @@ ENTRY(_ret_from_fork)
jump (p0);
ENDPROC(_ret_from_fork)
ENTRY(_sys_fork)
r0 = -EINVAL;
#if (ANOMALY_05000371)
nop;
nop;
nop;
#endif
rts;
ENDPROC(_sys_fork)
ENTRY(_sys_vfork)
r0 = sp;
r0 += 24;
......
arch/blackfin/kernel/gptimers.c
View file @ 8e95a53b
......@@ -23,7 +23,11 @@
printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__);
#endif
#define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
#ifndef CONFIG_BF60x
# define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
#else
# define BFIN_TIMER_NUM_GROUP 1
#endif
static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
{
......@@ -158,6 +162,74 @@ uint32_t get_gptimer_count(unsigned int timer_id)
}
EXPORT_SYMBOL(get_gptimer_count);
#ifdef CONFIG_BF60x
void set_gptimer_delay(unsigned int timer_id, uint32_t delay)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
bfin_write(&timer_regs[timer_id]->delay, delay);
SSYNC();
}
EXPORT_SYMBOL(set_gptimer_delay);
uint32_t get_gptimer_delay(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return bfin_read(&timer_regs[timer_id]->delay);
}
EXPORT_SYMBOL(get_gptimer_delay);
#endif
#ifdef CONFIG_BF60x
int get_gptimer_intr(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat) & timil_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_intr);
void clear_gptimer_intr(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat, timil_mask[timer_id]);
}
EXPORT_SYMBOL(clear_gptimer_intr);
int get_gptimer_over(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat) & tovf_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_over);
void clear_gptimer_over(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat, tovf_mask[timer_id]);
}
EXPORT_SYMBOL(clear_gptimer_over);
int get_gptimer_run(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->run) & trun_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_run);
uint32_t get_gptimer_status(unsigned int group)
{
tassert(group < BFIN_TIMER_NUM_GROUP);
return bfin_read(&group_regs[group]->data_ilat);
}
EXPORT_SYMBOL(get_gptimer_status);
void set_gptimer_status(unsigned int group, uint32_t value)
{
tassert(group < BFIN_TIMER_NUM_GROUP);
bfin_write(&group_regs[group]->data_ilat, value);
SSYNC();
}
EXPORT_SYMBOL(set_gptimer_status);
#else
uint32_t get_gptimer_status(unsigned int group)
{
tassert(group < BFIN_TIMER_NUM_GROUP);
......@@ -212,6 +284,7 @@ int get_gptimer_run(unsigned int timer_id)
return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_run);
#endif
void set_gptimer_config(unsigned int timer_id, uint16_t config)
{
......@@ -231,6 +304,12 @@ EXPORT_SYMBOL(get_gptimer_config);
void enable_gptimers(uint16_t mask)
{
int i;
#ifdef CONFIG_BF60x
uint16_t imask;
imask = bfin_read16(TIMER_DATA_IMSK);
imask &= ~mask;
bfin_write16(TIMER_DATA_IMSK, imask);
#endif
tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
bfin_write(&group_regs[i]->enable, mask & 0xFF);
......@@ -253,12 +332,16 @@ static void _disable_gptimers(uint16_t mask)
void disable_gptimers(uint16_t mask)
{
#ifndef CONFIG_BF60x
int i;
_disable_gptimers(mask);
for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
if (mask & (1 << i))
bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
SSYNC();
#else
_disable_gptimers(mask);
#endif
}
EXPORT_SYMBOL(disable_gptimers);
......
arch/blackfin/kernel/process.c
View file @ 8e95a53b
......@@ -95,7 +95,9 @@ void cpu_idle(void)
idle();
rcu_idle_exit();
tick_nohz_idle_exit();
schedule_preempt_disabled();
preempt_enable_no_resched();
schedule();
preempt_disable();
}
}
......@@ -329,12 +331,16 @@ int in_mem_const(unsigned long addr, unsigned long size,
{
return in_mem_const_off(addr, size, 0, const_addr, const_size);
}
#ifdef CONFIG_BF60x
#define ASYNC_ENABLED(bnum, bctlnum) 1
#else
#define ASYNC_ENABLED(bnum, bctlnum) \
({ \
(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
1; \
})
#endif
/*
* We can't read EBIU banks that aren't enabled or we end up hanging
* on the access to the async space. Make sure we validate accesses
......
arch/blackfin/kernel/reboot.c
View file @ 8e95a53b
......@@ -22,6 +22,7 @@
__attribute__ ((__l1_text__, __noreturn__))
static void bfin_reset(void)
{
#ifndef CONFIG_BF60x
if (!ANOMALY_05000353 && !ANOMALY_05000386)
bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
......@@ -57,7 +58,6 @@ static void bfin_reset(void)
if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
bfin_read_SWRST();
#endif
/* Wait for the SWRST write to complete. Cannot rely on SSYNC
* though as the System state is all reset now.
*/
......@@ -72,6 +72,10 @@ static void bfin_reset(void)
while (1)
/* Issue core reset */
asm("raise 1");
#else
while (1)
bfin_write_RCU0_CTL(0x1);
#endif
}
__attribute__((weak))
......
arch/blackfin/kernel/setup.c
View file @ 8e95a53b
......@@ -25,12 +25,16 @@
#include <asm/cacheflush.h>
#include <asm/blackfin.h>
#include <asm/cplbinit.h>
#include <asm/clocks.h>
#include <asm/div64.h>
#include <asm/cpu.h>
#include <asm/fixed_code.h>
#include <asm/early_printk.h>
#include <asm/irq_handler.h>
#include <asm/pda.h>
#ifdef CONFIG_BF60x
#include <mach/pm.h>
#endif
u16 _bfin_swrst;
EXPORT_SYMBOL(_bfin_swrst);
......@@ -550,7 +554,6 @@ static __init void memory_setup(void)
{
#ifdef CONFIG_MTD_UCLINUX
unsigned long mtd_phys = 0;
unsigned long n;
#endif
unsigned long max_mem;
......@@ -594,9 +597,9 @@ static __init void memory_setup(void)
mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
n = ext2_image_size((void *)(mtd_phys + 0x400));
if (n)
mtd_size = PAGE_ALIGN(n * 1024);
if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
mtd_size =
PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
# endif
# if defined(CONFIG_CRAMFS)
......@@ -612,7 +615,8 @@ static __init void memory_setup(void)
/* ROM_FS is XIP, so if we found it, we need to limit memory */
if (memory_end > max_mem) {
pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
(max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
memory_end = max_mem;
}
}
......@@ -642,7 +646,8 @@ static __init void memory_setup(void)
* doesn't exist, or we don't need to - then dont.
*/
if (memory_end > max_mem) {
pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
(max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
memory_end = max_mem;
}
......@@ -661,8 +666,8 @@ static __init void memory_setup(void)
init_mm.end_data = (unsigned long)_edata;
init_mm.brk = (unsigned long)0;
printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
printk(KERN_INFO "Memory map:\n"
" fixedcode = 0x%p-0x%p\n"
......@@ -705,7 +710,7 @@ void __init find_min_max_pfn(void)
int i;
max_pfn = 0;
min_low_pfn = memory_end;
min_low_pfn = PFN_DOWN(memory_end);
for (i = 0; i < bfin_memmap.nr_map; i++) {
unsigned long start, end;
......@@ -748,8 +753,7 @@ static __init void setup_bootmem_allocator(void)
/* pfn of the first usable page frame after kernel image*/
if (min_low_pfn < memory_start >> PAGE_SHIFT)
min_low_pfn = memory_start >> PAGE_SHIFT;
start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
end_pfn = memory_end >> PAGE_SHIFT;
/*
......@@ -794,8 +798,8 @@ static __init void setup_bootmem_allocator(void)
}
/* reserve memory before memory_start, including bootmap */
reserve_bootmem(PAGE_OFFSET,
memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
BOOTMEM_DEFAULT);
}
......@@ -844,13 +848,40 @@ static inline int __init get_mem_size(void)
break;
}
switch (ddrctl & 0x30000) {
case DEVWD_4: ret *= 2;
case DEVWD_8: ret *= 2;
case DEVWD_16: break;
case DEVWD_4:
ret *= 2;
case DEVWD_8:
ret *= 2;
case DEVWD_16:
break;
}
if ((ddrctl & 0xc000) == 0x4000)
ret *= 2;
return ret;
#elif defined(CONFIG_BF60x)
u32 ddrctl = bfin_read_DMC0_CFG();
int ret;
switch (ddrctl & 0xf00) {
case DEVSZ_64:
ret = 64 / 8;
break;
case DEVSZ_128:
ret = 128 / 8;
break;
case DEVSZ_256:
ret = 256 / 8;
break;
case DEVSZ_512:
ret = 512 / 8;
break;
case DEVSZ_1G:
ret = 1024 / 8;
break;
case DEVSZ_2G:
ret = 2048 / 8;
break;
}
return ret;
#endif
BUG();
}
......@@ -860,6 +891,22 @@ void __init native_machine_early_platform_add_devices(void)
{
}
#ifdef CONFIG_BF60x
static inline u_long bfin_get_clk(char *name)
{
struct clk *clk;
u_long clk_rate;
clk = clk_get(NULL, name);
if (IS_ERR(clk))
return 0;
clk_rate = clk_get_rate(clk);
clk_put(clk);
return clk_rate;
}
#endif
void __init setup_arch(char **cmdline_p)
{
u32 mmr;
......@@ -870,6 +917,7 @@ void __init setup_arch(char **cmdline_p)
enable_shadow_console();
/* Check to make sure we are running on the right processor */
mmr = bfin_cpuid();
if (unlikely(CPUID != bfin_cpuid()))
printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
CPU, bfin_cpuid(), bfin_revid());
......@@ -890,6 +938,10 @@ void __init setup_arch(char **cmdline_p)
memset(&bfin_memmap, 0, sizeof(bfin_memmap));
#ifdef CONFIG_BF60x
/* Should init clock device before parse command early */
clk_init();
#endif
/* If the user does not specify things on the command line, use
* what the bootloader set things up as
*/
......@@ -904,6 +956,7 @@ void __init setup_arch(char **cmdline_p)
memory_setup();
#ifndef CONFIG_BF60x
/* Initialize Async memory banks */
bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
......@@ -913,6 +966,7 @@ void __init setup_arch(char **cmdline_p)
bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
#endif
#endif
#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
......@@ -938,7 +992,7 @@ void __init setup_arch(char **cmdline_p)
printk(KERN_INFO "Hardware Trace %s and %sabled\n",
(mmr & 0x1) ? "active" : "off",
(mmr & 0x2) ? "en" : "dis");
#ifndef CONFIG_BF60x
mmr = bfin_read_SYSCR();
printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
......@@ -980,7 +1034,7 @@ void __init setup_arch(char **cmdline_p)
printk(KERN_INFO "Recovering from Watchdog event\n");
else if (_bfin_swrst & RESET_SOFTWARE)
printk(KERN_NOTICE "Reset caused by Software reset\n");
#endif
printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
if (bfin_compiled_revid() == 0xffff)
printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
......@@ -1008,8 +1062,13 @@ void __init setup_arch(char **cmdline_p)
printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
#ifdef CONFIG_BF60x
printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n",
cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000);
#else
printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
cclk / 1000000, sclk / 1000000);
#endif
setup_bootmem_allocator();
......@@ -1060,10 +1119,12 @@ subsys_initcall(topology_init);
/* Get the input clock frequency */
static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
#ifndef CONFIG_BF60x
static u_long get_clkin_hz(void)
{
return cached_clkin_hz;
}
#endif
static int __init early_init_clkin_hz(char *buf)
{
cached_clkin_hz = simple_strtoul(buf, NULL, 0);
......@@ -1075,6 +1136,7 @@ static int __init early_init_clkin_hz(char *buf)
}
early_param("clkin_hz=", early_init_clkin_hz);
#ifndef CONFIG_BF60x
/* Get the voltage input multiplier */
static u_long get_vco(void)
{
......@@ -1097,10 +1159,14 @@ static u_long get_vco(void)
cached_vco *= msel;
return cached_vco;
}
#endif
/* Get the Core clock */
u_long get_cclk(void)
{
#ifdef CONFIG_BF60x
return bfin_get_clk("CCLK");
#else
static u_long cached_cclk_pll_div, cached_cclk;
u_long csel, ssel;
......@@ -1120,12 +1186,39 @@ u_long get_cclk(void)
else
cached_cclk = get_vco() >> csel;
return cached_cclk;
#endif
}
EXPORT_SYMBOL(get_cclk);
/* Get the System clock */
#ifdef CONFIG_BF60x
/* Get the bf60x clock of SCLK0 domain */
u_long get_sclk0(void)
{
return bfin_get_clk("SCLK0");
}
EXPORT_SYMBOL(get_sclk0);
/* Get the bf60x clock of SCLK1 domain */
u_long get_sclk1(void)
{
return bfin_get_clk("SCLK1");
}
EXPORT_SYMBOL(get_sclk1);
/* Get the bf60x DRAM clock */
u_long get_dclk(void)
{
return bfin_get_clk("DCLK");
}
EXPORT_SYMBOL(get_dclk);
#endif
/* Get the default system clock */
u_long get_sclk(void)
{
#ifdef CONFIG_BF60x
return get_sclk0();
#else
static u_long cached_sclk;
u_long ssel;
......@@ -1146,6 +1239,7 @@ u_long get_sclk(void)
cached_sclk = get_vco() / ssel;
return cached_sclk;
#endif
}
EXPORT_SYMBOL(get_sclk);
......
arch/blackfin/kernel/shadow_console.c
View file @ 8e95a53b
......@@ -15,9 +15,9 @@
#include <asm/irq_handler.h>
#include <asm/early_printk.h>
#define SHADOW_CONSOLE_START (0x500)
#define SHADOW_CONSOLE_END (0x1000)
#define SHADOW_CONSOLE_MAGIC_LOC (0x4F0)
#define SHADOW_CONSOLE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500)
#define SHADOW_CONSOLE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000)
#define SHADOW_CONSOLE_MAGIC_LOC (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0)
#define SHADOW_CONSOLE_MAGIC (0xDEADBEEF)
static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START;
......
arch/blackfin/kernel/time-ts.c
View file @ 8e95a53b
......@@ -66,8 +66,14 @@ void __init setup_gptimer0(void)
{
disable_gptimers(TIMER0bit);
#ifdef CONFIG_BF60x
bfin_write16(TIMER_DATA_IMSK, 0);
set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
| TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
#else
set_gptimer_config(TIMER0_id, \
TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
#endif
set_gptimer_period(TIMER0_id, -1);
set_gptimer_pwidth(TIMER0_id, -2);
SSYNC();
......@@ -135,9 +141,15 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC: {
#ifndef CONFIG_BF60x
set_gptimer_config(TIMER0_id, \
TIMER_OUT_DIS | TIMER_IRQ_ENA | \
TIMER_PERIOD_CNT | TIMER_MODE_PWM);
#else
set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
| TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
#endif
set_gptimer_period(TIMER0_id, get_sclk() / HZ);
set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
enable_gptimers(TIMER0bit);
......@@ -145,8 +157,14 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
}
case CLOCK_EVT_MODE_ONESHOT:
disable_gptimers(TIMER0bit);
#ifndef CONFIG_BF60x
set_gptimer_config(TIMER0_id, \
TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
#else
set_gptimer_config(TIMER0_id, TIMER_OUT_DIS | TIMER_MODE_PWM
| TIMER_PULSE_HI | TIMER_IRQ_WID_DLY);
#endif
set_gptimer_period(TIMER0_id, 0);
break;
case CLOCK_EVT_MODE_UNUSED:
......@@ -160,7 +178,7 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
static void bfin_gptmr0_ack(void)
{
set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0);
clear_gptimer_intr(TIMER0_id);
}
static void __init bfin_gptmr0_init(void)
......@@ -307,6 +325,11 @@ void bfin_coretmr_clockevent_init(void)
unsigned int cpu = smp_processor_id();
struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
#ifdef CONFIG_SMP
evt->broadcast = smp_timer_broadcast;
#endif
#ifdef CONFIG_SMP
evt->broadcast = smp_timer_broadcast;
#endif
......
arch/blackfin/lib/divsi3.S
View file @ 8e95a53b
/*
* Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*
* 16 / 32 bit signed division.
* Special cases :
......
arch/blackfin/lib/memchr.S
View file @ 8e95a53b
/*
* Copyright 2005-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#include <linux/linkage.h>
......
arch/blackfin/lib/memcmp.S
View file @ 8e95a53b
/*
* Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#include <linux/linkage.h>
......
arch/blackfin/lib/memcpy.S
View file @ 8e95a53b
......@@ -7,7 +7,7 @@
*
* Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#include <linux/linkage.h>
......
arch/blackfin/lib/memmove.S
View file @ 8e95a53b
/*
* Copyright 2005-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#include <linux/linkage.h>
......
arch/blackfin/lib/memset.S
View file @ 8e95a53b
/*
* Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#include <linux/linkage.h>
......
arch/blackfin/lib/modsi3.S
View file @ 8e95a53b
......@@ -6,7 +6,7 @@
*
* Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
.global ___modsi3;
......
arch/blackfin/lib/muldi3.S
View file @ 8e95a53b
/*
* Copyright 2008 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
.align 2
......
arch/blackfin/lib/smulsi3_highpart.S
View file @ 8e95a53b
/*
* Copyright 2007 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
.align 2
......
arch/blackfin/lib/strcmp.S
View file @ 8e95a53b
/*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#include <linux/linkage.h>
......
arch/blackfin/lib/strcpy.S
View file @ 8e95a53b
/*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#include <linux/linkage.h>
......
arch/blackfin/lib/strncmp.S
View file @ 8e95a53b
/*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#include <linux/linkage.h>
......
arch/blackfin/lib/strncpy.S
View file @ 8e95a53b
/*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#include <linux/linkage.h>
......
arch/blackfin/lib/udivsi3.S
View file @ 8e95a53b
/*
* Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#include <linux/linkage.h>
......
arch/blackfin/lib/umodsi3.S
View file @ 8e95a53b
......@@ -3,7 +3,7 @@
*
* Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifdef CONFIG_ARITHMETIC_OPS_L1
......
arch/blackfin/lib/umulsi3_highpart.S
View file @ 8e95a53b
/*
* Copyright 2007 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
.align 2
......
arch/blackfin/mach-bf518/boards/ezbrd.c
View file @ 8e95a53b
......@@ -529,6 +529,8 @@ static struct platform_device bfin_i2s = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -547,6 +549,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......
arch/blackfin/mach-bf518/boards/tcm-bf518.c
View file @ 8e95a53b
......@@ -455,6 +455,8 @@ static struct platform_device bfin_sir1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -473,6 +475,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......
arch/blackfin/mach-bf518/include/mach/anomaly.h
View file @ 8e95a53b
......@@ -6,8 +6,7 @@
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
* Licensed under the Clear BSD license.
*/
/* This file should be up to date with:
......
arch/blackfin/mach-bf518/include/mach/cdefBF512.h
View file @ 8e95a53b
/*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _CDEF_BF512_H
......
arch/blackfin/mach-bf518/include/mach/cdefBF514.h
View file @ 8e95a53b
/*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _CDEF_BF514_H
......
arch/blackfin/mach-bf518/include/mach/cdefBF516.h
View file @ 8e95a53b
/*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _CDEF_BF516_H
......
arch/blackfin/mach-bf518/include/mach/cdefBF518.h
View file @ 8e95a53b
/*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _CDEF_BF518_H
......
arch/blackfin/mach-bf518/include/mach/defBF512.h
View file @ 8e95a53b
/*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF512_H
......@@ -1083,77 +1083,6 @@
#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
/* TWI_PRESCALE Masks */
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
#define TWI_ENA 0x0080 /* TWI Enable */
#define SCCB 0x0200 /* SCCB Compatibility Enable */
/* TWI_SLAVE_CTL Masks */
#define SEN 0x0001 /* Slave Enable */
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
/* TWI_SLAVE_STAT Masks */
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
#define GCALL 0x0002 /* General Call Indicator */
/* TWI_MASTER_CTL Masks */
#define MEN 0x0001 /* Master Mode Enable */
#define MADD_LEN 0x0002 /* Master Address Length */
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
#define FAST 0x0008 /* Use Fast Mode Timing Specs */
#define STOP 0x0010 /* Issue Stop Condition */
#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
#define DCNT 0x3FC0 /* Data Bytes To Transfer */
#define SDAOVR 0x4000 /* Serial Data Override */
#define SCLOVR 0x8000 /* Serial Clock Override */
/* TWI_MASTER_STAT Masks */
#define MPROG 0x0001 /* Master Transfer In Progress */
#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
#define ANAK 0x0004 /* Address Not Acknowledged */
#define DNAK 0x0008 /* Data Not Acknowledged */
#define BUFRDERR 0x0010 /* Buffer Read Error */
#define BUFWRERR 0x0020 /* Buffer Write Error */
#define SDASEN 0x0040 /* Serial Data Sense */
#define SCLSEN 0x0080 /* Serial Clock Sense */
#define BUSBUSY 0x0100 /* Bus Busy Indicator */
/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
#define SINIT 0x0001 /* Slave Transfer Initiated */
#define SCOMP 0x0002 /* Slave Transfer Complete */
#define SERR 0x0004 /* Slave Transfer Error */
#define SOVF 0x0008 /* Slave Overflow */
#define MCOMP 0x0010 /* Master Transfer Complete */
#define MERR 0x0020 /* Master Transfer Error */
#define XMTSERV 0x0040 /* Transmit FIFO Service */
#define RCVSERV 0x0080 /* Receive FIFO Service */
/* TWI_FIFO_CTRL Masks */
#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
/* TWI_FIFO_STAT Masks */
#define XMTSTAT 0x0003 /* Transmit FIFO Status */
#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
#define RCVSTAT 0x000C /* Receive FIFO Status */
#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
/* ******************* PIN CONTROL REGISTER MASKS ************************/
/* PORT_MUX Masks */
#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
......
arch/blackfin/mach-bf518/include/mach/defBF514.h
View file @ 8e95a53b
/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF514_H
......
arch/blackfin/mach-bf518/include/mach/defBF516.h
View file @ 8e95a53b
/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF516_H
......
arch/blackfin/mach-bf518/include/mach/defBF518.h
View file @ 8e95a53b
/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF518_H
......
arch/blackfin/mach-bf527/boards/ad7160eval.c
View file @ 8e95a53b
......@@ -569,6 +569,8 @@ static const struct ad7160_platform_data bfin_ad7160_ts_info = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -587,6 +589,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......@@ -681,6 +686,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = {
.rotary_button_key = KEY_ENTER,
.debounce = 10, /* 0..17 */
.mode = ROT_QUAD_ENC | ROT_DEBE,
.pm_wakeup = 1,
};
static struct resource bfin_rotary_resources[] = {
......
arch/blackfin/mach-bf527/boards/cm_bf527.c
View file @ 8e95a53b
......@@ -698,6 +698,8 @@ static struct platform_device bfin_sir1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -716,6 +718,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......
arch/blackfin/mach-bf527/boards/ezbrd.c
View file @ 8e95a53b
......@@ -576,6 +576,8 @@ static struct platform_device bfin_sir1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -594,6 +596,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......
arch/blackfin/mach-bf527/boards/ezkit.c
View file @ 8e95a53b
......@@ -869,6 +869,8 @@ static struct platform_device bfin_sir1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -887,6 +889,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......@@ -1105,6 +1110,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = {
.rotary_button_key = KEY_ENTER,
.debounce = 10, /* 0..17 */
.mode = ROT_QUAD_ENC | ROT_DEBE,
.pm_wakeup = 1,
};
static struct resource bfin_rotary_resources[] = {
......
arch/blackfin/mach-bf527/boards/tll6527m.c
View file @ 8e95a53b
......@@ -656,6 +656,8 @@ static struct platform_device bfin_sir1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -674,6 +676,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......
arch/blackfin/mach-bf527/include/mach/anomaly.h
View file @ 8e95a53b
......@@ -6,8 +6,7 @@
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
* Licensed under the Clear BSD license.
*/
/* This file should be up to date with:
......
arch/blackfin/mach-bf527/include/mach/defBF522.h
View file @ 8e95a53b
/*
* Copyright 2007-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF522_H
......@@ -1084,77 +1084,6 @@
#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
/* TWI_PRESCALE Masks */
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
#define TWI_ENA 0x0080 /* TWI Enable */
#define SCCB 0x0200 /* SCCB Compatibility Enable */
/* TWI_SLAVE_CTL Masks */
#define SEN 0x0001 /* Slave Enable */
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
/* TWI_SLAVE_STAT Masks */
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
#define GCALL 0x0002 /* General Call Indicator */
/* TWI_MASTER_CTL Masks */
#define MEN 0x0001 /* Master Mode Enable */
#define MADD_LEN 0x0002 /* Master Address Length */
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
#define FAST 0x0008 /* Use Fast Mode Timing Specs */
#define STOP 0x0010 /* Issue Stop Condition */
#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
#define DCNT 0x3FC0 /* Data Bytes To Transfer */
#define SDAOVR 0x4000 /* Serial Data Override */
#define SCLOVR 0x8000 /* Serial Clock Override */
/* TWI_MASTER_STAT Masks */
#define MPROG 0x0001 /* Master Transfer In Progress */
#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
#define ANAK 0x0004 /* Address Not Acknowledged */
#define DNAK 0x0008 /* Data Not Acknowledged */
#define BUFRDERR 0x0010 /* Buffer Read Error */
#define BUFWRERR 0x0020 /* Buffer Write Error */
#define SDASEN 0x0040 /* Serial Data Sense */
#define SCLSEN 0x0080 /* Serial Clock Sense */
#define BUSBUSY 0x0100 /* Bus Busy Indicator */
/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
#define SINIT 0x0001 /* Slave Transfer Initiated */
#define SCOMP 0x0002 /* Slave Transfer Complete */
#define SERR 0x0004 /* Slave Transfer Error */
#define SOVF 0x0008 /* Slave Overflow */
#define MCOMP 0x0010 /* Master Transfer Complete */
#define MERR 0x0020 /* Master Transfer Error */
#define XMTSERV 0x0040 /* Transmit FIFO Service */
#define RCVSERV 0x0080 /* Receive FIFO Service */
/* TWI_FIFO_CTRL Masks */
#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
/* TWI_FIFO_STAT Masks */
#define XMTSTAT 0x0003 /* Transmit FIFO Status */
#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
#define RCVSTAT 0x000C /* Receive FIFO Status */
#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
/* Omit CAN masks from defBF534.h */
/* ******************* PIN CONTROL REGISTER MASKS ************************/
......
arch/blackfin/mach-bf527/include/mach/defBF525.h
View file @ 8e95a53b
/*
* Copyright 2007-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF525_H
......
arch/blackfin/mach-bf527/include/mach/defBF527.h
View file @ 8e95a53b
/*
* Copyright 2007-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF527_H
......
arch/blackfin/mach-bf533/include/mach/anomaly.h
View file @ 8e95a53b
......@@ -6,8 +6,7 @@
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
* Licensed under the Clear BSD license.
*/
/* This file should be up to date with:
......
arch/blackfin/mach-bf533/include/mach/defBF532.h
View file @ 8e95a53b
......@@ -3,7 +3,7 @@
*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF532_H
......
arch/blackfin/mach-bf537/boards/cm_bf537e.c
View file @ 8e95a53b
......@@ -486,6 +486,8 @@ static struct platform_device bfin_sir1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -504,6 +506,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......
arch/blackfin/mach-bf537/boards/cm_bf537u.c
View file @ 8e95a53b
......@@ -451,6 +451,8 @@ static struct platform_device bfin_sir1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -469,6 +471,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......
arch/blackfin/mach-bf537/boards/dnp5370.c
View file @ 8e95a53b
......@@ -329,6 +329,8 @@ static struct platform_device bfin_uart1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -347,6 +349,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......
arch/blackfin/mach-bf537/boards/minotaur.c
View file @ 8e95a53b
......@@ -386,6 +386,8 @@ static struct platform_device bfin_sir1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -404,6 +406,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......
arch/blackfin/mach-bf537/boards/stamp.c
View file @ 8e95a53b
......@@ -1790,6 +1790,8 @@ static struct platform_device bfin_sir1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -1808,6 +1810,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......@@ -2361,7 +2366,13 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
},
#endif
};
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) \
|| defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
};
#endif
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
static struct resource bfin_sport0_uart_resources[] = {
......@@ -2382,11 +2393,6 @@ static struct resource bfin_sport0_uart_resources[] = {
},
};
static unsigned short bfin_sport0_peripherals[] = {
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
};
static struct platform_device bfin_sport0_uart_device = {
.name = "bfin-sport-uart",
.id = 0,
......@@ -2432,7 +2438,49 @@ static struct platform_device bfin_sport1_uart_device = {
};
#endif
#endif
#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
static struct resource bfin_sport0_resources[] = {
{
.start = SPORT0_TCR1,
.end = SPORT0_MRCS3+4,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_SPORT0_RX,
.end = IRQ_SPORT0_RX+1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_SPORT0_TX,
.end = IRQ_SPORT0_TX+1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_SPORT0_ERROR,
.end = IRQ_SPORT0_ERROR,
.flags = IORESOURCE_IRQ,
},
{
.start = CH_SPORT0_TX,
.end = CH_SPORT0_TX,
.flags = IORESOURCE_DMA,
},
{
.start = CH_SPORT0_RX,
.end = CH_SPORT0_RX,
.flags = IORESOURCE_DMA,
},
};
static struct platform_device bfin_sport0_device = {
.name = "bfin_sport_raw",
.id = 0,
.num_resources = ARRAY_SIZE(bfin_sport0_resources),
.resource = bfin_sport0_resources,
.dev = {
.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
},
};
#endif
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
......@@ -2754,7 +2802,9 @@ static struct platform_device bf5xx_adau1701_device = {
static struct platform_device *stamp_devices[] __initdata = {
&bfin_dpmc,
#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
&bfin_sport0_device,
#endif
#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
&bfin_pcmcia_cf_device,
#endif
......
arch/blackfin/mach-bf537/boards/tcm_bf537.c
View file @ 8e95a53b
......@@ -453,6 +453,8 @@ static struct platform_device bfin_sir1_device = {
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -471,6 +473,9 @@ static struct platform_device i2c_bfin_twi_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#endif
......
arch/blackfin/mach-bf537/include/mach/anomaly.h
View file @ 8e95a53b
......@@ -6,8 +6,7 @@
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
* Licensed under the Clear BSD license.
*/
/* This file should be up to date with:
......
arch/blackfin/mach-bf537/include/mach/defBF534.h
View file @ 8e95a53b
/*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF534_H
......@@ -1403,75 +1403,6 @@
#define ERR_DET 0x4000 /* Error Detected Indicator */
#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
/* TWI_PRESCALE Masks */
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
#define TWI_ENA 0x0080 /* TWI Enable */
#define SCCB 0x0200 /* SCCB Compatibility Enable */
/* TWI_SLAVE_CTL Masks */
#define SEN 0x0001 /* Slave Enable */
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
#define GEN 0x0010 /* General Call Address Matching Enabled */
/* TWI_SLAVE_STAT Masks */
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
#define GCALL 0x0002 /* General Call Indicator */
/* TWI_MASTER_CTL Masks */
#define MEN 0x0001 /* Master Mode Enable */
#define MADD_LEN 0x0002 /* Master Address Length */
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
#define FAST 0x0008 /* Use Fast Mode Timing Specs */
#define STOP 0x0010 /* Issue Stop Condition */
#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
#define DCNT 0x3FC0 /* Data Bytes To Transfer */
#define SDAOVR 0x4000 /* Serial Data Override */
#define SCLOVR 0x8000 /* Serial Clock Override */
/* TWI_MASTER_STAT Masks */
#define MPROG 0x0001 /* Master Transfer In Progress */
#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
#define ANAK 0x0004 /* Address Not Acknowledged */
#define DNAK 0x0008 /* Data Not Acknowledged */
#define BUFRDERR 0x0010 /* Buffer Read Error */
#define BUFWRERR 0x0020 /* Buffer Write Error */
#define SDASEN 0x0040 /* Serial Data Sense */
#define SCLSEN 0x0080 /* Serial Clock Sense */
#define BUSBUSY 0x0100 /* Bus Busy Indicator */
/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
#define SINIT 0x0001 /* Slave Transfer Initiated */
#define SCOMP 0x0002 /* Slave Transfer Complete */
#define SERR 0x0004 /* Slave Transfer Error */
#define SOVF 0x0008 /* Slave Overflow */
#define MCOMP 0x0010 /* Master Transfer Complete */
#define MERR 0x0020 /* Master Transfer Error */
#define XMTSERV 0x0040 /* Transmit FIFO Service */
#define RCVSERV 0x0080 /* Receive FIFO Service */
/* TWI_FIFO_CTRL Masks */
#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
/* TWI_FIFO_STAT Masks */
#define XMTSTAT 0x0003 /* Transmit FIFO Status */
#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
#define RCVSTAT 0x000C /* Receive FIFO Status */
#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
/* ******************* PIN CONTROL REGISTER MASKS ************************/
/* PORT_MUX Masks */
......
arch/blackfin/mach-bf537/include/mach/defBF537.h
View file @ 8e95a53b
/*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF537_H
......
arch/blackfin/mach-bf538/boards/ezkit.c
View file @ 8e95a53b
......@@ -718,6 +718,8 @@ static struct platform_device bf538_spi_master2 = {
};
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
......@@ -736,9 +738,13 @@ static struct platform_device i2c_bfin_twi0_device = {
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
.dev = {
.platform_data = &bfin_twi0_pins,
},
};
#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
static struct resource bfin_twi1_resource[] = {
[0] = {
.start = TWI1_REGBASE,
......
arch/blackfin/mach-bf538/include/mach/anomaly.h
View file @ 8e95a53b
......@@ -6,8 +6,7 @@
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
* Licensed under the Clear BSD license.
*/
/* This file should be up to date with:
......
arch/blackfin/mach-bf538/include/mach/defBF539.h
View file @ 8e95a53b
/*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF539_H
......
arch/blackfin/mach-bf548/boards/cm_bf548.c
View file @ 8e95a53b
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arch/blackfin/mach-bf548/include/mach/anomaly.h
View file @ 8e95a53b
......@@ -6,8 +6,7 @@
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
* Licensed under the Clear BSD license.
*/
/* This file should be up to date with:
......
arch/blackfin/mach-bf548/include/mach/defBF542.h
View file @ 8e95a53b
/*
* Copyright 2007-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF542_H
......
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